提交 9b949c28 编写于 作者: G Grissiom

rm48x50: add cache_{enable, disable}

上级 e8bbbe67
...@@ -52,4 +52,43 @@ int __rt_ffs(int value) ...@@ -52,4 +52,43 @@ int __rt_ffs(int value)
} }
#endif #endif
#ifdef __TI_COMPILER_VERSION__
void rt_hw_cpu_icache_enable()
{
__asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
__asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable");
__asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored");
__asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache");
__asm(" ISB");
}
void rt_hw_cpu_icache_disable()
{
__asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
__asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable");
__asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache");
__asm(" ISB");
}
void rt_hw_cpu_dcache_enable()
{
__asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data");
__asm(" ORR R1, R1, #0x1 <<2");
__asm(" DSB");
__asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache");
__asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache");
}
void rt_hw_cpu_dcache_disable()
{
/* FIXME: Clean entire data cache. This routine depends on the data cache
* size. It can be omitted if it is known that the data cache has no dirty
* data. */
__asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
__asm(" BIC r1, r1, #0x1 <<2");
__asm(" DSB");
__asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache");
}
#endif
/*@}*/ /*@}*/
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