diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/.config b/bsp/bluetrum/ab32vg1-ab-prougen/.config index b1a20104ab64f8b162bc53ec1c357418ba076e52..c5bca5ae40b6290f6d6878af06fad3208b810e38 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/.config +++ b/bsp/bluetrum/ab32vg1-ab-prougen/.config @@ -108,14 +108,6 @@ CONFIG_FINSH_ARG_MAX=10 # Device virtual file system # # CONFIG_RT_USING_DFS is not set -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set # # Device Drivers @@ -383,6 +375,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set # # peripheral libraries and drivers @@ -516,6 +509,8 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_WDT is not set # CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_ADC is not set # # Board extended module Drivers diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig index 0d8ffcf4bb48ed6d0b1cbb7f3fd1b60621291d42..47adcc7b0f0e5ac9b1a91541ad402be18a4a5d3a 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig @@ -162,6 +162,22 @@ menu "On-chip Peripheral Drivers" default n endif + config BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + endif + endmenu menu "Board extended module Drivers" diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/link.lds b/bsp/bluetrum/ab32vg1-ab-prougen/link.lds index 85ee5096c06a4420a2922421995b053f518e989c..4f79ad883aeb89128886aa62094c4ed0a71f099f 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/link.lds +++ b/bsp/bluetrum/ab32vg1-ab-prougen/link.lds @@ -40,16 +40,6 @@ SECTIONS KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); PROVIDE(__ctors_start__ = .); KEEP (*(SORT(.init_array.*))) @@ -59,8 +49,6 @@ SECTIONS . = ALIGN(4); *components*drivers**.o (.text*) *components.o (.text*) - *idle.o (.text*) - *object.o (.text*) } > ram1 AT > flash .comm __comm_vma : { @@ -69,7 +57,9 @@ SECTIONS EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o *romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o *letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o - *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o) *(.text) + *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o + *fixdfsi.o *addsf3.o *divsf3.o *eqsf2.o *gesf2.o *float*.o + *lesf2.o *mulsf3.o *subsf3.o *fixsfsi.o *fixunssfsi.o) *(.text) *finsh*shell.o (.text*) *(.text.unlikely) *(.text.startup) @@ -108,6 +98,17 @@ SECTIONS } > heap .flash : { + + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + *(.text*) *(.rodata*) *(.srodata*) diff --git a/bsp/bluetrum/libraries/hal_drivers/SConscript b/bsp/bluetrum/libraries/hal_drivers/SConscript index 7ec2f48a81df8f3f3b6b2be564ff1790d8a0766d..8544a2aef45ffe5855c84483c2e1cf4456b4108e 100644 --- a/bsp/bluetrum/libraries/hal_drivers/SConscript +++ b/bsp/bluetrum/libraries/hal_drivers/SConscript @@ -28,6 +28,12 @@ if GetDepend('RT_USING_HWTIMER'): if GetDepend('RT_USING_PWM'): src += ['drv_pwm.c'] +if GetDepend('RT_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('RT_USING_ADC'): + src += ['drv_adc.c'] + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) objs = [group] diff --git a/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h b/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h new file mode 100644 index 0000000000000000000000000000000000000000..9fc2df3a8a6118730ef08c984b9e63add8315e6b --- /dev/null +++ b/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2020-2021, Bluetrum Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-01 greedyhao first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC0 +#ifndef ADC0_CONFIG +#define ADC0_CONFIG \ + { \ + .adc_dat_handle = (hal_sfr_t)&SADCDAT0, \ + .name = "adc0", \ + } +#endif /* ADC0_CONFIG */ +#endif /* BSP_USING_ADC0 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_adc.c b/bsp/bluetrum/libraries/hal_drivers/drv_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..5f300ebe58c0fb14989edb5372b9bf0179c6bc82 --- /dev/null +++ b/bsp/bluetrum/libraries/hal_drivers/drv_adc.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2020-2021, Bluetrum Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-01 greedyhao first version + */ + +#include "drv_gpio.h" + +#ifdef BSP_USING_ADC0 + +#include "adc_config.h" + +// #define DRV_DEBUG +#define LOG_TAG "drv.adc" +#include + +struct ab32_adc +{ + struct rt_adc_device ab32_adc_device; + hal_sfr_t adc_dat_handle; + char *name; +}; + +enum +{ +#ifdef BSP_USING_ADC0 + ADC0_INDEX, +#endif + + ADC_INDEX_END +}; + +static struct ab32_adc ab32_adc_obj[] = +{ +#ifdef BSP_USING_ADC0 + ADC0_CONFIG, +#endif +}; + +static rt_err_t ab32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + RT_ASSERT(device != RT_NULL); + + hal_adc_enable(enabled); + + return RT_EOK; +} + +static rt_uint32_t ab32_adc_get_channel(rt_uint32_t channel) +{ + rt_uint32_t ab32_channel = 0; + + switch (channel) + { + case 0: + ab32_channel = ADC_CHANNEL_0; + break; + case 1: + ab32_channel = ADC_CHANNEL_1; + break; + case 2: + ab32_channel = ADC_CHANNEL_2; + break; + case 3: + ab32_channel = ADC_CHANNEL_3; + break; + case 4: + ab32_channel = ADC_CHANNEL_4; + break; + case 5: + ab32_channel = ADC_CHANNEL_5; + break; + case 6: + ab32_channel = ADC_CHANNEL_6; + break; + case 7: + ab32_channel = ADC_CHANNEL_7; + break; + case 8: + ab32_channel = ADC_CHANNEL_8; + break; + case 9: + ab32_channel = ADC_CHANNEL_9; + break; + case 10: + ab32_channel = ADC_CHANNEL_10; + break; + case 11: + ab32_channel = ADC_CHANNEL_11; + break; + case 12: + ab32_channel = ADC_CHANNEL_12; + break; + case 13: + ab32_channel = ADC_CHANNEL_13; + break; + case 14: + ab32_channel = ADC_CHANNEL_14; + break; + case 15: + ab32_channel = ADC_CHANNEL_15; + break; + } + + return ab32_channel; +} + +static rt_err_t ab32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + hal_sfr_t ab32_adc_handler; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + ab32_adc_handler = device->parent.user_data; + + hal_adc_start(ab32_adc_get_channel(channel)); + hal_adc_poll_for_conversion(1000); + + *value = ab32_adc_handler[channel]; + + return RT_EOK; +} + +static const struct rt_adc_ops _adc_ops = +{ + .enabled = ab32_adc_enabled, + .convert = ab32_get_adc_value, +}; + +static int ab32_adc_init(void) +{ + int result = RT_EOK; + int i = 0; + + if (ADC_INDEX_END == 0) { + return result; + } + + CLKCON0 |= BIT(28); // enable adc clock + + for (i = 0; i < sizeof(ab32_adc_obj) / sizeof(ab32_adc_obj[0]); i++) { + if (rt_hw_adc_register(&ab32_adc_obj[i].ab32_adc_device, ab32_adc_obj[i].name, &_adc_ops, (const void *)ab32_adc_obj[i].adc_dat_handle) == RT_EOK) + { + LOG_D("%s init success", ab32_adc_obj[i].name); + } + else + { + LOG_E("%s register failed", ab32_adc_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(ab32_adc_init); + +#endif + diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..9e84490158e4d1d965ad65357e2c5ce5b8668c47 --- /dev/null +++ b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2020-2021, Bluetrum Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-28 greedyhao first version + */ + +#include "board.h" +#include + +#ifdef BSP_USING_ONCHIP_RTC + +//#define DRV_DEBUG +#define LOG_TAG "drv.rtc" +#include + +static struct rt_device rtc; + +/************** HAL Start *******************/ +#define IRTC_ENTER_CRITICAL() uint32_t cpu_ie = PICCON & BIT(0); PICCONCLR = BIT(0); +#define IRTC_EXIT_CRITICAL() PICCON |= cpu_ie + +uint8_t get_weekday(struct tm *const _tm) +{ + uint8_t weekday; + time_t secs = mktime(_tm); + + weekday = (secs / 86400 + 4) % 7; + return weekday; +} + +void irtc_write(uint32_t cmd) +{ + RTCDAT = cmd; + while (RTCCON & RTC_CON_TRANS_DONE); +} + +uint8_t irtc_read(void) +{ + RTCDAT = 0x00; + while (RTCCON & RTC_CON_TRANS_DONE); + return (uint8_t)RTCDAT; +} + +void irtc_time_write(uint32_t cmd, uint32_t dat) +{ + IRTC_ENTER_CRITICAL(); + RTCCON |= RTC_CON_CHIP_SELECT; + irtc_write(cmd | RTC_WR); + irtc_write((uint8_t)(dat >> 24)); + irtc_write((uint8_t)(dat >> 16)); + irtc_write((uint8_t)(dat >> 8)); + irtc_write((uint8_t)(dat >> 0)); + RTCCON &= ~RTC_CON_CHIP_SELECT; + IRTC_EXIT_CRITICAL(); +} + +uint32_t irtc_time_read(uint32_t cmd) +{ + uint32_t rd_val; + IRTC_ENTER_CRITICAL(); + RTCCON |= RTC_CON_CHIP_SELECT; + irtc_write(cmd | RTC_RD); + *((uint8_t *)&rd_val + 3) = irtc_read(); + *((uint8_t *)&rd_val + 2) = irtc_read(); + *((uint8_t *)&rd_val + 1) = irtc_read(); + *((uint8_t *)&rd_val + 0) = irtc_read(); + RTCCON &= ~RTC_CON_CHIP_SELECT; + IRTC_EXIT_CRITICAL(); + return rd_val; +} + +void irtc_sfr_write(uint32_t cmd, uint8_t dat) +{ + IRTC_ENTER_CRITICAL(); + RTCCON |= RTC_CON_CHIP_SELECT; + irtc_write(cmd | RTC_WR); + irtc_write(dat); + RTCCON &= ~RTC_CON_CHIP_SELECT; + IRTC_EXIT_CRITICAL(); +} + +uint8_t irtc_sfr_read(uint32_t cmd) +{ + uint8_t rd_val; + IRTC_ENTER_CRITICAL(); + RTCCON |= RTC_CON_CHIP_SELECT; + irtc_write(cmd | RTC_RD); + rd_val = irtc_read(); + RTCCON &= ~RTC_CON_CHIP_SELECT; + IRTC_EXIT_CRITICAL(); +} + +void hal_rtc_init(void) +{ + time_t sec = 0; + struct tm tm_new = {0}; + + uint8_t temp = irtc_sfr_read(RTCCON0_CMD); + temp &= ~RTC_CON0_XOSC32K_ENABLE; + temp |= RTC_CON0_EXTERNAL_32K; + irtc_sfr_write(RTCCON0_CMD, temp); + temp = irtc_sfr_read(RTCCON2_CMD); + irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT); + + temp = irtc_sfr_read(RTCCON0_CMD); + if (temp & BIT(7)) { + temp &= ~BIT(7); + irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */ + } + + tm_new.tm_mday = 29; + tm_new.tm_mon = 1 - 1; + tm_new.tm_year = 2021 - 1900; + sec = mktime(&tm_new); + + irtc_time_write(RTCCNT_CMD, sec); +} +/************** HAL End *******************/ + +static time_t get_rtc_timestamp(void) +{ + time_t sec = 0; + + sec = irtc_time_read(RTCCNT_CMD); + LOG_D("get rtc time."); + return sec; +} + +static rt_err_t set_rtc_time_stamp(time_t time_stamp) +{ + irtc_time_write(RTCCNT_CMD, time_stamp); + + return RT_EOK; +} + +static void rt_rtc_init(void) +{ + hal_rtc_init(); +} + +static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + RT_ASSERT(dev != RT_NULL); + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(rt_uint32_t *)args = get_rtc_timestamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + if (set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; + } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); + break; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops rtc_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + rt_rtc_control +}; +#endif + +static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag) +{ + RT_ASSERT(device != RT_NULL); + + rt_rtc_init(); +#ifdef RT_USING_DEVICE_OPS + device->ops = &rtc_ops; +#else + device->init = RT_NULL; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = rt_rtc_control; +#endif + device->type = RT_Device_Class_RTC; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->user_data = RT_NULL; + + /* register a character device */ + return rt_device_register(device, name, flag); +} + +int rt_hw_rtc_init(void) +{ + rt_err_t result; + result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + if (result != RT_EOK) + { + LOG_E("rtc register err code: %d", result); + return result; + } + LOG_D("rtc init success"); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_ONCHIP_RTC */ diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript index e7227244bb60ecffb40476cc8f1667d6d71ec9b9..e30f2160939f94b049bde43e2cedb99906af7396 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript @@ -11,7 +11,6 @@ Import('rtconfig') PKGNAME = "ab32vg1_hal" VERSION = "v1.0.0" DEPENDS = [""] -#DEPENDS = ["PKG_USING_RW007"] #--------------------------------------------------------------------------------- # Compile the configuration @@ -35,6 +34,7 @@ DEPENDS = [""] # # LINKFLAGS: Link options #--------------------------------------------------------------------------------- +CWD = GetCurrentDir() SOURCES = Glob("./source/*.c") LOCAL_CPPPATH = [] @@ -48,8 +48,8 @@ ASFLAGS = "" CPPDEFINES = [] LOCAL_CPPDEFINES = [] -LIBS = [] -LIBPATH = [] +LIBS = ['hal'] +LIBPATH = [CWD] LINKFLAGS = "" diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..038355864695e38682be929d414eeea4d7f8ad7e --- /dev/null +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2020-2021, BLUETRUM Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef AB32VG1_HAL_ADC_H__ +#define AB32VG1_HAL_ADC_H__ + +#include "ab32vg1_hal_def.h" + +/** + * @defgroup ADC_channels + * @{ + */ +#define ADC_CHANNEL_0 (1u << 0) +#define ADC_CHANNEL_1 (1u << 1) +#define ADC_CHANNEL_2 (1u << 2) +#define ADC_CHANNEL_3 (1u << 3) +#define ADC_CHANNEL_4 (1u << 4) +#define ADC_CHANNEL_5 (1u << 5) +#define ADC_CHANNEL_6 (1u << 6) +#define ADC_CHANNEL_7 (1u << 7) +#define ADC_CHANNEL_8 (1u << 8) +#define ADC_CHANNEL_9 (1u << 9) +#define ADC_CHANNEL_10 (1u << 10) +#define ADC_CHANNEL_11 (1u << 11) +#define ADC_CHANNEL_12 (1u << 12) +#define ADC_CHANNEL_13 (1u << 13) +#define ADC_CHANNEL_14 (1u << 14) +#define ADC_CHANNEL_15 (1u << 15) +/** + * @} + * + */ + +/** + * @brief Enable ADC + * + * @param enable + */ +void hal_adc_enable(uint8_t enable); + +/** + * @brief Starts conversion of the channels + * + * @param channel @ref ADC_channels + */ +void hal_adc_start(uint32_t channel); + +/** + * @brief Poll for conversion complete + * + * @param timeout Timeout value in millisecond + * @return hal_error_t + */ +hal_error_t hal_adc_poll_for_conversion(uint32_t timeout); + +#endif diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_conf.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_conf.h index cf1a7cb763843481ca2e10a61e04c56406d4bf14..da64a2fced0059c51d4cca644025b2495f1f3aa7 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_conf.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_conf.h @@ -15,6 +15,8 @@ // #define HAL_DAC_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLE +#define HAL_ADC_MODULE_ENABLE /* Includes */ #ifdef HAL_GPIO_MODULE_ENABLED @@ -45,6 +47,14 @@ #include "ab32vg1_hal_tim.h" #endif +#ifdef HAL_RTC_MODULE_ENABLE +#include "ab32vg1_hal_rtc.h" +#endif + +#ifdef HAL_ADC_MODULE_ENABLE +#include "ab32vg1_hal_adc.h" +#endif + #include #endif diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..6c128567b59168a140f62788bf65b1cc7206cf06 --- /dev/null +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020-2020, BLUETRUM Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef AB32VG1_HAL_RTC_H__ +#define AB32VG1_HAL_RTC_H__ + +#define RTC_BASE ((hal_sfr_t)&RTCCON) + +enum +{ + RTCxCON, + RTCxDAT, + RTCxCPND = 3, +}; + +// RTCCON +#define RTC_CON_VUSB_OLINE (0x1u << 20) /*!< VUSB online state */ +#define RTC_CON_WK_PIN_STATE (0x1u << 19) /*!< RTC wakeup pin state */ +#define RTC_CON_1S_PEND (0x1u << 18) /*!< RTC 1s pending */ +#define RTC_CON_ALM_PEND (0x1u << 17) /*!< RTC alarm pending */ +#define RTC_CON_TRANS_DONE (0x1u << 16) /*!< RTC trans done */ +#define RTC_CON_ALM_WK_ENABLE (0x1u << 8) /*!< RTC alarm wakeup enable */ +#define RTC_CON_1S_WK_ENABLE (0x1u << 7) /*!< RTC 1s wakeup enable */ +#define RTC_CON_VUSB_RST_ENABLE (0x1u << 6) /*!< VUSB insert reset system enable */ +#define RTC_CON_WK_RST_ENABLE (0x1u << 5) /*!< RTC wakeup power down mode reset \ + system enable */ +#define RTC_CON_ALM_INTERRUPT (0x1u << 4) /*!< RTC alarm interrupt enable */ +#define RTC_CON_1S_INTERRUPT (0x1u << 3) /*!< RTC 1s interrupt enable */ +#define RTC_CON_BAUD_SELECT (0x3u << 1) /*!< Increase clock selection */ +#define RTC_CON_CHIP_SELECT (0x1u << 0) /*!< RTC chip select */ + +// RTCCON0 +#define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */ +#define RTC_CON0_EXTERNAL_32K (0x01u << 6) /*!< External 32K select */ +#define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */ +#define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */ +#define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */ +#define RTC_CON0_LVD_ENABLE (0x01u << 2) /*!< LVD enbale */ +#define RTC_CON0_XOSC32K_ENABLE (0x01u << 1) /*!< XOSC32K enable */ +#define RTC_CON0_RCOSC_ENABLE (0x01u << 0) /*!< RCOSC enable */ + +// RTCCON2 +#define RTC_CON2_32K_SELECT (0x01u << 7) /*!< 32K osc select */ + +#endif diff --git a/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h b/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h index b5ab98aace0124d21cbb33bfa891b0ec724cf8cb..9830369288a8a42d94fd7b042ebd2d96bc54d105 100644 --- a/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h +++ b/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h @@ -14,23 +14,23 @@ /*!< Interrupt Number Definition */ typedef enum { - IRQ_SW_VECTOR = 2, - IRQ_TMR0_VECTOR = 3, - IRQ_TMR1_VECTOR = 4, - IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */ - IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */ - IRQ_USB_VECTOR = 7, - IRQ_SD_VECTOR = 8, - IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */ - IRQ_SDADC_VECTOR = 10, - IRQ_AUDEC_VECTOR = 11, /*!< Audio codec, SBC encode and AEC FFT Interrupt */ - IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */ - IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */ - IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */ - IRQ_HSUART_VECTOR = 15, - IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */ - IRQ_I2S_VECTOR = 17, - IRQ_TOTAL_NUM = 23, + IRQ_SW_VECTOR = 2, + IRQ_TMR0_VECTOR = 3, + IRQ_TMR1_VECTOR = 4, + IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */ + IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */ + IRQ_USB_VECTOR = 7, + IRQ_SD_VECTOR = 8, + IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */ + IRQ_SDADC_VECTOR = 10, + IRQ_AUDEC_VECTOR = 11, /*!< Audio codec, SBC encode and AEC FFT Interrupt */ + IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */ + IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */ + IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */ + IRQ_HSUART_VECTOR = 15, + IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */ + IRQ_I2S_VECTOR = 17, + IRQ_TOTAL_NUM = 23, } irq_type; #endif // __ASSEMBLER__