diff --git a/bsp/qemu-vexpress-a9/SConstruct b/bsp/qemu-vexpress-a9/SConstruct
index 61af0ee6200bab2f34325d8b53e5a5ebd6cd34d5..638311d6977e1b7226d942d76d63626627c7b314 100644
--- a/bsp/qemu-vexpress-a9/SConstruct
+++ b/bsp/qemu-vexpress-a9/SConstruct
@@ -19,6 +19,7 @@ env = Environment(tools = ['mingw'],
     AR   = rtconfig.AR, ARFLAGS = '-rc',
     LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
 
 Export('RTT_ROOT')
 Export('rtconfig')
diff --git a/bsp/qemu-vexpress-gemini/SConstruct b/bsp/qemu-vexpress-gemini/SConstruct
index 6fa1553e4d902102041dad296128622489438153..765abd555aa166c8342404431c3dff303ea05a4b 100644
--- a/bsp/qemu-vexpress-gemini/SConstruct
+++ b/bsp/qemu-vexpress-gemini/SConstruct
@@ -13,11 +13,12 @@ from building import *
 TARGET = 'rtthread-vexpress.' + rtconfig.TARGET_EXT
 
 env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
 
 Export('RTT_ROOT')
 Export('rtconfig')
diff --git a/bsp/realview-a8/SConstruct b/bsp/realview-a8/SConstruct
index 67ae413023f3d7364236899c70dea8cecfd431f9..0885dbfc0e1d145221c2cbaf341e136123c124a9 100644
--- a/bsp/realview-a8/SConstruct
+++ b/bsp/realview-a8/SConstruct
@@ -13,11 +13,12 @@ from building import *
 TARGET = 'rtthread-realview.' + rtconfig.TARGET_EXT
 
 env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
 
 Export('RTT_ROOT')
 Export('rtconfig')
diff --git a/libcpu/SConscript b/libcpu/SConscript
index 568da67cc97929311bd5b5465fe89616444a7f95..774e7f4043f2ef28c194d2aa63604437c76e6329 100644
--- a/libcpu/SConscript
+++ b/libcpu/SConscript
@@ -1,38 +1,15 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-arch = rtconfig.ARCH
-comm = rtconfig.ARCH + '/common'
-path = rtconfig.ARCH + '/' + rtconfig.CPU
-src  = []
-ASFLAGS = ''
-
-# The set of source files associated with this SConscript file.
-if rtconfig.PLATFORM == 'armcc':
-    src += Glob(path + '/*.c') + Glob(path + '/*_rvds.S') 
-    src += Glob(comm + '/*.c') + Glob(comm + '/*_rvds.S')
-
-if rtconfig.PLATFORM == 'gcc':
-    src += Glob(path + '/*_init.S')
-    src += Glob(path + '/*.c') + Glob(path + '/*_gcc.S') 
-    src += Glob(comm + '/*.c') + Glob(comm + '/*_gcc.S')
+# RT-Thread building script for bridge
 
-if rtconfig.PLATFORM == 'iar':
-    src += Glob(path + '/*.c') + Glob(path + '/*_iar.S')
-    src += Glob(comm + '/*.c') + Glob(comm + '/*_iar.S')
-
-if rtconfig.PLATFORM == 'cl':
-    src = Glob(path + '/*.c')
-
-if rtconfig.PLATFORM == 'mingw':
-    src = Glob(path + '/*.c')
+import os
+from building import *
 
-if rtconfig.PLATFORM == 'armcc' and rtconfig.ARCH == 'arm' and rtconfig.CPU == 'arm926':
-    ASFLAGS = ' --cpreproc'
+Import('rtconfig')
 
-CPPPATH = [RTT_ROOT + '/libcpu/' + arch + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + arch + '/common']
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
 
-group = DefineGroup(rtconfig.CPU.upper(), src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+if rtconfig.ARCH in list:
+    group = group + SConscript(os.path.join(cwd, rtconfig.ARCH, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/arm/AT91SAM7S/SConscript b/libcpu/arm/AT91SAM7S/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/AT91SAM7S/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/AT91SAM7S/context_rvds.S b/libcpu/arm/AT91SAM7S/context_rvds.S
index 641ec7a6b1a18b5d8fff4b927e2ad5549ca65f01..78e3df97369b193a016c3878e737aeae9b62e4c6 100644
--- a/libcpu/arm/AT91SAM7S/context_rvds.S
+++ b/libcpu/arm/AT91SAM7S/context_rvds.S
@@ -1,43 +1,39 @@
-;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date           Author       Notes
-; * 2009-01-20     Bernard      first version
-; */
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-20     Bernard      first version
+ */
 
 NOINT	EQU		0xc0	; disable interrupt in psr
 
-	AREA |.text|, CODE, READONLY, ALIGN=2
-	ARM
-	REQUIRE8
-	PRESERVE8
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    ARM
+    REQUIRE8
+    PRESERVE8
 
 ;/*
 ; * rt_base_t rt_hw_interrupt_disable();
 ; */
 rt_hw_interrupt_disable	PROC
-	EXPORT rt_hw_interrupt_disable
-	MRS r0, cpsr
-	ORR r1, r0, #NOINT
-	MSR cpsr_c, r1
-	BX	lr
-	ENDP
+    EXPORT rt_hw_interrupt_disable
+    MRS r0, cpsr
+    ORR r1, r0, #NOINT
+    MSR cpsr_c, r1
+    BX	lr
+    ENDP
 
 ;/*
 ; * void rt_hw_interrupt_enable(rt_base_t level);
 ; */
 rt_hw_interrupt_enable	PROC
-	EXPORT rt_hw_interrupt_enable
-	MSR cpsr_c, r0
-	BX	lr
-	ENDP
+    EXPORT rt_hw_interrupt_enable
+    MSR cpsr_c, r0
+    BX	lr
+    ENDP
 
 ;/*
 ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
@@ -45,63 +41,63 @@ rt_hw_interrupt_enable	PROC
 ; * r1 --> to
 ; */
 rt_hw_context_switch	PROC
-	EXPORT rt_hw_context_switch
-	STMFD	sp!, {lr}			; push pc (lr should be pushed in place of PC)
-	STMFD	sp!, {r0-r12, lr}	; push lr & register file
+    EXPORT rt_hw_context_switch
+    STMFD	sp!, {lr}			; push pc (lr should be pushed in place of PC)
+    STMFD	sp!, {r0-r12, lr}	; push lr & register file
 
-	MRS		r4, cpsr
-	STMFD	sp!, {r4}			; push cpsr
-	MRS		r4, spsr
-	STMFD	sp!, {r4}			; push spsr
+    MRS		r4, cpsr
+    STMFD	sp!, {r4}			; push cpsr
+    MRS		r4, spsr
+    STMFD	sp!, {r4}			; push spsr
 
-	STR	sp, [r0]				; store sp in preempted tasks TCB
-	LDR	sp, [r1]				; get new task stack pointer
+    STR	sp, [r0]				; store sp in preempted tasks TCB
+    LDR	sp, [r1]				; get new task stack pointer
 
-	LDMFD	sp!, {r4}			; pop new task spsr
-	MSR	spsr_cxsf, r4
-	LDMFD	sp!, {r4}			; pop new task cpsr
-	MSR	cpsr_cxsf, r4
+    LDMFD	sp!, {r4}			; pop new task spsr
+    MSR	spsr_cxsf, r4
+    LDMFD	sp!, {r4}			; pop new task cpsr
+    MSR	cpsr_cxsf, r4
 
-	LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
-	ENDP
+    LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
+    ENDP
 
 ;/*
 ; * void rt_hw_context_switch_to(rt_uint32 to);
 ; * r0 --> to
 ; */
 rt_hw_context_switch_to	PROC
-	EXPORT rt_hw_context_switch_to
-	LDR	sp, [r0]				; get new task stack pointer
+    EXPORT rt_hw_context_switch_to
+    LDR	sp, [r0]				; get new task stack pointer
 
-	LDMFD	sp!, {r4}			; pop new task spsr
-	MSR	spsr_cxsf, r4
-	LDMFD	sp!, {r4}			; pop new task cpsr
-	MSR	cpsr_cxsf, r4
+    LDMFD	sp!, {r4}			; pop new task spsr
+    MSR	spsr_cxsf, r4
+    LDMFD	sp!, {r4}			; pop new task cpsr
+    MSR	cpsr_cxsf, r4
 
-	LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
-	ENDP
+    LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
+    ENDP
 
 ;/*
 ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
 ; */
-	IMPORT rt_thread_switch_interrupt_flag
-	IMPORT rt_interrupt_from_thread
-	IMPORT rt_interrupt_to_thread
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
 
 rt_hw_context_switch_interrupt	PROC
-	EXPORT rt_hw_context_switch_interrupt
-	LDR r2, =rt_thread_switch_interrupt_flag
-	LDR r3, [r2]
-	CMP r3, #1
-	BEQ _reswitch
-	MOV r3, #1							; set rt_thread_switch_interrupt_flag to 1
-	STR r3, [r2]
-	LDR r2, =rt_interrupt_from_thread	; set rt_interrupt_from_thread
-	STR r0, [r2]
+    EXPORT rt_hw_context_switch_interrupt
+    LDR r2, =rt_thread_switch_interrupt_flag
+    LDR r3, [r2]
+    CMP r3, #1
+    BEQ _reswitch
+    MOV r3, #1							; set rt_thread_switch_interrupt_flag to 1
+    STR r3, [r2]
+    LDR r2, =rt_interrupt_from_thread	; set rt_interrupt_from_thread
+    STR r0, [r2]
 _reswitch
-	LDR r2, =rt_interrupt_to_thread		; set rt_interrupt_to_thread
-	STR r1, [r2]
-	BX	lr
-	ENDP
+    LDR r2, =rt_interrupt_to_thread		; set rt_interrupt_to_thread
+    STR r1, [r2]
+    BX	lr
+    ENDP
 
-	END
\ No newline at end of file
+    END
\ No newline at end of file
diff --git a/libcpu/arm/AT91SAM7X/SConscript b/libcpu/arm/AT91SAM7X/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/AT91SAM7X/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/AT91SAM7X/context_rvds.S b/libcpu/arm/AT91SAM7X/context_rvds.S
index 641ec7a6b1a18b5d8fff4b927e2ad5549ca65f01..0d8bf562374334c0417d41c47ac3a98ca19abeb4 100644
--- a/libcpu/arm/AT91SAM7X/context_rvds.S
+++ b/libcpu/arm/AT91SAM7X/context_rvds.S
@@ -1,16 +1,12 @@
-;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date           Author       Notes
-; * 2009-01-20     Bernard      first version
-; */
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-20     Bernard      first version
+ */
 
 NOINT	EQU		0xc0	; disable interrupt in psr
 
diff --git a/libcpu/arm/SConscript b/libcpu/arm/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..36a214327b7407cb4830ddafe26e4f72b65fd1c0
--- /dev/null
+++ b/libcpu/arm/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/arm/am335x/SConscript b/libcpu/arm/am335x/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/am335x/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/arm926/SConscript b/libcpu/arm/arm926/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..00785a135b8cc7c4a02819199706c4cb53c64069
--- /dev/null
+++ b/libcpu/arm/arm926/SConscript
@@ -0,0 +1,25 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+    ASFLAGS = ' --cpreproc'
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/arm/arm926/context_gcc.S b/libcpu/arm/arm926/context_gcc.S
index 5152618d2406d602a6f9e00999a091172e627420..b6b78636790a3b0fdd8b3a828f8c2ec367bad4ea 100644
--- a/libcpu/arm/arm926/context_gcc.S
+++ b/libcpu/arm/arm926/context_gcc.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/arm926/context_iar.S b/libcpu/arm/arm926/context_iar.S
index 14110e52202a27af10a61d96d38a0e25f311e00f..902552734e491ff526d8a4e19d01ac889fde7c1b 100644
--- a/libcpu/arm/arm926/context_iar.S
+++ b/libcpu/arm/arm926/context_iar.S
@@ -1,27 +1,13 @@
-;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
-; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-; *
-; * Change Logs:
-; * Date           Author       Notes
-; * 2011-08-14     weety      copy from mini2440
-; * 2015-04-15     ArdaFu     convert from context_gcc.s
-; */
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-08-14     weety    copy from mini2440
+ * 2015-04-15     ArdaFu     convert from context_gcc.s
+ */
 
 #define NOINT            0xc0
 
diff --git a/libcpu/arm/arm926/context_rvds.S b/libcpu/arm/arm926/context_rvds.S
index 32bd235fef24250252bc1da49e12883fb7c87244..03eff68d4c6fe250baf6deb9580446b4e04a0168 100644
--- a/libcpu/arm/arm926/context_rvds.S
+++ b/libcpu/arm/arm926/context_rvds.S
@@ -1,24 +1,10 @@
 ;/*
-; * file      : context_rvds.s
-; * this file is part of rt-thread rtos
-; * copyright (c) 2006, rt-thread development team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  this program is free software; you can redistribute it and/or modify
-; *  it under the terms of the gnu general public license as published by
-; *  the free software foundation; either version 2 of the license, or
-; *  (at your option) any later version.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
-; *  this program is distributed in the hope that it will be useful,
-; *  but without any warranty; without even the implied warranty of
-; *  merchantability or fitness for a particular purpose.  see the
-; *  gnu general public license for more details.
-; *
-; *  you should have received a copy of the gnu general public license along
-; *  with this program; if not, write to the free software foundation, inc.,
-; *  51 franklin street, fifth floor, boston, ma 02110-1301 usa.
-; *
-; * change logs:
-; * date           author       notes
+; * Change Logs:
+; * Date           Author       Notes
 ; * 2011-08-14     weety    copy from mini2440
 ; */
 
diff --git a/libcpu/arm/arm926/start_iar.S b/libcpu/arm/arm926/start_iar.S
index 880f2d9706d0e72865eda7b151b6c28a5ca76f30..080acd57b6bce464b71c1a1ec0e270040394b38b 100644
--- a/libcpu/arm/arm926/start_iar.S
+++ b/libcpu/arm/arm926/start_iar.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : start.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/arm926/start_rvds.S b/libcpu/arm/arm926/start_rvds.S
index aca0e4577fb7915102cc7cd322b03864a1ada2c2..fc7e84ffaa4ab98bc5799e916094f7de24cafef3 100644
--- a/libcpu/arm/arm926/start_rvds.S
+++ b/libcpu/arm/arm926/start_rvds.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : start_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
@@ -25,7 +11,6 @@
 ; * 2015-06-04     aozima     Align stack address to 8 byte.
 ; */
 
-;#include "rt_low_level_init.h"
 UND_STK_SIZE EQU 512
 SVC_STK_SIZE EQU 4096
 ABT_STK_SIZE EQU 512
@@ -35,25 +20,7 @@ SYS_STK_SIZE EQU 512
 Heap_Size    EQU 512
 
 S_FRAME_SIZE    EQU     (18*4)   ;72
-;S_SPSR          EQU     (17*4)   ;SPSR
-;S_CPSR          EQU     (16*4)   ;CPSR
 S_PC            EQU     (15*4)   ;R15
-;S_LR            EQU     (14*4)   ;R14
-;S_SP            EQU     (13*4)   ;R13
-
-;S_IP            EQU     (12*4)   ;R12
-;S_FP            EQU     (11*4)   ;R11
-;S_R10           EQU     (10*4)
-;S_R9            EQU     (9*4)
-;S_R8            EQU     (8*4)
-;S_R7            EQU     (7*4)
-;S_R6            EQU     (6*4)
-;S_R5            EQU     (5*4)
-;S_R4            EQU     (4*4)
-;S_R3            EQU     (3*4)
-;S_R2            EQU     (2*4)
-;S_R1            EQU     (1*4)
-;S_R0            EQU     (0*4)
 
 MODE_USR        EQU     0X10
 MODE_FIQ        EQU     0X11
diff --git a/libcpu/arm/armv6/SConscript b/libcpu/arm/armv6/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/armv6/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/common/SConscript b/libcpu/arm/common/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/common/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c
index f61c69ef013da9ce100c9563b842c877d7130af2..4fc87b20d14642c3c64ff6c74f8b381cf6eaa310 100644
--- a/libcpu/arm/common/backtrace.c
+++ b/libcpu/arm/common/backtrace.c
@@ -13,51 +13,51 @@
 #ifdef __GNUC__
 /*
 -->High Address,Stack Top
-PC<-----|
-LR	 	 |
-IP	 	 |
-FP	 	 |
-......		 |
-PC<-|	 |
-LR	 |	 |
-IP	 |	 |
+PC<------|
+LR       |
+IP       |
+FP       |
+......   |
+PC <-|   |
+LR   |   |
+IP   |   |
 FP---|-- |
-......	 |
-PC	 |
-LR	 |
-IP 	 |
+......   |
+PC       |
+LR       |
+IP       |
 FP---
 -->Low Address,Stack Bottom
 */
 void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
 {
-	rt_uint32_t i, pc, func_entry;
+    rt_uint32_t i, pc, func_entry;
 
-	pc = *fp;
-	rt_kprintf("[0x%x]\n", pc-0xC);
+    pc = *fp;
+    rt_kprintf("[0x%x]\n", pc-0xC);
 
-	for(i=0; i<10; i++)
-	{
-		fp = (rt_uint32_t *)*(fp - 3);
-		pc = *fp ;
+    for(i=0; i<10; i++)
+    {
+        fp = (rt_uint32_t *)*(fp - 3);
+        pc = *fp ;
 
-		func_entry = pc - 0xC;
+        func_entry = pc - 0xC;
 
-		if(func_entry <= 0x30000000) break;
+        if(func_entry <= 0x30000000) break;
 
-		if(func_entry == thread_entry)
-		{
-			rt_kprintf("EntryPoint:0x%x\n", func_entry);
+        if(func_entry == thread_entry)
+        {
+            rt_kprintf("EntryPoint:0x%x\n", func_entry);
 
-			break;
-		}
+            break;
+        }
 
-		rt_kprintf("[0x%x]\n", func_entry);
-	}
+        rt_kprintf("[0x%x]\n", func_entry);
+    }
 }
 #else
 void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
 {
-	/* old compiler implementation */
+    /* old compiler implementation */
 }
 #endif
diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/cortex-a/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m0/SConscript b/libcpu/arm/cortex-m0/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/cortex-m0/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S
index 67ea808d8c71b8ba5d4ccac970275e6cc6a6746f..50d378135916b2c85a3be00e87fecbd7fb0d7e23 100644
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S
index bf68592e63e653b1d5919343966feb61daddb8db..fb9ce9b4bfa446c85d4d2cdede1a8b986d580b18 100644
--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m3/SConscript b/libcpu/arm/cortex-m3/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/cortex-m3/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m3/context_iar.S b/libcpu/arm/cortex-m3/context_iar.S
index 95dee8062de16edfa6b29ad9b9d8d60e979b3acb..91645c48b3fedc04939f9daa5c3df3985669572b 100644
--- a/libcpu/arm/cortex-m3/context_iar.S
+++ b/libcpu/arm/cortex-m3/context_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S
index 9a7ff10abefb5b4f3434024a9ba5c851473ebeaa..a2a7f41a27c4d402b6513c53fcda7247e92f9421 100644
--- a/libcpu/arm/cortex-m3/context_rvds.S
+++ b/libcpu/arm/cortex-m3/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m4/SConscript b/libcpu/arm/cortex-m4/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/cortex-m4/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S
index bf707d0d531c31b46aa2f36e191ec008b1d96be4..06b8c7f884354dbe2e78bdb02a3f4900ea826589 100644
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m7/SConscript b/libcpu/arm/cortex-m7/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/cortex-m7/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m7/context_iar.S b/libcpu/arm/cortex-m7/context_iar.S
index bf707d0d531c31b46aa2f36e191ec008b1d96be4..06b8c7f884354dbe2e78bdb02a3f4900ea826589 100644
--- a/libcpu/arm/cortex-m7/context_iar.S
+++ b/libcpu/arm/cortex-m7/context_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m7/context_rvds.S b/libcpu/arm/cortex-m7/context_rvds.S
index 1abe477eab99327c72b51b1f0d3fba84b3ab9543..ea9e9cb8b346f5a59393ae459225fd280bb5488c 100644
--- a/libcpu/arm/cortex-m7/context_rvds.S
+++ b/libcpu/arm/cortex-m7/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-r4/SConscript b/libcpu/arm/cortex-r4/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/cortex-r4/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-r4/context_ccs.asm b/libcpu/arm/cortex-r4/context_ccs.asm
index 2b459f82387b8035e9799687ecf0614962a18a57..9463556743a1f5babf29f8057074600b43d43376 100644
--- a/libcpu/arm/cortex-r4/context_ccs.asm
+++ b/libcpu/arm/cortex-r4/context_ccs.asm
@@ -1,14 +1,10 @@
 ;/*
-; * File      : context_ccs.asm
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
-; * Date       Author       Notes
+; * Date           Author       Notes
 ; * 2009-01-20     Bernard      first version
 ; * 2011-07-22     Bernard      added thumb mode porting
 ; * 2013-05-24     Grissiom     port to CCS
diff --git a/libcpu/arm/dm36x/SConscript b/libcpu/arm/dm36x/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/dm36x/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/dm36x/context_rvds.S b/libcpu/arm/dm36x/context_rvds.S
index 631da833720d111b7c7cbcfbd10199cf69177784..8e0fc4465ba8303e4b4440df45ba459cb4bf4410 100644
--- a/libcpu/arm/dm36x/context_rvds.S
+++ b/libcpu/arm/dm36x/context_rvds.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/lpc214x/SConscript b/libcpu/arm/lpc214x/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/lpc214x/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/lpc214x/context_rvds.S b/libcpu/arm/lpc214x/context_rvds.S
index 762b67d42e6fd3e2b8bb43bad3a7ab96d2f2a83d..47ca31cd1f344391a728a65d93e7c0f6bc96e637 100644
--- a/libcpu/arm/lpc214x/context_rvds.S
+++ b/libcpu/arm/lpc214x/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/lpc24xx/SConscript b/libcpu/arm/lpc24xx/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/lpc24xx/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/lpc24xx/context_rvds.S b/libcpu/arm/lpc24xx/context_rvds.S
index ecd20e4bbe818933206afb1c9bfd9028250745f5..0d9915f4f15f67d051f3d68ce3b2ae2758d0d070 100644
--- a/libcpu/arm/lpc24xx/context_rvds.S
+++ b/libcpu/arm/lpc24xx/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/realview-a8-vmm/SConscript b/libcpu/arm/realview-a8-vmm/SConscript
index 61057c04cc571a7a54781b4ed84f8906c74e2954..9ff30a796b5ca7b75c976f1e694598d125655840 100644
--- a/libcpu/arm/realview-a8-vmm/SConscript
+++ b/libcpu/arm/realview-a8-vmm/SConscript
@@ -1,17 +1,23 @@
-Import('rtconfig')
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src	= Glob('*.c')
+src     = Glob('*.c') + Glob('*.cpp')
 CPPPATH = [cwd]
 
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
 if rtconfig.PLATFORM == 'iar':
-        src += Glob('*_iar.S')
-elif rtconfig.PLATFORM == 'gcc':
-        src += Glob('*_gcc.S')
-elif rtconfig.PLATFORM == 'armcc':
-        src += Glob('*_rvds.S')
+    src += Glob('*_iar.S')
 
-group = DefineGroup('AM335x', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/libcpu/arm/s3c24x0/SConscript b/libcpu/arm/s3c24x0/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/s3c24x0/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/s3c24x0/context_rvds.S b/libcpu/arm/s3c24x0/context_rvds.S
index 54d655afe1d2f6346d29cbaa30ab7d71423b9ecc..9078f6173a8c60f7ee7b0d55d6eca8607bafc332 100644
--- a/libcpu/arm/s3c24x0/context_rvds.S
+++ b/libcpu/arm/s3c24x0/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/s3c44b0/SConscript b/libcpu/arm/s3c44b0/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/s3c44b0/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/s3c44b0/context_rvds.S b/libcpu/arm/s3c44b0/context_rvds.S
index 641ec7a6b1a18b5d8fff4b927e2ad5549ca65f01..27ebf8f5e3ffde66acdd090b167f0f122b50cdc6 100644
--- a/libcpu/arm/s3c44b0/context_rvds.S
+++ b/libcpu/arm/s3c44b0/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/sep4020/SConscript b/libcpu/arm/sep4020/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9ff30a796b5ca7b75c976f1e694598d125655840
--- /dev/null
+++ b/libcpu/arm/sep4020/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/sep4020/context_rvds.S b/libcpu/arm/sep4020/context_rvds.S
index 641ec7a6b1a18b5d8fff4b927e2ad5549ca65f01..27ebf8f5e3ffde66acdd090b167f0f122b50cdc6 100644
--- a/libcpu/arm/sep4020/context_rvds.S
+++ b/libcpu/arm/sep4020/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript
index 2ad51b573e9fb738f85c3c91aebd2e9319d2d60d..9ff30a796b5ca7b75c976f1e694598d125655840 100644
--- a/libcpu/arm/zynq7000/SConscript
+++ b/libcpu/arm/zynq7000/SConscript
@@ -1,17 +1,23 @@
-Import('rtconfig')
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src	= Glob('*.c')
+src     = Glob('*.c') + Glob('*.cpp')
 CPPPATH = [cwd]
 
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
 if rtconfig.PLATFORM == 'iar':
-        src += Glob('*_iar.S')
-elif rtconfig.PLATFORM == 'gcc':
-        src += Glob('*_gcc.S')
-elif rtconfig.PLATFORM == 'armcc':
-        src += Glob('*_rvds.S')
+    src += Glob('*_iar.S')
 
-group = DefineGroup('AM1808', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/libcpu/arm/zynq7000/context_gcc.S b/libcpu/arm/zynq7000/context_gcc.S
index 3dbf3c861dad162330d847b556e2f3e0467a9196..98f98a02446d40d1921b6b1607bf34159a8486a9 100644
--- a/libcpu/arm/zynq7000/context_gcc.S
+++ b/libcpu/arm/zynq7000/context_gcc.S
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, Shanghai Real-Thread Technology Co., Ltd
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-20     Bernard      first version
  */
 
 #define NOINT           0xc0
diff --git a/libcpu/arm/zynq7000/cp15.h b/libcpu/arm/zynq7000/cp15.h
index bd6a23f1b24520240ac07895521fbb497aeabe15..75d81736ab31ab0dfd9bd2287894ef95e0520594 100644
--- a/libcpu/arm/zynq7000/cp15.h
+++ b/libcpu/arm/zynq7000/cp15.h
@@ -1,25 +1,16 @@
-#ifndef __CP15_H__
-#define __CP15_H__
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
+#ifndef __CP15_H__
+#define __CP15_H__
+
 unsigned long rt_cpu_get_smp_id(void);
 
 void rt_cpu_mmu_disable(void);
diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c
index 498446db43934cbcbb5ba54d738431d9a8f05a55..e23a359e6e21804d74fbde4b92ffa82715ebf9ff 100644
--- a/libcpu/arm/zynq7000/gic.c
+++ b/libcpu/arm/zynq7000/gic.c
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
 #include <rtthread.h>
diff --git a/libcpu/arm/zynq7000/gic.h b/libcpu/arm/zynq7000/gic.h
index 4b89538948c97fba46424330e8e17b7b35558603..8fcdf05f6f646c414434bf9549f806a0a450860d 100644
--- a/libcpu/arm/zynq7000/gic.h
+++ b/libcpu/arm/zynq7000/gic.h
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
 #ifndef __GIC_H__
diff --git a/libcpu/arm/zynq7000/interrupt.h b/libcpu/arm/zynq7000/interrupt.h
index 07eafc84e56daceb37d2c374fe30937ab2f8cbf8..da266c42a2d3a23658680ccf388d9fe840ff37eb 100644
--- a/libcpu/arm/zynq7000/interrupt.h
+++ b/libcpu/arm/zynq7000/interrupt.h
@@ -1,25 +1,16 @@
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
 void rt_hw_interrupt_clear(int vector);
 
 #endif /* end of include guard: __INTERRUPT_H__ */
diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c
index 2a58fabe4fa007386153cc00824cbb592e4a9c38..fbdacca10f6c5dd0ad85cbc570ed614f4a140e18 100644
--- a/libcpu/arm/zynq7000/mmu.c
+++ b/libcpu/arm/zynq7000/mmu.c
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
 #include <rtthread.h>
diff --git a/libcpu/arm/zynq7000/trap.c b/libcpu/arm/zynq7000/trap.c
index 9bf58f916c930a51fc8acf1197394e5f3c7d37e8..6243ea82b4a96f07d129a975b63118e9e979a2ee 100644
--- a/libcpu/arm/zynq7000/trap.c
+++ b/libcpu/arm/zynq7000/trap.c
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
 #include <rtthread.h>
diff --git a/libcpu/avr32/SConscript b/libcpu/avr32/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/avr32/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/avr32/uc3/SConscript b/libcpu/avr32/uc3/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/avr32/uc3/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/blackfin/SConscript b/libcpu/blackfin/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/blackfin/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/blackfin/bf53x/SConscript b/libcpu/blackfin/bf53x/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..af9ba4bc8103f5b06f16dc5157d7f41bd2641dd1
--- /dev/null
+++ b/libcpu/blackfin/bf53x/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_vdsp.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/c-sky/SConscript b/libcpu/c-sky/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..36a214327b7407cb4830ddafe26e4f72b65fd1c0
--- /dev/null
+++ b/libcpu/c-sky/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/c-sky/ck802/SConscript b/libcpu/c-sky/ck802/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/c-sky/ck802/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/c-sky/common/SConscript b/libcpu/c-sky/common/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/c-sky/common/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/ia32/SConscript b/libcpu/ia32/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/ia32/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/m16c/SConscript b/libcpu/m16c/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/m16c/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/m16c/m16c62p/SConscript b/libcpu/m16c/m16c62p/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/m16c/m16c62p/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/SConscript b/libcpu/mips/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..36a214327b7407cb4830ddafe26e4f72b65fd1c0
--- /dev/null
+++ b/libcpu/mips/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/mips/common/SConscript b/libcpu/mips/common/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/mips/common/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/common/cache.h b/libcpu/mips/common/cache.h
deleted file mode 100644
index 1c7cf41324a67d25da8df928d8c33f091cf59ae1..0000000000000000000000000000000000000000
--- a/libcpu/mips/common/cache.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Cache operations for the cache instruction.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
- * (C) Copyright 1999 Silicon Graphics, Inc.
- */
-#ifndef __CACHE_H__
-#define __CACHE_H__
-
-
-#define KUSEG           		0x00000000
-#define KSEG0           		0x80000000
-#define KSEG1           		0xa0000000
-#define KSEG2           		0xc0000000
-#define KSEG3           		0xe0000000
-
-/*
- * Cache Operations available on all MIPS processors with R4000-style caches
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Writeback_Inv_D		0x15
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-
-/*
- *The lock state is cleared by executing an Index
-Invalidate, Index Writeback Invalidate, Hit
-Invalidate, or Hit Writeback Invalidate
-operation to the locked line, or via an Index
-Store Tag operation with the lock bit reset in
-the TagLo register.
- */
-#define Fetch_And_Lock_I  		0x1c
-#define Fetch_And_Lock_D  		0x1d
-/*
- * R4000-specific cacheops
- */
-#define Create_Dirty_Excl_D		0x0d
-#define Fill					0x14
-
-/*
- * R4000SC and R4400SC-specific cacheops
- */
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_SD		0x1b
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-/*
- * R5000-specific cacheops
- */
-#define R5K_Page_Invalidate_S	0x17
-
-/*
- * RM7000-specific cacheops
- */
-#define Page_Invalidate_T		0x16
-
-/*
- * R1000-specific cacheops
- *
- * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
- * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
- */
-#define Index_Writeback_Inv_S	0x03
-#define Index_Load_Tag_S		0x07
-#define Index_Store_Tag_S		0x0B
-#define Hit_Invalidate_S		0x13
-#define Cache_Barrier			0x14
-#define Hit_Writeback_Inv_S		0x17
-#define Index_Load_Data_I		0x18
-#define Index_Load_Data_D		0x19
-#define Index_Load_Data_S		0x1b
-#define Index_Store_Data_I		0x1c
-#define Index_Store_Data_D		0x1d
-#define Index_Store_Data_S		0x1f
-
-
-#ifndef __ASSEMBLER__
-
-#ifndef dcache_size
-#define dcache_size	(g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
-#endif
-
-#ifndef icache_size
-#define icache_size	(g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
-#endif
-
-#ifndef cpu_dcache_line_size
-#define cpu_dcache_line_size()	g_mips_core.icache_line_size
-#endif
-
-#ifndef cpu_icache_line_size
-#define cpu_icache_line_size()	g_mips_core.icache_line_size
-#endif
-
-#define cache_op(op, addr)						\
-	__asm__ __volatile__(						\
-	"	.set	noreorder				\n"	\
-	"	.set	mips3\n\t				\n"	\
-	"	cache	%0, %1					\n"	\
-	"	.set	mips0					\n"	\
-	"	.set	reorder"					\
-	:								\
-	: "i" (op), "m" (*(unsigned char *)(addr)))
-
-#define cache16_unroll32(base, op)					\
-	__asm__ __volatile__(						\
-	"	.set noreorder					\n"	\
-	"	.set mips3					\n"	\
-	"	cache %1, 0x000(%0); cache %1, 0x010(%0)	\n"	\
-	"	cache %1, 0x020(%0); cache %1, 0x030(%0)	\n"	\
-	"	cache %1, 0x040(%0); cache %1, 0x050(%0)	\n"	\
-	"	cache %1, 0x060(%0); cache %1, 0x070(%0)	\n"	\
-	"	cache %1, 0x080(%0); cache %1, 0x090(%0)	\n"	\
-	"	cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)	\n"	\
-	"	cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)	\n"	\
-	"	cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)	\n"	\
-	"	cache %1, 0x100(%0); cache %1, 0x110(%0)	\n"	\
-	"	cache %1, 0x120(%0); cache %1, 0x130(%0)	\n"	\
-	"	cache %1, 0x140(%0); cache %1, 0x150(%0)	\n"	\
-	"	cache %1, 0x160(%0); cache %1, 0x170(%0)	\n"	\
-	"	cache %1, 0x180(%0); cache %1, 0x190(%0)	\n"	\
-	"	cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)	\n"	\
-	"	cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)	\n"	\
-	"	cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)	\n"	\
-	"	.set mips0					\n"	\
-	"	.set reorder					\n"	\
-		:							\
-		: "r" (base),						\
-		  "i" (op));
-
-
-static inline void flush_icache_line_indexed(rt_ubase_t addr)
-{
-	cache_op(Index_Invalidate_I, addr);
-}
-
-static inline void flush_dcache_line_indexed(rt_ubase_t addr)
-{
-	cache_op(Index_Writeback_Inv_D, addr);
-}
-
-static inline void flush_icache_line(rt_ubase_t addr)
-{
-	cache_op(Hit_Invalidate_I, addr);
-}
-
-static inline void lock_icache_line(rt_ubase_t addr)
-{
-	cache_op(Fetch_And_Lock_I, addr);
-}
-
-static inline void lock_dcache_line(rt_ubase_t addr)
-{
-	cache_op(Fetch_And_Lock_D, addr);
-}
-
-static inline void flush_dcache_line(rt_ubase_t addr)
-{
-	cache_op(Hit_Writeback_Inv_D, addr);
-}
-
-static inline void invalidate_dcache_line(rt_ubase_t addr)
-{
-	cache_op(Hit_Invalidate_D, addr);
-}
-
-static inline void blast_dcache16(void)
-{
-	rt_ubase_t start = KSEG0;
-	rt_ubase_t end = start + dcache_size;
-	rt_ubase_t addr;
-
-	for (addr = start; addr < end; addr += 0x200)
-		cache16_unroll32(addr, Index_Writeback_Inv_D);
-}
-
-static inline void inv_dcache16(void)
-{
-	rt_ubase_t start = KSEG0;
-	rt_ubase_t end = start + dcache_size;
-	rt_ubase_t addr;
-
-	for (addr = start; addr < end; addr += 0x200)
-		cache16_unroll32(addr, Hit_Invalidate_D);
-}
-
-static inline void blast_icache16(void)
-{
-	rt_ubase_t start = KSEG0;
-	rt_ubase_t end = start + icache_size;
-	rt_ubase_t addr;
-
-	for (addr = start; addr < end; addr += 0x200)
-		cache16_unroll32(addr, Index_Invalidate_I);
-}
-
-
-
-void r4k_cache_init(void);
-void r4k_cache_flush_all(void);
-void r4k_icache_flush_all(void);
-void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
-void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
-void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
-void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
-
-#endif /*end of __ASSEMBLER__ */
-
-#endif /* end of __CACHE_H__ */
diff --git a/libcpu/mips/loongson_1b/SConscript b/libcpu/mips/loongson_1b/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/mips/loongson_1b/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/loongson_1c/SConscript b/libcpu/mips/loongson_1c/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/mips/loongson_1c/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/pic32/SConscript b/libcpu/mips/pic32/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/mips/pic32/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/x1000/SConscript b/libcpu/mips/x1000/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/mips/x1000/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/xburst/SConscript.1 b/libcpu/mips/xburst/SConscript.1
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/mips/xburst/SConscript.1
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/nios/SConscript b/libcpu/nios/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/nios/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/nios/nios_ii/SConscript b/libcpu/nios/nios_ii/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/nios/nios_ii/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/ppc/SConscript b/libcpu/ppc/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..36a214327b7407cb4830ddafe26e4f72b65fd1c0
--- /dev/null
+++ b/libcpu/ppc/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/ppc/common/SConscript b/libcpu/ppc/common/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/ppc/common/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h
index d60e7fdcefe178e2d6771b9ac178960f49251f1d..72ef31bfbcb01a03e69bc6cccb1fcc2cf7b22ac3 100644
--- a/libcpu/ppc/common/ptrace.h
+++ b/libcpu/ppc/common/ptrace.h
@@ -21,20 +21,20 @@
 #define PPC_REG unsigned long
 
 struct pt_regs {
-	PPC_REG gpr[32];
-	PPC_REG nip;
-	PPC_REG msr;
-	PPC_REG orig_gpr3;	/* Used for restarting system calls */
-	PPC_REG ctr;
-	PPC_REG link;
-	PPC_REG xer;
-	PPC_REG ccr;
-	PPC_REG mq;		/* 601 only (not used at present) */
-				    /* Used on APUS to hold IPL value. */
-	PPC_REG trap;		/* Reason for being here */
-	PPC_REG dar;		/* Fault registers */
-	PPC_REG dsisr;
-	PPC_REG result;		/* Result of a system call */
+    PPC_REG gpr[32];
+    PPC_REG nip;
+    PPC_REG msr;
+    PPC_REG orig_gpr3;	/* Used for restarting system calls */
+    PPC_REG ctr;
+    PPC_REG link;
+    PPC_REG xer;
+    PPC_REG ccr;
+    PPC_REG mq;		/* 601 only (not used at present) */
+                    /* Used on APUS to hold IPL value. */
+    PPC_REG trap;		/* Reason for being here */
+    PPC_REG dar;		/* Fault registers */
+    PPC_REG dsisr;
+    PPC_REG result;		/* Result of a system call */
 }__attribute__((packed)) CELL_STACK_FRAME_t;
 #endif
 
diff --git a/libcpu/ppc/ppc405/SConscript b/libcpu/ppc/ppc405/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/ppc/ppc405/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..36a214327b7407cb4830ddafe26e4f72b65fd1c0
--- /dev/null
+++ b/libcpu/risc-v/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/risc-v/common/SConscript b/libcpu/risc-v/common/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..2f698f530ad89c0fae239df5757292f849de0b2b
--- /dev/null
+++ b/libcpu/risc-v/common/SConscript
@@ -0,0 +1,12 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/e310/SConscript b/libcpu/risc-v/e310/SConscript
index 4e4bc0c3d92e418b5273a713b6ffcd6c2599edac..b0ae20ba0298e00e05eba2ddc73df9424d22ec79 100644
--- a/libcpu/risc-v/e310/SConscript
+++ b/libcpu/risc-v/e310/SConscript
@@ -1,13 +1,14 @@
-Import('rtconfig')
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src     = Glob('*.c')
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
 CPPPATH = [cwd]
+ASFLAGS = ''
 
-if rtconfig.PLATFORM == 'gcc':
-    src += Glob('*_gcc.S')
-
-group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
 
 Return('group')
diff --git a/libcpu/risc-v/k210/SConscript b/libcpu/risc-v/k210/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/risc-v/k210/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/rv32m1/SConscript b/libcpu/risc-v/rv32m1/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/risc-v/rv32m1/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/rx/SConscript b/libcpu/rx/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..e5890498c952fa41aad7f4cfb8a8bddbef2d45e0
--- /dev/null
+++ b/libcpu/rx/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_iar.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/sim/SConscript b/libcpu/sim/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/sim/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/sim/posix/SConscript b/libcpu/sim/posix/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/sim/posix/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/sim/win32/SConscript b/libcpu/sim/win32/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..afab42d47c41041d1d010c87f231d5da83c63ceb
--- /dev/null
+++ b/libcpu/sim/win32/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/ti-dsp/SConscript b/libcpu/ti-dsp/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/ti-dsp/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/ti-dsp/c28x/SConscript b/libcpu/ti-dsp/c28x/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..08b274341be171d5135e2c3449886aa2352930f1
--- /dev/null
+++ b/libcpu/ti-dsp/c28x/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.s')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/unicore32/SConscript b/libcpu/unicore32/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/unicore32/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/unicore32/sep6200/SConscript b/libcpu/unicore32/sep6200/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/unicore32/sep6200/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/v850/70f34/SConscript b/libcpu/v850/70f34/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/v850/70f34/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/v850/SConscript b/libcpu/v850/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/v850/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/xilinx/SConscript b/libcpu/xilinx/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..ebdd1357ee1ee74658f8daad9721f87d0d14b82b
--- /dev/null
+++ b/libcpu/xilinx/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/xilinx/microblaze/SConscript b/libcpu/xilinx/microblaze/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79
--- /dev/null
+++ b/libcpu/xilinx/microblaze/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')