From 2a9a9346395aaebeb4d7c205f87311695e5b87fe Mon Sep 17 00:00:00 2001 From: wuyangyong Date: Thu, 11 Mar 2010 08:37:47 +0000 Subject: [PATCH] stm32 StdPeriph_lib update to version 3.2.0 git-svn-id: https://rt-thread.googlecode.com/svn/trunk@477 bbd45198-f89e-11dd-88c7-29a3b14d5316 --- .../{Core/CM3 => CM3/CoreSupport}/core_cm3.c | 347 ++-- .../CMSIS/CM3/CoreSupport/core_cm3.h | 1818 +++++++++++++++++ .../ST/Release_Notes_for_STM32F10x_CMSIS.html | 204 ++ .../startup/arm/startup_stm32f10x_cl.s | 46 +- .../startup/arm/startup_stm32f10x_hd.s | 182 +- .../startup/arm/startup_stm32f10x_ld.s | 126 +- .../startup/arm/startup_stm32f10x_ld_vl.s | 304 +++ .../startup/arm/startup_stm32f10x_md.s | 130 +- .../startup/arm/startup_stm32f10x_md_vl.s | 315 +++ .../startup/gcc_ride7}/startup_stm32f10x_cl.s | 229 ++- .../startup/gcc_ride7}/startup_stm32f10x_hd.s | 97 +- .../startup/gcc_ride7/startup_stm32f10x_ld.s | 342 ++++ .../gcc_ride7/startup_stm32f10x_ld_vl.s} | 231 ++- .../startup/gcc_ride7/startup_stm32f10x_md.s | 357 ++++ .../gcc_ride7/startup_stm32f10x_md_vl.s} | 226 +- .../startup/iar/startup_stm32f10x_cl.s | 21 +- .../startup/iar/startup_stm32f10x_hd.s | 58 +- .../startup/iar/startup_stm32f10x_ld.s | 21 +- .../startup/iar/startup_stm32f10x_ld_vl.s | 369 ++++ .../startup/iar/startup_stm32f10x_md.s | 21 +- .../startup/iar/startup_stm32f10x_md_vl.s | 394 ++++ .../DeviceSupport/ST/STM32F10x}/stm32f10x.h | 389 +++- .../ST/STM32F10x}/system_stm32f10x.c | 258 ++- .../ST/STM32F10x}/system_stm32f10x.h | 15 +- .../Libraries/CMSIS/CMSIS debug support.htm | 243 +++ .../Libraries/CMSIS/CMSIS_changes.htm | 320 +++ .../Libraries/CMSIS/Core/CM3/core_cm3.h | 1367 ------------- .../{Core => }/Documentation/CMSIS_Core.htm | 300 ++- ..._Notes_for_STM32F10x_StdPeriph_Driver.html | 179 ++ .../STM32F10x_StdPeriph_Driver/inc/misc.h | 8 +- .../inc/stm32f10x_adc.h | 8 +- .../inc/stm32f10x_bkp.h | 8 +- .../inc/stm32f10x_can.h | 8 +- .../inc/stm32f10x_cec.h | 209 ++ .../inc/stm32f10x_crc.h | 8 +- .../inc/stm32f10x_dac.h | 44 +- .../inc/stm32f10x_dbgmcu.h | 15 +- .../inc/stm32f10x_dma.h | 8 +- .../inc/stm32f10x_exti.h | 16 +- .../inc/stm32f10x_flash.h | 8 +- .../inc/stm32f10x_fsmc.h | 8 +- .../inc/stm32f10x_gpio.h | 28 +- .../inc/stm32f10x_i2c.h | 8 +- .../inc/stm32f10x_iwdg.h | 8 +- .../inc/stm32f10x_pwr.h | 8 +- .../inc/stm32f10x_rcc.h | 48 +- .../inc/stm32f10x_rtc.h | 8 +- .../inc/stm32f10x_sdio.h | 8 +- .../inc/stm32f10x_spi.h | 36 +- .../inc/stm32f10x_tim.h | 39 +- .../inc/stm32f10x_usart.h | 12 +- .../inc/stm32f10x_wwdg.h | 8 +- .../STM32F10x_StdPeriph_Driver/src/misc.c | 8 +- .../src/stm32f10x_adc.c | 8 +- .../src/stm32f10x_bkp.c | 8 +- .../src/stm32f10x_can.c | 8 +- .../src/stm32f10x_cec.c | 432 ++++ .../src/stm32f10x_crc.c | 8 +- .../src/stm32f10x_dac.c | 156 +- .../src/stm32f10x_dbgmcu.c | 13 +- .../src/stm32f10x_dma.c | 8 +- .../src/stm32f10x_exti.c | 8 +- .../src/stm32f10x_flash.c | 51 +- .../src/stm32f10x_fsmc.c | 8 +- .../src/stm32f10x_gpio.c | 35 +- .../src/stm32f10x_i2c.c | 40 +- .../src/stm32f10x_iwdg.c | 8 +- .../src/stm32f10x_pwr.c | 13 +- .../src/stm32f10x_rcc.c | 68 +- .../src/stm32f10x_rtc.c | 8 +- .../src/stm32f10x_sdio.c | 8 +- .../src/stm32f10x_spi.c | 8 +- .../src/stm32f10x_tim.c | 151 +- .../src/stm32f10x_usart.c | 103 +- .../src/stm32f10x_wwdg.c | 8 +- bsp/stm32_radio/board.c | 10 +- bsp/stm32_radio/board.h | 2 +- bsp/stm32_radio/project.Uv2 | 12 +- 78 files changed, 7842 insertions(+), 2816 deletions(-) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/CoreSupport}/core_cm3.c (66%) create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32F10x_CMSIS.html rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/startup/arm/startup_stm32f10x_cl.s (88%) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/startup/arm/startup_stm32f10x_hd.s (61%) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/startup/arm/startup_stm32f10x_ld.s (64%) create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/startup/arm/startup_stm32f10x_md.s (65%) create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3/startup/gcc => CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7}/startup_stm32f10x_cl.s (74%) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3/startup/gcc => CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7}/startup_stm32f10x_hd.s (79%) create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3/startup/gcc/startup_stm32f10x_ld.s => CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s} (60%) create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3/startup/gcc/startup_stm32f10x_md.s => CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s} (61%) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/startup/iar/startup_stm32f10x_cl.s (93%) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/startup/iar/startup_stm32f10x_hd.s (89%) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/startup/iar/startup_stm32f10x_ld.s (92%) create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/startup/iar/startup_stm32f10x_md.s (92%) create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/stm32f10x.h (94%) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/system_stm32f10x.c (78%) rename bsp/stm32_radio/Libraries/CMSIS/{Core/CM3 => CM3/DeviceSupport/ST/STM32F10x}/system_stm32f10x.h (69%) create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CMSIS debug support.htm create mode 100644 bsp/stm32_radio/Libraries/CMSIS/CMSIS_changes.htm delete mode 100644 bsp/stm32_radio/Libraries/CMSIS/Core/CM3/core_cm3.h rename bsp/stm32_radio/Libraries/CMSIS/{Core => }/Documentation/CMSIS_Core.htm (78%) create mode 100644 bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes_for_STM32F10x_StdPeriph_Driver.html create mode 100644 bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h create mode 100644 bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/core_cm3.c b/bsp/stm32_radio/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c similarity index 66% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/core_cm3.c rename to bsp/stm32_radio/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c index ea8cb1ac07..56fddc52bf 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/core_cm3.c +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c @@ -1,16 +1,18 @@ -/****************************************************************************** - * @file: core_cm3.c - * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version: V1.20 - * @date: 22. May 2009 - *---------------------------------------------------------------------------- +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 * + * @note * Copyright (C) 2009 ARM Limited. All rights reserved. * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * + * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. @@ -19,39 +21,37 @@ * ******************************************************************************/ - - #include - /* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for armcc */ - #define __INLINE __inline /*!< inline keyword for armcc */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for iarcc */ - #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */ + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for gcc */ - #define __INLINE inline /*!< inline keyword for gcc */ +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #endif +/* ################### Compiler specific Intrinsics ########################### */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ /** * @brief Return the Process Stack Pointer * - * @param none - * @return uint32_t ProcessStackPointer + * @return ProcessStackPointer * * Return the actual process stack pointer */ @@ -64,8 +64,7 @@ __ASM uint32_t __get_PSP(void) /** * @brief Set the Process Stack Pointer * - * @param uint32_t Process Stack Pointer - * @return none + * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register @@ -79,8 +78,7 @@ __ASM void __set_PSP(uint32_t topOfProcStack) /** * @brief Return the Main Stack Pointer * - * @param none - * @return uint32_t Main Stack Pointer + * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register @@ -94,8 +92,7 @@ __ASM uint32_t __get_MSP(void) /** * @brief Set the Main Stack Pointer * - * @param uint32_t Main Stack Pointer - * @return none + * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register @@ -109,8 +106,8 @@ __ASM void __set_MSP(uint32_t mainStackPointer) /** * @brief Reverse byte order in unsigned short value * - * @param uint16_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in unsigned short value */ @@ -123,8 +120,8 @@ __ASM uint32_t __REV16(uint16_t value) /** * @brief Reverse byte order in signed short value with sign extension to integer * - * @param int16_t value to reverse - * @return int32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ @@ -140,9 +137,6 @@ __ASM int32_t __REVSH(int16_t value) /** * @brief Remove the exclusive lock created by ldrex * - * @param none - * @return none - * * Removes the exclusive lock which is created by ldrex. */ __ASM void __CLREX(void) @@ -153,8 +147,7 @@ __ASM void __CLREX(void) /** * @brief Return the Base Priority value * - * @param none - * @return uint32_t BasePriority + * @return BasePriority * * Return the content of the base priority register */ @@ -167,8 +160,7 @@ __ASM uint32_t __get_BASEPRI(void) /** * @brief Set the Base Priority value * - * @param uint32_t BasePriority - * @return none + * @param basePri BasePriority * * Set the base priority register */ @@ -181,11 +173,9 @@ __ASM void __set_BASEPRI(uint32_t basePri) /** * @brief Return the Priority Mask value * - * @param none - * @return uint32_t PriMask + * @return PriMask * - * Return the state of the priority mask bit from the priority mask - * register + * Return state of the priority mask bit from the priority mask register */ __ASM uint32_t __get_PRIMASK(void) { @@ -196,8 +186,7 @@ __ASM uint32_t __get_PRIMASK(void) /** * @brief Set the Priority Mask value * - * @param uint32_t PriMask - * @return none + * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ @@ -210,8 +199,7 @@ __ASM void __set_PRIMASK(uint32_t priMask) /** * @brief Return the Fault Mask value * - * @param none - * @return uint32_t FaultMask + * @return FaultMask * * Return the content of the fault mask register */ @@ -224,8 +212,7 @@ __ASM uint32_t __get_FAULTMASK(void) /** * @brief Set the Fault Mask value * - * @param uint32_t faultMask value - * @return none + * @param faultMask faultMask value * * Set the fault mask register */ @@ -238,12 +225,11 @@ __ASM void __set_FAULTMASK(uint32_t faultMask) /** * @brief Return the Control Register value * - * @param none - * @return uint32_t Control value + * @return Control value * * Return the content of the control register */ -__ASM uint32_t __get_CONTROL(void) +__ASM uint32_t __get_CONTROL(void) { mrs r0, control bx lr @@ -252,8 +238,7 @@ __ASM uint32_t __get_CONTROL(void) /** * @brief Set the Control Register value * - * @param uint32_t Control value - * @return none + * @param control Control value * * Set the control register */ @@ -266,14 +251,15 @@ __ASM void __set_CONTROL(uint32_t control) #endif /* __ARMCC_VERSION */ + #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ #pragma diag_suppress=Pe940 /** * @brief Return the Process Stack Pointer * - * @param none - * @return uint32_t ProcessStackPointer + * @return ProcessStackPointer * * Return the actual process stack pointer */ @@ -286,8 +272,7 @@ uint32_t __get_PSP(void) /** * @brief Set the Process Stack Pointer * - * @param uint32_t Process Stack Pointer - * @return none + * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register @@ -301,8 +286,7 @@ void __set_PSP(uint32_t topOfProcStack) /** * @brief Return the Main Stack Pointer * - * @param none - * @return uint32_t Main Stack Pointer + * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register @@ -316,8 +300,7 @@ uint32_t __get_MSP(void) /** * @brief Set the Main Stack Pointer * - * @param uint32_t Main Stack Pointer - * @return none + * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register @@ -331,8 +314,8 @@ void __set_MSP(uint32_t topOfMainStack) /** * @brief Reverse byte order in unsigned short value * - * @param uint16_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in unsigned short value */ @@ -345,8 +328,8 @@ uint32_t __REV16(uint16_t value) /** * @brief Reverse bit order of value * - * @param uint32_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse bit order of value */ @@ -357,12 +340,12 @@ uint32_t __RBIT(uint32_t value) } /** - * @brief LDR Exclusive + * @brief LDR Exclusive (8 bit) * - * @param uint8_t* address - * @return uint8_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 8 bit values) */ uint8_t __LDREXB(uint8_t *addr) { @@ -371,12 +354,12 @@ uint8_t __LDREXB(uint8_t *addr) } /** - * @brief LDR Exclusive + * @brief LDR Exclusive (16 bit) * - * @param uint16_t* address - * @return uint16_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 16 bit values */ uint16_t __LDREXH(uint16_t *addr) { @@ -385,12 +368,12 @@ uint16_t __LDREXH(uint16_t *addr) } /** - * @brief LDR Exclusive + * @brief LDR Exclusive (32 bit) * - * @param uint32_t* address - * @return uint32_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 32 bit values */ uint32_t __LDREXW(uint32_t *addr) { @@ -399,13 +382,13 @@ uint32_t __LDREXW(uint32_t *addr) } /** - * @brief STR Exclusive + * @brief STR Exclusive (8 bit) * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 8 bit values */ uint32_t __STREXB(uint8_t value, uint8_t *addr) { @@ -414,13 +397,13 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr) } /** - * @brief STR Exclusive + * @brief STR Exclusive (16 bit) * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 16 bit values */ uint32_t __STREXH(uint16_t value, uint16_t *addr) { @@ -429,13 +412,13 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr) } /** - * @brief STR Exclusive + * @brief STR Exclusive (32 bit) * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 32 bit values */ uint32_t __STREXW(uint32_t value, uint32_t *addr) { @@ -447,12 +430,12 @@ uint32_t __STREXW(uint32_t value, uint32_t *addr) #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ /** * @brief Return the Process Stack Pointer * - * @param none - * @return uint32_t ProcessStackPointer + * @return ProcessStackPointer * * Return the actual process stack pointer */ @@ -467,12 +450,10 @@ uint32_t __get_PSP(void) return(result); } - /** * @brief Set the Process Stack Pointer * - * @param uint32_t Process Stack Pointer - * @return none + * @param topOfProcStack Process Stack Pointer * * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register @@ -487,8 +468,7 @@ void __set_PSP(uint32_t topOfProcStack) /** * @brief Return the Main Stack Pointer * - * @param none - * @return uint32_t Main Stack Pointer + * @return Main Stack Pointer * * Return the current value of the MSP (main stack pointer) * Cortex processor register @@ -507,8 +487,7 @@ uint32_t __get_MSP(void) /** * @brief Set the Main Stack Pointer * - * @param uint32_t Main Stack Pointer - * @return none + * @param topOfMainStack Main Stack Pointer * * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register @@ -523,8 +502,7 @@ void __set_MSP(uint32_t topOfMainStack) /** * @brief Return the Base Priority value * - * @param none - * @return uint32_t BasePriority + * @return BasePriority * * Return the content of the base priority register */ @@ -539,8 +517,7 @@ uint32_t __get_BASEPRI(void) /** * @brief Set the Base Priority value * - * @param uint32_t BasePriority - * @return none + * @param basePri BasePriority * * Set the base priority register */ @@ -552,11 +529,9 @@ void __set_BASEPRI(uint32_t value) /** * @brief Return the Priority Mask value * - * @param none - * @return uint32_t PriMask + * @return PriMask * - * Return the state of the priority mask bit from the priority mask - * register + * Return state of the priority mask bit from the priority mask register */ uint32_t __get_PRIMASK(void) { @@ -569,8 +544,7 @@ uint32_t __get_PRIMASK(void) /** * @brief Set the Priority Mask value * - * @param uint32_t PriMask - * @return none + * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ @@ -582,8 +556,7 @@ void __set_PRIMASK(uint32_t priMask) /** * @brief Return the Fault Mask value * - * @param none - * @return uint32_t FaultMask + * @return FaultMask * * Return the content of the fault mask register */ @@ -598,8 +571,7 @@ uint32_t __get_FAULTMASK(void) /** * @brief Set the Fault Mask value * - * @param uint32_t faultMask value - * @return none + * @param faultMask faultMask value * * Set the fault mask register */ @@ -608,11 +580,39 @@ void __set_FAULTMASK(uint32_t faultMask) __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); } +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + /** * @brief Reverse byte order in integer value * - * @param uint32_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in integer value */ @@ -627,8 +627,8 @@ uint32_t __REV(uint32_t value) /** * @brief Reverse byte order in unsigned short value * - * @param uint16_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in unsigned short value */ @@ -643,8 +643,8 @@ uint32_t __REV16(uint16_t value) /** * @brief Reverse byte order in signed short value with sign extension to integer * - * @param int32_t value to reverse - * @return int32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ @@ -659,8 +659,8 @@ int32_t __REVSH(int16_t value) /** * @brief Reverse bit order of value * - * @param uint32_t value to reverse - * @return uint32_t reversed value + * @param value value to reverse + * @return reversed value * * Reverse bit order of value */ @@ -673,12 +673,12 @@ uint32_t __RBIT(uint32_t value) } /** - * @brief LDR Exclusive + * @brief LDR Exclusive (8 bit) * - * @param uint8_t* address - * @return uint8_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 8 bit value */ uint8_t __LDREXB(uint8_t *addr) { @@ -689,12 +689,12 @@ uint8_t __LDREXB(uint8_t *addr) } /** - * @brief LDR Exclusive + * @brief LDR Exclusive (16 bit) * - * @param uint16_t* address - * @return uint16_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 16 bit values */ uint16_t __LDREXH(uint16_t *addr) { @@ -705,12 +705,12 @@ uint16_t __LDREXH(uint16_t *addr) } /** - * @brief LDR Exclusive + * @brief LDR Exclusive (32 bit) * - * @param uint32_t* address - * @return uint32_t value of (*address) + * @param *addr address pointer + * @return value of (*address) * - * Exclusive LDR command + * Exclusive LDR command for 32 bit values */ uint32_t __LDREXW(uint32_t *addr) { @@ -721,13 +721,13 @@ uint32_t __LDREXW(uint32_t *addr) } /** - * @brief STR Exclusive + * @brief STR Exclusive (8 bit) * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 8 bit values */ uint32_t __STREXB(uint8_t value, uint8_t *addr) { @@ -738,13 +738,13 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr) } /** - * @brief STR Exclusive + * @brief STR Exclusive (16 bit) * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 16 bit values */ uint32_t __STREXH(uint16_t value, uint16_t *addr) { @@ -755,13 +755,13 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr) } /** - * @brief STR Exclusive + * @brief STR Exclusive (32 bit) * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed + * @param value value to store + * @param *addr address pointer + * @return successful / failed * - * Exclusive STR command + * Exclusive STR command for 32 bit values */ uint32_t __STREXW(uint32_t value, uint32_t *addr) { @@ -771,34 +771,6 @@ uint32_t __STREXW(uint32_t value, uint32_t *addr) return(result); } -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ /* TASKING carm specific functions */ @@ -810,20 +782,3 @@ void __set_CONTROL(uint32_t control) */ #endif - - - - - - - - - - - - - - - - - diff --git a/bsp/stm32_radio/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h b/bsp/stm32_radio/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h new file mode 100644 index 0000000000..2b6b51a7d5 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32F10x_CMSIS.html b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32F10x_CMSIS.html new file mode 100644 index 0000000000..407e7b6b41 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32F10x_CMSIS.html @@ -0,0 +1,204 @@ + + + + + + + +Release Notes for STM32F10x CMSIS + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F10x CMSIS

+

Copyright 2010 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x CMSIS +update History
    2. +
  2. License
    3. +
+ +

STM32F10x CMSIS +update History

+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
    • +
  • Directory structure updated to be aligned with CMSIS V1.30
    +
    • +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices. 
    • + +
+
    +
  1. CMSIS Core Peripheral Access Layer
+ +
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. + +
+ +
    + +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • +
      +
    • Update +the stm32f10x.h file to support new Value line devices features: CEC +peripheral, new General purpose timers TIM15, TIM16 and TIM17.
      • +
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
      +
      • +
    • HSE_Value, +HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, +HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy +purposes.
      +
      • +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • SystemFrequency variable name changed to SystemCoreClock
      +
      • +
    • Default + SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
      +
      • +
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
      +
      • +
    • Additional function void SystemCoreClockUpdate (void) is provided.
      +
      • +
    +
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • +
      +
    • Add new +startup files for STM32 Low-density Value line devices: + startup_stm32f10x_ld_vl.s
      • +
    • Add new startup +files for STM32 Medium-density Value line devices: + startup_stm32f10x_md_vl.s
      • +
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      +To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
      +
      • +
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
      +
      • +
    + +
+ +
    +
+

License

+

The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

+

THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

+

 

+
+
+

For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_cl.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s similarity index 88% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_cl.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s index 28c8775856..1796d1c40c 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_cl.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s @@ -1,14 +1,15 @@ -;******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_cl.s ;* Author : MCD Application Team -;* Version : V3.1.2 -;* Date : 09/28/2009 +;* Version : V3.2.0 +;* Date : 03/01/2010 ;* Description : STM32F10x Connectivity line devices vector table for RVMDK ;* toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM3 processor is in Thread mode, @@ -57,22 +58,22 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window Watchdog @@ -149,10 +150,13 @@ __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler routine +; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] + IMPORT SystemInit IMPORT __main + LDR R0, =SystemInit + BLX R0 LDR R0, =__main BX R0 ENDP @@ -361,4 +365,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_hd.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s similarity index 61% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_hd.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s index e7f99e2b84..1d7df99b48 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_hd.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s @@ -1,16 +1,17 @@ -;******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_hd.s ;* Author : MCD Application Team -;* Version : V3.1.2 -;* Date : 09/28/2009 +;* Version : V3.2.0 +;* Date : 03/01/2010 ;* Description : STM32F10x High Density Devices vector table for RVMDK ;* toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address -;* - Configure external SRAM mounted on STM3210E-EVAL board -;* to be used as data memory (optional, to be enabled by user) +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM3 processor is in Thread mode, @@ -36,9 +37,6 @@ Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp - -__initial_spTop EQU 0x20000400 ; stack used for SystemInit_ExtMemCtl - ; always internal RAM used ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> @@ -61,107 +59,97 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_spTop ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend - DCD TIM8_BRK_IRQHandler ; TIM8 Break - DCD TIM8_UP_IRQHandler ; TIM8 Update - DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD ADC3_IRQHandler ; ADC3 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 __Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors +__Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY - -; Dummy SystemInit_ExtMemCtl function -SystemInit_ExtMemCtl PROC - EXPORT SystemInit_ExtMemCtl [WEAK] - BX LR - ENDP -; Reset handler routine +; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main - - LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller - BLX R0 - - LDR R1, = __initial_sp ; restore original stack pointer - MSR MSP, R1 - + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 LDR R0, =__main BX R0 ENDP @@ -367,4 +355,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_ld.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s similarity index 64% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_ld.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s index 5c897844ad..2e3573b400 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_ld.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s @@ -1,14 +1,15 @@ -;******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_ld.s ;* Author : MCD Application Team -;* Version : V3.1.2 -;* Date : 09/28/2009 +;* Version : V3.2.0 +;* Date : 03/01/2010 ;* Description : STM32F10x Low Density Devices vector table for RVMDK ;* toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM3 processor is in Thread mode, @@ -57,67 +58,67 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1_2 + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -128,6 +129,9 @@ __Vectors_Size EQU __Vectors_End - __Vectors Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 LDR R0, =__main BX R0 ENDP @@ -290,4 +294,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000000..f1e5cf9752 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s @@ -0,0 +1,304 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.2.0 +;* Date : 03/01/2010 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for RVMDK toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_md.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s similarity index 65% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_md.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s index 753cfe9c45..7c4e8eaa0c 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_md.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s @@ -1,14 +1,15 @@ -;******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_md.s ;* Author : MCD Application Team -;* Version : V3.1.2 -;* Date : 09/28/2009 +;* Version : V3.2.0 +;* Date : 03/01/2010 ;* Description : STM32F10x Medium Density Devices vector table for RVMDK ;* toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM3 processor is in Thread mode, @@ -57,77 +58,80 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1_2 + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler routine +; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] - IMPORT __main + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 LDR R0, =__main BX R0 ENDP @@ -300,4 +304,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000000..8956fb6716 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s @@ -0,0 +1,315 @@ +;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.2.0 +;* Date : 03/01/2010 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for RVMDK toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_cl.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s similarity index 74% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_cl.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s index 621bf5180b..bb37cd6552 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_cl.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s @@ -1,20 +1,21 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_cl.s - * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 - * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR - * address. - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.2.0 + * @date 03/01/2010 + * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* * @copy * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS @@ -24,8 +25,8 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2009 STMicroelectronics

- */ + *

© COPYRIGHT 2010 STMicroelectronics

+ */ .syntax unified .cpu cortex-m3 @@ -60,48 +61,49 @@ defined in linker script */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function -Reset_Handler: +Reset_Handler: -/* Copy the data segment initializers from flash to SRAM */ +/* Copy the data segment initializers from flash to SRAM */ movs r1, #0 - b LoopCopyDataInit + b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata + ldr r0, =_sdata + ldr r3, =_edata adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss -/* Zero fill the bss segment. */ +/* Zero fill the bss segment. */ FillZerobss: movs r3, #0 - str r3, [r2], #4 + str r3, [r2], #4 LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit /* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler + bl main + bx lr +.size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving + * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. - * - * @param None - * @retval : None + * @param None + * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: @@ -111,12 +113,12 @@ Infinite_Loop: /****************************************************************************** * -* The minimal vector table for a Cortex M3. Note that the proper constructs +* The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors @@ -157,9 +159,9 @@ g_pfnVectors: .word DMA1_Channel6_IRQHandler .word DMA1_Channel7_IRQHandler .word ADC1_2_IRQHandler - .word CAN1_TX_IRQHandler - .word CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler .word CAN1_SCE_IRQHandler .word EXTI9_5_IRQHandler .word TIM1_BRK_IRQHandler @@ -180,71 +182,71 @@ g_pfnVectors: .word USART3_IRQHandler .word EXTI15_10_IRQHandler .word RTCAlarm_IRQHandler - .word OTG_FS_WKUP_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word ETH_IRQHandler - .word ETH_WKUP_IRQHandler - .word CAN2_TX_IRQHandler - .word CAN2_RX0_IRQHandler - .word CAN2_RX1_IRQHandler - .word CAN2_SCE_IRQHandler - .word OTG_FS_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for + .word OTG_FS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word OTG_FS_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for STM32F10x Connectivity line Devices. */ - + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. @@ -462,3 +464,4 @@ g_pfnVectors: .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler ,Default_Handler +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_hd.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s similarity index 79% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_hd.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s index 78c10c3c49..cce913b184 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_hd.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s @@ -1,40 +1,40 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_hd.s - * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 - * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure external SRAM mounted on STM3210E-EVAL board - * to be used as data memory (optional, to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.2.0 + * @date 03/01/2010 + * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ - .syntax unified + .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors -.global SystemInit_ExtMemCtl_Dummy .global Default_Handler /* start address for the initialization values of the .data section. @@ -50,7 +50,6 @@ defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ -.equ Initial_spTop, 0x20000400 .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first @@ -66,12 +65,6 @@ defined in linker script */ .type Reset_Handler, %function Reset_Handler: -/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is - required, then adjust the Register Addresses */ - bl SystemInit_ExtMemCtl -/* restore original stack pointer */ - LDR r0, =_estack - MSR msp, r0 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit @@ -99,28 +92,19 @@ LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler -/** - * @brief Dummy SystemInit_ExtMemCtl function - * @param None - * @retval : None -*/ - .section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits -SystemInit_ExtMemCtl_Dummy: - bx lr - .size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy - /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. - * * @param None - * @retval : None + * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: @@ -129,18 +113,18 @@ Infinite_Loop: .size Default_Handler, .-Default_Handler /****************************************************************************** * -* The minimal vector table for a Cortex M3. Note that the proper constructs +* The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. -* -******************************************************************************/ +* +*******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: - .word Initial_spTop + .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler @@ -262,13 +246,12 @@ g_pfnVectors: .word 0 .word BootRAM /* @0x1E0. This is for boot in RAM mode for STM32F10x High Density devices. */ - /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. -* +* *******************************************************************************/ .weak NMI_Handler @@ -478,6 +461,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - .weak SystemInit_ExtMemCtl - .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy - +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s new file mode 100644 index 0000000000..ed7917ed18 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.2.0 + * @date 03/01/2010 + * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Low Density devices.*/ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_ld.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s similarity index 60% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_ld.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s index 373f94cc6a..0e80bde51a 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_ld.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s @@ -1,30 +1,32 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_ld.s - * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 - * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address. - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.2.0 + * @date 03/01/2010 + * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ .syntax unified .cpu cortex-m3 @@ -53,71 +55,70 @@ defined in linker script */ * necessary set is performed, after which the application * supplied main() routine is called. * @param None - * @retval : None + * @retval None */ - .section .text.Reset_Handler + .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 - b LoopCopyDataInit + b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata + ldr r0, =_sdata + ldr r3, =_edata adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 - str r3, [r2], #4 + str r3, [r2], #4 LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit /* Call the application's entry point.*/ - bl main - bx lr + bl main + bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving + * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. - * * @param None - * @retval : None + * @retval None */ - .section .text.Default_Handler,"ax",%progbits + .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs +* The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. -* +* ******************************************************************************/ - .section .isr_vector,"a",%progbits + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - - + g_pfnVectors: .word _estack .word Reset_Handler @@ -153,31 +154,52 @@ g_pfnVectors: .word DMA1_Channel5_IRQHandler .word DMA1_Channel6_IRQHandler .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler .word TIM1_CC_IRQHandler .word TIM2_IRQHandler .word TIM3_IRQHandler - 0 + .word 0 .word I2C1_EV_IRQHandler .word I2C1_ER_IRQHandler - 0 - 0 + .word 0 + .word 0 .word SPI1_IRQHandler - 0 + .word 0 .word USART1_IRQHandler .word USART2_IRQHandler - 0 + .word 0 .word EXTI15_10_IRQHandler .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 .word 0 .word 0 .word 0 @@ -185,15 +207,41 @@ g_pfnVectors: .word 0 .word 0 .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F10x Low Density devices.*/ + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Low Density Value Line devices. */ /******************************************************************************* -* * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. -* *******************************************************************************/ .weak NMI_Handler @@ -277,32 +325,20 @@ g_pfnVectors: .weak DMA1_Channel7_IRQHandler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler @@ -334,6 +370,13 @@ g_pfnVectors: .weak RTCAlarm_IRQHandler .thumb_set RTCAlarm_IRQHandler,Default_Handler - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s new file mode 100644 index 0000000000..4d7d37aa28 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s @@ -0,0 +1,357 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.2.0 + * @date 03/01/2010 + * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_md.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s similarity index 61% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_md.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s index fef997826d..e158a992ef 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_md.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s @@ -1,30 +1,32 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_md.s - * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 - * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.2.0 + * @date 03/01/2010 + * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ .syntax unified .cpu cortex-m3 @@ -53,71 +55,71 @@ defined in linker script */ * necessary set is performed, after which the application * supplied main() routine is called. * @param None - * @retval : None + * @retval None */ - .section .text.Reset_Handler + .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 - b LoopCopyDataInit + b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata + ldr r0, =_sdata + ldr r3, =_edata adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 - str r3, [r2], #4 + str r3, [r2], #4 LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit /* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler + bl main + bx lr +.size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving + * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. - * * @param None - * @retval : None + * @retval None */ - .section .text.Default_Handler,"ax",%progbits + .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * -* The minimal vector table for a Cortex M3. Note that the proper constructs +* The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. -* +* ******************************************************************************/ - .section .isr_vector,"a",%progbits + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - - + g_pfnVectors: .word _estack .word Reset_Handler @@ -153,15 +155,15 @@ g_pfnVectors: .word DMA1_Channel5_IRQHandler .word DMA1_Channel6_IRQHandler .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler .word TIM1_CC_IRQHandler .word TIM2_IRQHandler .word TIM3_IRQHandler @@ -174,10 +176,34 @@ g_pfnVectors: .word SPI2_IRQHandler .word USART1_IRQHandler .word USART2_IRQHandler - .word USART3_IRQHandler + .word 0 .word EXTI15_10_IRQHandler .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 .word 0 .word 0 .word 0 @@ -185,15 +211,38 @@ g_pfnVectors: .word 0 .word 0 .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F10x Medium Density devices. */ + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ /******************************************************************************* -* * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. -* *******************************************************************************/ .weak NMI_Handler @@ -277,32 +326,20 @@ g_pfnVectors: .weak DMA1_Channel7_IRQHandler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler @@ -340,16 +377,19 @@ g_pfnVectors: .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTCAlarm_IRQHandler .thumb_set RTCAlarm_IRQHandler,Default_Handler - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_cl.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s similarity index 93% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_cl.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s index 42c5fd920f..729be8d5c6 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_cl.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s @@ -1,12 +1,13 @@ -;/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_cl.s ;* Author : MCD Application Team -;* Version : V3.1.2 -;* Date : 09/28/2009 +;* Version : V3.2.0 +;* Date : 03/01/2010 ;* Description : STM32F10x Connectivity line devices vector table for ;* EWARM5.x toolchain. ;* This module performs: ;* - Set the initial SP +;* - Configure the clock system ;* - Set the initial PC == __iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. @@ -45,13 +46,13 @@ SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start + EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) - DCD __iar_program_start - + DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -143,6 +144,14 @@ __vector_table ;; THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler @@ -495,4 +504,4 @@ OTG_FS_IRQHandler B OTG_FS_IRQHandler END -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_hd.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s similarity index 89% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_hd.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s index 5882cd5879..2e8c0ba228 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_hd.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s @@ -1,16 +1,17 @@ -;/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_hd.s ;* Author : MCD Application Team -;* Version : V3.1.2 -;* Date : 09/28/2009 +;* Version : V3.2.0 +;* Date : 03/01/2010 ;* Description : STM32F10x High Density Devices vector table for EWARM5.x ;* toolchain. ;* This module performs: ;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) ;* - Set the initial PC == __iar_program_start, ;* - Set the vector table entries with the exceptions ISR address, -;* - Configure external SRAM mounted on STM3210E-EVAL board -;* to be used as data memory (optional, to be enabled by user) ;* After Reset the Cortex-M3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** @@ -40,43 +41,20 @@ MODULE ?cstartup - ;; ICODE is the same segment as cstartup. By placing __low_level_init - ;; in the same segment, we make sure it can be reached with BL. */ - - SECTION CSTACK:DATA:NOROOT(3) - SECTION .icode:CODE:NOROOT(2) - PUBLIC __low_level_init - - PUBWEAK SystemInit_ExtMemCtl - SECTION .text:CODE:REORDER(2) - THUMB -SystemInit_ExtMemCtl - BX LR - -__low_level_init: - - ;; Initialize hardware. - LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller - MOV R11, LR - BLX R0 - LDR R1, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R1 - MOV R0,#1 - ;; Return with BX to be independent of mode of caller - BX R11 - ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start + EXTERN SystemInit PUBLIC __vector_table DATA -__intial_sp EQU 0x20000400 + __vector_table - DCD __intial_sp - DCD __iar_program_start - + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -158,7 +136,15 @@ __vector_table ;; Default interrupt handlers. ;; THUMB - + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler @@ -507,4 +493,4 @@ DMA2_Channel4_5_IRQHandler END -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_ld.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s similarity index 92% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_ld.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s index 13046d8df0..9c709518f2 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_ld.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s @@ -1,12 +1,13 @@ -;/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_ld.s ;* Author : MCD Application Team -;* Version : V3.1.2 -;* Date : 09/28/2009 +;* Version : V3.2.0 +;* Date : 03/01/2010 ;* Description : STM32F10x Low Density Devices vector table for EWARM5.x ;* toolchain. ;* This module performs: ;* - Set the initial SP +;* - Configure the clock system ;* - Set the initial PC == __iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. @@ -45,13 +46,13 @@ SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start + EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) - DCD __iar_program_start - + DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -118,6 +119,14 @@ __vector_table ;; THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler @@ -354,4 +363,4 @@ USBWakeUp_IRQHandler B USBWakeUp_IRQHandler END -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000000..511a4746c1 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s @@ -0,0 +1,369 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.2.0 +;* Date : 03/01/2010 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for EWARM5.x toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_md.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s similarity index 92% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_md.s rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s index e28a3ba727..b767c0e216 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_md.s +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s @@ -1,12 +1,13 @@ -;/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_md.s ;* Author : MCD Application Team -;* Version : V3.1.2 -;* Date : 09/28/2009 +;* Version : V3.2.0 +;* Date : 03/01/2010 ;* Description : STM32F10x Medium Density Devices vector table for ;* EWARM5.x toolchain. ;* This module performs: ;* - Set the initial SP +;* - Configure the clock system ;* - Set the initial PC == __iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. @@ -45,13 +46,13 @@ SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start + EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) - DCD __iar_program_start - + DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -118,6 +119,14 @@ __vector_table ;; THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler @@ -379,4 +388,4 @@ USBWakeUp_IRQHandler B USBWakeUp_IRQHandler END -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000000..e72a294013 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s @@ -0,0 +1,394 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.2.0 +;* Date : 03/01/2010 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for EWARM5.x toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/stm32f10x.h b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h similarity index 94% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/stm32f10x.h rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h index 48aeee3356..46098c283e 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/stm32f10x.h +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h @@ -2,12 +2,13 @@ ****************************************************************************** * @file stm32f10x.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F10x Connectivity line, High - * density, Medium density and Low density devices. + * density, Medium density, Medium density Value line, Low density + * and Low density Value line devices. ****************************************************************************** * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS @@ -17,7 +18,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2009 STMicroelectronics

+ *

© COPYRIGHT 2010 STMicroelectronics

****************************************************************************** */ @@ -44,19 +45,25 @@ application */ -#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL) - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - #define STM32F10X_CL /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + #define STM32F10X_MD_VL /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. - High density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. @@ -78,29 +85,29 @@ Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor. */ -#if !defined HSE_Value +#if !defined HSE_VALUE #ifdef STM32F10X_CL - #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ #else - #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ #endif /* STM32F10X_CL */ -#endif /* HSE_Value */ +#endif /* HSE_VALUE */ /** * @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ -#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ /** * @brief STM32F10x Standard Peripheral Library version number */ #define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x02) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ #define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ | __STM32F10X_STDPERIPH_VERSION_SUB2) @@ -155,9 +162,9 @@ typedef enum IRQn DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ #ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ @@ -179,7 +186,29 @@ typedef enum IRQn USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ #endif /* STM32F10X_LD */ +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + #ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ @@ -206,7 +235,34 @@ typedef enum IRQn USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ #endif /* STM32F10X_MD */ +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + #ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ @@ -251,6 +307,7 @@ typedef enum IRQn #endif /* STM32F10X_HD */ #ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ @@ -352,6 +409,10 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE /** * @} */ @@ -486,7 +547,7 @@ typedef struct __IO uint16_t DR42; uint16_t RESERVED45; } BKP_TypeDef; - + /** * @brief Controller Area Network TxMailBox */ @@ -555,6 +616,20 @@ typedef struct #endif /* STM32F10X_CL */ } CAN_TypeDef; +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + /** * @brief CRC calculation unit */ @@ -587,6 +662,9 @@ typedef struct __IO uint32_t DHR8RD; __IO uint32_t DOR1; __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + __IO uint32_t SR; +#endif } DAC_TypeDef; /** @@ -818,6 +896,8 @@ typedef struct __IO uint32_t EVCR; __IO uint32_t MAPR; __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; } AFIO_TypeDef; /** * @brief Inter-integrated Circuit Interface @@ -883,10 +963,16 @@ typedef struct __IO uint32_t APB1ENR; __IO uint32_t BDCR; __IO uint32_t CSR; + #ifdef STM32F10X_CL __IO uint32_t AHBRSTR; __IO uint32_t CFGR2; #endif /* STM32F10X_CL */ + +#if defined STM32F10X_LD_VL || defined STM32F10X_MD_VL + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL */ } RCC_TypeDef; /** @@ -1063,8 +1149,8 @@ typedef struct #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */ #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ @@ -1095,6 +1181,7 @@ typedef struct #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) #define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) @@ -1112,6 +1199,9 @@ typedef struct #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) #define USART1_BASE (APB2PERIPH_BASE + 0x3800) #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) #define SDIO_BASE (PERIPH_BASE + 0x18000) @@ -1179,6 +1269,7 @@ typedef struct #define BKP ((BKP_TypeDef *) BKP_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) #define AFIO ((AFIO_TypeDef *) AFIO_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -1195,6 +1286,9 @@ typedef struct #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) @@ -1580,6 +1674,40 @@ typedef struct #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ #else #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ @@ -1646,26 +1774,36 @@ typedef struct #endif /* STM32F10X_CL */ /***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */ -#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */ -#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */ - -#ifndef STM32F10X_LD - #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */ -#endif /* STM32F10X_HD */ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ #ifdef STM32F10X_HD - #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */ + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ #endif /* STM32F10X_HD */ /***************** Bit definition for RCC_APB1RSTR register *****************/ @@ -1674,16 +1812,20 @@ typedef struct #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ -#ifndef STM32F10X_LD +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_HD */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ @@ -1699,8 +1841,15 @@ typedef struct #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ #endif +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + #ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */ + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ #endif /* STM32F10X_CL */ /****************** Bit definition for RCC_AHBENR register ******************/ @@ -1726,26 +1875,36 @@ typedef struct #endif /* STM32F10X_CL */ /****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */ -#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */ -#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */ - -#ifndef STM32F10X_LD - #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_HD */ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ #ifdef STM32F10X_HD - #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */ + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ #endif /* STM32F10X_HD */ /***************** Bit definition for RCC_APB1ENR register ******************/ @@ -1754,16 +1913,20 @@ typedef struct #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ -#ifndef STM32F10X_LD +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_HD */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ @@ -1779,8 +1942,15 @@ typedef struct #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ #endif +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + #ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */ + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ #endif /* STM32F10X_CL */ /******************* Bit definition for RCC_BDCR register *******************/ @@ -1907,6 +2077,33 @@ typedef struct #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ #endif /* STM32F10X_CL */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + /******************************************************************************/ /* */ /* General Purpose and Alternate Function I/O */ @@ -2460,6 +2657,15 @@ typedef struct #define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ #define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + /******************************************************************************/ /* */ /* SystemTick */ @@ -3712,6 +3918,56 @@ typedef struct /******************* Bit definition for DAC_DOR2 register *******************/ #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!
© COPYRIGHT 2009 STMicroelectronics
+ *

© COPYRIGHT 2010 STMicroelectronics

****************************************************************************** */ @@ -62,6 +62,8 @@ source. 4. The System clock configuration functions provided within this file assume that: + - For Low and Medium density Value line devices an external 8MHz crystal + is used to drive the System clock. - For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock. - For Connectivity line devices an external 25MHz crystal is used to drive @@ -69,12 +71,17 @@ If you are using different crystal you have to adapt those functions accordingly. */ +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) /* #define SYSCLK_FREQ_HSE HSE_Value */ -/* #define SYSCLK_FREQ_24MHz 24000000 */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_Value */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ /* #define SYSCLK_FREQ_36MHz 36000000 */ /* #define SYSCLK_FREQ_48MHz 48000000 */ /* #define SYSCLK_FREQ_56MHz 56000000 */ #define SYSCLK_FREQ_72MHz 72000000 +#endif /*!< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density devices) as data memory */ @@ -102,49 +109,22 @@ * Clock Definitions *******************************************************************************/ #ifdef SYSCLK_FREQ_HSE - const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ - const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */ - const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */ - const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */ - const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */ + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_24MHz - const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ - const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */ - const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */ - const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */ - const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */ + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_36MHz - const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ - const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */ - const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */ - const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */ - const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */ + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_48MHz - const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ - const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */ - const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */ - const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */ - const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */ + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_56MHz - const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ - const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */ - const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */ - const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */ - const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */ + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_72MHz - const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ - const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */ - const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */ - const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */ - const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */ + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ - const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */ - const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */ - const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */ - const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */ - const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */ + uint32_t SystemCoreClock = HSI_Value; /*!< System Clock Frequency (Core Clock) */ #endif +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ @@ -169,6 +149,10 @@ static void SetSysClock(void); static void SetSysClockTo72(void); #endif +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + /** * @} */ @@ -179,7 +163,8 @@ static void SetSysClock(void); /** * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. * @note This function should be used only after reset. * @param None * @retval None @@ -206,10 +191,7 @@ void SystemInit (void) /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; -#ifndef STM32F10X_CL - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#else +#ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */ RCC->CR &= (uint32_t)0xEBFFFFFF; @@ -218,12 +200,141 @@ void SystemInit (void) /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; #endif /* STM32F10X_CL */ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); +#ifdef STM32F10X_HD + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F10X_HD */ + +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note None + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_Value; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_Value; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_Value >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_Value >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_Value * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_Value >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_Value; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; } /** @@ -338,6 +449,8 @@ static void SetSysClockToHSE(void) if (HSEStatus == (uint32_t)0x01) { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; @@ -356,6 +469,7 @@ static void SetSysClockToHSE(void) FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; } #endif /* STM32F10X_CL */ +#endif /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; @@ -377,12 +491,7 @@ static void SetSysClockToHSE(void) } else { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - - /* Go to infinite loop */ - while (1) - { - } + configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_24MHz @@ -419,12 +528,14 @@ static void SetSysClockTo24(void) if (HSEStatus == (uint32_t)0x01) { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 0 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; @@ -455,6 +566,10 @@ static void SetSysClockTo24(void) while((RCC->CR & RCC_CR_PLL2RDY) == 0) { } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); #else /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); @@ -480,12 +595,7 @@ static void SetSysClockTo24(void) } else { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - - /* Go to infinite loop */ - while (1) - { - } + configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_36MHz @@ -586,12 +696,7 @@ static void SetSysClockTo36(void) } else { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - - /* Go to infinite loop */ - while (1) - { - } + configuration. User can add here some code to deal with this error */ } } #elif defined SYSCLK_FREQ_48MHz @@ -641,7 +746,7 @@ static void SetSysClockTo48(void) /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - /* PCLK1 = HCLK/2 */ + /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL @@ -691,12 +796,7 @@ static void SetSysClockTo48(void) } else { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - - /* Go to infinite loop */ - while (1) - { - } + configuration. User can add here some code to deal with this error */ } } @@ -747,7 +847,7 @@ static void SetSysClockTo56(void) /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - /* PCLK1 = HCLK/2 */ + /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL @@ -798,12 +898,7 @@ static void SetSysClockTo56(void) } else { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - - /* Go to infinite loop */ - while (1) - { - } + configuration. User can add here some code to deal with this error */ } } @@ -855,7 +950,7 @@ static void SetSysClockTo72(void) /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - /* PCLK1 = HCLK/2 */ + /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; #ifdef STM32F10X_CL @@ -906,12 +1001,7 @@ static void SetSysClockTo72(void) } else { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - - /* Go to infinite loop */ - while (1) - { - } + configuration. User can add here some code to deal with this error */ } } #endif @@ -927,4 +1017,4 @@ static void SetSysClockTo72(void) /** * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/system_stm32f10x.h b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h similarity index 69% rename from bsp/stm32_radio/Libraries/CMSIS/Core/CM3/system_stm32f10x.h rename to bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h index 67b98d6944..8bbd2cb1ff 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/system_stm32f10x.h +++ b/bsp/stm32_radio/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @@ -14,7 +14,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2009 STMicroelectronics

+ *

© COPYRIGHT 2010 STMicroelectronics

****************************************************************************** */ @@ -49,11 +49,7 @@ * @{ */ -extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */ -extern const uint32_t SystemFrequency_SysClk; /*!< System clock */ -extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */ -extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */ -extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** * @} @@ -80,6 +76,7 @@ extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) */ extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); /** * @} */ @@ -97,4 +94,4 @@ extern void SystemInit(void); /** * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/CMSIS/CMSIS debug support.htm b/bsp/stm32_radio/Libraries/CMSIS/CMSIS debug support.htm new file mode 100644 index 0000000000..efda685be6 --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CMSIS debug support.htm @@ -0,0 +1,243 @@ + + + +CMSIS Debug Support + + + + + + + + +

CMSIS Debug Support

+ +
+ +

Cortex-M3 ITM Debug Access

+

+ The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with + the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has + 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM + communication channels are used by CMSIS to output the following information: +

+
    +
  • ITM Channel 0: used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for RTOS kernel awareness debugging.
    • +
+ +

Debug IN / OUT functions

+

CMSIS provides following debug functions:

+
    +
  • ITM_SendChar (uses ITM channel 0)
    • +
  • ITM_ReceiveChar (uses global variable)
    • +
  • ITM_CheckChar (uses global variable)
    • +
+ +

ITM_SendChar

+

+ ITM_SendChar is used to transmit a character over ITM channel 0 from + the microcontroller system to the debug system.
+ Only a 8 bit value is transmitted. +

+
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  /* check if debugger connected and ITM channel enabled for tracing */
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&
+      (ITM->TER & (1UL << 0))  ) 
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }  
+  return (ch);
+}
+ +

ITM_ReceiveChar

+

+ ITM communication channel is only capable for OUT direction. For IN direction + a globel variable is used. A simple mechansim detects if a character is received. + The project to test need to be build with debug information. +

+ +

+ The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system + to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake. +

+
+extern volatile int ITM_RxBuffer;                    /* variable to receive characters                             */
+
+

+ A dedicated bit pattern is used to determin if ITM_RxBuffer is empty + or contains a valid value. +

+
+#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
+
+

+ ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking. + It returns the received character or '-1' if no character was available. +

+
+static __INLINE int ITM_ReceiveChar (void) {
+  int ch = -1;                               /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+  
+  return (ch); 
+}
+
+ +

ITM_CheckChar

+

+ ITM_CheckChar is used to check if a character is received. +

+
+static __INLINE int ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+ + +

ITM Debug Support in uVision

+

+ uVision uses in a debug session the Debug (printf) Viewer window to + display the debug data. +

+

Direction microcontroller system -> uVision:

+
    +
  • + Characters received via ITM communication channel 0 are written in a printf style + to Debug (printf) Viewer window. +
    • +
+ +

Direction uVision -> microcontroller system:

+
    +
  • Check if ITM_RxBuffer variable is available (only performed once).
    • +
  • Read character from Debug (printf) Viewer window.
    • +
  • If ITM_RxBuffer empty write character to ITM_RxBuffer.
    • +
+ +

Note

+
    +

  • Current solution does not use a buffer machanism for trasmitting the characters.

    +
    • +
+ +

RTX Kernel awareness in uVision

+

+ uVision / RTX are using a simple and efficient solution for RTX Kernel awareness. + No format overhead is necessary.
+ uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access + to ITM communication channel 31. +

+ +

Following RTX events are traced:

+
    +
  • Task Create / Delete event +
      +
    1. 32 bit access. Task start address is transmitted
      2. +
    2. 16 bit access. Task ID and Create/Delete flag are transmitted
      + High byte holds Create/Delete flag, Low byte holds TASK ID. +
      3. +
    +
    • +
  • Task switch event +
      +
    1. 8 bit access. Task ID of current task is transmitted
      2. +
    +
    • +
+ +

Note

+
    +

  • Other RTOS information could be retrieved via memory read access in a polling mode manner.

    +
    • +
+ + +

 

+ +
+ +

Copyright © KEIL - An ARM Company.
+All rights reserved.
+Visit our web site at www.keil.com. +

+ + + + \ No newline at end of file diff --git a/bsp/stm32_radio/Libraries/CMSIS/CMSIS_changes.htm b/bsp/stm32_radio/Libraries/CMSIS/CMSIS_changes.htm new file mode 100644 index 0000000000..162ffcc9dc --- /dev/null +++ b/bsp/stm32_radio/Libraries/CMSIS/CMSIS_changes.htm @@ -0,0 +1,320 @@ + + + +CMSIS Changes + + + + + + + + +

Changes to CMSIS version V1.20

+ +
+ +

1. Removed CMSIS Middelware packages

+

+ CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. +

+ +

2. SystemFrequency renamed to SystemCoreClock

+

+ The variable name SystemCoreClock is more precise than SystemFrequency + because the variable holds the clock value at which the core is running. +

+ +

3. Changed startup concept

+

+ The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit + from main) has the weakness that it does not work for controllers which need a already + configuerd clock system to configure the external memory controller. +

+ +

Changed startup concept

+
    +
  • + SystemInit() is called from startup file before premain. +
    • +
  • + SystemInit() configures the clock system and also configures + an existing external memory controller. +
    • +
  • + SystemInit() must not use global variables. +
    • +
  • + SystemCoreClock is initialized with a correct predefined value. +
    • +
  • + Additional function void SystemCoreClockUpdate (void) is provided.
    + SystemCoreClockUpdate() updates the variable SystemCoreClock + and must be called whenever the core clock is changed.
    + SystemCoreClockUpdate() evaluates the clock register settings and calculates + the current core clock. +
    • +
+ + +

4. Advanced Debug Functions

+

+ ITM communication channel is only capable for OUT direction. To allow also communication for + IN direction a simple concept is provided. +

+
    +
  • + Global variable volatile int ITM_RxBuffer used for IN data. +
    • +
  • + Function int ITM_CheckChar (void) checks if a new character is available. +
    • +
  • + Function int ITM_ReceiveChar (void) retrieves the new character. +
    • +
+ +

+ For detailed explanation see file CMSIS debug support.htm. +

+ + +

5. Core Register Bit Definitions

+

+ Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the + defines correspond with the Cortex-M Technical Reference Manual. +

+

+ e.g. SysTick structure with bit definitions +

+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+  memory mapped structure for SysTick
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+ +

7. DoxyGen Tags

+

+ DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation + using DoxyGen. +

+ +

8. Folder Structure

+

+ The folder structure is changed to differentiate the single support packages. +

+ +
    +
  • CM0
    • +
  • CM3 +
      +
    • CoreSupport
      • +
    • DeviceSupport
      • +
        +
      • Vendor +
          +
        • Device +
            +
          • Startup +
              +
            • Toolchain
              • +
            • Toolchain
              • +
            • ...
              • +
            +
            • +
          +
          • +
        • Device
          • +
        • ...
          • +
        +
        • +
      • Vendor
        • +
      • ...
        • +
      + +
    • Example +
        +
      • Toolchain +
          +
        • Device
          • +
        • Device
          • +
        • ...
          • +
        +
        • +
      • Toolchain
        • +
      • ...
        • +
      +
      • +
    +
    • + +
  • Documentation
    • +
+ +

9. Open Points

+

+ Following points need to be clarified and solved: +

+
    +
  • +

    + Equivalent C and Assembler startup files. +

    +

    + Is there a need for having C startup files although assembler startup files are + very efficient and do not need to be changed? +

    +

    • +
  • +

    + Placing of HEAP in external RAM. +

    +

    + It must be possible to place HEAP in external RAM if the device supports an + external memory controller. +

    +
    • +
  • +

    + Placing of STACK /HEAP. +

    +

    + STACK should always be placed at the end of internal RAM. +

    +

    + If HEAP is placed in internal RAM than it should be placed after RW ZI section. +

    +
    • +
  • +

    + Removing core_cm3.c and core_cm0.c. +

    +

    + On a long term the functions in core_cm3.c and core_cm0.c must be replaced with + appropriate compiler intrinsics. +

    +
    • +
+ + +

10. Limitations

+

+ The following limitations are not covered with the current CMSIS version: +

+
    +
  • + No C startup files for ARM toolchain are provided. +
    • +
  • + No C startup files for GNU toolchain are provided. +
    • +
  • + No C startup files for IAR toolchain are provided. +
    • +
  • + No Tasking projects are provided yet. +
    • +
diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/core_cm3.h b/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/core_cm3.h deleted file mode 100644 index b6f9696bfc..0000000000 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/CM3/core_cm3.h +++ /dev/null @@ -1,1367 +0,0 @@ -/****************************************************************************** - * @file: core_cm3.h - * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version: V1.20 - * @date: 22. May 2009 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -/** - * Lint configuration \n - * ----------------------- \n - * - * The following Lint messages will be suppressed and not shown: \n - * \n - * --- Error 10: --- \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' \n - * \n - * --- Error 530: --- \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n - * \n - * --- Error 550: --- \n - * __regBasePri = (basePri & 0x1ff); \n - * } \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n - * \n - * --- Error 754: --- \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n - * \n - * --- Error 750: --- \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n - * \n - * --- Error 528: --- \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n - * \n - * --- Error 751: --- \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n - * \n - * \n - * Note: To re-enable a Message, insert a space before 'lint' * \n - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus -#define __I volatile /*!< defines 'read only' permissions */ -#else -#define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ - - -/* System Reset */ -#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ -#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ -#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ -#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ - -/* Core Debug */ -#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */ -#define ITM_TCR_ITMENA 1 /*!< ITM enable */ - - - - -/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Software Trigger Interrupt Register */ -} NVIC_Type; - - -/* memory mapping struct for System Control Block */ -typedef struct -{ - __I uint32_t CPUID; /*!< CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< System Control Register */ - __IO uint32_t CCR; /*!< Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Processor Feature Register */ - __I uint32_t DFR; /*!< Debug Feature Register */ - __I uint32_t ADR; /*!< Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< ISA Feature Register */ -} SCB_Type; - - -/* memory mapping struct for SysTick */ -typedef struct -{ - __IO uint32_t CTRL; /*!< SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< SysTick Current Value Register */ - __I uint32_t CALIB; /*!< SysTick Calibration Register */ -} SysTick_Type; - - -/* memory mapping structur for ITM */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< ITM Integration Write Register */ - __IO uint32_t IRR; /*!< ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< ITM Lock Access Register */ - __IO uint32_t LSR; /*!< ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< ITM Product ID Registers */ - __I uint32_t PID5; - __I uint32_t PID6; - __I uint32_t PID7; - __I uint32_t PID0; - __I uint32_t PID1; - __I uint32_t PID2; - __I uint32_t PID3; - __I uint32_t CID0; - __I uint32_t CID1; - __I uint32_t CID2; - __I uint32_t CID3; -} ITM_Type; - - -/* memory mapped struct for Interrupt Type */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - - -/* Memory Protection Unit */ -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -typedef struct -{ - __I uint32_t TYPE; /*!< MPU Type Register */ - __IO uint32_t CTRL; /*!< MPU Control Register */ - __IO uint32_t RNR; /*!< MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; -#endif - - -/* Core Debug Register */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/* - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * @param none - * @return none - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - - -/** - * @brief Remove the exclusive lock created by ldrex - * - * @param none - * @return none - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0x1ff); -} - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB() { __ASM volatile ("isb"); } -static __INLINE void __DSB() { __ASM volatile ("dsb"); } -static __INLINE void __DMB() { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @param none -* @return uint32_t Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/* - * Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * @brief Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - - -/* ########################## NVIC functions #################################### */ - - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param uint32_t priority_grouping is priority grouping field - * @return none - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ - reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @param none - * @return uint32_t priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn_Type IRQn specifies the interrupt number - * @return none - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn_Type IRQn is the positive number of the external interrupt - * @return none - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn_Type IRQn is the number of the device specifc interrupt - * @return uint32_t 1 if pending interrupt else 0 - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return none - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return none - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return uint32_t 1 if active else 0 - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @param priority is the priority for the interrupt - * @return none - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. \n - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return uint32_t priority is the priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param uint32_t PriorityGroup is the used priority group - * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0) - * @param uint32_t SubPriority is the sub priority value (starting from 0) - * @return uint32_t the priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param uint32_t Priority the priority for the interrupt - * @param uint32_t PrioGroup is the used priority group - * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0) - * @param uint32_t* pSubPrio is the sub priority value (starting from 0) - * @return none - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/* SysTick constants */ -#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ -#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ -#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ -#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param uint32_t ticks is the number of ticks between two interrupts - * @return none - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ - SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<DEMCR & CoreDebug_DEMCR_TRCENA) && - (ITM->TCR & ITM_TCR_ITMENA) && - (ITM->TER & (1UL << 0)) ) - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - -#ifdef __cplusplus -} -#endif - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/bsp/stm32_radio/Libraries/CMSIS/Core/Documentation/CMSIS_Core.htm b/bsp/stm32_radio/Libraries/CMSIS/Documentation/CMSIS_Core.htm similarity index 78% rename from bsp/stm32_radio/Libraries/CMSIS/Core/Documentation/CMSIS_Core.htm rename to bsp/stm32_radio/Libraries/CMSIS/Documentation/CMSIS_Core.htm index 60b79b8083..6fd131e125 100644 --- a/bsp/stm32_radio/Libraries/CMSIS/Core/Documentation/CMSIS_Core.htm +++ b/bsp/stm32_radio/Libraries/CMSIS/Documentation/CMSIS_Core.htm @@ -59,7 +59,7 @@ td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0

Cortex Microcontroller Software Interface Standard

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

-

Version: 1.20 - 22. May 2009

+

Version: 1.30 - 30. October 2009

Information in this file, the accompany manuals, and software is
Copyright © ARM Ltd.
All rights reserved. @@ -74,6 +74,9 @@ td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0

  • Version 1.02: added Cortex-M0.
  • Version 1.10: second review.
  • Version 1.20: third review.
    • +
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
    • +
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
    • +
  • Version 1.30: updated Device Support Packages.
    • @@ -93,8 +96,8 @@ td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0

    The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges that are faced when software components are deployed to physical microcontroller devices based on a - Cortex-M0 / Cortex-M1 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M - processor cores (the term Cortex-Mx is used to indicate that). The CMSIS is defined in close co-operation + Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M + processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components.

    @@ -104,14 +107,9 @@ available for various compiler implementations:

    • Core Peripheral Access Layer: contains name definitions, address definitions and helper functions to - access core registers and peripherals. It defines also an device + access core registers and peripherals. It defines also a device independent interface for RTOS Kernels that includes debug channel definitions.
      • -
    • Middleware Access Layer: provides common methods to - access peripherals for the software industry. The Middleware Access Layer - is adapted by the Silicon Vendor for the device specific peripherals used - by middleware components. The middleware access layer is currently in - development and not yet part of this documentation

    These software layers are expanded by Silicon partners with:

    @@ -122,7 +120,7 @@ available for various compiler implementations:

    additional helper functions for peripherals -

    CMSIS defines for a Cortex-Mx Microcontroller System:

    +

    CMSIS defines for a Cortex-M Microcontroller System:

    • A common way to access peripheral registers and a common way to define exception vectors.
      • @@ -131,8 +129,6 @@ available for various compiler implementations:

      Exception Vectors.
    • An device independent interface for RTOS Kernels including a debug channel.
      • -
    • Interfaces for middleware components (TCP/IP - Stack, Flash File System).

    @@ -159,8 +155,7 @@ available for various compiler implementations:

  • All functions in the Core Peripheral Access Layer are re-entrant.
  • The Core Peripheral Access Layer has no blocking code - (which means that wait/query loops are done at other software layers such as - the Middleware Access Layer).
    • + (which means that wait/query loops are done at other software layers).
  • For each exception/interrupt there is definition for:
    • an exception/interrupt handler with the postfix _Handler @@ -208,7 +203,7 @@ available for various compiler implementations:

      Data Types and IO Type Qualifiers

      - The Cortex-Mx HAL uses the standard types from the standard ANSI C header file + The Cortex-M HAL uses the standard types from the standard ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers. @@ -245,8 +240,8 @@ available for various compiler implementations:

      -#define __CM3_CMSIS_VERSION_MAIN  (0x00)      /* [31:16] main version       */
-#define __CM3_CMSIS_VERSION_SUB   (0x03)      /* [15:0]  sub version        */
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
+#define __CM3_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)

      @@ -254,21 +249,21 @@ available for various compiler implementations:

      -#define __CM0_CMSIS_VERSION_MAIN  (0x00)      /* [31:16] main version       */
-#define __CM0_CMSIS_VERSION_SUB   (0x00)      /* [15:0]  sub version        */
+#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
+#define __CM0_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
 #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)

      CMSIS Cortex Core

      - File core_cm3.h contains the type of the CMSIS Cortex-Mx with the following define: + File core_cm3.h contains the type of the CMSIS Cortex-M with the following define: 

       #define __CORTEX_M                (0x03)

      - File core_cm0.h contains the type of the CMSIS Cortex-Mx with the following define: + File core_cm0.h contains the type of the CMSIS Cortex-M with the following define: 

      @@ -277,7 +272,7 @@ available for various compiler implementations:
      
 
 
      CMSIS Files
      
 
      
-  This section describes the Files provided in context with the CMSIS to access the Cortex-Mx
+  This section describes the Files provided in context with the CMSIS to access the Cortex-M
   hardware and peripherals.
 
      
 
@@ -310,14 +305,14 @@ available for various compiler implementations:
      
       Provides helper functions that access core registers.
     
     
-      core_cm0.c
+      core_cm3.c
       ARM (for RealView ARMCC, IAR, and GNU GCC)
       Provides helper functions that access core registers.
     
     
       startup_device
       ARM (adapted by compiler partner / silicon partner)
-      Provides the Cortex-Mx startup code and the complete (device specific) Interrupt Vector Table
+      Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
     
     
       system_device
@@ -342,7 +337,7 @@ available for various compiler implementations:

    • Configuration for core_cm0.h / core_cm3.h: reflects the - actual configuration of the Cortex-Mx processor that is part of the actual + actual configuration of the Cortex-M processor that is part of the actual device. As such the file core_cm0.h / core_cm3.h is included that implements access to processor registers and core peripherals.

      • @@ -386,7 +381,7 @@ typedef enum IRQn

      Configuration for core_cm0.h / core_cm3.h

      - The Cortex-Mx core configuration options which are defined for each device implementation. Some + The Cortex-M core configuration options which are defined for each device implementation. Some configuration options are reflected in the CMSIS layer using the #define settings described below.

      @@ -436,18 +431,53 @@ typedef enum IRQn

      Device Peripheral Access Layer

      - Each peripheral uses a PERIPHERAL_ prefix to identify peripheral registers - and functions that access this specific peripheral. If more than one peripheral of the same - type exists, identifiers have a postfix (digit or letter). For example: + Each peripheral uses a prefix which consists of <device abbreviation>_ + and <peripheral name>_ to identify peripheral registers that access this + specific peripheral. The intention of this is to avoid name collisions caused + due to short names. If more than one peripheral of the same type exists, + identifiers have a postfix (digit or letter). For example:

        -
      • UART_Type: defines the generic register layout for all UART channels in a device.
        • -
      • UART1: is a pointer to a register structure that refers to a specific UART. - For example UART1->DR is the data register of UART1.
        • -
      • UART_SendChar(UART1, c): is a generic function that works with all UART's in the device. - To communicate the UART that it accesses the first parameter is a pointer to the actual - UART register structure.
        • -
      • UART1_SendChar(c): is an UART1 specific implementation (in this case the send function).
        • +
      • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device. + 
        +typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                     /*!< Offset: 0x000   Receiver Buffer Register    */
+  __O  uint8_t  THR;                     /*!< Offset: 0x000   Transmit Holding Register   */
+  __IO uint8_t  DLL;                     /*!< Offset: 0x000   Divisor Latch LSB           */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                     /*!< Offset: 0x004   Divisor Latch MSB           */
+  __IO uint32_t IER;                     /*!< Offset: 0x004   Interrupt Enable Register   */
+  };
+  union {
+  __I  uint32_t IIR;                     /*!< Offset: 0x008   Interrupt ID Register       */
+  __O  uint8_t  FCR;                     /*!< Offset: 0x008   FIFO Control Register       */
+  };
+  __IO uint8_t  LCR;                     /*!< Offset: 0x00C   Line Control Register       */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                     /*!< Offset: 0x014   Line Status Register        */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                     /*!< Offset: 0x01C   Scratch Pad Register        */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                     /*!< Offset: 0x020   Autobaud Control Register   */
+  __IO uint8_t  ICR;                     /*!< Offset: 0x024   IrDA Control Register       */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                     /*!< Offset: 0x028   Fractional Divider Register */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                     /*!< Offset: 0x030   Transmit Enable Register    */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058   FIFO Level Register         */
+} LPC_UART_TypeDef;
        +
        • +
      • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. + For example UART1->DR is the data register of UART1. + 
        +#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
        +
      Minimal Requiements
      @@ -468,15 +498,17 @@ typedef struct { } SysTick_Type; -
    • Base Address for each peripheral (in case of multiple peripherals - that use the same register layout typedef multiple base addresses are defined). For example: +
    • + Base Address for each peripheral (in case of multiple peripherals + that use the same register layout typedef multiple base addresses are defined). For example: 
       #define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
      • -
    • Access Definition for each peripheral (in case of multiple peripherals that use - the same register layout typedef multiple access definitions exist, i.e. UART0, - UART1). For Example: +
    • + Access Definition for each peripheral (in case of multiple peripherals that use + the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, + LPC_UART2). For Example: 
       #define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */
      • @@ -490,14 +522,18 @@ typedef struct {
      Optional Features

      In addition the device.h file may define:

        -
      • #define constants that simplify access to the peripheral registers. - These constant define bit-positions or other specific patterns are that - required for the programming of the peripheral registers. The identifiers - used start with the name of the PERIPERHAL_. It is - recommended to use CAPITAL letters for such #define constants.
        • -
      • Functions that perform more complex functions with the peripheral (i.e. - status query before a sending register is accessed). Again these function - start with the name of the PERIPHERAL_.
        • +
      • + #define constants that simplify access to the peripheral registers. + These constant define bit-positions or other specific patterns are that required for the + programming of the peripheral registers. The identifiers used start with + <device abbreviation>_ and <peripheral name>_. + It is recommended to use CAPITAL letters for such #define constants. +
        • +
      • + Functions that perform more complex functions with the peripheral (i.e. status query before + a sending register is accessed). Again these function start with + <device abbreviation>_ and <peripheral name>_. +

      core_cm0.h and core_cm0.c

      @@ -635,14 +671,22 @@ void WWDG_IRQHandler(void) void SystemInit (void) Setup the microcontroller system. Typically this function configures the oscillator (PLL) that is part of the microcontroller device. For systems - with variable clock speed it also updates the variable SystemFrequency. + with variable clock speed it also updates the variable SystemCoreClock.
      + SystemInit is called from startup_device file. + + + void SystemCoreClockUpdate (void) + Updates the variable SystemCoreClock and must be called whenever the + core clock is changed during program execution. SystemCoreClockUpdate() + evaluates the clock register settings and calculates the current core clock. +

      Also part of the file system_device.c - is the variable SystemFrequency which contains the current CPU clock speed shown below. + is the variable SystemCoreClock which contains the current CPU clock speed shown below.

      @@ -652,14 +696,13 @@ void WWDG_IRQHandler(void) - - + + + + + + + @@ -948,55 +997,55 @@ void WWDG_IRQHandler(void) - + - + - + - + - + - + - + - + - +
      Description
      uint32_t SystemFrequencyContains the system frequency (which is the system clock frequency supplied + uint32_t SystemCoreClockContains the system core clock (which is the system clock frequency supplied to the SysTick timer and the processor core clock). This variable can be - used by the user application after the call to the function SystemInit() - to setup the SysTick timer or configure other parameters. It may also be - used by debugger to query the frequency of the debug timer or configure - the trace clock speed.

      - This variable may also be defined in the const space. + used by the user application to setup the SysTick timer or configure other + parameters. It may also be used by debugger to query the frequency of the + debug timer or configure the trace clock speed.
      + SystemCoreClock is initialized with a correct predefined value.

      The compiler must be configured to avoid the removal of this variable in case that the application program is not using it. It is important for debug systems that the variable is physically present in memory so that @@ -680,10 +723,10 @@ void WWDG_IRQHandler(void)

      Core Peripheral Access Layer

      -

      Cortex-Mx Core Register Access

      +

      Cortex-M Core Register Access

      The following functions are defined in core_cm0.h / core_cm3.h - and provide access to Cortex-Mx core registers. + and provide access to Cortex-M core registers.

      @@ -803,10 +846,10 @@ void WWDG_IRQHandler(void)
      -

      Cortex-Mx Instruction Access

      +

      Cortex-M Instruction Access

      The following functions are defined in core_cm0.h / core_cm3.hand - generate specific Cortex-Mx instructions. The functions are implemented in the file + generate specific Cortex-M instructions. The functions are implemented in the file core_cm0.c / core_cm3.c.

      @@ -818,6 +861,12 @@ void WWDG_IRQHandler(void)       		Generated CPU Instruction Description
      void __NOP (void)M0, M3NOPNo Operation
      void __WFI (void) M0, M3NonMaskableInt_IRQn M0, M3 -14Cortex-Mx Non Maskable InterruptCortex-M Non Maskable Interrupt
      HardFault_IRQn M0, M3 -13Cortex-Mx Hard Fault InterruptCortex-M Hard Fault Interrupt
      MemoryManagement_IRQn M3 -12Cortex-Mx Memory Management InterruptCortex-M Memory Management Interrupt
      BusFault_IRQn M3 -11Cortex-Mx Bus Fault InterruptCortex-M Bus Fault Interrupt
      UsageFault_IRQn M3 -10Cortex-Mx Usage Fault InterruptCortex-M Usage Fault Interrupt
      SVCall_IRQn M0, M3 -5Cortex-Mx SV Call Interrupt Cortex-M SV Call Interrupt
      DebugMonitor_IRQn M3 -4Cortex-Mx Debug Monitor InterruptCortex-M Debug Monitor Interrupt
      PendSV_IRQn M0, M3 -2Cortex-Mx Pend SV InterruptCortex-M Pend SV Interrupt
      SysTick_IRQn M0, M3 -1Cortex-Mx System Tick InterruptCortex-M System Tick Interrupt
      @@ -1018,6 +1067,12 @@ The functions are defined as static inline.

      Priority Grouping Value Set the Priority Grouping (Groups . Subgroups) + + uint32_t NVIC_GetPriorityGrouping (void) + M3 + (void) + Get the Priority Grouping (Groups . Subgroups) + void NVIC_EnableIRQ (IRQn_Type IRQn) M0, M3 @@ -1071,14 +1126,14 @@ The functions are defined as static inline.

      uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) M3 - IRQ Number, Priority Group, Preemtive Priority, Sub Priority - Encode priority for given group, preemtive and sub priority + IRQ Number, Priority Group, Preemptive Priority, Sub Priority + Encode priority for given group, preemptive and sub priority NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) M3 - IRQ Number, Priority, pointer to Priority Group, pointer to Preemtive Priority, pointer to Sub Priority - Deccode given priority to group, preemtive and sub priority + IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority + Deccode given priority to group, preemptive and sub priority void NVIC_SystemReset (void) @@ -1137,7 +1192,7 @@ provides together with the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

        -
      • ITM Channel 0: implements the ITM_putchar function +
      • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
      • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.
        • @@ -1153,7 +1208,7 @@ communication channels are used by CMSIS to output the following information:

      -

      The prototype of the ITM_putchar routine is shown in the +

      The prototype of the ITM_SendChar routine is shown in the table below.

      @@ -1164,7 +1219,7 @@ table below.

      - +
      Description
      void uint32_t ITM_putchar(uint32_t chr)void uint32_t ITM_SendChar(uint32_t chr) character to output The function outputs a character via the ITM channel 0. The function returns when no debugger is connected that has booked the @@ -1175,7 +1230,6 @@ table below.
      -

      Example for the usage of the ITM Channel 31 for RTOS Kernels:

      @@ -1192,39 +1246,91 @@ table below.

      } +

      Cortex-M3 additional Debug Access

      + +

      CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. +Data can be transmitted via a certain global buffer variable towards the target system.

      + +

      The buffer variable and the prototypes of the additional functions are shown in the +table below.

      + + + + + + + + + + + + + + + + + + + + + + + + +
      NameParameterDescription
      extern volatile int ITM_RxBuffer Buffer to transmit data towards debug system.

      + Value 0x5AA55AA5 indicates that buffer is empty.
      int ITM_ReceiveChar (void)noneThe nonblocking functions returns the character stored in + ITM_RxBuffer.

      + Return: -1 indicates that no character was received.
      int ITM_CheckChar (void)noneThe function checks if a character is available in ITM_RxBuffer.

      + Return: 1 indicates that a character is available, 0 indicates that + no character is available.
      + +

      CMSIS Example

      The following section shows a typical example for using the CMSIS layer in user applications. + The example is based on a STM32F10x Device. 

      -#include <device.h>                              // file name depends on the device used.
+#include "stm32f10x.h"
 
-void SysTick_Handler (void)  {                   // SysTick Interrupt Handler
-  ;
+volatile uint32_t msTicks;                       /* timeTicks counter */
+
+void SysTick_Handler(void) {
+  msTicks++;                                     /* increment timeTicks counter */
 }
 
-void TIM1_UP_IRQHandler (void)  {                // Timer Interrupt Handler
-  ;
+__INLINE static void Delay (uint32_t dlyTicks) {
+  uint32_t curTicks = msTicks;
+
+  while ((msTicks - curTicks) < dlyTicks);
 }
 
-void timer1_init(int frequency) {
-                                                 // set up Timer (device specific)
-  NVIC_SetPriority (TIM1_UP_IRQn, 1);            // Set Timer priority
-  NVIC_EnableIRQ (TIM1_UP_IRQn);                 // Enable Timer Interrupt
+__INLINE static void LED_Config(void) {
+  ;                                              /* Configure the LEDs */
 }
 
-void main (void) {
-  SystemInit ();
+__INLINE static void LED_On (uint32_t led) {
+  ;                                              /* Turn On  LED */
+}
 
-  if (SysTick_Config (SystemFrequency / 1000)) { // Setup SysTick Timer for 1 msec interrupts
-    :                                            // Handle Error
-    :
+__INLINE static void LED_Off (uint32_t led) {
+  ;                                              /* Turn Off LED */
+}
+
+int main (void) {
+  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
+    ;                                            /* Handle Error */
     while (1);
   }
-
-  timer1_init ();                                // device specific timer
-
-  while (1);
+  
+  LED_Config();                                  /* configure the LEDs */                            
+ 
+  while(1) {
+    LED_On (0x100);                              /* Turn  on the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+    LED_Off (0x100);                             /* Turn off the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+  }
 }
      diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes_for_STM32F10x_StdPeriph_Driver.html b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes_for_STM32F10x_StdPeriph_Driver.html new file mode 100644 index 0000000000..56cc3cbfe5 --- /dev/null +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes_for_STM32F10x_StdPeriph_Driver.html @@ -0,0 +1,179 @@ + + + + + + +Release Notes for STM32F10x Standard Peripherals Library Drivers + + + + +
      +


      +

      +
      + + + + + + +
      + + + + + + + + + +
      Back to Release page
      +

      Release +Notes for STM32F10x Standard Peripherals Library Drivers +(StdPeriph_Driver)

      +

      Copyright 2010 STMicroelectronics

      +

      +
      +

       

      + + + + + + +
      +

      Contents

      +
        +
      1. STM32F10x Standard Peripherals Library +Drivers update History
        2. +
      2. License
        3. +
      + + +

      STM32F10x Standard +Peripherals Library Drivers  update History

      +

      3.2.0 +- 03/01/2010

      +
        +
      1. General
        2. +
      +
        + +
      • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices.
        • +
      • Almost +peripherals drivers were updated to support Value +line devices features
        • +
      • Drivers limitations fix and enhancements.
        • + +
      +
        +
      1. STM32F10x_StdPeriph_Driver
        2. +
      +
        +
      • Add new +firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
        • +
      • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
        • +
      • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
        • +
      • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
        • +
      • USART +driver: add support for Oversampling by 8 mode and onebit method. 2 +functions has been added: USART_OverSampling8Cmd() and +USART_OneBitMethodCmd().
        +
        • +
      • DAC +driver: add new functions handling the DAC under run feature: +DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() +and DAC_ClearITPendingBit().
        • +
      • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
        +
        • +
      • FLASH +driver: the FLASH_EraseOptionBytes() function updated. This is now just +erasing the option bytes without modifying the RDP status either +enabled or disabled.
        • +
      • PWR +driver: the PWR_EnterSTOPMode() function updated. When woken up from +STOP mode, this function resets again the SLEEPDEEP bit in the +Cortex-M3 System Control register to allow Sleep mode entering.
        • + + +
      +

      License

      +

      The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

      +

      THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

      +

       

      +
      +
      +

      For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

      +
      +

      +
      +
      +

       

      +
      + \ No newline at end of file diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h index 7f61f8317b..7e96ab8829 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file misc.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -216,4 +216,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h index c8a07be380..41942cfc9b 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_adc.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -476,4 +476,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h index 1c16cdaf12..8eba3b1736 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_bkp.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the BKP firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -191,4 +191,4 @@ void BKP_ClearITPendingBit(void); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h index e8b430fc60..900eb5e5fa 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_can.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the CAN firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -532,4 +532,4 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h new file mode 100644 index 0000000000..8210ce55ac --- /dev/null +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h @@ -0,0 +1,209 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.h + * @author MCD Application Team + * @version V3.2.0 + * @date 03/01/2010 + * @brief This file contains all the functions prototypes for the CEC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

      © COPYRIGHT 2010 STMicroelectronics

      + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CEC_H +#define __STM32F10x_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ + + +/** @defgroup CEC_Exported_Types + * @{ + */ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. + This parameter can be a value of @ref CEC_BitTiming_Mode */ + uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. + This parameter can be a value of @ref CEC_BitPeriod_Mode */ +}CEC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_BitTiming_Mode + * @{ + */ +#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ +#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ + +#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ + ((MODE) == CEC_BitTimingErrFreeMode)) +/** + * @} + */ + +/** @defgroup CEC_BitPeriod_Mode + * @{ + */ +#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ +#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ + +#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ + ((MODE) == CEC_BitPeriodFlexibleMode)) +/** + * @} + */ + + +/** @defgroup CEC_interrupts_definition + * @{ + */ +#define CEC_IT_TERR CEC_CSR_TERR +#define CEC_IT_TBTRF CEC_CSR_TBTRF +#define CEC_IT_RERR CEC_CSR_RERR +#define CEC_IT_RBTF CEC_CSR_RBTF +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ + ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) +/** + * @} + */ + + +/** @defgroup CEC_Own_Addres + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) +/** + * @} + */ + +/** @defgroup CEC_Prescaler + * @{ + */ +#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) + +/** + * @} + */ + +/** @defgroup CEC_flags_definition + * @{ + */ + +/** + * @brief ESR register flags + */ +#define CEC_FLAG_BTE ((uint32_t)0x10010000) +#define CEC_FLAG_BPE ((uint32_t)0x10020000) +#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) +#define CEC_FLAG_SBE ((uint32_t)0x10080000) +#define CEC_FLAG_ACKE ((uint32_t)0x10100000) +#define CEC_FLAG_LINE ((uint32_t)0x10200000) +#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) + +/** + * @brief CSR register flags + */ +#define CEC_FLAG_TEOM ((uint32_t)0x00000002) +#define CEC_FLAG_TERR ((uint32_t)0x00000004) +#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) +#define CEC_FLAG_RSOM ((uint32_t)0x00000010) +#define CEC_FLAG_REOM ((uint32_t)0x00000020) +#define CEC_FLAG_RERR ((uint32_t)0x00000040) +#define CEC_FLAG_RBTF ((uint32_t)0x00000080) + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ + ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ + ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ + ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ + ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ + ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ + ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions + * @{ + */ +void CEC_DeInit(void); +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ITConfig(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_SetPrescaler(uint16_t CEC_Prescaler); +void CEC_SendDataByte(uint8_t Data); +uint8_t CEC_ReceiveDataByte(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessageCmd(FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint8_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h index 7dec6d0e05..b65170ceaf 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_crc.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -90,4 +90,4 @@ uint8_t CRC_GetIDRegister(void); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h index 11ecaca506..fb6b543f4b 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dac.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -81,9 +81,11 @@ typedef struct #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel only in High-density devices*/ #define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in Connectivity line devices */ + only in Connectivity line, Medium-density and Low-density Value Line devices */ #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel + only in Medium-density and Low-density Value Line devices*/ #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ @@ -232,6 +234,29 @@ typedef struct /** * @} */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ +#endif /** * @} @@ -253,6 +278,9 @@ void DAC_DeInit(void); void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +#endif void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); @@ -261,6 +289,12 @@ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); +#endif #ifdef __cplusplus } @@ -279,4 +313,4 @@ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h index be48ed9c39..917334b1d1 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dbgmcu.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the DBGMCU * firmware library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -67,8 +67,11 @@ #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) - -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFC000F8) == 0x00) && ((PERIPH) != 0x00)) +#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) +#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFE0000F8) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ @@ -106,4 +109,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h index 376f8a32e5..6240aa5b44 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dma.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -434,4 +434,4 @@ void DMA_ClearITPendingBit(uint32_t DMA_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h index 442a19e5fc..df600833a1 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_exti.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -118,11 +118,10 @@ typedef struct #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ - + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) - #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ @@ -134,6 +133,7 @@ typedef struct ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) + /** * @} */ @@ -180,4 +180,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h index e2be14607a..54cf3c85a5 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_flash.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -343,4 +343,4 @@ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h index ce22848513..a74a2926bb 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_fsmc.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -713,4 +713,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h index 127d07550a..e1bbe2e375 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_gpio.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the GPIO * firmware library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -195,11 +195,18 @@ typedef enum #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ #define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ + #define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ @@ -215,7 +222,10 @@ typedef enum ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ - ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS)) + ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ + ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ + ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ + ((REMAP) == GPIO_Remap_TIM1_DMA)) /** * @} @@ -295,8 +305,8 @@ typedef enum /** @defgroup Ethernet_Media_Interface * @{ */ -#define GPIO_ETH_MediaInterface_MII ((uint32_t)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((uint32_t)0x00000001) +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) #define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) @@ -356,4 +366,4 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h index 7461770f3b..f58754cc5e 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_i2c.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -469,4 +469,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h index a46546a70d..af652df66f 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_iwdg.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -136,4 +136,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h index f8d59dfe31..b223b16a57 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_pwr.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -152,4 +152,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h index 2d18376724..496cbd9778 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_rcc.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the RCC firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -79,7 +79,7 @@ typedef struct #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) -#ifndef STM32F10X_CL +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_CL) #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ @@ -87,7 +87,7 @@ typedef struct ((SOURCE) == RCC_PLLSource_HSE_Div2)) #else #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ ((SOURCE) == RCC_PLLSource_PREDIV1)) #endif /* STM32F10X_CL */ @@ -141,10 +141,10 @@ typedef struct * @} */ -#ifdef STM32F10X_CL /** @defgroup PREDIV1_division_factor * @{ */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) @@ -170,6 +170,7 @@ typedef struct ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +#endif /** * @} */ @@ -178,17 +179,24 @@ typedef struct /** @defgroup PREDIV1_clock_source * @{ */ -/* PREDIV1 clock source (only for STM32 connectivity line devices) */ +#ifdef STM32F10X_CL +/* PREDIV1 clock source (for STM32 connectivity line devices) */ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ ((SOURCE) == RCC_PREDIV1_Source_PLL2)) +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/* PREDIV1 clock source (for STM32 Value line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) +#endif /** * @} */ - +#ifdef STM32F10X_CL /** @defgroup PREDIV2_division_factor * @{ */ @@ -368,6 +376,9 @@ typedef struct #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +/** + * @} + */ #else /** @defgroup USB_OTG_FS_clock_source * @{ @@ -377,10 +388,11 @@ typedef struct #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) -#endif /* STM32F10X_CL */ /** * @} */ +#endif /* STM32F10X_CL */ + #ifdef STM32F10X_CL /** @defgroup I2S2_clock_source @@ -496,8 +508,11 @@ typedef struct #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF80002) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ @@ -523,11 +538,13 @@ typedef struct #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) #define RCC_APB1Periph_USB ((uint32_t)0x00800000) #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC10137C0) == 0x00) && ((PERIPH) != 0x00)) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x810137C0) == 0x00) && ((PERIPH) != 0x00)) /** * @} @@ -628,8 +645,11 @@ void RCC_HSICmd(FunctionalState NewState); void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); void RCC_PLLCmd(FunctionalState NewState); -#ifdef STM32F10X_CL +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +#endif + +#ifdef STM32F10X_CL void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); void RCC_PLL2Config(uint32_t RCC_PLL2Mul); void RCC_PLL2Cmd(FunctionalState NewState); @@ -697,4 +717,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h index 1c76d58bf4..d0b1e5495f 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_rtc.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the RTC firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -131,4 +131,4 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h index 76736baf9d..72bf65389e 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_sdio.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the SDIO firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -527,4 +527,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h index 36fd845326..22e978145b 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_spi.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the SPI firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -49,32 +49,32 @@ typedef struct { uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be any combination of @ref SPI_data_direction */ + This parameter can be a value of @ref SPI_data_direction */ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be any combination of @ref SPI_mode */ + This parameter can be a value of @ref SPI_mode */ uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be any combination of @ref SPI_data_size */ + This parameter can be a value of @ref SPI_data_size */ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be any combination of @ref SPI_Clock_Polarity */ + This parameter can be a value of @ref SPI_Clock_Polarity */ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be any combination of @ref SPI_Clock_Phase */ + This parameter can be a value of @ref SPI_Clock_Phase */ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. - This parameter can be any combination of @ref SPI_Slave_Select_management */ + This parameter can be a value of @ref SPI_Slave_Select_management */ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. - This parameter can be any combination of @ref SPI_BaudRate_Prescaler. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. @note The communication clock is derived from the master clock. The slave clock does not need to be set. */ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be any combination of @ref SPI_MSB_LSB_transmission */ + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ }SPI_InitTypeDef; @@ -87,22 +87,22 @@ typedef struct { uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be any combination of @ref I2S_Mode */ + This parameter can be a value of @ref I2S_Mode */ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be any combination of @ref I2S_Standard */ + This parameter can be a value of @ref I2S_Standard */ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be any combination of @ref I2S_Data_Format */ + This parameter can be a value of @ref I2S_Data_Format */ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be any combination of @ref I2S_MCLK_Output */ + This parameter can be a value of @ref I2S_MCLK_Output */ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be any combination of @ref I2S_Audio_Frequency */ + This parameter can be a value of @ref I2S_Audio_Frequency */ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be any combination of @ref I2S_Clock_Polarity */ + This parameter can be a value of @ref I2S_Clock_Polarity */ }I2S_InitTypeDef; /** @@ -487,4 +487,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h index 6fa30b0ed7..de89ea64dd 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_tim.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the TIM firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -172,17 +172,44 @@ typedef struct ((PERIPH) == TIM5) || \ ((PERIPH) == TIM6) || \ ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15) || \ + ((PERIPH) == TIM16) || \ + ((PERIPH) == TIM17)) #define IS_TIM_18_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM8)) +#define IS_TIM_18151617_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15) || \ + ((PERIPH) == TIM16) || \ + ((PERIPH) == TIM17)) + #define IS_TIM_123458_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) + ((PERIPH) == TIM8)) + +#define IS_TIM_123458151617_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15) || \ + ((PERIPH) == TIM16) || \ + ((PERIPH) == TIM17)) + +#define IS_TIM_12345815_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)) /** * @} */ @@ -1037,4 +1064,4 @@ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h index 2c3ae4c2b5..bbf39eea26 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_usart.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the USART * firmware library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -51,7 +51,7 @@ typedef struct uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. The baud rate is computed using the following formula: - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_Word_Length */ @@ -382,6 +382,8 @@ void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); @@ -406,4 +408,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h index 2cd7ccdc9b..9828e1e3af 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_wwdg.h * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file contains all the functions prototypes for the WWDG firmware * library. ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -111,4 +111,4 @@ void WWDG_ClearFlag(void); * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c index fa3c212fa5..5ccce16e24 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file misc.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the miscellaneous firmware functions (add-on * to CMSIS functions). ****************************************************************************** @@ -16,7 +16,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -220,4 +220,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c index 412d9a923e..4528da7188 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_adc.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the ADC firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -1303,4 +1303,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c index f4970f18c8..a640868bae 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_bkp.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the BKP firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -308,4 +308,4 @@ void BKP_ClearITPendingBit(void) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c index 3e2aa23bc9..6e4723850a 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_can.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the CAN firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -987,4 +987,4 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c new file mode 100644 index 0000000000..1dd2ffdae8 --- /dev/null +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.c + * @author MCD Application Team + * @version V3.2.0 + * @date 03/01/2010 + * @brief This file provides all the CEC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

      © COPYRIGHT 2010 STMicroelectronics

      + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_cec.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/** @defgroup CEC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Defines + * @{ + */ + +/* ------------ CEC registers bit address in the alias region ----------- */ +#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) + +/* --- CFGR Register ---*/ + +/* Alias word address of PE bit */ +#define CFGR_OFFSET (CEC_OFFSET + 0x00) +#define PE_BitNumber 0x00 +#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) + +/* Alias word address of IE bit */ +#define IE_BitNumber 0x01 +#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TSOM bit */ +#define CSR_OFFSET (CEC_OFFSET + 0x10) +#define TSOM_BitNumber 0x00 +#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) + +/* Alias word address of TEOM bit */ +#define TEOM_BitNumber 0x01 +#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) + +#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + /* Enable CEC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + /* Release CEC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + + +/** + * @brief Initializes the CEC peripheral according to the specified + * parameters in the CEC_InitStruct. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that + * contains the configuration information for the specified + * CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); + assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); + + /*---------------------------- CEC CFGR Configuration -----------------*/ + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear BTEM and BPEM bits */ + tmpreg &= CFGR_CLEAR_Mask; + + /* Configure CEC: Bit Timing Error and Bit Period Error */ + tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); + + /* Write to CEC CFGR register*/ + CEC->CFGR = tmpreg; + +} + +/** + * @brief Enables or disables the specified CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; + + if(NewState == DISABLE) + { + /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ + while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) + { + } + } +} + +/** + * @brief Enables or disables the CEC interrupt. + * @param NewState: new state of the CEC interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + + /* Set the CEC own address */ + CEC->OAR = CEC_OwnAddress; +} + +/** + * @brief Sets the CEC prescaler value. + * @param CEC_Prescaler: CEC prescaler new value + * @retval None + */ +void CEC_SetPrescaler(uint16_t CEC_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); + + /* Set the Prescaler value*/ + CEC->PRES = CEC_Prescaler; +} + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendDataByte(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXD = Data ; +} + + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveDataByte(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXD); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; +} + +/** + * @brief Transmits message with or without an EOM bit. + * @param NewState: new state of the CEC Tx End Of Message. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_EndOfMessageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The data byte will be transmitted with or without an EOM bit*/ + *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; +} + +/** + * @brief Gets the CEC flag status + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_BTE: Bit Timing Error + * @arg CEC_FLAG_BPE: Bit Period Error + * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error + * @arg CEC_FLAG_SBE: Start Bit Error + * @arg CEC_FLAG_ACKE: Block Acknowledge Error + * @arg CEC_FLAG_LINE: Line Error + * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error + * @arg CEC_FLAG_TEOM: Tx End Of Message + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t cecreg = 0, cecbase = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Get the CEC peripheral base address */ + cecbase = (uint32_t)(CEC_BASE); + + /* Read flag register index */ + cecreg = CEC_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + CEC_FLAG &= FLAG_Mask; + + if(cecreg != 0) + { + /* Flag in CEC ESR Register */ + CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); + + /* Get the CEC ESR register address */ + cecbase += 0xC; + } + else + { + /* Get the CEC CSR register address */ + cecbase += 0x10; + } + + if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) + { + /* CEC_FLAG is set */ + bitstatus = SET; + } + else + { + /* CEC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CEC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC flags */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint8_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; + + /* Check the status of the specified CEC interrupt */ + if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC_IT is set */ + bitstatus = SET; + } + else + { + /* CEC_IT is reset */ + bitstatus = RESET; + } + /* Return the CEC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC interrupt pending bits */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c index d0c8d7a73f..13f07fc206 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_crc.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the CRC firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -160,4 +160,4 @@ uint8_t CRC_GetIDRegister(void) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c index f07e937cf6..eeb0d22e1e 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dac.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the DAC firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -194,6 +194,39 @@ void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) DAC->CR &= ~(CR_EN_Set << DAC_Channel); } } +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} +#endif /** * @brief Enables or disables the specified DAC channel DMA request. @@ -416,6 +449,121 @@ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) return (uint16_t) (*(__IO uint32_t*) tmp); } +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: thee selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's pending flags. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx’s interrupt pending bits. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} +#endif + /** * @} */ @@ -428,4 +576,4 @@ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c index 852f36527d..269d15195f 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dbgmcu.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the DBGMCU firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -116,7 +116,10 @@ uint32_t DBGMCU_GetDEVID(void) * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted * @param NewState: new state of the specified peripheral in Debug mode. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -149,4 +152,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c index f801b9bf11..cd8e43dd78 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dma.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the DMA firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -690,4 +690,4 @@ void DMA_ClearITPendingBit(uint32_t DMA_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c index 6963200a05..a79f575d68 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_exti.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the EXTI firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -265,4 +265,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c index ec194dc9c9..df2d494f42 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_flash.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the FLASH firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -77,8 +77,8 @@ #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /* Delay definition */ -#define EraseTimeout ((uint32_t)0x00000FFF) -#define ProgramTimeout ((uint32_t)0x0000000F) +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) /** * @} @@ -103,8 +103,7 @@ /** @defgroup FLASH_Private_FunctionPrototypes * @{ */ - -static void delay(void); + /** * @} */ @@ -264,18 +263,24 @@ FLASH_Status FLASH_EraseAllPages(void) /** * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes and then deactivates the Read - * protection. If the user needs to keep the Read protection activated, - * he has to enable it after this function call (using - * FLASH_ReadOutProtection function) + * @note This functions erases all option bytes except the Read protection + * (RDP). * @param None * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_EraseOptionBytes(void) { + uint16_t rdptmp = RDP_Key; + FLASH_Status status = FLASH_COMPLETE; - + + /* Get the actual read protection Option Byte value */ + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(EraseTimeout); if(status == FLASH_COMPLETE) @@ -297,8 +302,8 @@ FLASH_Status FLASH_EraseOptionBytes(void) /* Enable the Option Bytes Programming operation */ FLASH->CR |= CR_OPTPG_Set; - /* Disable the Read protection */ - OB->RDP= RDP_Key; + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(ProgramTimeout); @@ -582,7 +587,7 @@ FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) } } /* Return the protection operation Status */ - return status; + return status; } /** @@ -838,7 +843,6 @@ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for a Flash operation to complete or a TIMEOUT to occur */ while((status == FLASH_BUSY) && (Timeout != 0x00)) { - delay(); status = FLASH_GetStatus(); Timeout--; } @@ -850,19 +854,6 @@ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) return status; } -/** - * @brief Inserts a time delay. - * @param None - * @retval None - */ -static void delay(void) -{ - __IO uint32_t i = 0; - for(i = 0xFF; i != 0; i--) - { - } -} - /** * @} */ @@ -875,4 +866,4 @@ static void delay(void) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c index 9b7b077631..e5736872ea 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_fsmc.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the FSMC firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -855,4 +855,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c index 262992e0df..f2322a95d4 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_gpio.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the GPIO firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -57,7 +57,7 @@ /* --- MAPR Register ---*/ /* Alias word address of MII_RMII_SEL bit */ #define MAPR_OFFSET (AFIO_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) +#define MII_RMII_SEL_BitNumber ((u8)0x17) #define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) @@ -520,7 +520,12 @@ void GPIO_EventOutputCmd(FunctionalState NewState) * @arg GPIO_Remap_SWJ_Disable * @arg GPIO_Remap_SPI3 * @arg GPIO_Remap_TIM2ITR1_PTP_SOF - * @arg GPIO_Remap_PTP_PPS + * @arg GPIO_Remap_PTP_PPS + * @arg GPIO_Remap_TIM15 + * @arg GPIO_Remap_TIM16 + * @arg GPIO_Remap_TIM17 + * @arg GPIO_Remap_CEC + * @arg GPIO_Remap_TIM1_DMA * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. * @param NewState: new state of the port pin remapping. @@ -535,7 +540,14 @@ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) assert_param(IS_GPIO_REMAP(GPIO_Remap)); assert_param(IS_FUNCTIONAL_STATE(NewState)); - tmpreg = AFIO->MAPR; + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->MAPR2; + } + else + { + tmpreg = AFIO->MAPR; + } tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; tmp = GPIO_Remap & LSB_MASK; @@ -562,7 +574,14 @@ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); } - AFIO->MAPR = tmpreg; + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->MAPR2 = tmpreg; + } + else + { + AFIO->MAPR = tmpreg; + } } /** @@ -614,4 +633,4 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c index efcb211ee4..9fe53c3e03 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_i2c.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the I2C firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -360,7 +360,7 @@ void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) } /** - * @brief Specifies that the next DMA transfer is the last one. + * @brief Specifies if the next DMA transfer will be the last one. * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. * @param NewState: new state of the I2C DMA last transfer. * This parameter can be: ENABLE or DISABLE. @@ -885,16 +885,26 @@ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. * @param I2C_EVENT: specifies the event to be checked. * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2 - * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 - * @arg I2C_EVENT_MASTER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 * @retval An ErrorStatus enumuration value: * - SUCCESS: Last event is equal to the I2C_EVENT * - ERROR: Last event is different from the I2C_EVENT @@ -1149,4 +1159,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c index 11f6dbc0e3..f157ad5384 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_iwdg.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the IWDG firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -186,4 +186,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c index 2c8143b040..9066cdebf3 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_pwr.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the PWR firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -79,6 +79,8 @@ /* SLEEPDEEP bit mask */ #define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) +#define SysCtrl_SLEEPDEEP_Reset ((uint32_t)0xFFFFFFFB) + /** * @} */ @@ -230,6 +232,9 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) /* Request Wait For Event */ __WFE(); } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl &= SysCtrl_SLEEPDEEP_Reset; } /** @@ -308,4 +313,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c index c19915c789..55ae18dee6 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_rcc.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the RCC firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -124,10 +124,10 @@ #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) /* CFGR register bit mask */ -#ifndef STM32F10X_CL - #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) + #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) #else - #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) + #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) #endif /* STM32F10X_CL */ #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) @@ -147,10 +147,12 @@ /* CSR register bit mask */ #define CSR_RMVF_Set ((uint32_t)0x01000000) -#ifdef STM32F10X_CL +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) /* CFGR2 register bit mask */ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#endif +#ifdef STM32F10X_CL #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) @@ -242,10 +244,7 @@ void RCC_DeInit(void) /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; -#ifndef STM32F10X_CL - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#else +#ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */ RCC->CR &= (uint32_t)0xEBFFFFFF; @@ -254,7 +253,17 @@ void RCC_DeInit(void) /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; #endif /* STM32F10X_CL */ + } /** @@ -362,8 +371,8 @@ void RCC_HSICmd(FunctionalState NewState) * @brief Configures the PLL clock source and multiplication factor. * @note This function must be used only when the PLL is disabled. * @param RCC_PLLSource: specifies the PLL entry clock source. - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: + * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, + * this parameter can be one of the following values: * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry * For @b other_STM32_devices, this parameter can be one of the following values: @@ -406,16 +415,19 @@ void RCC_PLLCmd(FunctionalState NewState) *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; } -#ifdef STM32F10X_CL +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) /** * @brief Configures the PREDIV1 division factor. * @note * - This function must be used only when the PLL is disabled. - * - This function applies only to STM32 Connectivity line devices. + * - This function applies only to STM32 Connectivity line and Value line + * devices. * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. * This parameter can be one of the following values: * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock + * @note + * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. * This parameter can be RCC_PREDIV1_Divx where x:[1,16] * @retval None @@ -436,8 +448,9 @@ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) /* Store the new value */ RCC->CFGR2 = tmpreg; } +#endif - +#ifdef STM32F10X_CL /** * @brief Configures the PREDIV2 division factor. * @note @@ -906,6 +919,10 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) #ifdef STM32F10X_CL uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; #endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + uint32_t prediv1factor = 0; +#endif /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & CFGR_SWS_Mask; @@ -932,7 +949,13 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; } else - {/* HSE selected as PLL clock entry */ + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) {/* HSE oscillator clock divided by 2 */ RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; @@ -941,6 +964,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) { RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; } + #endif } #else pllmull = pllmull >> 18; @@ -1068,7 +1092,8 @@ void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3 + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17 * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1098,7 +1123,7 @@ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1156,6 +1181,7 @@ void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3 + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17 * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1185,7 +1211,7 @@ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1444,4 +1470,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c index 3bafe7ed12..559e3de300 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_rtc.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the RTC firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -338,4 +338,4 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c index e23372fcdd..46868b3655 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_sdio.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the SDIO firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -795,4 +795,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c index 427de6baba..004803d0c3 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_spi.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the SPI firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -904,4 +904,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c index b7daab9e78..10aa8dcd59 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_tim.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the TIM firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -224,12 +224,27 @@ void TIM_DeInit(TIM_TypeDef* TIMx) RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } else { - if (TIMx == TIM8) + if (TIMx == TIM17) { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); } } } @@ -245,13 +260,24 @@ void TIM_DeInit(TIM_TypeDef* TIMx) void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + /* Select the Counter Mode and set the clock division */ - TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; - TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision | - TIM_TimeBaseInitStruct->TIM_CounterMode; + if((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE) || + (((uint32_t) TIMx) == TIM2_BASE) || (((uint32_t) TIMx) == TIM3_BASE) || + (((uint32_t) TIMx) == TIM4_BASE) || (((uint32_t) TIMx) == TIM5_BASE)) + { + TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision | + TIM_TimeBaseInitStruct->TIM_CounterMode; + } + if((((uint32_t) TIMx) != TIM6_BASE) && (((uint32_t) TIMx) != TIM7_BASE)) + { + TIMx->CR1 &= CR1_CKD_Mask; + TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } /* Set the Autoreload value */ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; @@ -259,7 +285,9 @@ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseIn /* Set the Prescaler value */ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE)) + if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE) || + (((uint32_t) TIMx) == TIM15_BASE) || (((uint32_t) TIMx) == TIM16_BASE)|| + (((uint32_t) TIMx) == TIM17_BASE)) { /* Set the Repetition Counter value */ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; @@ -282,7 +310,7 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); @@ -310,8 +338,10 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Set the Output State */ tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) + + if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)|| + ((uint32_t) TIMx == TIM15_BASE)||((uint32_t) TIMx == TIM16_BASE)|| + ((uint32_t) TIMx == TIM17_BASE)) { assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); @@ -342,8 +372,8 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } @@ -361,7 +391,7 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); @@ -375,9 +405,9 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; - + /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask; + tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask; /* Select the Output Compare Mode */ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); @@ -456,7 +486,7 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= CCMR_OC13M_Mask & CCMR_CC13S_Mask; + tmpccmrx &= CCMR_OC13M_Mask & CCMR_CC13S_Mask; /* Select the Output Compare Mode */ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; @@ -468,7 +498,7 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - + if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) { assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); @@ -535,8 +565,8 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask; - + tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask; + /* Select the Output Compare Mode */ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); @@ -580,7 +610,6 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); @@ -589,6 +618,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) { + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); /* TI1 Configuration */ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, @@ -598,6 +628,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) } else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) { + assert_param(IS_TIM_12345815_PERIPH(TIMx)); /* TI2 Configuration */ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, @@ -607,6 +638,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) } else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) { + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); /* TI3 Configuration */ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, @@ -616,6 +648,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) } else { + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); /* TI4 Configuration */ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, @@ -638,7 +671,7 @@ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) uint16_t icoppositepolarity = TIM_ICPolarity_Rising; uint16_t icoppositeselection = TIM_ICSelection_DirectTI; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); /* Select the Opposite Input Polarity */ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) { @@ -694,7 +727,7 @@ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) { /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_18151617_PERIPH(TIMx)); assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); @@ -813,7 +846,7 @@ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_18151617_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { @@ -914,7 +947,7 @@ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); /* Set the DMA Base and the DMA Burst Length */ @@ -964,7 +997,7 @@ void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewSt void TIM_InternalClockConfig(TIM_TypeDef* TIMx) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); /* Disable slave mode to clock the prescaler directly with the internal clock */ TIMx->SMCR &= SMCR_SMS_Mask; } @@ -983,7 +1016,7 @@ void TIM_InternalClockConfig(TIM_TypeDef* TIMx) void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); /* Select the Internal Trigger */ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); @@ -1011,7 +1044,7 @@ void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSo uint16_t TIM_ICPolarity, uint16_t ICFilter) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); assert_param(IS_TIM_IC_FILTER(ICFilter)); @@ -1205,7 +1238,7 @@ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) { uint16_t tmpsmcr = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; @@ -1244,7 +1277,7 @@ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, uint16_t tmpccer = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); @@ -1293,7 +1326,7 @@ void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr1 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC1M Bits */ @@ -1317,7 +1350,7 @@ void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr1 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC2M Bits */ @@ -1410,7 +1443,7 @@ void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_18151617_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { @@ -1434,7 +1467,7 @@ void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { @@ -1458,7 +1491,7 @@ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_18151617_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { @@ -1485,7 +1518,7 @@ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr1 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC1PE Bit */ @@ -1509,7 +1542,7 @@ void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr1 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC2PE Bit */ @@ -1581,7 +1614,7 @@ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr1 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; @@ -1606,7 +1639,7 @@ void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr1 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; @@ -1777,7 +1810,7 @@ void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC1P Bit */ @@ -1800,7 +1833,7 @@ void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_18151617_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; @@ -1824,7 +1857,7 @@ void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC2P Bit */ @@ -1947,7 +1980,7 @@ void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) uint16_t tmp = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_Channel)); assert_param(IS_TIM_CCX(TIM_CCx)); @@ -1977,7 +2010,7 @@ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) uint16_t tmp = 0; /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_18151617_PERIPH(TIMx)); assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); assert_param(IS_TIM_CCXN(TIM_CCxN)); @@ -2019,7 +2052,7 @@ void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode uint16_t tmp1 = 0; /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_Channel)); assert_param(IS_TIM_OCM(TIM_OCMode)); @@ -2115,7 +2148,7 @@ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { @@ -2196,7 +2229,7 @@ void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); /* Reset the SMS Bits */ TIMx->SMCR &= SMCR_SMS_Mask; @@ -2217,7 +2250,7 @@ void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); /* Reset the MSM Bit */ TIMx->SMCR &= SMCR_MSM_Reset; @@ -2263,7 +2296,7 @@ void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); /* Set the Capture Compare1 Register value */ TIMx->CCR1 = Compare1; } @@ -2277,7 +2310,7 @@ void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); /* Set the Capture Compare2 Register value */ TIMx->CCR2 = Compare2; } @@ -2324,7 +2357,7 @@ void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC1PSC Bits */ TIMx->CCMR1 &= CCMR_IC13PSC_Mask; @@ -2346,7 +2379,7 @@ void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC2PSC Bits */ TIMx->CCMR1 &= CCMR_IC24PSC_Mask; @@ -2411,7 +2444,7 @@ void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); assert_param(IS_TIM_CKD_DIV(TIM_CKD)); /* Reset the CKD Bits */ TIMx->CR1 &= CR1_CKD_Mask; @@ -2427,7 +2460,7 @@ void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_123458151617_PERIPH(TIMx)); /* Get the Capture 1 Register value */ return TIMx->CCR1; } @@ -2440,7 +2473,7 @@ uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) { /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_12345815_PERIPH(TIMx)); /* Get the Capture 2 Register value */ return TIMx->CCR2; } @@ -2796,4 +2829,4 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c index 0e642d4b3f..c23a51d48f 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_usart.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the USART firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -79,6 +79,14 @@ #define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ #define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ +/* USART OverSampling-8 Mask */ +#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ +#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ + /** * @} */ @@ -230,12 +238,33 @@ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) { apbclock = RCC_ClocksStatus.PCLK1_Frequency; } + /* Determine the integer part */ - integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate))); - tmpreg = (integerdivider / 0x64) << 0x04; + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + /* Determine the fractional part */ - fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04)); - tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((uint8_t)0x0F); + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + /* Write to USART BRR */ USARTx->BRR = (uint16_t)tmpreg; } @@ -713,6 +742,64 @@ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) } } + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling methode. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= CR1_OVER8_Set; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= CR1_OVER8_Reset; + } +} + +/** + * @brief Enables or disables the USART's one bit sampling methode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling methode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= CR3_ONEBITE_Set; + } + else + { + /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= CR3_ONEBITE_Reset; + } +} + /** * @brief Configures the USART’s IrDA interface. * @param USARTx: Select the USART or the UART peripheral. @@ -964,4 +1051,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c index e5b74afa8d..7805d3c050 100644 --- a/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c +++ b/bsp/stm32_radio/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_wwdg.c * @author MCD Application Team - * @version V3.1.2 - * @date 09/28/2009 + * @version V3.2.0 + * @date 03/01/2010 * @brief This file provides all the WWDG firmware functions. ****************************************************************************** * @copy @@ -15,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

      © COPYRIGHT 2009 STMicroelectronics

      + *

      © COPYRIGHT 2010 STMicroelectronics

      */ /* Includes ------------------------------------------------------------------*/ @@ -220,4 +220,4 @@ void WWDG_ClearFlag(void) * @} */ -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32_radio/board.c b/bsp/stm32_radio/board.c index 33bbb98cb7..ac30a6c8d5 100644 --- a/bsp/stm32_radio/board.c +++ b/bsp/stm32_radio/board.c @@ -206,7 +206,7 @@ void rt_hw_board_init() NVIC_Configuration(); /* Configure the SysTick */ - SysTick_Config( SystemFrequency_SysClk / RT_TICK_PER_SECOND ); + SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND ); /* Console Initialization*/ rt_hw_usart_init(); @@ -220,17 +220,17 @@ void rt_hw_board_init() /* memtest */ { - unsigned char * p_extram = (unsigned char *)0x68000000; + unsigned char * p_extram = (unsigned char *)STM32_EXT_SRAM_BEGIN; unsigned int temp; rt_kprintf("\r\nmem testing...."); - for(temp=0; temp<0x80000; temp++) + for(temp=0; temp<(STM32_EXT_SRAM_END-STM32_EXT_SRAM_BEGIN); temp++) { *p_extram++ = (unsigned char)temp; } - p_extram = (unsigned char *)0x68000000; - for(temp=0; temp<0x80000; temp++) + p_extram = (unsigned char *)STM32_EXT_SRAM_BEGIN; + for(temp=0; temp<(STM32_EXT_SRAM_END-STM32_EXT_SRAM_BEGIN); temp++) { if( *p_extram++ != (unsigned char)temp ) { diff --git a/bsp/stm32_radio/board.h b/bsp/stm32_radio/board.h index 5adb58e2e2..9406283eae 100644 --- a/bsp/stm32_radio/board.h +++ b/bsp/stm32_radio/board.h @@ -46,7 +46,7 @@ // <1=>Version 1:fmt0371 // <2=>Version 2:ili9320/9325 // Default: 1 -#define LCD_VERSION 1 +#define LCD_VERSION 2 /* * IMPORTANT NOTICE: diff --git a/bsp/stm32_radio/project.Uv2 b/bsp/stm32_radio/project.Uv2 index 43a7277e30..2ee4fc2dc3 100644 --- a/bsp/stm32_radio/project.Uv2 +++ b/bsp/stm32_radio/project.Uv2 @@ -101,8 +101,8 @@ File 5,1,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_int.c> File 5,1,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_mem.c> File 5,1,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_regs.c> File 5,1,<.\Libraries\STM32_USB-FS-Device_Driver\src\usb_sil.c> -File 6,1,<.\Libraries\CMSIS\Core\CM3\core_cm3.c> -File 6,1,<.\Libraries\CMSIS\Core\CM3\system_stm32f10x.c> +File 6,1,<.\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c> +File 6,1,<.\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c> File 7,1,<..\..\finsh\finsh_compiler.c> File 7,1,<..\..\finsh\finsh_error.c> File 7,1,<..\..\finsh\finsh_heap.c> @@ -248,8 +248,8 @@ Options 1,0,0 // Target 'RT-Thread STM32 Radio' EnvBin () EnvInc () EnvLib () - EnvReg (ÿST\STM32F10x\) - OrgReg (ÿST\STM32F10x\) + EnvReg (ST\STM32F10x\) + OrgReg (ST\STM32F10x\) TgStat=16 OutDir (.\obj\) OutName (rtthread-stm32) @@ -284,7 +284,7 @@ Options 1,0,0 // Target 'RT-Thread STM32 Radio' ADSCMISC (--diag_suppress=870) ADSCDEFN (USE_STDPERIPH_DRIVER, STM32F10X_HD,) ADSCUDEF () - ADSCINCD (.;.\Libraries\STM32F10x_StdPeriph_Driver\inc;.\Libraries\CMSIS\Core\CM3;..\..\include;..\..\libcpu\arm\stm32;..\..\finsh;..\..\net\lwip\src;..\..\net\lwip\src\include;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include;..\..\rtgui\include;..\..\rtgui\common\libz) + ADSCINCD (.;.\Libraries\CMSIS\CM3\CoreSupport;.\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;.\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\include;..\..\libcpu\arm\stm32;..\..\finsh;..\..\net\lwip\src;..\..\net\lwip\src\include;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include;..\..\rtgui\include;..\..\rtgui\common\libz) ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ADSAMISC () ADSADEFN () @@ -312,7 +312,7 @@ Options 1,0,0 // Target 'RT-Thread STM32 Radio' OPTDBG 49142,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()() FLASH1 { 1,0,0,0,1,0,0,0,6,16,0,0,0,0,0,0,0,0,0,0 } FLASH2 (Segger\JL2CM3.dll) - FLASH3 ("" ()) + FLASH3 () FLASH4 () EndOpt -- GitLab