diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c
index d74ab47e23394f5e4fc9c7987b68c12293a6b50f..1f4a98c57cd86c9c8d38b59ea5174060d6761c52 100644
--- a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c
+++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c
@@ -33,7 +33,6 @@
  */
 
 #include "fsl_flexspi.h"
-
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.flexspi"
@@ -113,21 +112,21 @@ static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT];
 #endif
 
 /*! @brief Pointers to flexspi bases for each instance. */
-static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
+static FLEXSPI_Type *const s_flexspiBases[] SECTION("itcm") = FLEXSPI_BASE_PTRS;
 
 /*! @brief Pointers to flexspi IRQ number for each instance. */
-static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS;
+static const IRQn_Type s_flexspiIrqs[] SECTION("itcm") = FLEXSPI_IRQS;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Clock name array */
-static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS;
+static const clock_ip_name_t s_flexspiClock[] SECTION("itcm") = FLEXSPI_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
  ******************************************************************************/
 
-uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
+SECTION("itcm") uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
 {
     uint32_t instance;
 
@@ -145,7 +144,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
     return instance;
 }
 
-static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
+SECTION("itcm") static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
 {
     bool isUnifiedConfig = true;
     uint32_t flexspiDllValue;
@@ -199,7 +198,7 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t
     return flexspiDllValue;
 }
 
-status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
+SECTION("itcm") status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
 {
     status_t result = kStatus_Success;
 
@@ -236,7 +235,7 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
     return result;
 }
 
-void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
+SECTION("itcm") void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
 {
     uint32_t configValue = 0;
     uint8_t i = 0;
@@ -309,7 +308,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
     base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1);
 }
 
-void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
+SECTION("itcm") void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
 {
     config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
     config->enableSckFreeRunning = false;
@@ -339,13 +338,13 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
     config->ahbConfig.enableAHBCachable = false;
 }
 
-void FLEXSPI_Deinit(FLEXSPI_Type *base)
+SECTION("itcm") void FLEXSPI_Deinit(FLEXSPI_Type *base) 
 {
     /* Reset peripheral. */
     FLEXSPI_SoftwareReset(base);
 }
 
-void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
+SECTION("itcm") void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
 {
     uint32_t configValue = 0;
     uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */
@@ -416,7 +415,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
     base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
 }
 
-void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
+SECTION("itcm") void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
 {
     assert(index < 64U);
 
@@ -443,7 +442,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
     base->LUTCR = 0x01;
 }
 
-status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
+SECTION("itcm") status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
 {
     uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1;
     uint32_t status;
@@ -491,7 +490,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size
     return result;
 }
 
-status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
+SECTION("itcm") status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
 {
     uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1;
     uint32_t status;
@@ -561,7 +560,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
     return result;
 }
 
-status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
+SECTION("itcm") status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
 {
     uint32_t configValue = 0;
     status_t result = kStatus_Success;
@@ -618,7 +617,7 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
     return result;
 }
 
-void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
+SECTION("itcm") void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
                                   flexspi_handle_t *handle,
                                   flexspi_transfer_callback_t callback,
                                   void *userData)
@@ -643,7 +642,7 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
     EnableIRQ(s_flexspiIrqs[instance]);
 }
 
-status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
+SECTION("itcm") status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
 {
     uint32_t configValue = 0;
     status_t result = kStatus_Success;
@@ -709,7 +708,7 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl
     return result;
 }
 
-status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
+SECTION("itcm") status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
 {
     assert(handle);
 
@@ -727,7 +726,7 @@ status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle,
     return result;
 }
 
-void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
+SECTION("itcm") void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
 {
     assert(handle);
 
@@ -735,7 +734,7 @@ void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
     handle->state = kFLEXSPI_Idle;
 }
 
-void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
+SECTION("itcm") void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
 {
     uint8_t status;
     status_t result;
@@ -832,7 +831,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
 
 #if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
 #if defined(FLEXSPI)
-void FLEXSPI_DriverIRQHandler(void)
+SECTION("itcm") void FLEXSPI_DriverIRQHandler(void)
 {
     FLEXSPI_TransferHandleIRQ(FLEXSPI, s_flexspiHandle[0]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -844,7 +843,7 @@ void FLEXSPI_DriverIRQHandler(void)
 #endif
 
 #if defined(FLEXSPI0)
-void FLEXSPI0_DriverIRQHandler(void)
+void FLEXSPI0_DriverIRQHandler(void) SECTION("itcm")
 {
     FLEXSPI_TransferHandleIRQ(FLEXSPI0, s_flexspiHandle[0]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -855,7 +854,7 @@ void FLEXSPI0_DriverIRQHandler(void)
 }
 #endif
 #if defined(FLEXSPI1)
-void FLEXSPI1_DriverIRQHandler(void)
+void FLEXSPI1_DriverIRQHandler(void) SECTION("itcm")
 {
     FLEXSPI_TransferHandleIRQ(FLEXSPI1, s_flexspiHandle[1]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h
index e2f00393b3dff3b7569a19d81cc4688050574db8..b1162924f90e5f9786dc53791e25a5653bf5c526 100644
--- a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h
+++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h
@@ -34,7 +34,7 @@
 
 #ifndef __FSL_FLEXSPI_H_
 #define __FSL_FLEXSPI_H_
-
+#include <rtthread.h>
 #include <stddef.h>
 #include "fsl_device_registers.h"
 #include "fsl_common.h"
@@ -401,7 +401,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
  *
  * @param base FLEXSPI peripheral base address.
  */
-static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
+static SECTION("itcm") inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
 {
     base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
     while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
@@ -415,7 +415,7 @@ static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param enable True means enable FLEXSPI, false means disable.
  */
-static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -439,7 +439,7 @@ static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
  * @param base FLEXSPI peripheral base address.
  * @param mask FLEXSPI interrupt source.
  */
-static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
 {
     base->INTEN |= mask;
 }
@@ -450,7 +450,7 @@ static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
  * @param base FLEXSPI peripheral base address.
  * @param mask FLEXSPI interrupt source.
  */
-static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
 {
     base->INTEN &= ~mask;
 }
@@ -466,7 +466,7 @@ static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
  * @param base FLEXSPI peripheral base address.
  * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable.
  */
-static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -484,7 +484,7 @@ static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
  * @param base FLEXSPI peripheral base address.
  * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable.
  */
-static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -502,7 +502,7 @@ static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
  * @param base FLEXSPI peripheral base address.
  * @retval The tx fifo address.
  */
-static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
 {
     return (uint32_t)&base->TFDR[0];
 }
@@ -513,7 +513,7 @@ static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @retval The rx fifo address.
  */
-static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
 {
     return (uint32_t)&base->RFDR[0];
 }
@@ -529,7 +529,7 @@ static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
  * @param txFifo Pass true to reset TX FIFO.
  * @param rxFifo Pass true to reset RX FIFO.
  */
-static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
+static SECTION("itcm") inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
 {
     if (txFifo)
     {
@@ -550,7 +550,7 @@ static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFi
  * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
  *      Pass NULL if this value is not required.
  */
-static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
+static SECTION("itcm") inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
 {
     if (txCount)
     {
@@ -574,7 +574,7 @@ static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, si
  * @param base FLEXSPI peripheral base address.
  * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status.
  */
-static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
 {
     return base->INTR;
 }
@@ -585,7 +585,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param interrupt status flag.
  */
-static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
 {
     base->INTR |= mask;
 }
@@ -616,7 +616,7 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por
  * @param base FLEXSPI peripheral base address.
  * @retval trigger source of current command sequence.
  */
-static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
+static SECTION("itcm") inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
 {
     return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT);
 }
@@ -627,7 +627,7 @@ static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FL
  * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
  * @retval error code when IP command error detected.
  */
-static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+static SECTION("itcm") inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
 {
     *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT;
     return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT);
@@ -639,7 +639,7 @@ static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type
  * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
  * @retval error code when AHB command error detected.
  */
-static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+static SECTION("itcm") inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
 {
     *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
     return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >>
@@ -652,7 +652,7 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty
  * @retval true Bus is idle.
  * @retval false Bus is busy.
  */
-static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
+static SECTION("itcm") inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
 {
     return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK);
 }
@@ -668,7 +668,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param enable True means enable parallel mode, false means disable parallel mode.
  */
-static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -685,7 +685,7 @@ static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
  * @param base FLEXSPI peripheral base address.
  * @param enable True means enable parallel mode, false means disable parallel mode.
  */
-static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
 {
     if (enable)
     {
@@ -715,7 +715,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
  * @param data The data bytes to send
  * @param fifoIndex Destination fifo index.
  */
-static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
+static SECTION("itcm") inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
 {
     base->TFDR[fifoIndex] = data;
 }
@@ -727,7 +727,7 @@ static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t
  * @param fifoIndex Source fifo index.
  * @return The data in the FIFO.
  */
-static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
+static SECTION("itcm") inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
 {
     return base->RFDR[fifoIndex];
 }
diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
index fa1b4693f54cf346148dcbe5d1fc7e9b57092442..d22ab2b10a602061c5444efcecbbb5a587f917d9 100644
--- a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
@@ -11,7 +11,13 @@ drv_cache.c
 CPPPATH = [cwd]
 CPPDEFINES = []
 
-# add sdram driver code
+if GetDepend('BOARD_USING_QSPIFLASH'):
+    src += ['drv_flexspi_nor.c'] 
+
+if GetDepend('BOARD_USING_HYPERFLASH'):
+    src += ['drv_flexspi_hyper.c'] 
+    
+# add sdram driver code 
 if GetDepend('RT_USING_SDRAM'):
     src = src + ['drv_sdram.c'] 
 
@@ -21,7 +27,7 @@ if GetDepend('RT_USING_PIN'):
 
 # add rtc driver code
 if GetDepend('RT_USING_RTC_HP'):
-    src = src + ['drv_rtc.c'] 
+    src += ['drv_rtc.c'] 
 
 # add spibus driver code
 if GetDepend('RT_USING_SPI'):
diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi.h
new file mode 100644
index 0000000000000000000000000000000000000000..83291c8275c7a6bfb8eb1bbc5a3531b095f7b3f2
--- /dev/null
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi.h
@@ -0,0 +1,18 @@
+#ifndef __DRV_FLEXSPI_H__
+#define __DRV_FLEXSPI_H__
+#include "fsl_flexspi.h"
+#include "fsl_common.h"
+#ifdef BOARD_USING_QSPIFLASH
+#define FLASH_SIZE 0x8000 /* 256Mb/KByte */
+#define FLASH_PAGE_SIZE 256
+#define FLEXSPI_NOR_SECTOR_SIZE 0x1000 /* 4K */
+#elif defined(BOARD_USING_HYPERFLASH)
+#define FLASH_SIZE 0x10000 /* 512Mb/KByte */
+#define FLASH_PAGE_SIZE 512
+#define FLEXSPI_NOR_SECTOR_SIZE 0x40000 /* 256K */
+#endif
+#define FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE
+extern int      rt_hw_flexspi_init(void);
+extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address);
+extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src);
+#endif
diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c
new file mode 100644
index 0000000000000000000000000000000000000000..124ec5cce133ef902a161ce2e17ce915dec69288
--- /dev/null
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c
@@ -0,0 +1,464 @@
+/*
+ * File      : code_run.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERsrcANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * srcange Logs:
+ * Date           Author       Notes
+ * 2018-07-05     ZYH    the first version
+ */
+
+#include <rtthread.h>
+#define PRINTF rt_kprintf
+#include "board.h"
+#include <rthw.h>
+#include "drv_flexspi.h"
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[Hyper]"
+#define DBG_LEVEL         DBG_LOG
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#define FLEXSPI_CLOCK kCLOCK_FlexSpi
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
+#define CUSTOM_LUT_LENGTH 48
+
+static flexspi_device_config_t deviceconfig = {
+    .flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */
+    .isSck2Enabled = false,
+    .flashSize = FLASH_SIZE,
+    .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval = 2,
+    .CSHoldTime = 0,
+    .CSSetupTime = 3,
+    .dataValidTime = 1,
+    .columnspace = 3,
+    .enableWordAddress = true,
+    .AWRSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA,
+    .AWRSeqNumber = 1,
+    .ARDSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA,
+    .ARDSeqNumber = 1,
+    .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 20,
+};
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
+        /* Read Data */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
+
+        /* Write Data */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
+        /* Read Status */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
+
+        /* Write Enable */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+
+        /* Erase Sector  */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+        /* program page */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
+};
+
+
+
+SECTION("itcm") status_t flexspi_nor_hyperbus_read(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    flashXfer.deviceAddress = addr * 2;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA;
+    flashXfer.data = buffer;
+    flashXfer.dataSize = bytes;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_hyperbus_write(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    flashXfer.deviceAddress = addr * 2;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA;
+    flashXfer.data = buffer;
+    flashXfer.dataSize = bytes;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    /* Write neable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) 
+{
+    /* Wait status ready. */
+    bool isBusy;
+    uint32_t readValue;
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
+    flashXfer.data = &readValue;
+    flashXfer.dataSize = 2;
+
+    do
+    {
+        status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+        if (readValue & 0x8000)
+        {
+            isBusy = false;
+        }
+        else
+        {
+            isBusy = true;
+        }
+
+        if (readValue & 0x3200)
+        {
+            status = kStatus_Fail;
+            break;
+        }
+
+    } while (isBusy);
+
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) 
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    /* Write enable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 4;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return status;
+}
+
+ SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    /* Prepare page program command */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = FLASH_PAGE_SIZE;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_hyperflash_cfi(FLEXSPI_Type *base)
+{
+    /*
+     * Read ID-CFI Parameters
+     */
+    // CFI Entry
+    status_t status;
+    uint32_t buffer[2];
+    uint32_t data = 0x9800;
+    status = flexspi_nor_hyperbus_write(base, 0x555, &data, 2);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    // ID-CFI Read
+    // Read Query Unique ASCII String
+    status = flexspi_nor_hyperbus_read(base, 0x10, &buffer[0], sizeof(buffer));
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    buffer[1] &= 0xFFFF;
+    // Check that the data read out is  unicode "QRY" in big-endian order
+    if ((buffer[0] != 0x52005100) || (buffer[1] != 0x5900))
+    {
+        status = kStatus_Fail;
+        return status;
+    }
+    // ASO Exit
+    data = 0xF000;
+    status = flexspi_nor_hyperbus_write(base, 0x0, &data, 2);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+SECTION("itcm") int rt_hw_flexspi_init(void)
+{
+    flexspi_config_t config;
+    status_t status;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    // Set flexspi root clock to 166MHZ.
+    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
+
+    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26);   /* Set PLL3 PFD0 clock 332MHZ. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
+    
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);   /* flexspi clock 83M, DDR mode, internal clock 42M. */
+
+    
+    /*Get FLEXSPI default settings and configure the flexspi. */
+    FLEXSPI_GetDefaultConfig(&config);
+
+    /*Set AHB buffer size for reading data through AHB bus. */
+    config.ahbConfig.enableAHBPrefetch = true;
+    /*Allow AHB read start address do not follow the alignment requirement. */
+    config.ahbConfig.enableReadAddressOpt = true;
+    /* enable diff clock and DQS */
+    config.enableSckBDiffOpt = true;
+    config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
+    config.enableCombination = true;
+    FLEXSPI_Init(FLEXSPI, &config);
+    
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+    
+    /* Update LUT table. */
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    status = flexspi_nor_hyperflash_cfi(FLEXSPI);
+    /* Get vendor ID. */
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return 0;
+}
+INIT_PREV_EXPORT(rt_hw_flexspi_init);
diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c
new file mode 100644
index 0000000000000000000000000000000000000000..af8247cd8846f89ffc226fbc2ba3e16f5476263f
--- /dev/null
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c
@@ -0,0 +1,388 @@
+/*
+ * File      : code_run.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERsrcANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * srcange Logs:
+ * Date           Author       Notes
+ * 2018-07-05     ZYH    the first version
+ */
+#include <rtthread.h>
+#define PRINTF rt_kprintf
+#include "board.h"
+#include <rthw.h>
+#include "drv_flexspi.h"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[FLEXSPI]"
+#define DBG_LEVEL         DBG_LOG
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#define FLEXSPI_CLOCK kCLOCK_FlexSpi
+#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 1
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 3
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 4
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
+#define NOR_CMD_LUT_SEQ_IDX_READID 8
+#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9
+#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
+#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12
+#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 13
+#define CUSTOM_LUT_LENGTH 60
+#define FLASH_BUSY_STATUS_POL 1
+#define FLASH_BUSY_STATUS_OFFSET 0
+
+static flexspi_device_config_t deviceconfig =
+{
+    .flexspiRootClk = 100000000,
+    .flashSize = FLASH_SIZE,
+    .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval = 2,
+    .CSHoldTime = 3,
+    .CSSetupTime = 3,
+    .dataValidTime = 0,
+    .columnspace = 0,
+    .enableWordAddress = 0,
+    .AWRSeqIndex = 0,
+    .AWRSeqNumber = 0,
+    .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD,
+    .ARDSeqNumber = 1,
+    .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 0,
+};
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] =
+{
+    /* Normal read mode -SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Fast read mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Fast read quad mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x6B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),
+
+    /* Read extend parameters */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Write Enable */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Erase Sector  */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+
+    /* Page Program - single mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Page Program - quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read ID */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READID] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xAB, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Enable Quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Enter QPI mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x38, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Exit QPI mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xFF, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read status register */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Erase Chip */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+};
+
+
+
+SECTION("itcm") static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+
+    /* Write neable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base)
+{
+    /* Wait status ready. */
+    bool isBusy;
+    uint32_t readValue;
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
+    flashXfer.data = &readValue;
+    flashXfer.dataSize = 1;
+
+    do
+    {
+        status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+        if (FLASH_BUSY_STATUS_POL)
+        {
+            if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
+            {
+                isBusy = true;
+            }
+            else
+            {
+                isBusy = false;
+            }
+        }
+        else
+        {
+            if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
+            {
+                isBusy = false;
+            }
+            else
+            {
+                isBusy = true;
+            }
+        }
+
+    }
+    while (isBusy);
+
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    uint32_t writeValue = 0x40;
+
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, 0);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Enable quad mode. */
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
+    flashXfer.data = &writeValue;
+    flashXfer.dataSize = 1;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    /* Write enable */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Prepare page program command */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = FLASH_PAGE_SIZE;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId)
+{
+    uint32_t temp;
+    flexspi_transfer_t flashXfer;
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID;
+    flashXfer.data = &temp;
+    flashXfer.dataSize = 1;
+
+    status_t status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    *vendorId = temp;
+
+    return status;
+}
+
+SECTION("itcm") int rt_hw_flexspi_init(void)
+{
+    flexspi_config_t config;
+    status_t status;
+    uint8_t vendorID = 0;
+
+    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24);   /* Set PLL3 PFD0 clock 360MHZ. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);   /* flexspi clock 120M. */
+
+    dbg_log(DBG_INFO, "NorFlash Init\r\n");
+
+    FLEXSPI_GetDefaultConfig(&config);
+
+    config.ahbConfig.enableAHBPrefetch = true;
+    FLEXSPI_Init(FLEXSPI, &config);
+
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    status = flexspi_nor_get_vendor_id(FLEXSPI, &vendorID);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    dbg_log(DBG_INFO, "Vendor ID: 0x%x\r\n", vendorID);
+
+    status = flexspi_nor_enable_quad_mode(FLEXSPI);
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "Entry Quad mode failed\r\n");
+        return status;
+    }
+    dbg_log(DBG_INFO, "NorFlash Init Done\r\n");
+    rt_hw_interrupt_enable(level);
+    return 0;
+}
+INIT_PREV_EXPORT(rt_hw_flexspi_init);
diff --git a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf
index 5e0834cd48fab619722b8e6734afcb45684f4e3e..268ea3642ee1008493f72cd6c350f9850c39cf4a 100644
--- a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf
+++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf
@@ -122,4 +122,13 @@ LR_IROM1 m_text_start m_text_size
         * (NonCacheable.init)
         * (NonCacheable)
     }
+  ITCM 0x400 0xFBFF {
+		;drv_flexspi_hyper.o(+RO)
+		;fsl_flexspi.o(+RO)
+		* (*CLOCK_DisableClock)
+		* (*CLOCK_ControlGate)
+		* (*CLOCK_EnableClock)
+		* (*CLOCK_SetDiv)
+		* (itcm)
+	}
 }
diff --git a/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf b/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf
index 5e0834cd48fab619722b8e6734afcb45684f4e3e..268ea3642ee1008493f72cd6c350f9850c39cf4a 100644
--- a/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf
+++ b/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf
@@ -122,4 +122,13 @@ LR_IROM1 m_text_start m_text_size
         * (NonCacheable.init)
         * (NonCacheable)
     }
+  ITCM 0x400 0xFBFF {
+		;drv_flexspi_hyper.o(+RO)
+		;fsl_flexspi.o(+RO)
+		* (*CLOCK_DisableClock)
+		* (*CLOCK_ControlGate)
+		* (*CLOCK_EnableClock)
+		* (*CLOCK_SetDiv)
+		* (itcm)
+	}
 }