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体验新版 GitCode,发现更多精彩内容 >>
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9b750eba
编写于
8月 23, 2022
作者:
L
liyangyang
提交者:
mysterywolf
8月 22, 2022
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电子邮件补丁
差异文件
libcpu 支持 ch32v3系列单片机
上级
a02ab79f
变更
5
显示空白变更内容
内联
并排
Showing
5 changed file
with
666 addition
and
0 deletion
+666
-0
libcpu/risc-v/ch32v3/SConscript
libcpu/risc-v/ch32v3/SConscript
+16
-0
libcpu/risc-v/ch32v3/context_gcc.S
libcpu/risc-v/ch32v3/context_gcc.S
+214
-0
libcpu/risc-v/ch32v3/cpuport.c
libcpu/risc-v/ch32v3/cpuport.c
+197
-0
libcpu/risc-v/ch32v3/cpuport.h
libcpu/risc-v/ch32v3/cpuport.h
+44
-0
libcpu/risc-v/ch32v3/interrupt_gcc.S
libcpu/risc-v/ch32v3/interrupt_gcc.S
+195
-0
未找到文件。
libcpu/risc-v/ch32v3/SConscript
0 → 100644
浏览文件 @
9b750eba
# RT-Thread building script for component
from
building
import
*
Import
(
'rtconfig'
)
cwd
=
GetCurrentDir
()
src
=
Glob
(
'*.c'
)
+
Glob
(
'*.cpp'
)
CPPPATH
=
[
cwd
]
if
rtconfig
.
PLATFORM
==
'gcc'
:
src
+=
Glob
(
'*_gcc.S'
)
group
=
DefineGroup
(
'cpu'
,
src
,
depend
=
[
''
],
CPPPATH
=
CPPPATH
)
Return
(
'group'
)
libcpu/risc-v/ch32v3/context_gcc.S
0 → 100644
浏览文件 @
9b750eba
/*
*
Copyright
(
c
)
2006
-
2018
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
*
Change
Logs
:
*
Date
Author
Notes
*
2021
-
09
-
09
WCH
the
first
version
*/
#include "cpuport.h"
/*
*
#
ifdef
RT_USING_SMP
*
void
rt_hw_context_switch_to
(
rt_ubase_t
to
,
stuct
rt_thread
*
to_thread
)
;
*
#
else
*
void
rt_hw_context_switch_to
(
rt_ubase_t
to
)
;
*
#
endif
*
a0
-->
to
*
a1
-->
to_thread
*/
.
globl
rt_hw_context_switch_to
rt_hw_context_switch_to
:
/
*
first
save
interrupt
stack
*/
la
t0
,
_eusrstack
addi
t0
,
t0
,
-
512
csrw
mscratch
,
t0
LOAD
sp
,
(
a0
)
LOAD
a0
,
2
*
REGBYTES
(
sp
)
csrw
mstatus
,
a0
j
rt_hw_context_switch_exit
/*
*
void
rt_hw_context_switch
(
rt_ubase_t
from
,
rt_ubase_t
to
)
;
*
a0
-->
from
*
a1
-->
to
*/
.
globl
rt_hw_context_switch
rt_hw_context_switch
:
/
*
switch
in
thread
*/
#ifdef ARCH_RISCV_FPU
addi
sp
,
sp
,
-
32
*
FREGBYTES
FSTORE
f0
,
0
*
FREGBYTES
(
sp
)
FSTORE
f1
,
1
*
FREGBYTES
(
sp
)
FSTORE
f2
,
2
*
FREGBYTES
(
sp
)
FSTORE
f3
,
3
*
FREGBYTES
(
sp
)
FSTORE
f4
,
4
*
FREGBYTES
(
sp
)
FSTORE
f5
,
5
*
FREGBYTES
(
sp
)
FSTORE
f6
,
6
*
FREGBYTES
(
sp
)
FSTORE
f7
,
7
*
FREGBYTES
(
sp
)
FSTORE
f8
,
8
*
FREGBYTES
(
sp
)
FSTORE
f9
,
9
*
FREGBYTES
(
sp
)
FSTORE
f10
,
10
*
FREGBYTES
(
sp
)
FSTORE
f11
,
11
*
FREGBYTES
(
sp
)
FSTORE
f12
,
12
*
FREGBYTES
(
sp
)
FSTORE
f13
,
13
*
FREGBYTES
(
sp
)
FSTORE
f14
,
14
*
FREGBYTES
(
sp
)
FSTORE
f15
,
15
*
FREGBYTES
(
sp
)
FSTORE
f16
,
16
*
FREGBYTES
(
sp
)
FSTORE
f17
,
17
*
FREGBYTES
(
sp
)
FSTORE
f18
,
18
*
FREGBYTES
(
sp
)
FSTORE
f19
,
19
*
FREGBYTES
(
sp
)
FSTORE
f20
,
20
*
FREGBYTES
(
sp
)
FSTORE
f21
,
21
*
FREGBYTES
(
sp
)
FSTORE
f22
,
22
*
FREGBYTES
(
sp
)
FSTORE
f23
,
23
*
FREGBYTES
(
sp
)
FSTORE
f24
,
24
*
FREGBYTES
(
sp
)
FSTORE
f25
,
25
*
FREGBYTES
(
sp
)
FSTORE
f26
,
26
*
FREGBYTES
(
sp
)
FSTORE
f27
,
27
*
FREGBYTES
(
sp
)
FSTORE
f28
,
28
*
FREGBYTES
(
sp
)
FSTORE
f29
,
29
*
FREGBYTES
(
sp
)
FSTORE
f30
,
30
*
FREGBYTES
(
sp
)
FSTORE
f31
,
31
*
FREGBYTES
(
sp
)
#endif
addi
sp
,
sp
,
-
32
*
REGBYTES
/
*
save
from
sp
*/
STORE
sp
,
0
(
a0
)
/
*
save
ra
to
epc
*/
STORE
x1
,
0
*
REGBYTES
(
sp
)
STORE
x1
,
1
*
REGBYTES
(
sp
)
STORE
x5
,
5
*
REGBYTES
(
sp
)
csrr
t0
,
mstatus
andi
t0
,
t0
,
8
/
*
if
MIE
be
enabled
,
set
MPIE
*/
beqz
t0
,
1
f
li
t0
,
0x80
1
:
STORE
t0
,
2
*
REGBYTES
(
sp
)
STORE
x4
,
4
*
REGBYTES
(
sp
)
STORE
x6
,
6
*
REGBYTES
(
sp
)
STORE
x7
,
7
*
REGBYTES
(
sp
)
STORE
x8
,
8
*
REGBYTES
(
sp
)
STORE
x9
,
9
*
REGBYTES
(
sp
)
STORE
x10
,
10
*
REGBYTES
(
sp
)
STORE
x11
,
11
*
REGBYTES
(
sp
)
STORE
x12
,
12
*
REGBYTES
(
sp
)
STORE
x13
,
13
*
REGBYTES
(
sp
)
STORE
x14
,
14
*
REGBYTES
(
sp
)
STORE
x15
,
15
*
REGBYTES
(
sp
)
STORE
x16
,
16
*
REGBYTES
(
sp
)
STORE
x17
,
17
*
REGBYTES
(
sp
)
STORE
x18
,
18
*
REGBYTES
(
sp
)
STORE
x19
,
19
*
REGBYTES
(
sp
)
STORE
x20
,
20
*
REGBYTES
(
sp
)
STORE
x21
,
21
*
REGBYTES
(
sp
)
STORE
x22
,
22
*
REGBYTES
(
sp
)
STORE
x23
,
23
*
REGBYTES
(
sp
)
STORE
x24
,
24
*
REGBYTES
(
sp
)
STORE
x25
,
25
*
REGBYTES
(
sp
)
STORE
x26
,
26
*
REGBYTES
(
sp
)
STORE
x27
,
27
*
REGBYTES
(
sp
)
STORE
x28
,
28
*
REGBYTES
(
sp
)
STORE
x29
,
29
*
REGBYTES
(
sp
)
STORE
x30
,
30
*
REGBYTES
(
sp
)
STORE
x31
,
31
*
REGBYTES
(
sp
)
/
*
get
"to"
thread
sp
*/
LOAD
sp
,
0
(
a1
)
j
rt_hw_context_switch_exit
.
global
rt_hw_context_switch_exit
rt_hw_context_switch_exit
:
/
*
resw
ra
to
mepc
*/
LOAD
a0
,
0
*
REGBYTES
(
sp
)
csrw
mepc
,
a0
LOAD
x1
,
1
*
REGBYTES
(
sp
)
/
*
keep
machine
mode
*/
li
a0
,
0x7800
csrs
mstatus
,
a0
/
*
resume
MPIE
*/
LOAD
a0
,
2
*
REGBYTES
(
sp
)
csrs
mstatus
,
a0
LOAD
x4
,
4
*
REGBYTES
(
sp
)
LOAD
x5
,
5
*
REGBYTES
(
sp
)
LOAD
x6
,
6
*
REGBYTES
(
sp
)
LOAD
x7
,
7
*
REGBYTES
(
sp
)
LOAD
x8
,
8
*
REGBYTES
(
sp
)
LOAD
x9
,
9
*
REGBYTES
(
sp
)
LOAD
x10
,
10
*
REGBYTES
(
sp
)
LOAD
x11
,
11
*
REGBYTES
(
sp
)
LOAD
x12
,
12
*
REGBYTES
(
sp
)
LOAD
x13
,
13
*
REGBYTES
(
sp
)
LOAD
x14
,
14
*
REGBYTES
(
sp
)
LOAD
x15
,
15
*
REGBYTES
(
sp
)
LOAD
x16
,
16
*
REGBYTES
(
sp
)
LOAD
x17
,
17
*
REGBYTES
(
sp
)
LOAD
x18
,
18
*
REGBYTES
(
sp
)
LOAD
x19
,
19
*
REGBYTES
(
sp
)
LOAD
x20
,
20
*
REGBYTES
(
sp
)
LOAD
x21
,
21
*
REGBYTES
(
sp
)
LOAD
x22
,
22
*
REGBYTES
(
sp
)
LOAD
x23
,
23
*
REGBYTES
(
sp
)
LOAD
x24
,
24
*
REGBYTES
(
sp
)
LOAD
x25
,
25
*
REGBYTES
(
sp
)
LOAD
x26
,
26
*
REGBYTES
(
sp
)
LOAD
x27
,
27
*
REGBYTES
(
sp
)
LOAD
x28
,
28
*
REGBYTES
(
sp
)
LOAD
x29
,
29
*
REGBYTES
(
sp
)
LOAD
x30
,
30
*
REGBYTES
(
sp
)
LOAD
x31
,
31
*
REGBYTES
(
sp
)
addi
sp
,
sp
,
32
*
REGBYTES
/
*
load
float
reg
*/
#ifdef ARCH_RISCV_FPU
FLOAD
f0
,
0
*
FREGBYTES
(
sp
)
FLOAD
f1
,
1
*
FREGBYTES
(
sp
)
FLOAD
f2
,
2
*
FREGBYTES
(
sp
)
FLOAD
f3
,
3
*
FREGBYTES
(
sp
)
FLOAD
f4
,
4
*
FREGBYTES
(
sp
)
FLOAD
f5
,
5
*
FREGBYTES
(
sp
)
FLOAD
f6
,
6
*
FREGBYTES
(
sp
)
FLOAD
f7
,
7
*
FREGBYTES
(
sp
)
FLOAD
f8
,
8
*
FREGBYTES
(
sp
)
FLOAD
f9
,
9
*
FREGBYTES
(
sp
)
FLOAD
f10
,
10
*
FREGBYTES
(
sp
)
FLOAD
f11
,
11
*
FREGBYTES
(
sp
)
FLOAD
f12
,
12
*
FREGBYTES
(
sp
)
FLOAD
f13
,
13
*
FREGBYTES
(
sp
)
FLOAD
f14
,
14
*
FREGBYTES
(
sp
)
FLOAD
f15
,
15
*
FREGBYTES
(
sp
)
FLOAD
f16
,
16
*
FREGBYTES
(
sp
)
FLOAD
f17
,
17
*
FREGBYTES
(
sp
)
FLOAD
f18
,
18
*
FREGBYTES
(
sp
)
FLOAD
f19
,
19
*
FREGBYTES
(
sp
)
FLOAD
f20
,
20
*
FREGBYTES
(
sp
)
FLOAD
f21
,
21
*
FREGBYTES
(
sp
)
FLOAD
f22
,
22
*
FREGBYTES
(
sp
)
FLOAD
f23
,
23
*
FREGBYTES
(
sp
)
FLOAD
f24
,
24
*
FREGBYTES
(
sp
)
FLOAD
f25
,
25
*
FREGBYTES
(
sp
)
FLOAD
f26
,
26
*
FREGBYTES
(
sp
)
FLOAD
f27
,
27
*
FREGBYTES
(
sp
)
FLOAD
f28
,
28
*
FREGBYTES
(
sp
)
FLOAD
f29
,
29
*
FREGBYTES
(
sp
)
FLOAD
f30
,
30
*
FREGBYTES
(
sp
)
FLOAD
f31
,
31
*
FREGBYTES
(
sp
)
addi
sp
,
sp
,
32
*
FREGBYTES
#endif
mret
libcpu/risc-v/ch32v3/cpuport.c
0 → 100644
浏览文件 @
9b750eba
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WCH the first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "ch32v30x.h"
#include "cpuport.h"
#ifndef RT_USING_SMP
volatile
rt_ubase_t
rt_interrupt_from_thread
=
0
;
volatile
rt_ubase_t
rt_interrupt_to_thread
=
0
;
volatile
rt_uint32_t
rt_thread_switch_interrupt_flag
=
0
;
#endif
struct
rt_hw_stack_frame
{
rt_ubase_t
epc
;
/* epc - epc - program counter */
rt_ubase_t
ra
;
/* x1 - ra - return address for jumps */
rt_ubase_t
mstatus
;
/* - machine status register */
rt_ubase_t
gp
;
/* x3 - gp - global pointer */
rt_ubase_t
tp
;
/* x4 - tp - thread pointer */
rt_ubase_t
t0
;
/* x5 - t0 - temporary register 0 */
rt_ubase_t
t1
;
/* x6 - t1 - temporary register 1 */
rt_ubase_t
t2
;
/* x7 - t2 - temporary register 2 */
rt_ubase_t
s0_fp
;
/* x8 - s0/fp - saved register 0 or frame pointer */
rt_ubase_t
s1
;
/* x9 - s1 - saved register 1 */
rt_ubase_t
a0
;
/* x10 - a0 - return value or function argument 0 */
rt_ubase_t
a1
;
/* x11 - a1 - return value or function argument 1 */
rt_ubase_t
a2
;
/* x12 - a2 - function argument 2 */
rt_ubase_t
a3
;
/* x13 - a3 - function argument 3 */
rt_ubase_t
a4
;
/* x14 - a4 - function argument 4 */
rt_ubase_t
a5
;
/* x15 - a5 - function argument 5 */
rt_ubase_t
a6
;
/* x16 - a6 - function argument 6 */
rt_ubase_t
a7
;
/* x17 - s7 - function argument 7 */
rt_ubase_t
s2
;
/* x18 - s2 - saved register 2 */
rt_ubase_t
s3
;
/* x19 - s3 - saved register 3 */
rt_ubase_t
s4
;
/* x20 - s4 - saved register 4 */
rt_ubase_t
s5
;
/* x21 - s5 - saved register 5 */
rt_ubase_t
s6
;
/* x22 - s6 - saved register 6 */
rt_ubase_t
s7
;
/* x23 - s7 - saved register 7 */
rt_ubase_t
s8
;
/* x24 - s8 - saved register 8 */
rt_ubase_t
s9
;
/* x25 - s9 - saved register 9 */
rt_ubase_t
s10
;
/* x26 - s10 - saved register 10 */
rt_ubase_t
s11
;
/* x27 - s11 - saved register 11 */
rt_ubase_t
t3
;
/* x28 - t3 - temporary register 3 */
rt_ubase_t
t4
;
/* x29 - t4 - temporary register 4 */
rt_ubase_t
t5
;
/* x30 - t5 - temporary register 5 */
rt_ubase_t
t6
;
/* x31 - t6 - temporary register 6 */
/* float register */
#ifdef ARCH_RISCV_FPU
rv_floatreg_t
f0
;
/* f0 */
rv_floatreg_t
f1
;
/* f1 */
rv_floatreg_t
f2
;
/* f2 */
rv_floatreg_t
f3
;
/* f3 */
rv_floatreg_t
f4
;
/* f4 */
rv_floatreg_t
f5
;
/* f5 */
rv_floatreg_t
f6
;
/* f6 */
rv_floatreg_t
f7
;
/* f7 */
rv_floatreg_t
f8
;
/* f8 */
rv_floatreg_t
f9
;
/* f9 */
rv_floatreg_t
f10
;
/* f10 */
rv_floatreg_t
f11
;
/* f11 */
rv_floatreg_t
f12
;
/* f12 */
rv_floatreg_t
f13
;
/* f13 */
rv_floatreg_t
f14
;
/* f14 */
rv_floatreg_t
f15
;
/* f15 */
rv_floatreg_t
f16
;
/* f16 */
rv_floatreg_t
f17
;
/* f17 */
rv_floatreg_t
f18
;
/* f18 */
rv_floatreg_t
f19
;
/* f19 */
rv_floatreg_t
f20
;
/* f20 */
rv_floatreg_t
f21
;
/* f21 */
rv_floatreg_t
f22
;
/* f22 */
rv_floatreg_t
f23
;
/* f23 */
rv_floatreg_t
f24
;
/* f24 */
rv_floatreg_t
f25
;
/* f25 */
rv_floatreg_t
f26
;
/* f26 */
rv_floatreg_t
f27
;
/* f27 */
rv_floatreg_t
f28
;
/* f28 */
rv_floatreg_t
f29
;
/* f29 */
rv_floatreg_t
f30
;
/* f30 */
rv_floatreg_t
f31
;
/* f31 */
#endif
};
/*
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t
*
rt_hw_stack_init
(
void
*
tentry
,
void
*
parameter
,
rt_uint8_t
*
stack_addr
,
void
*
texit
)
{
struct
rt_hw_stack_frame
*
frame
;
rt_uint8_t
*
stk
;
int
i
;
stk
=
stack_addr
+
sizeof
(
rt_ubase_t
);
stk
=
(
rt_uint8_t
*
)
RT_ALIGN_DOWN
((
rt_ubase_t
)
stk
,
REGBYTES
);
stk
-=
sizeof
(
struct
rt_hw_stack_frame
);
frame
=
(
struct
rt_hw_stack_frame
*
)
stk
;
for
(
i
=
0
;
i
<
sizeof
(
struct
rt_hw_stack_frame
)
/
sizeof
(
rt_ubase_t
);
i
++
)
{
((
rt_ubase_t
*
)
frame
)[
i
]
=
0xdeadbeef
;
}
frame
->
ra
=
(
rt_ubase_t
)
texit
;
frame
->
a0
=
(
rt_ubase_t
)
parameter
;
frame
->
epc
=
(
rt_ubase_t
)
tentry
;
/* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */
frame
->
mstatus
=
0x00007880
;
return
stk
;
}
/*
* trigger soft interrupt
*/
void
sw_setpend
(
void
)
{
SysTick
->
CTLR
|=
(
1
<<
31
);
}
/*
* clear soft interrupt
*/
void
sw_clearpend
(
void
)
{
SysTick
->
CTLR
&=
~
(
1
<<
31
);
}
/*
* disable interrupt and save mstatus
*/
rt_base_t
rt_hw_interrupt_disable
(
void
)
{
rt_base_t
value
=
0
;
asm
(
"csrrw %0, mstatus, %1"
:
"=r"
(
value
)
:
"r"
(
0x7800
));
return
value
;
}
/*
* enable interrupt and resume mstatus
*/
void
rt_hw_interrupt_enable
(
rt_base_t
level
)
{
asm
(
"csrw mstatus, %0"
:
:
"r"
(
level
));
}
/*
* #ifdef RT_USING_SMP
* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
* #else
* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
* #endif
*/
void
rt_hw_context_switch_interrupt
(
rt_ubase_t
from
,
rt_ubase_t
to
)
{
if
(
rt_thread_switch_interrupt_flag
==
0
)
rt_interrupt_from_thread
=
from
;
rt_interrupt_to_thread
=
to
;
rt_thread_switch_interrupt_flag
=
1
;
/* switch just in sw_handler */
sw_setpend
();
}
/* shutdown CPU */
void
rt_hw_cpu_shutdown
(
void
)
{
rt_uint32_t
level
;
rt_kprintf
(
"shutdown...
\n
"
);
level
=
rt_hw_interrupt_disable
();
while
(
level
)
{
RT_ASSERT
(
0
);
}
}
libcpu/risc-v/ch32v3/cpuport.h
0 → 100644
浏览文件 @
9b750eba
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WCH the first version
*/
#ifndef CPUPORT_H__
#define CPUPORT_H__
/* bytes of register width */
//#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#ifdef ARCH_CPU_64BIT
#define STORE sd
#define LOAD ld
#define REGBYTES 8
#else
#define STORE sw
#define LOAD lw
#define REGBYTES 4
#endif
/* FPU */
#ifdef ARCH_RISCV_FPU
#ifdef ARCH_RISCV_FPU_D
#define FSTORE fsd
#define FLOAD fld
#define FREGBYTES 8
#define rv_floatreg_t rt_int64_t
#endif
#ifdef ARCH_RISCV_FPU_S
#define FSTORE fsw
#define FLOAD flw
#define FREGBYTES 4
#define rv_floatreg_t rt_int32_t
#endif
#endif
#endif
libcpu/risc-v/ch32v3/interrupt_gcc.S
0 → 100644
浏览文件 @
9b750eba
/*
*
Copyright
(
c
)
2006
-
2018
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
*
Change
Logs
:
*
Date
Author
Notes
*
2021
-
09
-
09
WCH
the
first
version
*/
#include "cpuport.h"
.
global
SW_handler
.
align
2
SW_handler
:
/
*
save
all
from
thread
context
*/
#ifdef ARCH_RISCV_FPU
addi
sp
,
sp
,
-
32
*
FREGBYTES
FSTORE
f0
,
0
*
FREGBYTES
(
sp
)
FSTORE
f1
,
1
*
FREGBYTES
(
sp
)
FSTORE
f2
,
2
*
FREGBYTES
(
sp
)
FSTORE
f3
,
3
*
FREGBYTES
(
sp
)
FSTORE
f4
,
4
*
FREGBYTES
(
sp
)
FSTORE
f5
,
5
*
FREGBYTES
(
sp
)
FSTORE
f6
,
6
*
FREGBYTES
(
sp
)
FSTORE
f7
,
7
*
FREGBYTES
(
sp
)
FSTORE
f8
,
8
*
FREGBYTES
(
sp
)
FSTORE
f9
,
9
*
FREGBYTES
(
sp
)
FSTORE
f10
,
10
*
FREGBYTES
(
sp
)
FSTORE
f11
,
11
*
FREGBYTES
(
sp
)
FSTORE
f12
,
12
*
FREGBYTES
(
sp
)
FSTORE
f13
,
13
*
FREGBYTES
(
sp
)
FSTORE
f14
,
14
*
FREGBYTES
(
sp
)
FSTORE
f15
,
15
*
FREGBYTES
(
sp
)
FSTORE
f16
,
16
*
FREGBYTES
(
sp
)
FSTORE
f17
,
17
*
FREGBYTES
(
sp
)
FSTORE
f18
,
18
*
FREGBYTES
(
sp
)
FSTORE
f19
,
19
*
FREGBYTES
(
sp
)
FSTORE
f20
,
20
*
FREGBYTES
(
sp
)
FSTORE
f21
,
21
*
FREGBYTES
(
sp
)
FSTORE
f22
,
22
*
FREGBYTES
(
sp
)
FSTORE
f23
,
23
*
FREGBYTES
(
sp
)
FSTORE
f24
,
24
*
FREGBYTES
(
sp
)
FSTORE
f25
,
25
*
FREGBYTES
(
sp
)
FSTORE
f26
,
26
*
FREGBYTES
(
sp
)
FSTORE
f27
,
27
*
FREGBYTES
(
sp
)
FSTORE
f28
,
28
*
FREGBYTES
(
sp
)
FSTORE
f29
,
29
*
FREGBYTES
(
sp
)
FSTORE
f30
,
30
*
FREGBYTES
(
sp
)
FSTORE
f31
,
31
*
FREGBYTES
(
sp
)
#endif
addi
sp
,
sp
,
-
32
*
REGBYTES
STORE
x5
,
5
*
REGBYTES
(
sp
)
/
*
saved
MPIE
*/
li
t0
,
0x80
STORE
t0
,
2
*
REGBYTES
(
sp
)
/
*
Temporarily
disable
HPE
*/
li
t0
,
0x20
csrs
0x804
,
t0
STORE
x1
,
1
*
REGBYTES
(
sp
)
STORE
x4
,
4
*
REGBYTES
(
sp
)
STORE
x6
,
6
*
REGBYTES
(
sp
)
STORE
x7
,
7
*
REGBYTES
(
sp
)
STORE
x8
,
8
*
REGBYTES
(
sp
)
STORE
x9
,
9
*
REGBYTES
(
sp
)
STORE
x10
,
10
*
REGBYTES
(
sp
)
STORE
x11
,
11
*
REGBYTES
(
sp
)
STORE
x12
,
12
*
REGBYTES
(
sp
)
STORE
x13
,
13
*
REGBYTES
(
sp
)
STORE
x14
,
14
*
REGBYTES
(
sp
)
STORE
x15
,
15
*
REGBYTES
(
sp
)
STORE
x16
,
16
*
REGBYTES
(
sp
)
STORE
x17
,
17
*
REGBYTES
(
sp
)
STORE
x18
,
18
*
REGBYTES
(
sp
)
STORE
x19
,
19
*
REGBYTES
(
sp
)
STORE
x20
,
20
*
REGBYTES
(
sp
)
STORE
x21
,
21
*
REGBYTES
(
sp
)
STORE
x22
,
22
*
REGBYTES
(
sp
)
STORE
x23
,
23
*
REGBYTES
(
sp
)
STORE
x24
,
24
*
REGBYTES
(
sp
)
STORE
x25
,
25
*
REGBYTES
(
sp
)
STORE
x26
,
26
*
REGBYTES
(
sp
)
STORE
x27
,
27
*
REGBYTES
(
sp
)
STORE
x28
,
28
*
REGBYTES
(
sp
)
STORE
x29
,
29
*
REGBYTES
(
sp
)
STORE
x30
,
30
*
REGBYTES
(
sp
)
STORE
x31
,
31
*
REGBYTES
(
sp
)
/
*
switch
to
interrupt
stack
*/
csrrw
sp
,
mscratch
,
sp
call
rt_interrupt_enter
/
*
clear
interrupt
*/
jal
sw_clearpend
call
rt_interrupt_leave
/
*
switch
to
from
thread
stack
*/
csrrw
sp
,
mscratch
,
sp
/
*
if
rt_thread_switch_interrupt_flag
=
1
,
then
clear
it
*/
la
s0
,
rt_thread_switch_interrupt_flag
lw
s2
,
0
(
s0
)
beqz
s2
,
1
f
sw
zero
,
0
(
s0
)
#
1
:
csrr
a0
,
mepc
STORE
a0
,
0
*
REGBYTES
(
sp
)
la
s0
,
rt_interrupt_from_thread
LOAD
s1
,
0
(
s0
)
STORE
sp
,
0
(
s1
)
la
s0
,
rt_interrupt_to_thread
LOAD
s1
,
0
(
s0
)
LOAD
sp
,
0
(
s1
)
LOAD
a0
,
0
*
REGBYTES
(
sp
)
csrw
mepc
,
a0
1
:
LOAD
x1
,
1
*
REGBYTES
(
sp
)
li
t0
,
0x7800
csrs
mstatus
,
t0
LOAD
t0
,
2
*
REGBYTES
(
sp
)
csrs
mstatus
,
t0
LOAD
x4
,
4
*
REGBYTES
(
sp
)
LOAD
x5
,
5
*
REGBYTES
(
sp
)
LOAD
x6
,
6
*
REGBYTES
(
sp
)
LOAD
x7
,
7
*
REGBYTES
(
sp
)
LOAD
x8
,
8
*
REGBYTES
(
sp
)
LOAD
x9
,
9
*
REGBYTES
(
sp
)
LOAD
x10
,
10
*
REGBYTES
(
sp
)
LOAD
x11
,
11
*
REGBYTES
(
sp
)
LOAD
x12
,
12
*
REGBYTES
(
sp
)
LOAD
x13
,
13
*
REGBYTES
(
sp
)
LOAD
x14
,
14
*
REGBYTES
(
sp
)
LOAD
x15
,
15
*
REGBYTES
(
sp
)
LOAD
x16
,
16
*
REGBYTES
(
sp
)
LOAD
x17
,
17
*
REGBYTES
(
sp
)
LOAD
x18
,
18
*
REGBYTES
(
sp
)
LOAD
x19
,
19
*
REGBYTES
(
sp
)
LOAD
x20
,
20
*
REGBYTES
(
sp
)
LOAD
x21
,
21
*
REGBYTES
(
sp
)
LOAD
x22
,
22
*
REGBYTES
(
sp
)
LOAD
x23
,
23
*
REGBYTES
(
sp
)
LOAD
x24
,
24
*
REGBYTES
(
sp
)
LOAD
x25
,
25
*
REGBYTES
(
sp
)
LOAD
x26
,
26
*
REGBYTES
(
sp
)
LOAD
x27
,
27
*
REGBYTES
(
sp
)
LOAD
x28
,
28
*
REGBYTES
(
sp
)
LOAD
x29
,
29
*
REGBYTES
(
sp
)
LOAD
x30
,
30
*
REGBYTES
(
sp
)
LOAD
x31
,
31
*
REGBYTES
(
sp
)
addi
sp
,
sp
,
32
*
REGBYTES
/
*
load
float
reg
*/
#ifdef ARCH_RISCV_FPU
FLOAD
f0
,
0
*
FREGBYTES
(
sp
)
FLOAD
f1
,
1
*
FREGBYTES
(
sp
)
FLOAD
f2
,
2
*
FREGBYTES
(
sp
)
FLOAD
f3
,
3
*
FREGBYTES
(
sp
)
FLOAD
f4
,
4
*
FREGBYTES
(
sp
)
FLOAD
f5
,
5
*
FREGBYTES
(
sp
)
FLOAD
f6
,
6
*
FREGBYTES
(
sp
)
FLOAD
f7
,
7
*
FREGBYTES
(
sp
)
FLOAD
f8
,
8
*
FREGBYTES
(
sp
)
FLOAD
f9
,
9
*
FREGBYTES
(
sp
)
FLOAD
f10
,
10
*
FREGBYTES
(
sp
)
FLOAD
f11
,
11
*
FREGBYTES
(
sp
)
FLOAD
f12
,
12
*
FREGBYTES
(
sp
)
FLOAD
f13
,
13
*
FREGBYTES
(
sp
)
FLOAD
f14
,
14
*
FREGBYTES
(
sp
)
FLOAD
f15
,
15
*
FREGBYTES
(
sp
)
FLOAD
f16
,
16
*
FREGBYTES
(
sp
)
FLOAD
f17
,
17
*
FREGBYTES
(
sp
)
FLOAD
f18
,
18
*
FREGBYTES
(
sp
)
FLOAD
f19
,
19
*
FREGBYTES
(
sp
)
FLOAD
f20
,
20
*
FREGBYTES
(
sp
)
FLOAD
f21
,
21
*
FREGBYTES
(
sp
)
FLOAD
f22
,
22
*
FREGBYTES
(
sp
)
FLOAD
f23
,
23
*
FREGBYTES
(
sp
)
FLOAD
f24
,
24
*
FREGBYTES
(
sp
)
FLOAD
f25
,
25
*
FREGBYTES
(
sp
)
FLOAD
f26
,
26
*
FREGBYTES
(
sp
)
FLOAD
f27
,
27
*
FREGBYTES
(
sp
)
FLOAD
f28
,
28
*
FREGBYTES
(
sp
)
FLOAD
f29
,
29
*
FREGBYTES
(
sp
)
FLOAD
f30
,
30
*
FREGBYTES
(
sp
)
FLOAD
f31
,
31
*
FREGBYTES
(
sp
)
addi
sp
,
sp
,
32
*
FREGBYTES
#endif
mret
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