From 35cd668cf7ce1aee242f8b265db6a59a0583c864 Mon Sep 17 00:00:00 2001 From: yangjie Date: Fri, 19 Jul 2019 14:59:21 +0800 Subject: [PATCH] =?UTF-8?q?[bsp][stm32/libraries/HAL=5FDrivers]=20F0=20?= =?UTF-8?q?=E7=B3=BB=E5=88=97=E6=94=AF=E6=8C=81SPI=EF=BC=8C=E5=B9=B6?= =?UTF-8?q?=E4=BF=AE=E5=A4=8DDMA=E4=B8=AD=E6=96=AD=E5=87=BD=E6=95=B0?= =?UTF-8?q?=E9=87=8D=E5=A4=8D=E5=AE=9A=E4=B9=89?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../HAL_Drivers/config/f0/dma_config.h | 12 +++ .../HAL_Drivers/config/f0/spi_config.h | 74 +++++++++++++++---- bsp/stm32/libraries/HAL_Drivers/drv_spi.c | 34 +++++++-- 3 files changed, 102 insertions(+), 18 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h index 9c7c222559..a8d177801c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h @@ -26,6 +26,18 @@ extern "C" { #define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN #define UART1_RX_DMA_INSTANCE DMA1_Channel3 #define UART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn +#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define SPI1_RX_DMA_INSTANCE DMA1_Channel2 +#define SPI1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn +#endif + +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN +#define SPI1_TX_DMA_INSTANCE DMA1_Channel3 +#define SPI1_TX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn #endif /* DMA1 channel2-3 DMA2 channel1-2 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h index 5aacf9de90..3d66d703e8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2019-01-05 SummerGift modify DMA support */ #ifndef __SPI_CONFIG_H__ @@ -18,21 +19,68 @@ extern "C" { #endif #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Channel2, \ - .dma_rx.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \ - .dma_tx.Instance = DMA1_Channel3, \ - .dma_tx.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ -#define SPI1_DMA_RX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler -#endif +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ #ifdef __cplusplus } diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index 7bb28fcc16..36b50492f6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -203,7 +203,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur spi_handle->Init.TIMode = SPI_TIMODE_DISABLE; spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; spi_handle->State = HAL_SPI_STATE_RESET; -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; #endif @@ -409,7 +409,7 @@ static int rt_hw_spi_bus_init(void) { rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); @@ -447,10 +447,10 @@ static int rt_hw_spi_bus_init(void) { rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); + SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc); #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); /* Delay after an RCC peripheral clock enabling */ @@ -861,6 +861,30 @@ static void stm32_get_dma_info(void) #endif } +#if defined(SOC_SERIES_STM32F0) +void SPI1_DMA_RX_TX_IRQHandler(void) +{ +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA) + SPI1_DMA_TX_IRQHandler(); +#endif + +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA) + SPI1_DMA_RX_IRQHandler(); +#endif +} + +void SPI2_DMA_RX_TX_IRQHandler(void) +{ +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA) + SPI2_DMA_TX_IRQHandler(); +#endif + +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA) + SPI2_DMA_RX_IRQHandler(); +#endif +} +#endif /* SOC_SERIES_STM32F0 */ + int rt_hw_spi_init(void) { stm32_get_dma_info(); -- GitLab