diff --git a/bsp/stm32f20x/stm32_rom.icf b/bsp/stm32f20x/stm32_rom.icf index 293cd6ab0173b8e4e78185c712146dbbf57a403b..95cc8d50cf68829b94ee8dfdddadb92e89ad3538 100644 --- a/bsp/stm32f20x/stm32_rom.icf +++ b/bsp/stm32f20x/stm32_rom.icf @@ -28,8 +28,8 @@ do not initialize { section .noinit }; keep { section FSymTab }; keep { section VSymTab }; +keep { section .rti_fn* }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly, block RTT_INIT_FUNC }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file +place in RAM_region { readwrite, block CSTACK, last block HEAP}; diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S index 3186a5ae9f446365862dd96f4237794ce0b10cf0..c95582630a5e59228a2144a272375b85fc191b49 100644 --- a/libcpu/arm/cortex-m0/context_gcc.S +++ b/libcpu/arm/cortex-m0/context_gcc.S @@ -181,7 +181,9 @@ rt_hw_context_switch_to: NOP MSR MSP, R0 - CPSIE I /* enable interrupts at processor level */ + /* enable interrupts at processor level */ + CPSIE F + CPSIE I /* never reach here! */ diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S index 67ea808d8c71b8ba5d4ccac970275e6cc6a6746f..e7d680867a61a2cb78e4b1907f1c44a634b4f2d7 100644 --- a/libcpu/arm/cortex-m0/context_iar.S +++ b/libcpu/arm/cortex-m0/context_iar.S @@ -188,6 +188,7 @@ rt_hw_context_switch_to: MSR msp, r0 ; enable interrupts at processor level + CPSIE F CPSIE I ; never reach here! diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S index bf68592e63e653b1d5919343966feb61daddb8db..5411162e5678fc3dd8997beabf3dd3efdcef4486 100644 --- a/libcpu/arm/cortex-m0/context_rvds.S +++ b/libcpu/arm/cortex-m0/context_rvds.S @@ -191,6 +191,7 @@ rt_hw_context_switch_to PROC MSR msp, r0 ; enable interrupts at processor level + CPSIE F CPSIE I ; never reach here! diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S index ca961bbd87f40795676fa6904edf3173585ffbc5..5181cb2712ec34487967047a8b2602fa41c50a6e 100644 --- a/libcpu/arm/cortex-m3/context_gcc.S +++ b/libcpu/arm/cortex-m3/context_gcc.S @@ -162,7 +162,9 @@ rt_hw_context_switch_to: NOP MSR msp, r0 - CPSIE I /* enable interrupts at processor level */ + /* enable interrupts at processor level */ + CPSIE F + CPSIE I /* never reach here! */ diff --git a/libcpu/arm/cortex-m3/context_iar.S b/libcpu/arm/cortex-m3/context_iar.S index ad9fa0dd0f82008bb22bff047f3ade4919bbb732..95dee8062de16edfa6b29ad9b9d8d60e979b3acb 100644 --- a/libcpu/arm/cortex-m3/context_iar.S +++ b/libcpu/arm/cortex-m3/context_iar.S @@ -161,7 +161,9 @@ rt_hw_context_switch_to: NOP MSR msp, r0 - CPSIE I ; enable interrupts at processor level + ; enable interrupts at processor level + CPSIE F + CPSIE I ; never reach here! diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S index ebfd5c8da8c39aadbe784e6463f40af363c194cb..a4191203be39a5a6fa7f71199d0f2ac4ab3ae4e0 100644 --- a/libcpu/arm/cortex-m3/context_rvds.S +++ b/libcpu/arm/cortex-m3/context_rvds.S @@ -168,6 +168,7 @@ rt_hw_context_switch_to PROC MSR msp, r0 ; enable interrupts at processor level + CPSIE F CPSIE I ; never reach here! diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S index 908a44f8472557da629729f1abec3dc9d86b07ea..af6c9934d49da5ee4c1912314adfede4112da158 100644 --- a/libcpu/arm/cortex-m4/context_gcc.S +++ b/libcpu/arm/cortex-m4/context_gcc.S @@ -203,7 +203,9 @@ rt_hw_context_switch_to: NOP MSR msp, r0 - CPSIE I /* enable interrupts at processor level */ + /* enable interrupts at processor level */ + CPSIE F + CPSIE I /* never reach here! */ diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S index 8761a9705299d564dd51ae3909ab4a2ab79b2842..4cc9539112b0a936ad31a2410aa13e2736aef993 100644 --- a/libcpu/arm/cortex-m4/context_iar.S +++ b/libcpu/arm/cortex-m4/context_iar.S @@ -207,7 +207,9 @@ rt_hw_context_switch_to: NOP MSR msp, r0 - CPSIE I ; enable interrupts at processor level + ; enable interrupts at processor level + CPSIE F + CPSIE I ; never reach here! diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S index fa7a1c90f8de443f5c2464a1d1514f02115ba0c6..ea894ed0003fb43c372ee897cb5d9faab7c53f15 100644 --- a/libcpu/arm/cortex-m4/context_rvds.S +++ b/libcpu/arm/cortex-m4/context_rvds.S @@ -208,6 +208,7 @@ rt_hw_context_switch_to PROC MSR msp, r0 ; enable interrupts at processor level + CPSIE F CPSIE I ; never reach here! diff --git a/libcpu/arm/cortex-m7/context_gcc.S b/libcpu/arm/cortex-m7/context_gcc.S index 908a44f8472557da629729f1abec3dc9d86b07ea..af6c9934d49da5ee4c1912314adfede4112da158 100644 --- a/libcpu/arm/cortex-m7/context_gcc.S +++ b/libcpu/arm/cortex-m7/context_gcc.S @@ -203,7 +203,9 @@ rt_hw_context_switch_to: NOP MSR msp, r0 - CPSIE I /* enable interrupts at processor level */ + /* enable interrupts at processor level */ + CPSIE F + CPSIE I /* never reach here! */ diff --git a/libcpu/arm/cortex-m7/context_iar.S b/libcpu/arm/cortex-m7/context_iar.S index 8761a9705299d564dd51ae3909ab4a2ab79b2842..4cc9539112b0a936ad31a2410aa13e2736aef993 100644 --- a/libcpu/arm/cortex-m7/context_iar.S +++ b/libcpu/arm/cortex-m7/context_iar.S @@ -207,7 +207,9 @@ rt_hw_context_switch_to: NOP MSR msp, r0 - CPSIE I ; enable interrupts at processor level + ; enable interrupts at processor level + CPSIE F + CPSIE I ; never reach here! diff --git a/libcpu/arm/cortex-m7/context_rvds.S b/libcpu/arm/cortex-m7/context_rvds.S index 53a3756783bcfb3c59c5c9a95e050cc2b840d264..38410c8a3b3e2d32ec728a46e6ee8ca2700326b7 100644 --- a/libcpu/arm/cortex-m7/context_rvds.S +++ b/libcpu/arm/cortex-m7/context_rvds.S @@ -208,6 +208,7 @@ rt_hw_context_switch_to PROC MSR msp, r0 ; enable interrupts at processor level + CPSIE F CPSIE I ; never reach here!