diff --git a/bsp/stm32f20x/SConstruct b/bsp/stm32f20x/SConstruct
index f9942ef0c7c663ec8bec96b6903bd74306a43f15..63b1130d6ac4f39c6bf879a63c43aacd782f43ea 100644
--- a/bsp/stm32f20x/SConstruct
+++ b/bsp/stm32f20x/SConstruct
@@ -17,6 +17,7 @@ env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
Export('RTT_ROOT')
diff --git a/bsp/stm32f20x/project.ewp b/bsp/stm32f20x/project.ewp
new file mode 100644
index 0000000000000000000000000000000000000000..0150e990182db1640ccd126c98eb4351973d5b09
--- /dev/null
+++ b/bsp/stm32f20x/project.ewp
@@ -0,0 +1,1967 @@
+
+ 2
+
+ Debug
+
+ ARM
+
+ 1
+
+ General
+ 3
+
+ 18
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ICCARM
+ 2
+
+ 26
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ AARM
+ 2
+
+ 8
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 1
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+
+
+
+ BICOMP
+ 0
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 11
+ 1
+ 1
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 1
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
+ Release
+
+ ARM
+
+ 0
+
+ General
+ 3
+
+ 18
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ICCARM
+ 2
+
+ 26
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ AARM
+ 2
+
+ 8
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+
+
+
+ BICOMP
+ 0
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 11
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
+ Startup
+
+ $PROJ_DIR$\.\application.c
+
+
+ $PROJ_DIR$\.\startup.c
+
+
+ $PROJ_DIR$\.\board.c
+
+
+ $PROJ_DIR$\.\stm32f20x_it.c
+
+
+ $PROJ_DIR$\.\usart.c
+
+
+ $PROJ_DIR$\.\serial.c
+
+
+
+ Kernel
+
+ $PROJ_DIR$\..\..\src\clock.c
+
+
+ $PROJ_DIR$\..\..\src\device.c
+
+
+ $PROJ_DIR$\..\..\src\idle.c
+
+
+ $PROJ_DIR$\..\..\src\ipc.c
+
+
+ $PROJ_DIR$\..\..\src\irq.c
+
+
+ $PROJ_DIR$\..\..\src\kservice.c
+
+
+ $PROJ_DIR$\..\..\src\mem.c
+
+
+ $PROJ_DIR$\..\..\src\mempool.c
+
+
+ $PROJ_DIR$\..\..\src\module.c
+
+
+ $PROJ_DIR$\..\..\src\object.c
+
+
+ $PROJ_DIR$\..\..\src\rtm.c
+
+
+ $PROJ_DIR$\..\..\src\scheduler.c
+
+
+ $PROJ_DIR$\..\..\src\slab.c
+
+
+ $PROJ_DIR$\..\..\src\thread.c
+
+
+ $PROJ_DIR$\..\..\src\timer.c
+
+
+
+ STM32
+
+ $PROJ_DIR$\..\..\libcpu\arm\stm32\cpuport.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\stm32\context_iar.S
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\div0.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c
+
+
+
+ finsh
+
+ $PROJ_DIR$\..\..\components\finsh\cmd.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_error.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_heap.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_init.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_node.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_ops.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_parser.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_token.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_var.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_vm.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\shell.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\symbol.c
+
+
+
+ STM32_StdPeriph
+
+ $PROJ_DIR$\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c
+
+
+ $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c
+
+
+ $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\iar\startup_stm32f2xx.s
+
+
+
diff --git a/bsp/stm32f20x/project.eww b/bsp/stm32f20x/project.eww
new file mode 100644
index 0000000000000000000000000000000000000000..faa93f37cdf824efd53c15b77e75dc1f03727d9a
--- /dev/null
+++ b/bsp/stm32f20x/project.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\project.ewp
+
+
+
+
+
diff --git a/bsp/stm32f20x/rtconfig.py b/bsp/stm32f20x/rtconfig.py
index 752da4c029d06c05385fd54be267d62bcfc6198d..3e8a6779ebda2c6799b1516db23fbca8ca3af9d4 100644
--- a/bsp/stm32f20x/rtconfig.py
+++ b/bsp/stm32f20x/rtconfig.py
@@ -77,9 +77,9 @@ elif PLATFORM == 'iar':
LINK = 'ilinkarm'
TARGET_EXT = 'out'
- DEVICE = ' --cpu DARMSTM --thumb'
+ DEVICE = ' -D USE_STDPERIPH_DRIVER'
- CFLAGS = ''
+ CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
@@ -93,9 +93,8 @@ elif PLATFORM == 'iar':
CFLAGS += ' --cpu=Cortex-M3'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
- CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/DLib_Config_Normal.h"'
+ CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
- CFLAGS += ' -I"' + IAR_PATH + '/arm/inc"'
AFLAGS = ''
AFLAGS += ' -s+'
@@ -103,11 +102,9 @@ elif PLATFORM == 'iar':
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M3'
AFLAGS += ' --fpu None'
- AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
- LFLAGS = ' --config stm32f10x_flash.icf'
- LFLAGS += ' --redirect _Printf=_PrintfTiny'
- LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+ LFLAGS = ' --config stm32_rom.icf'
+ LFLAGS += ' --semihosting'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = IAR_PATH + '/arm/bin/'
diff --git a/bsp/stm32f20x/stm32_rom.icf b/bsp/stm32f20x/stm32_rom.icf
new file mode 100644
index 0000000000000000000000000000000000000000..bf3e6860dffcba170b8cdd4c94bab5eed874260e
--- /dev/null
+++ b/bsp/stm32f20x/stm32_rom.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+do not initialize { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file