diff --git a/bsp/beaglebone/.config b/bsp/beaglebone/.config index 2d1d261f557885941287cbdfc3f3b0923fee2975..efd2c2ccc1a9bb321ab0fead02d4c898cc726859 100644 --- a/bsp/beaglebone/.config +++ b/bsp/beaglebone/.config @@ -77,8 +77,8 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" -CONFIG_RT_VER_NUM=0x40101 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -428,6 +428,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_HASH_MATCH is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set # # system packages @@ -463,7 +464,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set @@ -498,6 +498,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KMULTI_RTIMER is not set # CONFIG_PKG_USING_TFDB is not set # CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set # # peripheral libraries and drivers @@ -666,60 +667,36 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QPARAM is not set # -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_SMODULE is not set -# CONFIG_PKG_USING_SNFD is not set -# CONFIG_PKG_USING_UDBD is not set -# CONFIG_PKG_USING_BENCHMARK is not set -# CONFIG_PKG_USING_UBJSON is not set -# CONFIG_PKG_USING_DATATYPE is not set -# CONFIG_PKG_USING_FASTFS is not set -# CONFIG_PKG_USING_RIL is not set -# CONFIG_PKG_USING_WATCH_DCM_SVC is not set -# CONFIG_PKG_USING_WATCH_APP_FWK is not set -# CONFIG_PKG_USING_GUI_TEST is not set -# CONFIG_PKG_USING_PMEM is not set -# CONFIG_PKG_USING_LWRDP is not set -# CONFIG_PKG_USING_MASAN is not set -# CONFIG_PKG_USING_BSDIFF_LIB is not set -# CONFIG_PKG_USING_PRC_DIFF is not set - -# -# RT-Thread Smart -# -# CONFIG_PKG_USING_UKERNEL is not set -# CONFIG_PKG_USING_TRACE_AGENT is not set +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Sensor libraries +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_DHT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display libraries +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set + +# +# Timing libraries +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Project libraries +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set CONFIG_SOC_AM335X=y -CONFIG_RT_USING_UART1=y +CONFIG_RT_USING_UART0=y +# CONFIG_RT_USING_UART1 is not set diff --git a/bsp/beaglebone/Kconfig b/bsp/beaglebone/Kconfig index 2784e360686115e9edfb9e9280f520a811f9fbf0..10b5465b2527037daa810b895b445830e98d758e 100644 --- a/bsp/beaglebone/Kconfig +++ b/bsp/beaglebone/Kconfig @@ -32,6 +32,10 @@ config SOC_AM335X select RT_USING_USER_MAIN default y +config RT_USING_UART0 + bool "Using RT_USING_UART0" + default n + config RT_USING_UART1 bool "Using RT_USING_UART1" default y diff --git a/bsp/beaglebone/applications/board.c b/bsp/beaglebone/applications/board.c index e1e1f8cae2a8b005d603427e72a84d5203ec9997..ae110fb57feec41036712eb27bf87eeba700c531 100644 --- a/bsp/beaglebone/applications/board.c +++ b/bsp/beaglebone/applications/board.c @@ -13,6 +13,7 @@ #include #include "board.h" +#include #include #ifdef RT_USING_VMM @@ -147,6 +148,16 @@ INIT_BOARD_EXPORT(rt_hw_timer_init); */ void rt_hw_board_init(void) { + rt_hw_mmu_init(); + + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + rt_components_board_init(); rt_console_set_device(RT_CONSOLE_DEVICE_NAME); } diff --git a/bsp/beaglebone/drivers/gpio.c b/bsp/beaglebone/drivers/gpio.c index 9fc0280b7db0f3d0b013f636b5ea9825013020d2..e21da9e0ef333c698e83a1f1bcf57215f4ae0a4a 100644 --- a/bsp/beaglebone/drivers/gpio.c +++ b/bsp/beaglebone/drivers/gpio.c @@ -3,14 +3,20 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Change Logs: + * Date Author Notes + * 2015-06-19 ItsEddy add gpio driver support + * 2022-09-14 YangZhongQing full gpio driver support + * I referred AM335X_StarterWare_02_00_01_01 */ - +#include #include #include #include #include +#include #include "gpio.h" #ifdef RT_USING_PIN @@ -20,12 +26,31 @@ #define GPIO_PIN_LOW (0x0) #define GPIO_PIN_HIGH (0x1) -#define GPIO_CLEARDATAOUT (0x190) -#define GPIO_SETDATAOUT (0x194) -#define GPIO_DATAIN (0x138) -#define GPIO_OE (0x134) +/* Values denoting the Interrupt Line number to be used. */ +#define GPIO_INT_LINE_1 (0x0) +#define GPIO_INT_LINE_2 (0x1) + +#define GPIO_REVISION (0x0) +#define GPIO_SYSCONFIG (0x10) +#define GPIO_IRQSTATUS_RAW(n) (0x24 + (n * 4)) +#define GPIO_IRQSTATUS(n) (0x2C + (n * 4)) +#define GPIO_IRQSTATUS_SET(n) (0x34 + (n * 4)) +#define GPIO_IRQSTATUS_CLR(n) (0x3C + (n * 4)) +#define GPIO_IRQWAKEN(n) (0x44 + (n * 4)) +#define GPIO_SYSSTATUS (0x114) +#define GPIO_CTRL (0x130) +#define GPIO_OE (0x134) +#define GPIO_DATAIN (0x138) +#define GPIO_DATAOUT (0x13C) +#define GPIO_LEVELDETECT(n) (0x140 + (n * 4)) +#define GPIO_RISINGDETECT (0x148) +#define GPIO_FALLINGDETECT (0x14C) +#define GPIO_DEBOUNCENABLE (0x150) +#define GPIO_DEBOUNCINGTIME (0x154) +#define GPIO_CLEARDATAOUT (0x190) +#define GPIO_SETDATAOUT (0x194) -static rt_base_t GPIO_BASE[] = +static const rt_base_t GPIO_BASE[] = { AM33XX_GPIO_0_REGS, AM33XX_GPIO_1_REGS, @@ -33,6 +58,85 @@ static rt_base_t GPIO_BASE[] = AM33XX_GPIO_3_REGS }; +#define GPIO_INT0x GPIO_INT0A +#define GPIO_INT1x GPIO_INT1A +#define GPIO_INT2x GPIO_INT2A +#define GPIO_INT3x GPIO_INT3A +static const rt_uint8_t GPIO_INTx[] = {GPIO_INT0x, GPIO_INT1x, GPIO_INT2x, GPIO_INT3x}; + +// auto determine which int line +#define GPIO_INT0_LINE ((GPIO_INT0x == GPIO_INT0A) ? GPIO_INT_LINE_1 : GPIO_INT_LINE_2) +#define GPIO_INT1_LINE ((GPIO_INT1x == GPIO_INT1A) ? GPIO_INT_LINE_1 : GPIO_INT_LINE_2) +#define GPIO_INT2_LINE ((GPIO_INT2x == GPIO_INT2A) ? GPIO_INT_LINE_1 : GPIO_INT_LINE_2) +#define GPIO_INT3_LINE ((GPIO_INT3x == GPIO_INT3A) ? GPIO_INT_LINE_1 : GPIO_INT_LINE_2) +static const rt_uint8_t GPIO_INT_LINEx[] = {GPIO_INT0_LINE, GPIO_INT1_LINE, GPIO_INT2_LINE, GPIO_INT3_LINE}; + +struct am33xx_pin_irq_hdr +{ + void (*hdr)(void *args); + void *args; +}; + +struct am33xx_gpio_irq_param +{ + struct am33xx_pin_irq_hdr hdr_tab[32]; +}; + +static struct am33xx_gpio_irq_param GPIO_PARAMx[sizeof(GPIO_BASE) / sizeof(GPIO_BASE[0])]; + +rt_inline void am33xx_gpio_hdr(rt_base_t base, rt_base_t int_line, void *param) +{ + struct am33xx_gpio_irq_param *irq_param = param; + struct am33xx_pin_irq_hdr *irq_hdr; + int pinNumber; + rt_ubase_t irqstatus; + + irqstatus = REG32(base + GPIO_IRQSTATUS(int_line)); + REG32(base + GPIO_IRQSTATUS(int_line)) = irqstatus; + + for (pinNumber = 0; pinNumber < sizeof(irq_param->hdr_tab); pinNumber++) + { + if (irqstatus & 0x1) + { + irq_hdr = &irq_param->hdr_tab[pinNumber]; + if (irq_hdr->hdr) + irq_hdr->hdr(irq_hdr->args); + // if the last one, exit immediately + if (irqstatus == 0x1) + break; + } + irqstatus >>= 1; + } +} + +static void am33xx_gpio0_isr(int vector, void *param) +{ + am33xx_gpio_hdr(AM33XX_GPIO_0_REGS, GPIO_INT0_LINE, param); +} + +static void am33xx_gpio1_isr(int vector, void *param) +{ + am33xx_gpio_hdr(AM33XX_GPIO_1_REGS, GPIO_INT1_LINE, param); +} + +static void am33xx_gpio2_isr(int vector, void *param) +{ + am33xx_gpio_hdr(AM33XX_GPIO_2_REGS, GPIO_INT2_LINE, param); +} + +static void am33xx_gpio3_isr(int vector, void *param) +{ + am33xx_gpio_hdr(AM33XX_GPIO_3_REGS, GPIO_INT3_LINE, param); +} + +static const rt_isr_handler_t GPIO_ISRx[] = +{ + am33xx_gpio0_isr, + am33xx_gpio1_isr, + am33xx_gpio2_isr, + am33xx_gpio3_isr, +}; + static void am33xx_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode) { RT_ASSERT(pin >= 0 && pin < 128); @@ -40,11 +144,11 @@ static void am33xx_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t m rt_base_t gpiox = pin >> 5; rt_base_t pinNumber = pin & 0x1F; - if(PIN_MODE_OUTPUT == mode) + if (PIN_MODE_OUTPUT == mode) { reg(GPIO_BASE[gpiox] + GPIO_OE) &= ~(1 << pinNumber); } - else if(PIN_MODE_INPUT == mode) + else if (PIN_MODE_INPUT == mode) { reg(GPIO_BASE[gpiox] + GPIO_OE) |= (1 << pinNumber); } @@ -56,7 +160,7 @@ static void am33xx_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t rt_base_t gpiox = pin >> 5; rt_base_t pinNumber = pin & 0x1F; - if(GPIO_PIN_HIGH == value) + if (GPIO_PIN_HIGH == value) { reg(GPIO_BASE[gpiox] + GPIO_SETDATAOUT) = (1 << pinNumber); } @@ -75,20 +179,196 @@ static int am33xx_pin_read(struct rt_device *device, rt_base_t pin) return reg(GPIO_BASE[gpiox] + GPIO_DATAIN) & (1 << pinNumber) ? 1 : 0; } -static struct rt_pin_ops am33xx_pin_ops = +static rt_err_t am33xx_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + RT_ASSERT(pin >= 0 && pin < 128); + rt_base_t gpiox = pin >> 5; + rt_base_t pinNumber = pin & 0x1F; + rt_base_t baseAdd = GPIO_BASE[gpiox]; + struct am33xx_pin_irq_hdr *irq_hdr = &GPIO_PARAMx[gpiox].hdr_tab[pinNumber]; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + + if (irq_hdr->hdr != RT_NULL) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + + irq_hdr->hdr = hdr; + irq_hdr->args = args; + + switch (mode) + { + case PIN_IRQ_MODE_RISING: + /* Enabling rising edge detect interrupt generation. */ + REG32(baseAdd + GPIO_RISINGDETECT) |= (1 << pinNumber); + + /* Disabling falling edge detect interrupt generation. */ + REG32(baseAdd + GPIO_FALLINGDETECT) &= ~(1 << pinNumber); + + /* Disabling logic LOW level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(0)) &= ~(1 << pinNumber); + + /* Disabling logic HIGH level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(1)) &= ~(1 << pinNumber); + break; + case PIN_IRQ_MODE_FALLING: + /* Disabling rising edge detect interrupt generation. */ + REG32(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber); + + /* Enabling falling edge detect interrupt generation. */ + REG32(baseAdd + GPIO_FALLINGDETECT) |= (1 << pinNumber); + + /* Disabling logic LOW level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(0)) &= ~(1 << pinNumber); + + /* Disabling logic HIGH level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(1)) &= ~(1 << pinNumber); + break; + case PIN_IRQ_MODE_RISING_FALLING: + /* Enabling rising edge detect interrupt generation. */ + REG32(baseAdd + GPIO_RISINGDETECT) |= (1 << pinNumber); + + /* Enabling falling edge detect interrupt generation. */ + REG32(baseAdd + GPIO_FALLINGDETECT) |= (1 << pinNumber); + + /* Disabling logic LOW level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(0)) &= ~(1 << pinNumber); + + /* Disabling logic HIGH level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(1)) &= ~(1 << pinNumber); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + /* Disabling logic LOW level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(0)) &= ~(1 << pinNumber); + + /* Enabling logic HIGH level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(1)) |= (1 << pinNumber); + + /* Disabling rising edge detect interrupt generation. */ + REG32(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber); + + /* Disabling falling edge detect interrupt generation. */ + REG32(baseAdd + GPIO_FALLINGDETECT) &= ~(1 << pinNumber); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + /* Enabling logic LOW level detect interrupt geenration. */ + REG32(baseAdd + GPIO_LEVELDETECT(0)) |= (1 << pinNumber); + + /* Disabling logic HIGH level detect interrupt generation. */ + REG32(baseAdd + GPIO_LEVELDETECT(1)) &= ~(1 << pinNumber); + + /* Disabling rising edge detect interrupt generation. */ + REG32(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber); + + /* Disabling falling edge detect interrupt generation. */ + REG32(baseAdd + GPIO_FALLINGDETECT) &= ~(1 << pinNumber); + break; + } + + rt_hw_interrupt_enable(level); + return 0; +} + +static rt_err_t am33xx_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + RT_ASSERT(pin >= 0 && pin < 128); + rt_base_t gpiox = pin >> 5; + rt_base_t pinNumber = pin & 0x1F; + struct am33xx_pin_irq_hdr *irq_hdr = &GPIO_PARAMx[gpiox].hdr_tab[pinNumber]; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + + irq_hdr->hdr = RT_NULL; + irq_hdr->args = RT_NULL; + + rt_hw_interrupt_enable(level); + return 0; +} + +static rt_err_t am33xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + RT_ASSERT(pin >= 0 && pin < 128); + rt_base_t gpiox = pin >> 5; + rt_base_t pinNumber = pin & 0x1F; + rt_base_t baseAdd = GPIO_BASE[gpiox]; + rt_base_t intLine = GPIO_INT_LINEx[gpiox]; + + if (enabled == PIN_IRQ_ENABLE) + REG32(baseAdd + GPIO_IRQSTATUS_SET(intLine)) = (1 << pinNumber); + else + REG32(baseAdd + GPIO_IRQSTATUS_CLR(intLine)) = (1 << pinNumber); + + return 0; +} + +// name format: P0.0, range: GPIO0_[31:0] ... GPIO5_[31:0] +static rt_base_t am33xx_pin_get(const char *name) +{ + rt_base_t gpiox; + rt_base_t pinNumber; + + if (!isdigit((int)name[1])) + return -RT_EINVAL; + gpiox = name[1] - '0'; + + if (name[2] != '.') + return -RT_EINVAL; + + if (!isdigit((int)name[3])) + return -RT_EINVAL; + pinNumber = name[3] - '0'; + + if (name[4] == '\0') + goto done; + else if (!isdigit((int)name[4])) + return -RT_EINVAL; + + pinNumber *= 10; + pinNumber += name[4] - '0'; + + if (name[5] != '\0') + return -RT_EINVAL; + +done: + if (pinNumber > 0x1F) + return -RT_EINVAL; + + return GET_PIN(gpiox, pinNumber); +} + +static const struct rt_pin_ops am33xx_pin_ops = { am33xx_pin_mode, am33xx_pin_write, am33xx_pin_read, - RT_NULL, - RT_NULL, - RT_NULL, - RT_NULL, + am33xx_pin_attach_irq, + am33xx_pin_detach_irq, + am33xx_pin_irq_enable, + am33xx_pin_get, }; int rt_hw_gpio_init(void) { - rt_device_pin_register("gpio", &am33xx_pin_ops , RT_NULL); + int vector; + rt_base_t gpiox; + char name[RT_NAME_MAX]; + + for (gpiox = 0; gpiox < 4; gpiox++) + { + rt_snprintf(name, sizeof(name), "%s%d", "gpio", gpiox); + vector = GPIO_INTx[gpiox]; + + rt_hw_interrupt_install(vector, GPIO_ISRx[gpiox], &GPIO_PARAMx[gpiox], name); + rt_hw_interrupt_control(vector, 0, 0); + rt_hw_interrupt_umask(vector); + } + + rt_device_pin_register("gpio", &am33xx_pin_ops, RT_NULL); return 0; } INIT_BOARD_EXPORT(rt_hw_gpio_init); diff --git a/bsp/beaglebone/drivers/gpio.h b/bsp/beaglebone/drivers/gpio.h index ffc4fce78091c7fb82f981d41559bd7c06b4c75d..b2be7d1837af4b409861a3853eb4afc4c839ee7a 100644 --- a/bsp/beaglebone/drivers/gpio.h +++ b/bsp/beaglebone/drivers/gpio.h @@ -8,6 +8,8 @@ #ifndef __GPIO_H__ #define __GPIO_H__ +#define GET_PIN(gpiox, pinNumber) (rt_base_t)(gpiox << 5 | pinNumber) + int rt_hw_gpio_init(void); #endif diff --git a/bsp/beaglebone/drivers/uart.c b/bsp/beaglebone/drivers/uart.c index 887bf2b1cd9fc6e08491155cd52ecb448cbd11d4..11d177359b0bfe23aa2ee8089cb0914c9b1dbd18 100644 --- a/bsp/beaglebone/drivers/uart.c +++ b/bsp/beaglebone/drivers/uart.c @@ -259,6 +259,7 @@ static void start_uart_clk(void) prcm_base = AM33XX_PRCM_REGS; +#if defined(RT_USING_UART1) || defined(RT_USING_UART2) || defined(RT_USING_UART3) || defined(RT_USING_UART4) || defined(RT_USING_UART5) /* software forced wakeup */ CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2; @@ -305,6 +306,26 @@ static void start_uart_clk(void) /* Waiting for the L4LS UART clock */ while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10))) ; +#endif + +#ifdef RT_USING_UART0 + /* software forced wakeup */ + CM_WKUP_CLKSTCTRL_REG(prcm_base) |= 0x2; + + /* Waiting for the L4_WKUP clock */ + while (!(CM_WKUP_CLKSTCTRL_REG(prcm_base) & (1<<2))) + ; + + /* enable uart0 */ + CM_WKUP_UART0_CLKCTRL_REG(prcm_base) |= 0x2; + /* wait for uart0 clk */ + while ((CM_WKUP_UART0_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; + + /* Waiting for the L4_WKUP UART0 clock */ + while (!(CM_WKUP_CLKSTCTRL_REG(prcm_base) & (1<<12))) + ; +#endif } static void config_pinmux(void) @@ -314,6 +335,11 @@ static void config_pinmux(void) ctlm_base = AM33XX_CTLM_REGS; /* make sure the pin mux is OK for uart */ +#ifdef RT_USING_UART0 + REG32(ctlm_base + 0x800 + 0x170) = 0x20; + REG32(ctlm_base + 0x800 + 0x174) = 0x00; +#endif + #ifdef RT_USING_UART1 REG32(ctlm_base + 0x800 + 0x180) = 0x20; REG32(ctlm_base + 0x800 + 0x184) = 0x00; diff --git a/bsp/beaglebone/rtconfig.h b/bsp/beaglebone/rtconfig.h index 798f314100cde0582f8891ef6b79cb53f12735f0..1a65854759ed17d5a05919566521a8b45adbe55c 100644 --- a/bsp/beaglebone/rtconfig.h +++ b/bsp/beaglebone/rtconfig.h @@ -43,8 +43,8 @@ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" -#define RT_VER_NUM 0x40101 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50000 /* RT-Thread Components */ @@ -181,15 +181,21 @@ /* entertainment: terminal games and other interesting software packages */ -/* Privated Packages of RealThread */ +/* Arduino libraries */ -/* Network Utilities */ +/* Sensor libraries */ -/* RT-Thread Smart */ +/* Display libraries */ + + +/* Timing libraries */ + + +/* Project libraries */ #define SOC_AM335X -#define RT_USING_UART1 +#define RT_USING_UART0 #endif diff --git a/bsp/beaglebone/uboot_cmd.txt b/bsp/beaglebone/uboot_cmd.txt index 08c49d2bf25177fc7ebbed636372dc0cccc4cf92..cba53f3a6950171b6324e0d725ede0465d1ed240 100644 --- a/bsp/beaglebone/uboot_cmd.txt +++ b/bsp/beaglebone/uboot_cmd.txt @@ -1,5 +1,11 @@ +通过SD卡加载 mmcinfo fatload mmc 0 0x80200000 rtthread.bin + +通过TFTP下载 +tftpboot 0x80200000 rtthread.bin + +跳转运行 go 0x80200000 其中的地址0x80200000根据链接地址确定 \ No newline at end of file diff --git a/libcpu/arm/am335x/am33xx.h b/libcpu/arm/am335x/am33xx.h index 3112a8ac1505d32a805673f9848e76ab9114298a..c74a0c1d62e2ffaa7a84932cd7f21fe80a87cb41 100644 --- a/libcpu/arm/am335x/am33xx.h +++ b/libcpu/arm/am335x/am33xx.h @@ -98,6 +98,8 @@ #define CM_PER_UART4_CLKCTRL(base) (CM_PER(base) + 0x78) #define CM_PER_UART5_CLKCTRL(base) (CM_PER(base) + 0x38) #define CM_WKUP(base) ((base) + 0x400) +#define CM_WKUP_CLKSTCTRL(base) (CM_WKUP(base) + 0) +#define CM_WKUP_UART0_CLKCTRL(base) (CM_WKUP(base) + 0xB4) #define CM_DPLL(base) ((base) + 0x500) #define CM_MPU(base) ((base) + 0x600) #define CM_DEVICE(base) ((base) + 0x700) @@ -194,6 +196,9 @@ #define PRM_PER_PWRSTST_REG(base) REG32(PRM_PER_PWRSTST(base)) #define PRM_PER_PWRSTCTRL_REG(base) REG32(PRM_PER_PWRSTCTRL(base)) +#define CM_WKUP_CLKSTCTRL_REG(base) REG32(CM_WKUP_CLKSTCTRL(base)) +#define CM_WKUP_UART0_CLKCTRL_REG(base) REG32(CM_WKUP_UART0_CLKCTRL(base)) + #define CM_DPLL_CLKSEL_TIMER7_CLK(base) REG32(CM_DPLL(base) + 0x4) #define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8) diff --git a/libcpu/arm/am335x/interrupt.c b/libcpu/arm/am335x/interrupt.c index c4c5e8d7eb6f082a93e2af564da1a2d9aabbad15..1810a92a65ba2cb55517754b07d108f2116a4b24 100644 --- a/libcpu/arm/am335x/interrupt.c +++ b/libcpu/arm/am335x/interrupt.c @@ -75,6 +75,16 @@ static void rt_hw_vector_init(void) */ void rt_hw_interrupt_init(void) { + /* Reset the ARM interrupt controller */ + INTC_SYSCONFIG(AINTC_BASE) = INTC_SYSCONFIG_SOFTRESET; + + /* Wait for the reset to complete */ + while((INTC_SYSSTATUS(AINTC_BASE) + & INTC_SYSSTATUS_RESETDONE) != INTC_SYSSTATUS_RESETDONE); + + /* Enable any interrupt generation by setting priority threshold */ + INTC_THRESHOLD(AINTC_BASE) = INTC_THRESHOLD_PRIORITYTHRESHOLD; + /* initialize vector table */ rt_hw_vector_init(); diff --git a/libcpu/arm/am335x/interrupt.h b/libcpu/arm/am335x/interrupt.h index 90f392f40704998553aa4a27226846d025666a9f..35239b198f65c694f464d9ab67a073880ea9891c 100644 --- a/libcpu/arm/am335x/interrupt.h +++ b/libcpu/arm/am335x/interrupt.h @@ -14,6 +14,9 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 +/*************************************************************************\ + * Registers Definition +\*************************************************************************/ #define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) #define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) #define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) @@ -37,6 +40,212 @@ #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) #define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* REVISION */ +#define INTC_REVISION_REV (0x000000FFu) +#define INTC_REVISION_REV_SHIFT (0x00000000u) + +/* SYSCONFIG */ +#define INTC_SYSCONFIG_SOFTRESET (0x00000002u) +#define INTC_SYSCONFIG_SOFTRESET_SHIFT (0x00000001u) + +#define INTC_SYSCONFIG_AUTOIDLE (0x00000001u) +#define INTC_SYSCONFIG_AUTOIDLE_SHIFT (0x00000000u) + +/* SYSSTATUS */ +#define INTC_SYSSTATUS_RESETDONE (0x00000001u) +#define INTC_SYSSTATUS_RESETDONE_SHIFT (0x00000000u) + +/* SIR_IRQ */ +#define INTC_SIR_IRQ_SPURIOUSIRQ (0xFFFFFF80u) +#define INTC_SIR_IRQ_SPURIOUSIRQ_SHIFT (0x00000007u) + +#define INTC_SIR_IRQ_ACTIVEIRQ (0x0000007F) +#define INTC_SIR_IRQ_ACTIVEIRQ_SHIFT (0x00000000) + +/* SIR_FIQ */ +#define INTC_SIR_FIQ_SPURIOUSFIQ (0xFFFFFF80) +#define INTC_SIR_FIQ_SPURIOUSFIQ_SHIFT (0x00000007) + +#define INTC_SIR_FIQ_ACTIVEFIQ (0x0000007F) +#define INTC_SIR_FIQ_ACTIVEFIQ_SHIFT (0x00000000) + +/* CONTROL */ +#define INTC_CONTROL_NEWFIQAGR (0x00000002) +#define INTC_CONTROL_NEWFIQAGR_SHIFT (0x00000001) + +#define INTC_CONTROL_NEWIRQAGR (0x00000001) +#define INTC_CONTROL_NEWIRQAGR_SHIFT (0x00000000) + +/* PROTECTION */ +#define INTC_PROTECTION_PROTECTION (0x00000001u) +#define INTC_PROTECTION_PROTECTION_SHIFT (0x00000000u) + +/* IDLE */ +#define INTC_IDLE_TURBO (0x00000002u) +#define INTC_IDLE_TURBO_SHIFT (0x00000001u) + +#define INTC_IDLE_FUNCIDLE (0x00000001u) +#define INTC_IDLE_FUNCIDLE_SHIFT (0x00000000u) + +/* IRQ_PRIORITY */ +#define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG (0xFFFFFFC0u) +#define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG_SHIFT (0x00000006u) + +#define INTC_IRQ_PRIORITY_IRQPRIORITY (0x0000003Fu) +#define INTC_IRQ_PRIORITY_IRQPRIORITY_SHIFT (0x00000000u) + +/* FIQ_PRIORITY */ +#define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG (0xFFFFFFC0u) +#define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG_SHIFT (0x00000006u) + +#define INTC_FIQ_PRIORITY_FIQPRIORITY (0x0000003Fu) +#define INTC_FIQ_PRIORITY_FIQPRIORITY_SHIFT (0x00000000u) + +/* THRESHOLD */ +#define INTC_THRESHOLD_PRIORITYTHRESHOLD (0x000000FFu) +#define INTC_THRESHOLD_PRIORITYTHRESHOLD_SHIFT (0x00000000u) + +/* SICR */ +#define INTC_SICR_GLOBALMASK (0x00000040u) +#define INTC_SICR_GLOBALMASK_SHIFT (0x00000006u) + +#define INTC_SICR_SOFTRESETINH (0x00000020u) +#define INTC_SICR_SOFTRESETINH_SHIFT (0x00000005u) + +#define INTC_SICR_PUBLICMASKFEEDBACK (0x00000010u) +#define INTC_SICR_PUBLICMASKFEEDBACK_SHIFT (0x00000004u) + +#define INTC_SICR_PUBLICINHIBIT (0x00000008u) +#define INTC_SICR_PUBLICINHIBIT_SHIFT (0x00000003u) + +#define INTC_SICR_AUTOINHIBIT (0x00000004u) +#define INTC_SICR_AUTOINHIBIT_SHIFT (0x00000002u) + +#define INTC_SICR_SSMFIQENABLE (0x00000002u) +#define INTC_SICR_SSMFIQENABLE_SHIFT (0x00000001u) + +#define INTC_SICR_SSMFIQSTATUS (0x00000001u) +#define INTC_SICR_SSMFIQSTATUS_SHIFT (0x00000000u) + +/* SCR0 */ +#define INTC_SCR0_SECUREENABLE (0xFFFFFFFFu) +#define INTC_SCR0_SECUREENABLE_SHIFT (0x00000000u) + +/* SCR1 */ +#define INTC_SCR1_SECUREENABLE (0xFFFFFFFFu) +#define INTC_SCR1_SECUREENABLE_SHIFT (0x00000000u) + +/* SCR2 */ +#define INTC_SCR2_SECUREENABLE (0xFFFFFFFFu) +#define INTC_SCR2_SECUREENABLE_SHIFT (0x00000000u) + +/* ITR0 */ +#define INTC_ITR0_ITR (0xFFFFFFFFu) +#define INTC_ITR0_ITR_SHIFT (0x00000000u) + +/* MIR0 */ +#define INTC_MIR0_MIR (0xFFFFFFFFu) +#define INTC_MIR0_MIR_SHIFT (0x00000000u) + +/* MIR_CLEAR0 */ +#define INTC_MIR_CLEAR0_MIRCLEAR (0xFFFFFFFFu) +#define INTC_MIR_CLEAR0_MIRCLEAR_SHIFT (0x00000000u) + +/* MIR_SET0 */ +#define INTC_MIR_SET0_MIRSET (0xFFFFFFFFu) +#define INTC_MIR_SET0_MIRSET_SHIFT (0x00000000u) + +/* ISR_SET0 */ +#define INTC_ISR_SET0_ISRSET (0xFFFFFFFFu) +#define INTC_ISR_SET0_ISRSET_SHIFT (0x00000000u) + +/* ISR_CLEAR0 */ +#define INTC_ISR_CLEAR0_ISRCLEAR (0xFFFFFFFFu) +#define INTC_ISR_CLEAR0_ISRCLEAR_SHIFT (0x00000000u) + +/* PENDING_IRQ0 */ +#define INTC_PENDING_IRQ0_PENDING_IRQ (0xFFFFFFFFu) +#define INTC_PENDING_IRQ0_PENDING_IRQ_SHIFT (0x00000000u) + +/* PENDING_FIQ0 */ +#define INTC_PENDING_FIQ0_PENDING_FIQ (0xFFFFFFFFu) +#define INTC_PENDING_FIQ0_PENDING_FIQ_SHIFT (0x00000000u) + +/* ITR1 */ +#define INTC_ITR1_ITR (0xFFFFFFFFu) +#define INTC_ITR1_ITR_SHIFT (0x00000000u) + +/* MIR1 */ +#define INTC_MIR1_MIR (0xFFFFFFFFu) +#define INTC_MIR1_MIR_SHIFT (0x00000000u) + +/* MIR_CLEAR1 */ +#define INTC_MIR_CLEAR1_MIRCLEAR (0xFFFFFFFFu) +#define INTC_MIR_CLEAR1_MIRCLEAR_SHIFT (0x00000000u) + +/* MIR_SET1 */ +#define INTC_MIR_SET1_MIRSET (0xFFFFFFFFu) +#define INTC_MIR_SET1_MIRSET_SHIFT (0x00000000u) + +/* ISR_SET1 */ +#define INTC_ISR_SET1_ISRSET (0xFFFFFFFFu) +#define INTC_ISR_SET1_ISRSET_SHIFT (0x00000000u) + +/* ISR_CLEAR1 */ +#define INTC_ISR_CLEAR1_ISRCLEAR (0xFFFFFFFFu) +#define INTC_ISR_CLEAR1_ISRCLEAR_SHIFT (0x00000000u) + +/* PENDING_IRQ1 */ +#define INTC_PENDING_IRQ1_PENDING_IRQ (0xFFFFFFFFu) +#define INTC_PENDING_IRQ1_PENDING_IRQ_SHIFT (0x00000000u) + +/* PENDING_FIQ1 */ +#define INTC_PENDING_FIQ1_PENDING_FIQ (0xFFFFFFFFu) +#define INTC_PENDING_FIQ1_PENDING_FIQ_SHIFT (0x00000000u) + +/* ITR2 */ +#define INTC_ITR2_ITR (0xFFFFFFFFu) +#define INTC_ITR2_ITR_SHIFT (0x00000000u) + +/* MIR2 */ +#define INTC_MIR2_MIR (0xFFFFFFFFu) +#define INTC_MIR2_MIR_SHIFT (0x00000000u) + +/* MIR_CLEAR2 */ +#define INTC_MIR_CLEAR2_MIRCLEAR (0xFFFFFFFFu) +#define INTC_MIR_CLEAR2_MIRCLEAR_SHIFT (0x00000000u) + +/* MIR_SET2 */ +#define INTC_MIR_SET2_MIRSET (0xFFFFFFFFu) +#define INTC_MIR_SET2_MIRSET_SHIFT (0x00000000u) + +/* ISR_SET2 */ +#define INTC_ISR_SET2_ISRSET (0xFFFFFFFFu) +#define INTC_ISR_SET2_ISRSET_SHIFT (0x00000000u) + +/* ISR_CLEAR2 */ +#define INTC_ISR_CLEAR2_ISRCLEAR (0xFFFFFFFFu) +#define INTC_ISR_CLEAR2_ISRCLEAR_SHIFT (0x00000000u) + +/* PENDING_IRQ2 */ +#define INTC_PENDING_IRQ2_PENDING_IRQ (0xFFFFFFFFu) +#define INTC_PENDING_IRQ2_PENDING_IRQ_SHIFT (0x00000000u) + +/* PENDING_FIQ2 */ +#define INTC_PENDING_FIQ2_PENDING_FIQ (0xFFFFFFFFu) +#define INTC_PENDING_FIQ2_PENDING_FIQ_SHIFT (0x00000000u) + +/* ILR */ +#define INTC_ILR_PRIORITY (0x000001FCu) +#define INTC_ILR_PRIORITY_SHIFT (0x00000002u) + +#define INTC_ILR_FIQNIRQ (0x00000001u) +#define INTC_ILR_FIQNIRQ_SHIFT (0x00000000u) + void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); void rt_hw_interrupt_ack(int fiq_irq);