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体验新版 GitCode,发现更多精彩内容 >>
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e5398b23
编写于
3月 30, 2013
作者:
B
Ben Skeggs
浏览文件
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电子邮件补丁
差异文件
drm/nvf0/disp: expose display class 2.2
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
893e90c5
变更
6
显示空白变更内容
内联
并排
Showing
6 changed file
with
107 addition
and
0 deletion
+107
-0
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/Makefile
+1
-0
drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
+89
-0
drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
+3
-0
drivers/gpu/drm/nouveau/core/include/core/class.h
drivers/gpu/drm/nouveau/core/include/core/class.h
+12
-0
drivers/gpu/drm/nouveau/core/include/engine/disp.h
drivers/gpu/drm/nouveau/core/include/engine/disp.h
+1
-0
drivers/gpu/drm/nouveau/nv50_display.c
drivers/gpu/drm/nouveau/nv50_display.c
+1
-0
未找到文件。
drivers/gpu/drm/nouveau/Makefile
浏览文件 @
e5398b23
...
...
@@ -160,6 +160,7 @@ nouveau-y += core/engine/disp/nva0.o
nouveau-y
+=
core/engine/disp/nva3.o
nouveau-y
+=
core/engine/disp/nvd0.o
nouveau-y
+=
core/engine/disp/nve0.o
nouveau-y
+=
core/engine/disp/nvf0.o
nouveau-y
+=
core/engine/disp/dacnv50.o
nouveau-y
+=
core/engine/disp/dport.o
nouveau-y
+=
core/engine/disp/hdanva3.o
...
...
drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
0 → 100644
浏览文件 @
e5398b23
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <engine/software.h>
#include <engine/disp.h>
#include <core/class.h>
#include "nv50.h"
static
struct
nouveau_oclass
nvf0_disp_sclass
[]
=
{
{
NVF0_DISP_MAST_CLASS
,
&
nvd0_disp_mast_ofuncs
},
{
NVF0_DISP_SYNC_CLASS
,
&
nvd0_disp_sync_ofuncs
},
{
NVF0_DISP_OVLY_CLASS
,
&
nvd0_disp_ovly_ofuncs
},
{
NVF0_DISP_OIMM_CLASS
,
&
nvd0_disp_oimm_ofuncs
},
{
NVF0_DISP_CURS_CLASS
,
&
nvd0_disp_curs_ofuncs
},
{}
};
static
struct
nouveau_oclass
nvf0_disp_base_oclass
[]
=
{
{
NVF0_DISP_CLASS
,
&
nvd0_disp_base_ofuncs
,
nva3_disp_base_omthds
},
{}
};
static
int
nvf0_disp_ctor
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nouveau_object
**
pobject
)
{
struct
nv50_disp_priv
*
priv
;
int
heads
=
nv_rd32
(
parent
,
0x022448
);
int
ret
;
ret
=
nouveau_disp_create
(
parent
,
engine
,
oclass
,
heads
,
"PDISP"
,
"display"
,
&
priv
);
*
pobject
=
nv_object
(
priv
);
if
(
ret
)
return
ret
;
nv_engine
(
priv
)
->
sclass
=
nvf0_disp_base_oclass
;
nv_engine
(
priv
)
->
cclass
=
&
nv50_disp_cclass
;
nv_subdev
(
priv
)
->
intr
=
nvd0_disp_intr
;
INIT_WORK
(
&
priv
->
supervisor
,
nvd0_disp_intr_supervisor
);
priv
->
sclass
=
nvf0_disp_sclass
;
priv
->
head
.
nr
=
heads
;
priv
->
dac
.
nr
=
3
;
priv
->
sor
.
nr
=
4
;
priv
->
dac
.
power
=
nv50_dac_power
;
priv
->
dac
.
sense
=
nv50_dac_sense
;
priv
->
sor
.
power
=
nv50_sor_power
;
priv
->
sor
.
hda_eld
=
nvd0_hda_eld
;
priv
->
sor
.
hdmi
=
nvd0_hdmi_ctrl
;
priv
->
sor
.
dp
=
&
nvd0_sor_dp_func
;
return
0
;
}
struct
nouveau_oclass
nvf0_disp_oclass
=
{
.
handle
=
NV_ENGINE
(
DISP
,
0x92
),
.
ofuncs
=
&
(
struct
nouveau_ofuncs
)
{
.
ctor
=
nvf0_disp_ctor
,
.
dtor
=
_nouveau_disp_dtor
,
.
init
=
_nouveau_disp_init
,
.
fini
=
_nouveau_disp_fini
,
},
};
drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
浏览文件 @
e5398b23
...
...
@@ -50,6 +50,9 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
case
NVE0_DISP_MAST_CLASS
:
case
NVE0_DISP_SYNC_CLASS
:
case
NVE0_DISP_OVLY_CLASS
:
case
NVF0_DISP_MAST_CLASS
:
case
NVF0_DISP_SYNC_CLASS
:
case
NVF0_DISP_OVLY_CLASS
:
break
;
default:
return
-
EINVAL
;
...
...
drivers/gpu/drm/nouveau/core/include/core/class.h
浏览文件 @
e5398b23
...
...
@@ -169,6 +169,7 @@ struct nv04_display_class {
* 8570: NVA3_DISP
* 9070: NVD0_DISP
* 9170: NVE0_DISP
* 9270: NVF0_DISP
*/
#define NV50_DISP_CLASS 0x00005070
...
...
@@ -178,6 +179,7 @@ struct nv04_display_class {
#define NVA3_DISP_CLASS 0x00008570
#define NVD0_DISP_CLASS 0x00009070
#define NVE0_DISP_CLASS 0x00009170
#define NVF0_DISP_CLASS 0x00009270
#define NV50_DISP_SOR_MTHD 0x00010000
#define NV50_DISP_SOR_MTHD_TYPE 0x0000f000
...
...
@@ -246,6 +248,7 @@ struct nv50_display_class {
* 857a: NVA3_DISP_CURS
* 907a: NVD0_DISP_CURS
* 917a: NVE0_DISP_CURS
* 927a: NVF0_DISP_CURS
*/
#define NV50_DISP_CURS_CLASS 0x0000507a
...
...
@@ -255,6 +258,7 @@ struct nv50_display_class {
#define NVA3_DISP_CURS_CLASS 0x0000857a
#define NVD0_DISP_CURS_CLASS 0x0000907a
#define NVE0_DISP_CURS_CLASS 0x0000917a
#define NVF0_DISP_CURS_CLASS 0x0000927a
struct
nv50_display_curs_class
{
u32
head
;
...
...
@@ -267,6 +271,7 @@ struct nv50_display_curs_class {
* 857b: NVA3_DISP_OIMM
* 907b: NVD0_DISP_OIMM
* 917b: NVE0_DISP_OIMM
* 927b: NVE0_DISP_OIMM
*/
#define NV50_DISP_OIMM_CLASS 0x0000507b
...
...
@@ -276,6 +281,7 @@ struct nv50_display_curs_class {
#define NVA3_DISP_OIMM_CLASS 0x0000857b
#define NVD0_DISP_OIMM_CLASS 0x0000907b
#define NVE0_DISP_OIMM_CLASS 0x0000917b
#define NVF0_DISP_OIMM_CLASS 0x0000927b
struct
nv50_display_oimm_class
{
u32
head
;
...
...
@@ -288,6 +294,7 @@ struct nv50_display_oimm_class {
* 857c: NVA3_DISP_SYNC
* 907c: NVD0_DISP_SYNC
* 917c: NVE0_DISP_SYNC
* 927c: NVF0_DISP_SYNC
*/
#define NV50_DISP_SYNC_CLASS 0x0000507c
...
...
@@ -297,6 +304,7 @@ struct nv50_display_oimm_class {
#define NVA3_DISP_SYNC_CLASS 0x0000857c
#define NVD0_DISP_SYNC_CLASS 0x0000907c
#define NVE0_DISP_SYNC_CLASS 0x0000917c
#define NVF0_DISP_SYNC_CLASS 0x0000927c
struct
nv50_display_sync_class
{
u32
pushbuf
;
...
...
@@ -310,6 +318,7 @@ struct nv50_display_sync_class {
* 857d: NVA3_DISP_MAST
* 907d: NVD0_DISP_MAST
* 917d: NVE0_DISP_MAST
* 927d: NVF0_DISP_MAST
*/
#define NV50_DISP_MAST_CLASS 0x0000507d
...
...
@@ -319,6 +328,7 @@ struct nv50_display_sync_class {
#define NVA3_DISP_MAST_CLASS 0x0000857d
#define NVD0_DISP_MAST_CLASS 0x0000907d
#define NVE0_DISP_MAST_CLASS 0x0000917d
#define NVF0_DISP_MAST_CLASS 0x0000927d
struct
nv50_display_mast_class
{
u32
pushbuf
;
...
...
@@ -331,6 +341,7 @@ struct nv50_display_mast_class {
* 857e: NVA3_DISP_OVLY
* 907e: NVD0_DISP_OVLY
* 917e: NVE0_DISP_OVLY
* 927e: NVF0_DISP_OVLY
*/
#define NV50_DISP_OVLY_CLASS 0x0000507e
...
...
@@ -340,6 +351,7 @@ struct nv50_display_mast_class {
#define NVA3_DISP_OVLY_CLASS 0x0000857e
#define NVD0_DISP_OVLY_CLASS 0x0000907e
#define NVE0_DISP_OVLY_CLASS 0x0000917e
#define NVF0_DISP_OVLY_CLASS 0x0000927e
struct
nv50_display_ovly_class
{
u32
pushbuf
;
...
...
drivers/gpu/drm/nouveau/core/include/engine/disp.h
浏览文件 @
e5398b23
...
...
@@ -44,5 +44,6 @@ extern struct nouveau_oclass nv94_disp_oclass;
extern
struct
nouveau_oclass
nva3_disp_oclass
;
extern
struct
nouveau_oclass
nvd0_disp_oclass
;
extern
struct
nouveau_oclass
nve0_disp_oclass
;
extern
struct
nouveau_oclass
nvf0_disp_oclass
;
#endif
drivers/gpu/drm/nouveau/nv50_display.c
浏览文件 @
e5398b23
...
...
@@ -2174,6 +2174,7 @@ int
nv50_display_create
(
struct
drm_device
*
dev
)
{
static
const
u16
oclass
[]
=
{
NVF0_DISP_CLASS
,
NVE0_DISP_CLASS
,
NVD0_DISP_CLASS
,
NVA3_DISP_CLASS
,
...
...
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