diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 37d1bb002aa97bbd3ea52b19304f746521e30bff..1557e7c2c7e15bc45120eedde3d288792676f235 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -56,7 +56,6 @@ _GLOBAL(__setup_cpu_power8) li r0,0 mtspr SPRN_LPID,r0 mfspr r3,SPRN_LPCR - oris r3, r3, LPCR_AIL_3@h bl __init_LPCR bl __init_HFSCR bl __init_tlb_power8 @@ -75,7 +74,6 @@ _GLOBAL(__restore_cpu_power8) li r0,0 mtspr SPRN_LPID,r0 mfspr r3,SPRN_LPCR - oris r3, r3, LPCR_AIL_3@h bl __init_LPCR bl __init_HFSCR bl __init_tlb_power8 diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index 1d33e817ab2d96e43317d2096e125354ea341109..3d7a50a08f5e17d080f701ff4a14a39da39aa6a1 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c @@ -195,6 +195,18 @@ static void fixup_boot_paca(void) get_paca()->data_offset = 0; } +static void cpu_ready_for_interrupts(void) +{ + /* Set IR and DR in PACA MSR */ + get_paca()->kernel_msr = MSR_KERNEL; + + /* Enable AIL if supported */ + if (cpu_has_feature(CPU_FTR_ARCH_207S)) { + unsigned long lpcr = mfspr(SPRN_LPCR); + mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); + } +} + /* * Early initialization entry point. This is called by head.S * with MMU translation disabled. We rely on the "feature" of @@ -264,9 +276,9 @@ void __init early_setup(unsigned long dt_ptr) /* * At this point, we can let interrupts switch to virtual mode * (the MMU has been setup), so adjust the MSR in the PACA to - * have IR and DR set. + * have IR and DR set and enable AIL if it exists */ - get_paca()->kernel_msr = MSR_KERNEL; + cpu_ready_for_interrupts(); /* Reserve large chunks of memory for use by CMA for KVM */ kvm_cma_reserve(); @@ -307,7 +319,7 @@ void early_setup_secondary(void) * (the MMU has been setup), so adjust the MSR in the PACA to * have IR and DR set. */ - get_paca()->kernel_msr = MSR_KERNEL; + cpu_ready_for_interrupts(); } #endif /* CONFIG_SMP */