drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag
Some asic revisions need to disable PG when UVD is active.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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Some asic revisions need to disable PG when UVD is active.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>