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由 Greg Ungerer 提交于
The ACR registers of the ColdFire define at a macro level what regions of the addresses space should have caching or other attribute types applied. Currently for the MMU enabled setups we map the interal IO peripheral addres space as uncachable based on the define for the MBAR address (CONFIG_MBAR). Not all ColdFire SoC use a programmable MBAR register address. Some parts have fixed addressing for their internal peripheral registers. Generalize the way we get the internal peripheral base address so all types can be accomodated in the ACR definitions. Each ColdFire SoC type now sets its IO memory base and size definitions (which may be based on MBAR) which are then used in the ACR definitions. Signed-off-by: NGreg Ungerer <gerg@linux-m68k.org>
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