提交 035f1324 编写于 作者: B Bin Li

Integrate hexnn wrapper and support unsigned PD

上级 8a0abcac
...@@ -328,6 +328,18 @@ class MACE_API MaceEngineConfig { ...@@ -328,6 +328,18 @@ class MACE_API MaceEngineConfig {
MaceStatus SetCPUThreadPolicy(int num_threads_hint, MaceStatus SetCPUThreadPolicy(int num_threads_hint,
CPUAffinityPolicy policy); CPUAffinityPolicy policy);
/// \brief Set Hexagon NN to run on unsigned PD
///
/// Caution: This function must be called before any Hexagon related
/// functions and it should only be called once.
/// Starting in the SM8150 family, signature-free dynamic module offload is
/// enabled on cDSP in a low-rights process (Unsigned PD). A success from this
/// function allows the clients to offload the dynamic shared object to cDSP
/// without signing. However, some older cDSP firmware may not work due to
/// access limitations.
/// \return MaceStatus::MACE_SUCCESS for success, other for failure.
MaceStatus SetHexagonToUnsignedPD();
/// \brief Set Hexagon DSP power parameters /// \brief Set Hexagon DSP power parameters
/// ///
/// Caution: this function may hurt performance if improper /// Caution: this function may hurt performance if improper
......
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#include "mace/port/env.h" #include "mace/port/env.h"
#include "mace/utils/memory.h" #include "mace/utils/memory.h"
#include "third_party/nnlib/hexagon_nn.h" #include "third_party/nnlib/hexagon_nn.h"
#include "third_party/nnlib/hexnn_dsp_controller.h"
namespace mace { namespace mace {
...@@ -106,6 +107,8 @@ hexagon_nn_corner_type TransformCornerType(HexagonNNCornerType corner) { ...@@ -106,6 +107,8 @@ hexagon_nn_corner_type TransformCornerType(HexagonNNCornerType corner) {
} // namespace } // namespace
HexagonDSPWrapper::HexagonDSPWrapper() { HexagonDSPWrapper::HexagonDSPWrapper() {
hexnn_controller_init();
std::string env_log_execute_time_str; std::string env_log_execute_time_str;
GetEnv("MACE_DSP_LOG_EXECUTE_TIME", &env_log_execute_time_str); GetEnv("MACE_DSP_LOG_EXECUTE_TIME", &env_log_execute_time_str);
if (env_log_execute_time_str.empty()) { if (env_log_execute_time_str.empty()) {
...@@ -115,6 +118,9 @@ HexagonDSPWrapper::HexagonDSPWrapper() { ...@@ -115,6 +118,9 @@ HexagonDSPWrapper::HexagonDSPWrapper() {
} }
} }
HexagonDSPWrapper::~HexagonDSPWrapper() {
hexnn_controller_deinit();
}
int HexagonDSPWrapper::GetVersion() { int HexagonDSPWrapper::GetVersion() {
int version; int version;
...@@ -122,6 +128,14 @@ int HexagonDSPWrapper::GetVersion() { ...@@ -122,6 +128,14 @@ int HexagonDSPWrapper::GetVersion() {
return version; return version;
} }
bool HexagonDSPWrapper::RequestUnsignedPD() {
int ret = hexnn_controller_request_unsigned_pd();
if (ret != 0) {
LOG(WARNING) << "Request unsigned PD failed: " << ret;
}
return ret == 0;
}
bool HexagonDSPWrapper::SetPower(HexagonNNCornerType corner, bool HexagonDSPWrapper::SetPower(HexagonNNCornerType corner,
bool dcvs_enable, bool dcvs_enable,
int latency) { int latency) {
...@@ -129,6 +143,9 @@ bool HexagonDSPWrapper::SetPower(HexagonNNCornerType corner, ...@@ -129,6 +143,9 @@ bool HexagonDSPWrapper::SetPower(HexagonNNCornerType corner,
dcvs_enable ? NN_DCVS_ENABLE dcvs_enable ? NN_DCVS_ENABLE
: NN_DCVS_DISABLE, : NN_DCVS_DISABLE,
static_cast<uint32_t>(std::max(0, latency))); static_cast<uint32_t>(std::max(0, latency)));
if (ret != 0) {
LOG(WARNING) << "Hexagon set power failed: " << ret;
}
return ret == 0; return ret == 0;
} }
...@@ -157,7 +174,6 @@ bool HexagonDSPWrapper::SetupGraph(const NetDef &net_def, ...@@ -157,7 +174,6 @@ bool HexagonDSPWrapper::SetupGraph(const NetDef &net_def,
int64_t t0 = NowMicros(); int64_t t0 = NowMicros();
// const node // const node
std::vector<hexagon_nn_const_node> const_node_list;
for (const ConstTensor &const_tensor : net_def.tensors()) { for (const ConstTensor &const_tensor : net_def.tensors()) {
std::vector<int> tensor_shape(const_tensor.dims().begin(), std::vector<int> tensor_shape(const_tensor.dims().begin(),
const_tensor.dims().end()); const_tensor.dims().end());
...@@ -165,48 +181,32 @@ bool HexagonDSPWrapper::SetupGraph(const NetDef &net_def, ...@@ -165,48 +181,32 @@ bool HexagonDSPWrapper::SetupGraph(const NetDef &net_def,
tensor_shape.insert(tensor_shape.begin(), 1); tensor_shape.insert(tensor_shape.begin(), 1);
} }
hexagon_nn_const_node const_node; unsigned char *data;
const_node.node_id = node_id(const_tensor.node_id()); int data_len;
const_node.tensor.batches = tensor_shape[0];
const_node.tensor.height = tensor_shape[1];
const_node.tensor.width = tensor_shape[2];
const_node.tensor.depth = tensor_shape[3];
if (const_tensor.data_type() == DataType::DT_INT32 && if (const_tensor.data_type() == DataType::DT_INT32 &&
const_tensor.data_size() == 0) { const_tensor.data_size() == 0) {
const_node.tensor.data = NULL; data = NULL;
const_node.tensor.dataLen = 0; data_len = 0;
} else { } else {
const_node.tensor.data = data = const_cast<unsigned char *>(model_data + const_tensor.offset());
const_cast<unsigned char *>(model_data + const_tensor.offset()); data_len =
const_node.tensor.dataLen = const_tensor.data_size() * const_tensor.data_size() * GetEnumTypeSize(const_tensor.data_type());
GetEnumTypeSize(const_tensor.data_type());
}
const_node_list.push_back(const_node);
// 255 is magic number: why fastrpc limits sequence length to that?
if (const_node_list.size() >= 250) {
MACE_CHECK(
hexagon_nn_append_const_node_list(nn_id_, const_node_list.data(),
const_node_list.size()) == 0,
"append const node error");
const_node_list.clear();
}
} }
if (!const_node_list.empty()) {
MACE_CHECK( MACE_CHECK(
hexagon_nn_append_const_node_list(nn_id_, const_node_list.data(), hexagon_nn_append_const_node(nn_id_,
const_node_list.size()) == 0, node_id(const_tensor.node_id()),
tensor_shape[0],
tensor_shape[1],
tensor_shape[2],
tensor_shape[3],
data,
data_len) == 0,
"append const node error"); "append const node error");
} }
const_node_list.clear();
// op node // op node
OpMap op_map; OpMap op_map;
op_map.Init(); op_map.Init();
std::vector<hexagon_nn_op_node> op_node_list;
std::vector<std::vector<hexagon_nn_input>> cached_inputs;
std::vector<std::vector<hexagon_nn_output>> cached_outputs;
std::vector<hexagon_nn_input> inputs; std::vector<hexagon_nn_input> inputs;
std::vector<hexagon_nn_output> outputs; std::vector<hexagon_nn_output> outputs;
...@@ -233,40 +233,18 @@ bool HexagonDSPWrapper::SetupGraph(const NetDef &net_def, ...@@ -233,40 +233,18 @@ bool HexagonDSPWrapper::SetupGraph(const NetDef &net_def,
outputs[i].zero_offset = 0; outputs[i].zero_offset = 0;
outputs[i].stepsize = 0; outputs[i].stepsize = 0;
} }
cached_inputs.push_back(inputs); auto padding_type = static_cast<hexagon_nn_padding_type>(op.padding());
cached_outputs.push_back(outputs);
hexagon_nn_padding_type padding_type =
static_cast<hexagon_nn_padding_type>(op.padding());
hexagon_nn_op_node op_node;
op_node.node_id = node_id(op.node_id());
op_node.operation = op_id;
op_node.padding = padding_type;
op_node.inputs = cached_inputs.back().data();
op_node.inputsLen = inputs.size();
op_node.outputs = cached_outputs.back().data();
op_node.outputsLen = outputs.size();
op_node_list.push_back(op_node);
if (op_node_list.size() >= 125) {
MACE_CHECK(hexagon_nn_append_node_list(nn_id_, op_node_list.data(),
op_node_list.size()) == 0,
"append node error");
op_node_list.clear();
cached_inputs.clear();
cached_outputs.clear();
}
}
if (!op_node_list.empty()) { MACE_CHECK(hexagon_nn_append_node(nn_id_,
MACE_CHECK(hexagon_nn_append_node_list(nn_id_, op_node_list.data(), node_id(op.node_id()),
op_node_list.size()) == 0, op_id,
padding_type,
inputs.data(),
inputs.size(),
outputs.data(),
outputs.size()) == 0,
"append node error"); "append node error");
} }
op_node_list.clear();
cached_inputs.clear();
cached_outputs.clear();
// input info // input info
num_inputs_ = net_def.input_info_size(); num_inputs_ = net_def.input_info_size();
...@@ -372,7 +350,8 @@ void HexagonDSPWrapper::GetPerfInfo() { ...@@ -372,7 +350,8 @@ void HexagonDSPWrapper::GetPerfInfo() {
std::vector<std::vector<std::string>> run_order_data; std::vector<std::vector<std::string>> run_order_data;
for (unsigned int i = 0; i < n_items; ++i) { for (unsigned int i = 0; i < n_items; ++i) {
unsigned int node_id = perf_info[i].node_id; unsigned int node_id = perf_info[i].node_id;
unsigned int node_type_id = perf_info[i].node_type; unsigned int node_type_id = 0;
hexagon_nn_get_nodetype(nn_id_, node_id, &node_type_id);
node_id_counters[node_id] = node_id_counters[node_id] =
((static_cast<uint64_t>(perf_info[i].counter_hi) << 32) + ((static_cast<uint64_t>(perf_info[i].counter_hi) << 32) +
perf_info[i].counter_lo) * perf_info[i].counter_lo) *
......
...@@ -28,6 +28,7 @@ namespace mace { ...@@ -28,6 +28,7 @@ namespace mace {
class HexagonDSPWrapper : public HexagonControlWrapper { class HexagonDSPWrapper : public HexagonControlWrapper {
public: public:
HexagonDSPWrapper(); HexagonDSPWrapper();
~HexagonDSPWrapper();
int GetVersion() override; int GetVersion() override;
bool Config() override; bool Config() override;
...@@ -49,6 +50,7 @@ class HexagonDSPWrapper : public HexagonControlWrapper { ...@@ -49,6 +50,7 @@ class HexagonDSPWrapper : public HexagonControlWrapper {
static bool SetPower(HexagonNNCornerType corner, static bool SetPower(HexagonNNCornerType corner,
bool dcvs_enable, bool dcvs_enable,
int latency); int latency);
static bool RequestUnsignedPD();
private: private:
uint64_t GetLastExecuteCycles(); uint64_t GetLastExecuteCycles();
......
...@@ -192,6 +192,8 @@ class MaceEngineConfig::Impl { ...@@ -192,6 +192,8 @@ class MaceEngineConfig::Impl {
MaceStatus SetCPUThreadPolicy(int num_threads_hint, MaceStatus SetCPUThreadPolicy(int num_threads_hint,
CPUAffinityPolicy policy); CPUAffinityPolicy policy);
MaceStatus SetHexagonToUnsignedPD();
MaceStatus SetHexagonPower(HexagonNNCornerType corner, MaceStatus SetHexagonPower(HexagonNNCornerType corner,
bool dcvs_enable, bool dcvs_enable,
int latency); int latency);
...@@ -220,6 +222,18 @@ class MaceEngineConfig::Impl { ...@@ -220,6 +222,18 @@ class MaceEngineConfig::Impl {
return gpu_perf_hint_; return gpu_perf_hint_;
} }
inline HexagonNNCornerType hexagon_corner() const {
return hexagon_corner_;
}
inline bool hexagon_dcvs_enable() const {
return hexagon_dcvs_enable_;
}
inline int hexagon_latency() const {
return hexagon_latency_;
}
private: private:
DeviceType device_type_; DeviceType device_type_;
int num_threads_; int num_threads_;
...@@ -227,6 +241,9 @@ class MaceEngineConfig::Impl { ...@@ -227,6 +241,9 @@ class MaceEngineConfig::Impl {
std::shared_ptr<GPUContext> gpu_context_; std::shared_ptr<GPUContext> gpu_context_;
GPUPriorityHint gpu_priority_hint_; GPUPriorityHint gpu_priority_hint_;
GPUPerfHint gpu_perf_hint_; GPUPerfHint gpu_perf_hint_;
HexagonNNCornerType hexagon_corner_;
bool hexagon_dcvs_enable_;
int hexagon_latency_;
}; };
MaceEngineConfig::Impl::Impl(const DeviceType device_type) MaceEngineConfig::Impl::Impl(const DeviceType device_type)
...@@ -235,13 +252,10 @@ MaceEngineConfig::Impl::Impl(const DeviceType device_type) ...@@ -235,13 +252,10 @@ MaceEngineConfig::Impl::Impl(const DeviceType device_type)
cpu_affinity_policy_(CPUAffinityPolicy::AFFINITY_NONE), cpu_affinity_policy_(CPUAffinityPolicy::AFFINITY_NONE),
gpu_context_(nullptr), gpu_context_(nullptr),
gpu_priority_hint_(GPUPriorityHint::PRIORITY_LOW), gpu_priority_hint_(GPUPriorityHint::PRIORITY_LOW),
gpu_perf_hint_(GPUPerfHint::PERF_NORMAL) { gpu_perf_hint_(GPUPerfHint::PERF_NORMAL),
#ifdef MACE_ENABLE_HEXAGON hexagon_corner_(HexagonNNCornerType::HEXAGON_NN_CORNER_TURBO),
if (!HexagonDSPWrapper::SetPower(HEXAGON_NN_CORNER_TURBO, true, 100)) { hexagon_dcvs_enable_(true),
LOG(WARNING) << "Hexagon set default clocks failed!"; hexagon_latency_(100) {}
}
#endif
}
MaceStatus MaceEngineConfig::Impl::SetGPUContext( MaceStatus MaceEngineConfig::Impl::SetGPUContext(
std::shared_ptr<GPUContext> context) { std::shared_ptr<GPUContext> context) {
...@@ -265,13 +279,21 @@ MaceStatus MaceEngineConfig::Impl::SetCPUThreadPolicy( ...@@ -265,13 +279,21 @@ MaceStatus MaceEngineConfig::Impl::SetCPUThreadPolicy(
return MaceStatus::MACE_SUCCESS; return MaceStatus::MACE_SUCCESS;
} }
MaceStatus MaceEngineConfig::Impl::SetHexagonToUnsignedPD() {
bool ret = false;
#ifdef MACE_ENABLE_HEXAGON
ret = HexagonDSPWrapper::RequestUnsignedPD();
#endif
return ret ? MaceStatus::MACE_SUCCESS : MaceStatus::MACE_RUNTIME_ERROR;
}
MaceStatus MaceEngineConfig::Impl::SetHexagonPower( MaceStatus MaceEngineConfig::Impl::SetHexagonPower(
HexagonNNCornerType corner, HexagonNNCornerType corner,
bool dcvs_enable, bool dcvs_enable,
int latency) { int latency) {
MACE_UNUSED(corner); hexagon_corner_ = corner;
MACE_UNUSED(dcvs_enable); hexagon_dcvs_enable_ = dcvs_enable;
MACE_UNUSED(latency); hexagon_latency_ = latency;
bool ret = false; bool ret = false;
#ifdef MACE_ENABLE_HEXAGON #ifdef MACE_ENABLE_HEXAGON
ret = HexagonDSPWrapper::SetPower(corner, dcvs_enable, latency); ret = HexagonDSPWrapper::SetPower(corner, dcvs_enable, latency);
...@@ -302,6 +324,10 @@ MaceStatus MaceEngineConfig::SetCPUThreadPolicy( ...@@ -302,6 +324,10 @@ MaceStatus MaceEngineConfig::SetCPUThreadPolicy(
return impl_->SetCPUThreadPolicy(num_threads_hint, policy); return impl_->SetCPUThreadPolicy(num_threads_hint, policy);
} }
MaceStatus MaceEngineConfig::SetHexagonToUnsignedPD() {
return impl_->SetHexagonToUnsignedPD();
}
MaceStatus MaceEngineConfig::SetHexagonPower( MaceStatus MaceEngineConfig::SetHexagonPower(
HexagonNNCornerType corner, HexagonNNCornerType corner,
bool dcvs_enable, bool dcvs_enable,
...@@ -434,6 +460,11 @@ class MaceEngine::Impl { ...@@ -434,6 +460,11 @@ class MaceEngine::Impl {
std::map<std::string, mace::InputOutputInfo> input_info_map_; std::map<std::string, mace::InputOutputInfo> input_info_map_;
std::map<std::string, mace::InputOutputInfo> output_info_map_; std::map<std::string, mace::InputOutputInfo> output_info_map_;
std::unique_ptr<utils::ThreadPool> thread_pool_; std::unique_ptr<utils::ThreadPool> thread_pool_;
#ifdef MACE_ENABLE_HEXAGON
HexagonNNCornerType hexagon_corner_;
bool hexagon_dcvs_enable_;
int hexagon_latency_;
#endif
#if defined(MACE_ENABLE_HEXAGON) || defined(MACE_ENABLE_HTA) #if defined(MACE_ENABLE_HEXAGON) || defined(MACE_ENABLE_HTA)
std::unique_ptr<HexagonControlWrapper> hexagon_controller_; std::unique_ptr<HexagonControlWrapper> hexagon_controller_;
#endif #endif
...@@ -454,8 +485,13 @@ MaceEngine::Impl::Impl(const MaceEngineConfig &config) ...@@ -454,8 +485,13 @@ MaceEngine::Impl::Impl(const MaceEngineConfig &config)
is_quantized_model_(false), is_quantized_model_(false),
thread_pool_(new utils::ThreadPool(config.impl_->num_threads(), thread_pool_(new utils::ThreadPool(config.impl_->num_threads(),
config.impl_->cpu_affinity_policy())) config.impl_->cpu_affinity_policy()))
#ifdef MACE_ENABLE_HEXAGON
, hexagon_corner_(config.impl_->hexagon_corner())
, hexagon_dcvs_enable_(config.impl_->hexagon_dcvs_enable())
, hexagon_latency_(config.impl_->hexagon_latency())
#endif
#if defined(MACE_ENABLE_HEXAGON) || defined(MACE_ENABLE_HTA) #if defined(MACE_ENABLE_HEXAGON) || defined(MACE_ENABLE_HTA)
, hexagon_controller_(nullptr) , hexagon_controller_(nullptr)
#endif #endif
#ifdef MACE_ENABLE_APU #ifdef MACE_ENABLE_APU
, apu_controller_(nullptr) , apu_controller_(nullptr)
...@@ -554,6 +590,13 @@ MaceStatus MaceEngine::Impl::Init( ...@@ -554,6 +590,13 @@ MaceStatus MaceEngine::Impl::Init(
output_tensor->set_data_format(DataFormat::NHWC); output_tensor->set_data_format(DataFormat::NHWC);
#endif #endif
} }
#ifdef MACE_ENABLE_HEXAGON
if (device_type_ == HEXAGON) {
HexagonDSPWrapper::SetPower(hexagon_corner_,
hexagon_dcvs_enable_,
hexagon_latency_);
}
#endif
#if defined(MACE_ENABLE_HEXAGON) || defined(MACE_ENABLE_HTA) #if defined(MACE_ENABLE_HEXAGON) || defined(MACE_ENABLE_HTA)
if (device_type_ == HEXAGON || device_type_ == HTA) { if (device_type_ == HEXAGON || device_type_ == HTA) {
hexagon_controller_ = CreateHexagonControlWrapper(device_.get()); hexagon_controller_ = CreateHexagonControlWrapper(device_.get());
......
...@@ -197,6 +197,9 @@ bool RunModel(const std::string &model_name, ...@@ -197,6 +197,9 @@ bool RunModel(const std::string &model_name,
} }
#endif // MACE_ENABLE_OPENCL #endif // MACE_ENABLE_OPENCL
#ifdef MACE_ENABLE_HEXAGON #ifdef MACE_ENABLE_HEXAGON
// SetHexagonToUnsignedPD() can be called for 8150 family(with new cDSP
// firmware) or 8250 family above to run hexagon nn on unsigned PD.
// config.SetHexagonToUnsignedPD();
config.SetHexagonPower(HEXAGON_NN_CORNER_TURBO, true, 100); config.SetHexagonPower(HEXAGON_NN_CORNER_TURBO, true, 100);
#endif #endif
std::unique_ptr<mace::port::ReadOnlyMemoryRegion> model_graph_data = std::unique_ptr<mace::port::ReadOnlyMemoryRegion> model_graph_data =
......
...@@ -20,6 +20,7 @@ cc_library( ...@@ -20,6 +20,7 @@ cc_library(
]), ]),
hdrs = [ hdrs = [
"hexagon_nn.h", "hexagon_nn.h",
"hexnn_dsp_controller.h",
"ops.h", "ops.h",
], ],
visibility = ["//visibility:public"], visibility = ["//visibility:public"],
......
/* /*
* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the * modification, are permitted (subject to the limitations in the
...@@ -87,13 +87,15 @@ struct hexagon_nn_output { ...@@ -87,13 +87,15 @@ struct hexagon_nn_output {
typedef struct hexagon_nn_perfinfo hexagon_nn_perfinfo; typedef struct hexagon_nn_perfinfo hexagon_nn_perfinfo;
struct hexagon_nn_perfinfo { struct hexagon_nn_perfinfo {
unsigned int node_id; unsigned int node_id;
unsigned int node_type;
unsigned int executions; unsigned int executions;
unsigned int unused;
unsigned int counter_lo; unsigned int counter_lo;
unsigned int counter_hi; unsigned int counter_hi;
}; };
typedef int hexagon_nn_nn_id; typedef int hexagon_nn_nn_id;
typedef struct hexagon_nn_initinfo hexagon_nn_initinfo;
struct hexagon_nn_initinfo {
int priority;
};
enum hexagon_nn_padding_type { enum hexagon_nn_padding_type {
NN_PAD_NA, NN_PAD_NA,
NN_PAD_SAME, NN_PAD_SAME,
...@@ -133,7 +135,47 @@ struct hexagon_nn_tensordef { ...@@ -133,7 +135,47 @@ struct hexagon_nn_tensordef {
unsigned int data_valid_len; unsigned int data_valid_len;
unsigned int unused; unsigned int unused;
}; };
enum hexagon_nn_execute_result {
NN_EXECUTE_SUCCESS,
NN_EXECUTE_ERROR,
NN_EXECUTE_BUFFER_SIZE_ERROR,
_32BIT_PLACEHOLDER_hexagon_nn_execute_result = 0x7fffffff
};
typedef enum hexagon_nn_execute_result hexagon_nn_execute_result;
typedef struct hexagon_nn_execute_info hexagon_nn_execute_info;
struct hexagon_nn_execute_info {
hexagon_nn_execute_result result;
unsigned char* extraInfo;
int extraInfoLen;
unsigned int extraInfoValidLen;
};
enum hexagon_nn_option_type {
NN_OPTION_NOSUCHOPTION,
NN_OPTION_SCALAR_THREADS,
NN_OPTION_HVX_THREADS,
NN_OPTION_VTCM_REQ,
NN_OPTION_ENABLE_GRAPH_PRINT,
NN_OPTION_ENABLE_TENSOR_PRINT,
NN_OPTION_TENSOR_PRINT_FILTER,
NN_OPTION_HAP_MEM_GROW_SIZE,
NN_OPTION_ENABLE_CONST_PRINT,
NN_OPTION_LASTPLUSONE,
_32BIT_PLACEHOLDER_hexagon_nn_option_type = 0x7fffffff
};
typedef enum hexagon_nn_option_type hexagon_nn_option_type;
typedef struct hexagon_nn_uint_option hexagon_nn_uint_option;
struct hexagon_nn_uint_option {
unsigned int option_id;
unsigned int uint_value;
};
typedef struct hexagon_nn_string_option hexagon_nn_string_option;
struct hexagon_nn_string_option {
unsigned int option_id;
char string_data[256];
};
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_config)(void) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_config)(void) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_config_with_options)(const hexagon_nn_uint_option* uint_options, int uint_optionsLen, const hexagon_nn_string_option* string_options, int string_optionsLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_graph_config)(hexagon_nn_nn_id id, const hexagon_nn_uint_option* uint_options, int uint_optionsLen, const hexagon_nn_string_option* string_options, int string_optionsLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_get_dsp_offset)(unsigned int* libhexagon_addr, unsigned int* fastrpc_shell_addr) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_get_dsp_offset)(unsigned int* libhexagon_addr, unsigned int* fastrpc_shell_addr) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_init)(hexagon_nn_nn_id* g) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_init)(hexagon_nn_nn_id* g) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_debug_level)(hexagon_nn_nn_id id, int level) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_debug_level)(hexagon_nn_nn_id id, int level) __QAIC_HEADER_ATTRIBUTE;
...@@ -143,26 +185,12 @@ __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_append_node)(hexagon_nn_nn_id ...@@ -143,26 +185,12 @@ __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_append_node)(hexagon_nn_nn_id
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_append_const_node)(hexagon_nn_nn_id id, unsigned int node_id, unsigned int batches, unsigned int height, unsigned int width, unsigned int depth, const unsigned char* data, int dataLen) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_append_const_node)(hexagon_nn_nn_id id, unsigned int node_id, unsigned int batches, unsigned int height, unsigned int width, unsigned int depth, const unsigned char* data, int dataLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_append_empty_const_node)(hexagon_nn_nn_id id, unsigned int node_id, unsigned int batches, unsigned int height, unsigned int width, unsigned int depth, unsigned int size) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_append_empty_const_node)(hexagon_nn_nn_id id, unsigned int node_id, unsigned int batches, unsigned int height, unsigned int width, unsigned int depth, unsigned int size) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_populate_const_node)(hexagon_nn_nn_id id, unsigned int node_id, const unsigned char* data, int dataLen, unsigned int target_offset) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_populate_const_node)(hexagon_nn_nn_id id, unsigned int node_id, const unsigned char* data, int dataLen, unsigned int target_offset) __QAIC_HEADER_ATTRIBUTE;
typedef struct hexagon_nn_op_node hexagon_nn_op_node;
struct hexagon_nn_op_node {
unsigned int node_id;
unsigned int operation;
hexagon_nn_padding_type padding;
hexagon_nn_input* inputs;
int inputsLen;
hexagon_nn_output* outputs;
int outputsLen;
};
typedef struct hexagon_nn_const_node hexagon_nn_const_node;
struct hexagon_nn_const_node {
unsigned int node_id;
hexagon_nn_tensordef tensor;
};
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_append_node_list)(hexagon_nn_nn_id id, const hexagon_nn_op_node* ops, int opsLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_append_const_node_list)(hexagon_nn_nn_id id, const hexagon_nn_const_node* consts, int constsLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_prepare)(hexagon_nn_nn_id id) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_prepare)(hexagon_nn_nn_id id) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_execute)(hexagon_nn_nn_id id, unsigned int batches_in, unsigned int height_in, unsigned int width_in, unsigned int depth_in, const unsigned char* data_in, int data_inLen, unsigned int* batches_out, unsigned int* height_out, unsigned int* width_out, unsigned int* depth_out, unsigned char* data_out, int data_outLen, unsigned int* data_len_out) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_execute)(hexagon_nn_nn_id id, unsigned int batches_in, unsigned int height_in, unsigned int width_in, unsigned int depth_in, const unsigned char* data_in, int data_inLen, unsigned int* batches_out, unsigned int* height_out, unsigned int* width_out, unsigned int* depth_out, unsigned char* data_out, int data_outLen, unsigned int* data_len_out) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_teardown)(hexagon_nn_nn_id id) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_teardown)(hexagon_nn_nn_id id) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_variable_read)(hexagon_nn_nn_id id, unsigned int node_id, int output_index, unsigned int* batches_out, unsigned int* height_out, unsigned int* width_out, unsigned int* depth_out, unsigned char* data_out, int data_outLen, unsigned int* data_len_out) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_variable_write)(hexagon_nn_nn_id id, unsigned int node_id, int output_index, unsigned int batches, unsigned int height, unsigned int width, unsigned int depth, const unsigned char* data_in, int data_inLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_variable_write_flat)(hexagon_nn_nn_id id, unsigned int node_id, int output_index, const unsigned char* data_in, int data_inLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_powersave_level)(unsigned int level) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_powersave_level)(unsigned int level) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_powersave_details)(hexagon_nn_corner_type corner, hexagon_nn_dcvs_type dcvs, unsigned int latency) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_powersave_details)(hexagon_nn_corner_type corner, hexagon_nn_dcvs_type dcvs, unsigned int latency) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_clocks)(hexagon_nn_corner_type corner, hexagon_nn_dcvs_type dcvs, unsigned int latency) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_clocks)(hexagon_nn_corner_type corner, hexagon_nn_dcvs_type dcvs, unsigned int latency) __QAIC_HEADER_ATTRIBUTE;
...@@ -173,10 +201,19 @@ __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_last_execution_cycles)(hexagon ...@@ -173,10 +201,19 @@ __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_last_execution_cycles)(hexagon
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_version)(int* ver) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_version)(int* ver) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_op_name_to_id)(const char* name, unsigned int* node_id) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_op_name_to_id)(const char* name, unsigned int* node_id) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_op_id_to_name)(unsigned int node_id, char* name, int nameLen) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_op_id_to_name)(unsigned int node_id, char* name, int nameLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_get_num_nodes_in_graph)(hexagon_nn_nn_id id, unsigned int* num_nodes) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_disable_dcvs)(void) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_disable_dcvs)(void) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_GetHexagonBinaryVersion)(int* ver) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_GetHexagonBinaryVersion)(int* ver) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_PrintLog)(const unsigned char* buf, int bufLen) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_PrintLog)(const unsigned char* buf, int bufLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_execute_new)(hexagon_nn_nn_id id, const hexagon_nn_tensordef* inputs, int inputsLen, hexagon_nn_tensordef* outputs, int outputsLen) __QAIC_HEADER_ATTRIBUTE; __QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_execute_new)(hexagon_nn_nn_id id, const hexagon_nn_tensordef* inputs, int inputsLen, hexagon_nn_tensordef* outputs, int outputsLen) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_execute_with_info)(hexagon_nn_nn_id id, const hexagon_nn_tensordef* inputs, int inputsLen, hexagon_nn_tensordef* outputs, int outputsLen, hexagon_nn_execute_info* execute_info) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_init_with_info)(hexagon_nn_nn_id* g, const hexagon_nn_initinfo* info) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_get_nodetype)(hexagon_nn_nn_id graph_id, hexagon_nn_nn_id node_id, unsigned int* node_type) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_multi_execution_cycles)(hexagon_nn_nn_id id, unsigned int* cycles_lo, unsigned int* cycles_hi) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_get_power)(int type) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_set_graph_option)(hexagon_nn_nn_id id, const char* name, int value) __QAIC_HEADER_ATTRIBUTE;
__QAIC_HEADER_EXPORT int __QAIC_HEADER(hexagon_nn_populate_graph)(hexagon_nn_nn_id id, const unsigned char* graph_data, int graph_dataLen) __QAIC_HEADER_ATTRIBUTE;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
......
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef THIRD_PARTY_NNLIB_HEXNN_DSP_CONTROLLER_H_
#define THIRD_PARTY_NNLIB_HEXNN_DSP_CONTROLLER_H_
#ifdef __cplusplus
extern "C" {
#endif
int hexnn_controller_request_unsigned_pd();
int hexnn_controller_init();
int hexnn_controller_deinit();
#ifdef __cplusplus
}
#endif
#endif // THIRD_PARTY_NNLIB_HEXNN_DSP_CONTROLLER_H_
/* /*
* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the * modification, are permitted (subject to the limitations in the
......
/* /*
* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the * modification, are permitted (subject to the limitations in the
......
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