diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html new file mode 100644 index 0000000000000000000000000000000000000000..b80f38df1cace2d8ef9f127285850ea813d953b5 --- /dev/null +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html @@ -0,0 +1,284 @@ + + + + + + + + + + + + +Release Notes for STM32F10x CMSIS + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F10x CMSIS

+

Copyright 2011 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x CMSIS +update History
    2. +
  2. License
    3. +
+ +

STM32F10x CMSIS +update History


+

V3.5.0 / 11-March-2011

+

Main +Changes

+ +
    +
  • stm32f10x.h +and startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt +definition for STM32F10x High-density Value line devices.
    +
    • +
  • system_stm32f10x.c file provided within the CMSIS folder.
    +
    • + +
+ +

3.4.0 +- 10/15/2010

+ +
    +
  1. General
    2. +
+ +
    +
  • Add support +for STM32F10x High-density Value line devices.
    • +
+
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. +
+ + + +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
        • +
      • RCC, AFIO, FSMC bits definition updated
        • +
      +
    • + + All +STM32 devices definitions are commented by default. User has to select the +appropriate device before starting else an error will be signaled on compile +time.
      • +
    • Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.
      • +
    • "bool" type removed.
      +
      • +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • "system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
      +
      • +
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
      • +
    • Add "VECT_TAB_SRAM" inside "system_stm32f10x.c" +to select if the user want to place the Vector Table in internal SRAM. +An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
      +
      • + +
    +
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three +startup files for STM32 High-density Value line devices: + startup_stm32f10x_hd_vl.s
    +
+

3.3.0 +- 04/16/2010

+ +
  1. General
+
  • Add support +for STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  1. STM32F10x CMSIS Device Peripheral Access Layer
+ +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. 
      +
  • STM32F10x CMSIS startup files:
    • add three +startup files for STM32 XL-density devices: + startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain
+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
    • +
  • Directory structure updated to be aligned with CMSIS V1.30
    +
    • +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices. 
    • + +
+
    +
  1. CMSIS Core Peripheral Access Layer
+ +
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. + +
+ +
    + +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • +
      +
    • Update +the stm32f10x.h file to support new Value line devices features: CEC +peripheral, new General purpose timers TIM15, TIM16 and TIM17.
      • +
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
      +
      • +
    • HSE_Value, +HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, +HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy +purposes.
      +
      • +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • SystemFrequency variable name changed to SystemCoreClock
      +
      • +
    • Default + SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
      +
      • +
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
      +
      • +
    • Additional function void SystemCoreClockUpdate (void) is provided.
      +
      • +
    +
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • +
      +
    • Add new +startup files for STM32 Low-density Value line devices: + startup_stm32f10x_ld_vl.s
      • +
    • Add new startup +files for STM32 Medium-density Value line devices: + startup_stm32f10x_md_vl.s
      • +
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      +To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
      +
      • +
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
      +
      • +
    + +
+ +
    +
+

License

+

The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

+

THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

+

 

+
+
+

For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s index 2ca88c254820e8ea42d6519fe3a835c60f3f337c..e34a520671a3664298d813eb8b58d3f01c3756f1 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s @@ -1,33 +1,34 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_cl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Connectivity line Devices vector table for Atollic - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR - * address. - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Connectivity line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -469,4 +470,4 @@ g_pfnVectors: .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler ,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s index dc976502ebe8bd4f1da64bf2febd05a067f2bc9f..0aa91884f27623cc000d5a894af7b7addde1b54c 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s @@ -1,33 +1,34 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_hd.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x High Density Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure the clock system - * - Configure external SRAM mounted on STM3210E-EVAL board - * to be used as data memory (optional, to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x High Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Configure external SRAM mounted on STM3210E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -465,4 +466,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s index 179299095e324178555371261bf33579576fe3fc..55aa398616bc08c94c683701ca2dac5c39536677 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s @@ -1,33 +1,35 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_hd_vl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x High Density Value Line Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Configure external SRAM mounted on STM32100E-EVAL board - * to be used as data memory (optional, to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x High Density Value Line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Configure external SRAM mounted on STM32100E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -191,7 +193,7 @@ g_pfnVectors: .word TIM14_IRQHandler .word 0 .word 0 - .word FSMC_IRQHandler + .word 0 .word 0 .word TIM5_IRQHandler .word SPI3_IRQHandler @@ -412,9 +414,6 @@ g_pfnVectors: .weak TIM14_IRQHandler .thumb_set TIM14_IRQHandler,Default_Handler - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler @@ -448,5 +447,5 @@ g_pfnVectors: .weak DMA2_Channel5_IRQHandler .thumb_set DMA2_Channel5_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s index 828fc8e18fac5deba31c89e6a0113bad5549bdda..2c5aaa06be416e5933dcabe2adb1dd7142de2e5f 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s @@ -1,31 +1,32 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_ld.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Low Density Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address. - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Low Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -343,4 +344,4 @@ g_pfnVectors: .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s index 6ac820acddba2ef5a1554b37b55174d235c834c8..9af6e8ba0b135d7721bdc2f3353d81c7e757e58d 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s @@ -1,31 +1,32 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_ld_vl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -387,5 +388,5 @@ g_pfnVectors: .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s index cc92a1e31ae393270444e96089452f2f3a3e2269..c14ba210426ec0340526efef9175c7d6d7226eef 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s @@ -1,31 +1,32 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_md.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -358,5 +359,5 @@ g_pfnVectors: .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s index abb71f65bbdc55db314cdd14625b8293e354fe0b..4ac1230db377105c6c3d95a0b7c2a24a4d082363 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s @@ -1,31 +1,33 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_md_vl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -402,5 +404,5 @@ g_pfnVectors: .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s index 46bdf874d78677d180914ff13ae5e1487ff4119a..19bdf5a8c9defbea5bde3443732c6fd517b9b008 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s @@ -1,33 +1,34 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_xl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM3210E-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_xl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -463,4 +464,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s index 47da7d8acfecf47441821539d86ad2715c4fd5ab..8196e697fd0cef12b399d4225832b6e34770bf02 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_cl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM ;* toolchain. ;* This module performs: @@ -365,4 +365,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s index 179921d8750cdcd685d974bb47931ad54a80210c..adc9b94a93bcd33646138ee08ae32479c2cb28a2 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_hd.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x High Density Devices vector table for MDK-ARM ;* toolchain. ;* This module performs: @@ -355,4 +355,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s index 4465a1a6bb702a2879c0be2e7486482ae1459bbb..d6082b09614880736dfcd678a346b738a6cf6396 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_hd_vl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x High Density Value Line Devices vector table ;* for MDK-ARM toolchain. ;* This module performs: @@ -126,7 +126,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TIM14_IRQHandler ; TIM14 DCD 0 ; Reserved DCD 0 ; Reserved - DCD FSMC_IRQHandler ; FSMC + DCD 0 ; Reserved DCD 0 ; Reserved DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 @@ -244,7 +244,6 @@ Default_Handler PROC EXPORT TIM12_IRQHandler [WEAK] EXPORT TIM13_IRQHandler [WEAK] EXPORT TIM14_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] @@ -299,7 +298,6 @@ CEC_IRQHandler TIM12_IRQHandler TIM13_IRQHandler TIM14_IRQHandler -FSMC_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler @@ -345,4 +343,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s index 54c7187a502669458a7b99eb1f2457b5c759f80d..3f3ac2ffd384fd8a6118c7065c0b87415f6cd0bc 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_ld.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Low Density Devices vector table for MDK-ARM ;* toolchain. ;* This module performs: @@ -294,4 +294,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s index bcb7aaf307244e410341145d99abb62fc57a3fbc..fe22fc011b1ece401386dea6d5ac84b7ab6abfa4 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_ld_vl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Low Density Value Line Devices vector table ;* for MDK-ARM toolchain. ;* This module performs: @@ -301,4 +301,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s index bb65342ad3308a1c7866924266be76ee57e839ae..3223fc95b3307d001799a339ac9fd46f953e8986 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_md.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM ;* toolchain. ;* This module performs: @@ -304,4 +304,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s index 67109eed817fef2ae758470a0920eb614874b933..d3b8aa6c1532fdb7c9c58958f15310b657e2719d 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_md_vl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Medium Density Value Line Devices vector table ;* for MDK-ARM toolchain. ;* This module performs: @@ -312,4 +312,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s index b3b6484c1f96900c6b3de31db14beadb114ae480..7970052d7c24e7ce6db36520dc283ca0d6ddd370 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_xl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM ;* toolchain. ;* This module performs: @@ -355,4 +355,4 @@ __user_initial_stackheap END -;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***** +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s index b017eb811af454b2c7413620a39f16e65f77f8e4..039ec06ca0a370cbba7b8a9d56072cfed1a96c80 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s @@ -1,32 +1,33 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_cl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR - * address. - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -464,4 +465,4 @@ g_pfnVectors: .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler ,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s index a1b1f93974d01dc0d1305d623a55fa50db1c5524..e4ba08c4191235ec5c9e4afd537752c6d278bdaa 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s @@ -1,33 +1,34 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_hd.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM3210E-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -461,4 +462,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s index 9bfd877aba6c7924b8941207db6306aafda52235..daad5cc34b53e44a458cad800eca3502862afe4a 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s @@ -1,34 +1,35 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_hd_vl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x High Density Value Line Devices vector table for RIDE7 - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM32100E-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x High Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM32100E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -187,7 +188,7 @@ g_pfnVectors: .word TIM14_IRQHandler .word 0 .word 0 - .word FSMC_IRQHandler + .word 0 .word 0 .word TIM5_IRQHandler .word SPI3_IRQHandler @@ -405,9 +406,6 @@ g_pfnVectors: .weak TIM14_IRQHandler .thumb_set TIM14_IRQHandler,Default_Handler - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler @@ -441,4 +439,4 @@ g_pfnVectors: .weak DMA2_Channel5_IRQHandler .thumb_set DMA2_Channel5_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s index c3dbf4147ab69a292628a1a225d5fadd943bd1ca..aaa09ecd4b604895223b9260120ce23329956c7c 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s @@ -1,31 +1,32 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_ld.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -339,4 +340,4 @@ g_pfnVectors: .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s index c2e23536d141b00334cd9b3a33347d83a1fce505..d4401be2f56cce63960af7b1e67b8095d33b3b72 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s @@ -1,32 +1,33 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_ld_vl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -379,4 +380,4 @@ g_pfnVectors: .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s index b91fbd7db47d3f3484b3f66747aa53f7eacdd5f1..4b4a0502be35098ee511c7bf78dd1a2434bfe218 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s @@ -1,31 +1,32 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_md.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -354,4 +355,4 @@ g_pfnVectors: .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s index 368b91519fe8a5125621842ea45f12c9a5513aed..8bce9979bcc5b3abc4cbb335693fecf5ad7e4d58 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s @@ -1,32 +1,33 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_md_vl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -395,4 +396,4 @@ g_pfnVectors: .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s index 4ae953823a5b9beb100b19ba4ab818e0c5f016fd..3d727a0d55ffb090c405fd49302933799e275390 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s @@ -1,33 +1,34 @@ /** - ****************************************************************************** - * @file startup_stm32f10x_xl.s - * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 - * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM3210E-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + ****************************************************************************** + * @file startup_stm32f10x_xl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ .syntax unified .cpu cortex-m3 @@ -461,4 +462,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s index 8e317de20b8a8854212c9bd7d508daf59b344317..55a79320bdcf1ee547fcd2119a1e9151dc5c77c1 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************* ;* File Name : startup_stm32f10x_cl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Connectivity line devices vector table for -;* EWARM5.x toolchain. +;* EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Configure the clock system @@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ +;******************************************************************************* ; ; ; The modules in this file are included in the libraries, and may be replaced @@ -504,4 +504,4 @@ OTG_FS_IRQHandler B OTG_FS_IRQHandler END -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s index cb30e58d6958e6d993693d70e11734201f21c952..37ee7a203f89e7719162a2cc8d76d260e64cd24e 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s @@ -1,9 +1,9 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_hd.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 -;* Description : STM32F10x High Density Devices vector table for EWARM5.x +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x High Density Devices vector table for EWARM ;* toolchain. ;* This module performs: ;* - Set the initial SP @@ -21,7 +21,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ +;******************************************************************************* ; ; ; The modules in this file are included in the libraries, and may be replaced @@ -493,4 +493,4 @@ DMA2_Channel4_5_IRQHandler END -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s index 5d872cbfb958b1318eeb4d829e8e28b7b75fa0bf..33f592f1a5689160aab6afb498cb1d81349d92bd 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_hd_vl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x High Density Value Line Devices vector table -;* for EWARM5.x toolchain. +;* for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Configure the clock system and the external SRAM @@ -22,7 +22,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ +;******************************************************************************* ; ; ; The modules in this file are included in the libraries, and may be replaced @@ -119,7 +119,7 @@ __vector_table DCD TIM14_IRQHandler ; TIM14 DCD 0 ; Reserved DCD 0 ; Reserved - DCD FSMC_IRQHandler ; FSMC + DCD 0 ; Reserved DCD 0 ; Reserved DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 @@ -402,11 +402,6 @@ TIM13_IRQHandler TIM14_IRQHandler B TIM14_IRQHandler - PUBWEAK FSMC_IRQHandler - SECTION .text:CODE:REORDER(1) -FSMC_IRQHandler - B FSMC_IRQHandler - PUBWEAK TIM5_IRQHandler SECTION .text:CODE:REORDER(1) TIM5_IRQHandler @@ -463,4 +458,4 @@ DMA2_Channel5_IRQHandler B DMA2_Channel5_IRQHandler END -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s index 8377fbba2e7ef01286b1ec50391ca42b66ed9029..e2b2b4df0671d796b3d41680b841575c4a7927b9 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s @@ -1,9 +1,9 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_ld.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 -;* Description : STM32F10x Low Density Devices vector table for EWARM5.x +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Low Density Devices vector table for EWARM ;* toolchain. ;* This module performs: ;* - Set the initial SP @@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ +;******************************************************************************* ; ; ; The modules in this file are included in the libraries, and may be replaced @@ -363,4 +363,4 @@ USBWakeUp_IRQHandler B USBWakeUp_IRQHandler END -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s index ec86189757dc6638c83ef222a0e0bbd7e6b1f172..a4a49331c5b7c09d3b15d3ccf85bc7fc67be57a5 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_ld_vl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Low Density Value Line Devices vector table -;* for EWARM5.x toolchain. +;* for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Configure the clock system @@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ +;******************************************************************************* ; ; ; The modules in this file are included in the libraries, and may be replaced @@ -366,4 +366,4 @@ TIM7_IRQHandler B TIM7_IRQHandler END -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s index f06c5435cd075a5c6a683557e2d371ece2430103..5863eb90f471205cf9261ba7493002e9c891e5a1 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_md.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Medium Density Devices vector table for -;* EWARM5.x toolchain. +;* EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Configure the clock system @@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ +;******************************************************************************* ; ; ; The modules in this file are included in the libraries, and may be replaced @@ -388,4 +388,4 @@ USBWakeUp_IRQHandler B USBWakeUp_IRQHandler END -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s index 5d3b7134c71e9c3406ff01061f729a6d8be65da1..add509da6c08119952a1414264af30de08d4e0d2 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_md_vl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 +;* Version : V3.5.0 +;* Date : 11-March-2011 ;* Description : STM32F10x Medium Density Value Line Devices vector table -;* for EWARM5.x toolchain. +;* for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Configure the clock system @@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ +;******************************************************************************* ; ; ; The modules in this file are included in the libraries, and may be replaced @@ -391,4 +391,4 @@ TIM7_IRQHandler B TIM7_IRQHandler END -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s index 9ed63d54a933a13d1cad89e2fbd15376b77b82a3..a7f49c56dd06776231cee4196ce37d4455a56f8d 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s @@ -1,9 +1,9 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** ;* File Name : startup_stm32f10x_xl.s ;* Author : MCD Application Team -;* Version : V3.4.0 -;* Date : 10/15/2010 -;* Description : STM32F10x XL-Density Devices vector table for EWARM5.x +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x XL-Density Devices vector table for EWARM ;* toolchain. ;* This module performs: ;* - Set the initial SP @@ -21,7 +21,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ +;******************************************************************************* ; ; ; The modules in this file are included in the libraries, and may be replaced @@ -493,4 +493,4 @@ DMA2_Channel4_5_IRQHandler END -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h index fc6d74dc6ec3ba6c3b5593c4ca2134d165e24b2d..af0c7c9af19790ef545988914bbed1b3b8c217ba 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h @@ -2,15 +2,31 @@ ****************************************************************************** * @file stm32f10x.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F10x Connectivity line, * High density, High density value line, Medium density, * Medium density Value line, Low density, Low density Value line * and XL-density devices. - ****************************************************************************** + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -19,7 +35,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

+ *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ @@ -116,12 +132,14 @@ /** * @brief STM32F10x Standard Peripheral Library version number */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ - | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ - | __STM32F10X_STDPERIPH_VERSION_SUB2) +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F10X_STDPERIPH_VERSION_RC)) /** * @} @@ -346,7 +364,6 @@ typedef enum IRQn TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ @@ -358,7 +375,7 @@ typedef enum IRQn DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is - mapped at postion 60 only if the MISC_REMAP bit in + mapped at position 60 only if the MISC_REMAP bit in the AFIO_MAPR2 register is set) */ #endif /* STM32F10X_HD_VL */ @@ -1005,7 +1022,7 @@ typedef struct __IO uint32_t MAPR2; } AFIO_TypeDef; /** - * @brief Inter-integrated Circuit Interface + * @brief Inter Integrated Circuit Interface */ typedef struct @@ -1953,7 +1970,7 @@ typedef struct #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ #endif /* STM32F10X_LD && STM32F10X_LD_VL */ @@ -2663,7 +2680,7 @@ typedef struct #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ /*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ #endif /***************** Bit definition for AFIO_EXTICR1 register *****************/ @@ -3210,7 +3227,7 @@ typedef struct #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ /*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ @@ -3218,7 +3235,7 @@ typedef struct #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ /******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ @@ -3413,7 +3430,7 @@ typedef struct #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ @@ -3468,7 +3485,7 @@ typedef struct /******************* Bit definition for DMA_CCR2 register *******************/ #define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ #define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ #define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ #define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ @@ -3515,166 +3532,166 @@ typedef struct #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ /*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*!
© COPYRIGHT 2011 STMicroelectronics
+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h index 22ce5a06fc9c332e9ce3688380f1ed78c4af7801..739f33283e5a64b1913a5476d430ba11a8bbbd4e 100644 --- a/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h +++ b/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h @@ -2,10 +2,11 @@ ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** + ****************************************************************************** + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -14,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

+ *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ @@ -94,4 +95,4 @@ extern void SystemCoreClockUpdate(void); /** * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html new file mode 100644 index 0000000000000000000000000000000000000000..633e42e35edab2cdf33ee38a40243aaf36de2d0e --- /dev/null +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html @@ -0,0 +1,342 @@ + + + + + + + + + + + + +Release Notes for STM32F10x Standard Peripherals Library Drivers + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F10x Standard Peripherals Library Drivers +(StdPeriph_Driver)

+

Copyright 2011 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x Standard Peripherals Library +Drivers update History
    2. +
  2. License
    3. +
+ + +

STM32F10x Standard +Peripherals Library Drivers  update History


+

V3.5.0 / 11-March-2011

+

Main +Changes

+ +
    +
  • stm32f10x_can.h/.c files:
    • +
      +
    • Add 5 new functions
      • +
        +
      • 3 +new functions controlling the counter errors: CAN_GetLastErrorCode(), +CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().
        • +
      +
        +
      • 1 new function to select the CAN operating mode: CAN_OperatingModeRequest().
        • +
      +
        +
      • 1 new function to support CAN TT mode: CAN_TTComModeCmd().
        +
        • +
      +
    • CAN_TransmitStatus() function updated to support all CAN transmit intermediate states
      +
      • +
    +
  • stm32f10x_i2c.h/.c files:
    • +
      +
    • Add 1 new function:
      • +
        +
      • I2C_NACKPositionConfig(): +This function configures the same bit (POS) as I2C_PECPositionConfig() +but is intended to be used in I2C mode while I2C_PECPositionConfig() is +intended to used in SMBUS mode.
        • +
      +
    +
  • stm32f10x_tim.h/.c files:
    • +
      +
    • Change the TIM_DMABurstLength_xBytes definitions to TIM_DMABurstLength_xTansfers
      +
      • +
    + + +
+ +

3.4.0 +- 10/15/2010

+ +
    +
  1. General
    2. +
+ +
    +
  • Add support for STM32F10x High-density value line devices.
    • +
+ +
    +
  1. STM32F10x_StdPeriph_Driver
    2. +
+ + +
    + +
  • stm32f10x_bkp.h/.c
    • +
      +
    • Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_can.h/.c
    • +
      +
    • Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.
      +
      • +
    • Update the wording of some defines and Asserts macro.
      +
      • +
    • CAN_GetFlagStatus() +and CAN_ClearFlag() functions: updated to support new flags (were not +supported in previous version). These flags are:  CAN_FLAG_RQCP0, +CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1, +CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,   CAN_FLAG_FOV0, +CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC.
      +
      • +
    • CAN_GetITStatus() +function: add a check of the interrupt enable bit before getting the +status of corresponding interrupt pending bit.
      +
      • +
    • CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit.
      +
      • +
    +
  • stm32f10x_crc.h/.c
    • +
      +
    • Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_dac.h/.c
    • +
      +
    • Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_dbgmcu.h/.c
    • +
      +
    • Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_dma.h/.c
    • +
      +
    • Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.
      • +
    • Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"
      +
      • +
    +
  • stm32f10x_flash.h/.c
    • +
      +
    • FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.
      • +
    +
  • stm32f10x_fsmc.h/.c
    • +
      +
    • Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.
      • +
    +
  • stm32f10x_gpio.h/.c
    • +
      +
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.
      • +
    +
  • stm32f10x_pwr.h/.c
    • +
      +
    • Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.
      • +
    +
  • stm32f10x_rtc.h/.c
    • +
      +
    • Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.
      • +
    +
  • stm32f10x_spi.h/.c
    • +
      +
    • Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".
      • +
    +
  • stm32f10x_tim.h/.c
    • +
    • Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".
    + +
+ +

3.3.0 +- 04/16/2010

+ +
  1. General
+
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
+
  1. STM32F10x_StdPeriph_Driver
+
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: +updated to support Bank2 of XL-density devices (up to 1MByte of Flash +memory). For more details, refer to the description provided within +stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() +function: updated to check whether the last event contains the +I2C_EVENT  (instead of check whether the last event is equal to +I2C_EVENT)
    • Add +detailed description of I2C events and how to manage them using the +functions provided by this driver. For more information, refer to +stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h: 
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
        +#define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000000)
        #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000001)
      by
        #define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000001)
        #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000000)
+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices.
    • +
  • Almost +peripherals drivers were updated to support Value +line devices features
    • +
  • Drivers limitations fix and enhancements.
    • + +
+
    +
  1. STM32F10x_StdPeriph_Driver
    2. +
+
    +
  • Add new +firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
    • +
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
    • +
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
    • +
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
    • +
  • USART +driver: add support for Oversampling by 8 mode and onebit method. 2 +functions has been added: USART_OverSampling8Cmd() and +USART_OneBitMethodCmd().
    +
    • +
  • DAC +driver: add new functions handling the DAC under run feature: +DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() +and DAC_ClearITPendingBit().
    • +
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
    +
    • +
  • FLASH +driver: the FLASH_EraseOptionBytes() function updated. This is now just +erasing the option bytes without modifying the RDP status either +enabled or disabled.
    • +
  • PWR +driver: the PWR_EnterSTOPMode() function updated. When woken up from +STOP mode, this function resets again the SLEEPDEEP bit in the +Cortex-M3 System Control register to allow Sleep mode entering.
    • + + +
+

License

+

The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

+

THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

+

 

+
+
+

For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h index 7a93d5a1ad77e87c72157b58b49eebee5dc58871..7d401ca9be1ef48a98fc453bdf441259c3887271 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file misc.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MISC_H @@ -216,4 +217,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h index 26e725fa17d027e908b915e1cd35857205bd39e6..d1b2653a66e0a6644bcabb8828b695433098be32 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_adc.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_ADC_H @@ -479,4 +480,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h index dc40ec22ec44e5da4f59f9a61bbdfbdfd25e5dc9..b620753eff8d56b0fba3752f68e698f4fca02923 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_bkp.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the BKP firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_BKP_H @@ -191,4 +192,4 @@ void BKP_ClearITPendingBit(void); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h index 544d779c0a5f91209080051862da3c9185ee7d4f..648f747cdc8d8fffb9f2de6695cd77252197d7f5 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_can.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CAN firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CAN_H @@ -51,38 +52,51 @@ typedef struct { - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware - is allowed to lengthen or shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ + This parameter can be set either to ENABLE or + DISABLE. */ - FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ + FunctionalState CAN_NART; /*!< Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ + This parameter can be set either to ENABLE + or DISABLE. */ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ + This parameter can be set either to ENABLE + or DISABLE. */ } CAN_InitTypeDef; /** @@ -91,36 +105,36 @@ typedef struct typedef struct { - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. This parameter can be a value of @ref CAN_filter_scale */ - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. This parameter can be set either to ENABLE or DISABLE. */ } CAN_FilterInitTypeDef; @@ -136,16 +150,20 @@ typedef struct uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ - uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_identifier_type */ + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ - uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ - uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter can be a value between 0 to 8 */ + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ } CanTxMsg; /** @@ -160,19 +178,23 @@ typedef struct uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ - uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_identifier_type */ + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + This parameter can be a value of + @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8 */ - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ - uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter can be a value between 0 to 0xFF */ + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ } CanRxMsg; /** @@ -187,14 +209,14 @@ typedef struct * @{ */ -#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ /** * @} */ -/** @defgroup CAN_operating_mode +/** @defgroup CAN_Mode * @{ */ @@ -203,8 +225,40 @@ typedef struct #define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ #define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ + ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || \ + ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + + +/** + * @defgroup CAN_Operating_Mode + * @{ + */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)) +/** + * @} + */ + +/** + * @defgroup CAN_Mode_Status + * @{ + */ + +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ + + /** * @} */ @@ -295,7 +349,7 @@ typedef struct * @{ */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ #define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ @@ -322,11 +376,10 @@ typedef struct * @{ */ -#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ ((FIFO) == CAN_FilterFIFO1)) - /** * @} */ @@ -356,10 +409,10 @@ typedef struct * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) - +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) /** * @} */ @@ -368,9 +421,9 @@ typedef struct * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) /** * @} @@ -380,10 +433,10 @@ typedef struct * @{ */ -#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */ -#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ /** * @} @@ -393,8 +446,8 @@ typedef struct * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) @@ -406,8 +459,8 @@ typedef struct * @{ */ -#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ /** * @} @@ -417,8 +470,27 @@ typedef struct * @{ */ -#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** + * @defgroup CAN_Error_Code_constants + * @{ + */ + +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ + /** * @} @@ -508,20 +580,44 @@ typedef struct #define CAN_IT_RQCP2 CAN_IT_TME -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +/** + * @} + */ + +/** @defgroup CAN_Legacy + * @{ + */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok /** * @} @@ -542,22 +638,40 @@ typedef struct /** @defgroup CAN_Exported_Functions * @{ */ - +/* Function used to set the CAN configuration to the default reset state *****/ void CAN_DeInit(CAN_TypeDef* CANx); + +/* Initialization and Configuration functions *********************************/ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); + +/* Transmit functions *********************************************************/ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); + +/* Receive functions **********************************************************/ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); + + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); uint8_t CAN_Sleep(CAN_TypeDef* CANx); uint8_t CAN_WakeUp(CAN_TypeDef* CANx); + +/* Error management functions *************************************************/ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); @@ -580,4 +694,4 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h index 10aaba7b1d69b8db8e5fc76067a1c39de8ec7986..a3f8fc78535333a8c9314e7bc61a097943ec3276 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_cec.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CEC firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CEC_H @@ -101,7 +102,7 @@ typedef struct */ -/** @defgroup CEC_Own_Addres +/** @defgroup CEC_Own_Address * @{ */ #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) @@ -206,4 +207,4 @@ void CEC_ClearITPendingBit(uint16_t CEC_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h index 12acce09dad041aca8b1a47b2955eb30cd2c5bc5..658a51cefdf144c7351795e67287a37a4919d5a9 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_crc.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_CRC_H @@ -90,4 +91,4 @@ uint8_t CRC_GetIDRegister(void); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h index 9abd63618afdc302552a480fb3e9fd0602d87fcd..710616412cdef7b5967dc64825b4aed69440cba8 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_dac.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DAC_H @@ -200,7 +201,7 @@ typedef struct * @} */ -/** @defgroup DAC_data_alignement +/** @defgroup DAC_data_alignment * @{ */ @@ -313,4 +314,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h index 918e25fa7af9628cc1ad8faa711815ead02bebb4..1e6a68acb43f28f5972450ec28a2d0c56f7a1c4e 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_dbgmcu.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DBGMCU * firmware library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DBGMCU_H @@ -115,4 +116,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h index 2c5302b20c0d64b8d4990e7c6f18ad8c12d6b4e9..b5dc6a80ab63ee64032ecdde2c67e06af48c0c43 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_dma.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_DMA_H @@ -413,10 +414,10 @@ void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); -void DMA_ClearFlag(uint32_t DMA_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMA_IT); -void DMA_ClearITPendingBit(uint32_t DMA_IT); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); #ifdef __cplusplus } @@ -435,4 +436,4 @@ void DMA_ClearITPendingBit(uint32_t DMA_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h index 29bed11cf1e215745e215ba9a7ab3ee67ea52268..a1ab7d03e047850fb775ed4a0fd127fb3fa2c8fd 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_exti.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_EXTI_H @@ -180,4 +181,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h index 5e2047d67e76659ab0c3d6cea811123e8fbc60d1..f46d4e873b3c0d3c42ce1f4cc8d405ff58ee0b12 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_flash.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_FLASH_H @@ -422,4 +423,4 @@ FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h index 9cf9847dadee2d71b20bb4fe7922f2476839984f..ee707e74394103d57ef5346539acf985d837b16b 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_fsmc.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_FSMC_H @@ -76,7 +77,7 @@ typedef struct to the memory before getting the first data. The value of this parameter depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - - It is don’t care in asynchronous NOR, SRAM or ROM accesses + - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable */ @@ -729,4 +730,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h index 1d99df02e084bd1e0ce9ad310981437b09b5bdb4..b8aa49a2a8b995c532948b53e3542c59d2054c7b 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_gpio.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the GPIO * firmware library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_GPIO_H @@ -195,7 +196,7 @@ typedef enum #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ #define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) */ @@ -381,4 +382,4 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h index 4726509505db98920176af0a45c55559414c538a..2d42e5ce366aa55d0f050202a921df49105b9bf6 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_i2c.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_I2C_H @@ -190,6 +191,18 @@ typedef struct * @} */ +/** @defgroup I2C_NCAK_position + * @{ + */ + +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ + ((POSITION) == I2C_NACKPosition_Current)) +/** + * @} + */ + /** @defgroup I2C_interrupts_definition * @{ */ @@ -433,7 +446,7 @@ typedef struct * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of tranfer. + * current byte end of transfer. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission * shall end (before sending the STOP condition). In this case slave has to stop sending * data bytes and expect a Stop condition on the bus. @@ -536,6 +549,7 @@ uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); @@ -577,10 +591,10 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); * @note * For error management, it is advised to use the following functions: * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. * Where x is the peripheral instance (I2C1, I2C2 ...) * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occured. + * in order to determine which error occurred. * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() * and/or I2C_GenerateStop() in order to clear the error flag and source, * and return to correct communication status. @@ -667,4 +681,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h index 4325ad4508eb4a10979d5b1b5796b8be115a7fa3..7f5ab7642c32138aaa157437901a5a889b703ca0 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_iwdg.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_IWDG_H @@ -136,4 +137,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h index ad93abdca4591517c05147635a2ed32853c817e0..76e6ce91f994af3c529ef4fdf94e59f7be063935 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_pwr.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_PWR_H @@ -152,4 +153,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h index 8f1473f921d559a2b7056a1902031008b21b59b1..b3b7d821d770f32d11ae6c8424eb3feb913a1986 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_rcc.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the RCC firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_RCC_H @@ -723,4 +724,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h index ac34ca971b8b092857ff11fb591bbaa8992fc4a8..214a5893a00815ebb1020d2b42a83b99a0b1a630 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_rtc.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the RTC firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_RTC_H @@ -131,4 +132,4 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h index d15556ce7d58c9dfbf5fb8c2a06e88bc4a40572f..40cfdedc30bde7e915558b996ad1d9fcc191bfa4 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_sdio.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the SDIO firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_SDIO_H @@ -189,7 +190,7 @@ typedef struct */ -/** @defgroup SDIO_Interrupt_soucres +/** @defgroup SDIO_Interrupt_sources * @{ */ @@ -527,4 +528,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h index 30b558bee64f411e75154c2225df3c7444234ca1..6056c4c6baaa87e94570b6a3c96b41c3bcb72cb0 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_spi.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the SPI firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_SPI_H @@ -339,7 +340,7 @@ typedef struct * @} */ -/** @defgroup SPI_NSS_internal_software_mangement +/** @defgroup SPI_NSS_internal_software_management * @{ */ @@ -483,4 +484,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h index 6529c0b0a76ba90dc2eb1e5f21741fc7e97166f4..cd7ac3e9c78db12cad9663598cacf65ab0516ac2 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_tim.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the TIM firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_TIM_H @@ -44,7 +45,7 @@ /** * @brief TIM Time Base Init structure definition - * @note This sturcture is used with all TIMx except for TIM6 and TIM7. + * @note This structure is used with all TIMx except for TIM6 and TIM7. */ typedef struct @@ -132,7 +133,7 @@ typedef struct /** * @brief BDTR structure definition - * @note This sturcture is used only with TIM1 and TIM8. + * @note This structure is used only with TIM1 and TIM8. */ typedef struct @@ -669,42 +670,42 @@ typedef struct * @{ */ -#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ - ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_18Bytes)) +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) /** * @} */ @@ -866,7 +867,7 @@ typedef struct * @} */ -/** @defgroup TIM_Ouput_Compare_Preload_State +/** @defgroup TIM_Output_Compare_Preload_State * @{ */ @@ -878,7 +879,7 @@ typedef struct * @} */ -/** @defgroup TIM_Ouput_Compare_Fast_State +/** @defgroup TIM_Output_Compare_Fast_State * @{ */ @@ -891,7 +892,7 @@ typedef struct * @} */ -/** @defgroup TIM_Ouput_Compare_Clear_State +/** @defgroup TIM_Output_Compare_Clear_State * @{ */ @@ -1008,6 +1009,32 @@ typedef struct * @} */ +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + /** * @} */ @@ -1134,4 +1161,4 @@ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h index 8d3c3818ab55a52f9c1da7627e940336ee4965b6..61ae249a4748317174da77e8a9fd8c039a653c1c 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_usart.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the USART * firmware library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_USART_H @@ -408,4 +409,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h index 859569841c66f7ca4f2c438bcbbcbb1d10575ac0..cd573da4454f7dd2ffbf37eec1b63abfc2183fbf 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f10x_wwdg.h * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file contains all the functions prototypes for the WWDG firmware * library. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F10x_WWDG_H @@ -111,4 +112,4 @@ void WWDG_ClearFlag(void); * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c index 6b72c99a232681834713233bce080830f8428c32..ec9165f71fdc71bbbead52b202c9df1d24650258 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c @@ -2,12 +2,12 @@ ****************************************************************************** * @file misc.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the miscellaneous firmware functions (add-on * to CMSIS functions). ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "misc.h" @@ -103,9 +104,9 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) /** * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. + * parameters in the NVIC_InitStruct. * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. + * the configuration information for the specified NVIC peripheral. * @retval None */ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) @@ -148,7 +149,8 @@ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) * This parameter can be one of the following values: * @arg NVIC_VectTab_RAM * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. + * @param Offset: Vector Table base offset field. This value must be a multiple + * of 0x200. * @retval None */ void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) @@ -220,4 +222,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c index 663b9bb3acb7623bcf63227fad1a0c844affac51..916a096d4b74fa2d6c60d1e6fa53e27bfc426053 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_adc.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the ADC firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_adc.h" @@ -208,10 +209,10 @@ void ADC_DeInit(ADC_TypeDef* ADCx) /** * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. + * in the ADC_InitStruct. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. + * the configuration information for the specified ADC peripheral. * @retval None */ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) @@ -379,7 +380,7 @@ void ADC_ResetCalibration(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Resets the selected ADC calibartion registers */ + /* Resets the selected ADC calibration registers */ ADCx->CR2 |= CR2_RSTCAL_Set; } @@ -499,10 +500,10 @@ FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) /** * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. + * group channel. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param Number: specifies the discontinuous mode regular channel - * count value. This number must be between 1 and 8. + * count value. This number must be between 1 and 8. * @retval None */ void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) @@ -525,11 +526,11 @@ void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) /** * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC + * channel for the specified ADC * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC discontinuous mode - * on regular group channel. - * This parameter can be: ENABLE or DISABLE. + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) @@ -551,7 +552,7 @@ void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) /** * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. + * rank in the sequencer and its sample time. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure. * This parameter can be one of the following values: @@ -724,7 +725,7 @@ uint32_t ADC_GetDualModeConversionValue(void) /** * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. + * conversion after regular one. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC auto injected conversion * This parameter can be: ENABLE or DISABLE. @@ -749,10 +750,10 @@ void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) /** * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC + * channel for the specified ADC * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. + * on injected group channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -813,10 +814,10 @@ void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_External /** * @brief Enables or disables the ADCx injected channels conversion through - * external trigger + * external trigger * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC external trigger start of - * injected conversion. + * injected conversion. * This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -839,7 +840,7 @@ void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState /** * @brief Enables or disables the selected ADC start of the injected - * channels conversion. + * channels conversion. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC software start injected conversion. * This parameter can be: ENABLE or DISABLE. @@ -891,7 +892,7 @@ FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) /** * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. + * rank in the sequencer and its sample time. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure. * This parameter can be one of the following values: @@ -1065,7 +1066,7 @@ uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedC /** * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels + * or injected channels * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. * This parameter can be one of the following values: @@ -1270,7 +1271,7 @@ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) } /** - * @brief Clears the ADCx’s interrupt pending bits. + * @brief Clears the ADCx's interrupt pending bits. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_IT: specifies the ADC interrupt pending bit to clear. * This parameter can be any combination of the following values: @@ -1303,4 +1304,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c index 3ad63af35ad3b97584f42bf0e566ab1820673482..3004b9ef806149d5146fb86c0b43cb9e026db10a 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_bkp.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the BKP firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_bkp.h" @@ -304,4 +305,4 @@ void BKP_ClearITPendingBit(void) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c index 043819a6f3a110e02c6e57ce884eaebe254f333a..607d6924f7c2715b5f7aa3a854e891d4afde5953 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_can.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the CAN firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_can.h" @@ -71,7 +72,14 @@ /* Flags in ESR register */ #define CAN_FLAGS_ESR ((uint32_t)0x00F00000) +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) /** * @} */ @@ -134,16 +142,18 @@ void CAN_DeInit(CAN_TypeDef* CANx) /** * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN + * peripheral. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the CAN peripheral. + * contains the configuration information for the + * CAN peripheral. * @retval Constant indicates initialization succeed which will be - * CANINITFAILED or CANINITOK. + * CAN_InitStatus_Failed or CAN_InitStatus_Success. */ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) { - uint8_t InitStatus = CANINITFAILED; + uint8_t InitStatus = CAN_InitStatus_Failed; uint32_t wait_ack = 0x00000000; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); @@ -159,7 +169,7 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - /* exit from sleep mode */ + /* Exit from sleep mode */ CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); /* Request initialisation */ @@ -171,10 +181,10 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) wait_ack++; } - /* ...and check acknowledged */ + /* Check acknowledge */ if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { - InitStatus = CANINITFAILED; + InitStatus = CAN_InitStatus_Failed; } else { @@ -239,15 +249,17 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) } /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); /* Request leave initialisation */ CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; /* Wait the acknowledge */ - wait_ack = 0x00; + wait_ack = 0; while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) { @@ -257,11 +269,11 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) /* ...and check acknowledged */ if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { - InitStatus = CANINITFAILED; + InitStatus = CAN_InitStatus_Failed; } else { - InitStatus = CANINITOK ; + InitStatus = CAN_InitStatus_Success ; } } @@ -271,9 +283,10 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) /** * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. + * parameters in the CAN_FilterInitStruct. * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration information. + * structure that contains the configuration + * information. * @retval None. */ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) @@ -286,7 +299,7 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; /* Initialisation mode for the filter */ CAN1->FMR |= FMR_FINIT; @@ -340,13 +353,13 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) } /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) { /* FIFO 0 assignation for the filter */ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; } - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) { /* FIFO 1 assignation for the filter */ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; @@ -365,32 +378,43 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) /** * @brief Fills each CAN_InitStruct member with its default value. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which - * will be initialized. + * will be initialized. * @retval None. */ void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) { /* Reset CAN init structure parameters values */ + /* Initialize the time triggered communication mode */ CAN_InitStruct->CAN_TTCM = DISABLE; + /* Initialize the automatic bus-off management */ CAN_InitStruct->CAN_ABOM = DISABLE; + /* Initialize the automatic wake-up mode */ CAN_InitStruct->CAN_AWUM = DISABLE; + /* Initialize the no automatic retransmission */ CAN_InitStruct->CAN_NART = DISABLE; + /* Initialize the receive FIFO locked mode */ CAN_InitStruct->CAN_RFLM = DISABLE; + /* Initialize the transmit FIFO priority */ CAN_InitStruct->CAN_TXFP = DISABLE; + /* Initialize the CAN_Mode member */ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + /* Initialize the CAN_SJW member */ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + /* Initialize the CAN_BS1 member */ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + /* Initialize the CAN_BS2 member */ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + /* Initialize the CAN_Prescaler member */ CAN_InitStruct->CAN_Prescaler = 1; } @@ -405,63 +429,88 @@ void CAN_SlaveStartBank(uint8_t CAN_BankNumber) { /* Check the parameters */ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - /* enter Initialisation mode for the filter */ + + /* Enter Initialisation mode for the filter */ CAN1->FMR |= FMR_FINIT; + /* Select the start slave bank */ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + /* Leave Initialisation mode for the filter */ CAN1->FMR &= ~FMR_FINIT; } /** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * -CAN_IT_TME, - * -CAN_IT_FMP0, - * -CAN_IT_FF0, - * -CAN_IT_FOV0, - * -CAN_IT_FMP1, - * -CAN_IT_FF1, - * -CAN_IT_FOV1, - * -CAN_IT_EWG, - * -CAN_IT_EPV, - * -CAN_IT_LEC, - * -CAN_IT_ERR, - * -CAN_IT_WKU or - * -CAN_IT_SLK. - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. This parameter can + * be: ENABLE or DISABLE. * @retval None. */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; } else { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; } } + +/** + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState : Mode new state , can be one of @ref FunctionalState. + * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last + * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 + * and TIME[15:8] in data byte 7 + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * @retval None + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCR |= CAN_MCR_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); + } +} /** * @brief Initiates the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param TxMessage: pointer to a structure which contains CAN Id, CAN - * DLC and CAN datas. + * DLC and CAN data. * @retval The number of the mailbox that is used for transmission - * or CAN_NO_MB if there is no empty mailbox. + * or CAN_TxStatus_NoMailBox if there is no empty mailbox. */ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) { @@ -487,26 +536,27 @@ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) } else { - transmit_mailbox = CAN_NO_MB; + transmit_mailbox = CAN_TxStatus_NoMailBox; } - if (transmit_mailbox != CAN_NO_MB) + if (transmit_mailbox != CAN_TxStatus_NoMailBox) { /* Set up the Id */ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_ID_STD) + if (TxMessage->IDE == CAN_Id_Standard) { assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); } else { assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | - TxMessage->RTR); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); } - /* Set up the DLC */ TxMessage->DLC &= (uint8_t)0x0000000F; CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; @@ -529,57 +579,65 @@ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) /** * @brief Checks the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case. + * @param CANx: where x can be 1 or 2 to to select the + * CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for + * transmission. + * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed + * in an other case. */ uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) { - /* RQCP, TXOK and TME bits */ - uint8_t state = 0; + uint32_t state = 0; + /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + switch (TransmitMailbox) { - case (0): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP0) << 2); - state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK0) >> 0); - state |= (uint8_t)((CANx->TSR & CAN_TSR_TME0) >> 26); + case (CAN_TXMAILBOX_0): + state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); break; - case (1): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP1) >> 6); - state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK1) >> 8); - state |= (uint8_t)((CANx->TSR & CAN_TSR_TME1) >> 27); + case (CAN_TXMAILBOX_1): + state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); break; - case (2): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP2) >> 14); - state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK2) >> 16); - state |= (uint8_t)((CANx->TSR & CAN_TSR_TME2) >> 28); + case (CAN_TXMAILBOX_2): + state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); break; default: - state = CANTXFAILED; + state = CAN_TxStatus_Failed; break; } switch (state) { /* transmit pending */ - case (0x0): state = CANTXPENDING; + case (0x0): state = CAN_TxStatus_Pending; break; /* transmit failed */ - case (0x5): state = CANTXFAILED; + case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; break; - /* transmit succedeed */ - case (0x7): state = CANTXOK; + case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; break; - default: - state = CANTXFAILED; + case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; + break; + /* transmit succeeded */ + case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; + break; + default: state = CAN_TxStatus_Failed; break; } - return state; + return (uint8_t) state; } /** * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param Mailbox: Mailbox number. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox: Mailbox number. * @retval None. */ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) @@ -590,20 +648,72 @@ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) /* abort transmission */ switch (Mailbox) { - case (0): CANx->TSR |= CAN_TSR_ABRQ0; + case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; break; - case (1): CANx->TSR |= CAN_TSR_ABRQ1; + case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; break; - case (2): CANx->TSR |= CAN_TSR_ABRQ2; + case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; break; default: break; } } + +/** + * @brief Receives a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * @retval None. + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + /** - * @brief Releases a FIFO. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @brief Releases the specified FIFO. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. * @retval None. */ @@ -626,9 +736,9 @@ void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) /** * @brief Returns the number of pending messages. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage which is the number of pending message. + * @retval NbMessage : which is the number of pending message. */ uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) { @@ -651,81 +761,101 @@ uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) return message_pending; } + /** - * @brief Receives a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive message which - * contains CAN Id, CAN DLC, CAN datas and FMI number. - * @retval None. + * @brief Select the CAN Operation mode. + * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one + * of @ref CAN_OperatingMode_TypeDef enumeration. + * @retval status of the requested mode which can be + * - CAN_ModeStatus_Failed CAN failed entering the specific mode + * - CAN_ModeStatus_Success CAN Succeed entering the specific mode + */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) { + uint8_t status = CAN_ModeStatus_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INAK_TIMEOUT; + /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_ID_STD) + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + /* Request initialisation */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } } - else + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - CAN_FIFORelease(CANx, FIFONumber); -} + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; + /* Request Sleep mode */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } } else { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; + status = CAN_ModeStatus_Failed; } + + return (uint8_t) status; } /** * @brief Enters the low power mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an + * other case. */ uint8_t CAN_Sleep(CAN_TypeDef* CANx) { - uint8_t sleepstatus = CANSLEEPFAILED; + uint8_t sleepstatus = CAN_Sleep_Failed; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); @@ -737,21 +867,22 @@ uint8_t CAN_Sleep(CAN_TypeDef* CANx) if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) { /* Sleep mode not entered */ - sleepstatus = CANSLEEPOK; + sleepstatus = CAN_Sleep_Ok; } - /* At this step, sleep mode status */ + /* return sleep mode status */ return (uint8_t)sleepstatus; } /** * @brief Wakes the CAN up. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an + * other case. */ uint8_t CAN_WakeUp(CAN_TypeDef* CANx) { uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CANWAKEUPFAILED; + uint8_t wakeupstatus = CAN_WakeUp_Failed; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); @@ -766,33 +897,147 @@ uint8_t CAN_WakeUp(CAN_TypeDef* CANx) } if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) { - /* Sleep mode exited */ - wakeupstatus = CANWAKEUPOK; + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WakeUp_Ok; } - /* At this step, sleep mode status */ + /* return wakeup status */ return (uint8_t)wakeupstatus; } + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN_ErrorCode: specifies the Error code : + * - CAN_ERRORCODE_NoErr No Error + * - CAN_ERRORCODE_StuffErr Stuff Error + * - CAN_ERRORCODE_FormErr Form Error + * - CAN_ERRORCODE_ACKErr Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error + * - CAN_ERRORCODE_CRCErr CRC Error + * - CAN_ERRORCODE_SoftwareSetErr Software Set Error + */ + +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); + + /* Return the error code*/ + return errorcode; +} +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} + + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * - CAN_IT_TME, + * - CAN_IT_FMP0, + * - CAN_IT_FF0, + * - CAN_IT_FOV0, + * - CAN_IT_FMP1, + * - CAN_IT_FF1, + * - CAN_IT_FOV1, + * - CAN_IT_EWG, + * - CAN_IT_EPV, + * - CAN_IT_LEC, + * - CAN_IT_ERR, + * - CAN_IT_WKU or + * - CAN_IT_SLK. + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} /** * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following flags: - * - CAN_FLAG_EWG - * - CAN_FLAG_EPV - * - CAN_FLAG_BOF - * - CAN_FLAG_RQCP0 - * - CAN_FLAG_RQCP1 - * - CAN_FLAG_RQCP2 - * - CAN_FLAG_FMP1 - * - CAN_FLAG_FF1 - * - CAN_FLAG_FOV1 - * - CAN_FLAG_FMP0 - * - CAN_FLAG_FF0 - * - CAN_FLAG_FOV0 - * - CAN_FLAG_WKU - * - CAN_FLAG_SLAK - * - CAN_FLAG_LEC + * This parameter can be one of the following flags: + * - CAN_FLAG_EWG + * - CAN_FLAG_EPV + * - CAN_FLAG_BOF + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FMP1 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FMP0 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC * @retval The new state of CAN_FLAG (SET or RESET). */ FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) @@ -880,19 +1125,19 @@ FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) /** * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following flags: - * - CAN_FLAG_RQCP0 - * - CAN_FLAG_RQCP1 - * - CAN_FLAG_RQCP2 - * - CAN_FLAG_FF1 - * - CAN_FLAG_FOV1 - * - CAN_FLAG_FF0 - * - CAN_FLAG_FOV0 - * - CAN_FLAG_WKU - * - CAN_FLAG_SLAK - * - CAN_FLAG_LEC + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC * @retval None. */ void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) @@ -936,24 +1181,24 @@ void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) /** * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following flags: - * - CAN_IT_TME - * - CAN_IT_FMP0 - * - CAN_IT_FF0 - * - CAN_IT_FOV0 - * - CAN_IT_FMP1 - * - CAN_IT_FF1 - * - CAN_IT_FOV1 - * - CAN_IT_WKU - * - CAN_IT_SLK - * - CAN_IT_EWG - * - CAN_IT_EPV - * - CAN_IT_BOF - * - CAN_IT_LEC - * - CAN_IT_ERR - * @retval The current state of CAN_IT (SET or RESET). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_IT_TME + * - CAN_IT_FMP0 + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FMP1 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval The current state of CAN_IT (SET or RESET). */ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) { @@ -970,60 +1215,59 @@ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) { case CAN_IT_TME: /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); break; case CAN_IT_FMP0: /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); break; case CAN_IT_FF0: /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); break; case CAN_IT_FOV0: /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); break; case CAN_IT_FMP1: /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); break; case CAN_IT_FF1: /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); break; case CAN_IT_FOV1: /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); break; case CAN_IT_WKU: /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); break; case CAN_IT_SLK: /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); break; case CAN_IT_EWG: /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); break; case CAN_IT_EPV: /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); break; case CAN_IT_BOF: /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); break; case CAN_IT_LEC: /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); break; case CAN_IT_ERR: - /* Check CAN_MSR_ERRI, CAN_ESR_EWGF, CAN_ESR_EPVF, CAN_ESR_BOFF and CAN_ESR_LEC bits */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC); - itstatus |= CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + /* Check CAN_MSR_ERRI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); break; default : /* in case of error, return RESET */ @@ -1042,21 +1286,21 @@ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) } /** - * @brief Clears the CANx’s interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @brief Clears the CANx's interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_IT: specifies the interrupt pending bit to clear. - * - CAN_IT_TME - * - CAN_IT_FF0 - * - CAN_IT_FOV0 - * - CAN_IT_FF1 - * - CAN_IT_FOV1 - * - CAN_IT_WKU - * - CAN_IT_SLK - * - CAN_IT_EWG - * - CAN_IT_EPV - * - CAN_IT_BOF - * - CAN_IT_LEC - * - CAN_IT_ERR + * - CAN_IT_TME + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR * @retval None. */ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) @@ -1098,17 +1342,20 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) case CAN_IT_EWG: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ break; case CAN_IT_EPV: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ break; case CAN_IT_BOF: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ break; case CAN_IT_LEC: /* Clear LEC bits */ @@ -1121,7 +1368,8 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) CANx->ESR = RESET; /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; - /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending of the CAN Bus status*/ + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending + of the CAN Bus status*/ break; default : break; @@ -1131,7 +1379,7 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) /** * @brief Checks whether the CAN interrupt has occurred or not. * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. + * @param It_Bit: specifies the interrupt source bit to check. * @retval The new state of the CAN Interrupt (SET or RESET). */ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) @@ -1151,6 +1399,7 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) return pendingbitstatus; } + /** * @} */ @@ -1163,4 +1412,4 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c index 5b3f9b51383cda36a6e6f0e9b80495e3138e50cd..08b501a0c4e2aec349d5b4c18c1f13f9b60f1612 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_cec.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the CEC firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_cec.h" @@ -277,7 +278,7 @@ void CEC_EndOfMessageCmd(FunctionalState NewState) * @arg CEC_FLAG_SBE: Start Bit Error * @arg CEC_FLAG_ACKE: Block Acknowledge Error * @arg CEC_FLAG_LINE: Line Error - * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error + * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error * @arg CEC_FLAG_TEOM: Tx End Of Message * @arg CEC_FLAG_TERR: Tx Error * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished @@ -429,4 +430,4 @@ void CEC_ClearITPendingBit(uint16_t CEC_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c index 511a7b90e844b32b6340cbefcde6fb4ef04783d5..ef0c047d8ff434c1898759315da4220fdd960789 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_crc.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the CRC firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_crc.h" @@ -156,4 +157,4 @@ uint8_t CRC_GetIDRegister(void) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c index 55e91c0a79bb34f3aff6fd68e575aa6d1caf494a..025b8e28375959bd36e037b2a9b6159fff5544d8 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_dac.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the DAC firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_dac.h" @@ -104,13 +105,13 @@ void DAC_DeInit(void) /** * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. + * parameters in the DAC_InitStruct. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. + * contains the configuration information for the specified DAC channel. * @retval None */ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) @@ -126,8 +127,8 @@ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) tmpreg1 = DAC->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave genration, - mask/amplitude for wave genration */ + /* Configure for the selected DAC channel: buffer output, trigger, wave generation, + mask/amplitude for wave generation */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set WAVEx bits according to DAC_WaveGeneration value */ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ @@ -143,7 +144,7 @@ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) /** * @brief Fills each DAC_InitStruct member with its default value. * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will - * be initialized. + * be initialized. * @retval None */ void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) @@ -330,11 +331,11 @@ void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalSt /** * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignement for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data : Data to be loaded in the selected data holding register. * @retval None */ @@ -355,11 +356,11 @@ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) /** * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignement for DAC channel2. + * @param DAC_Align: Specifies the data alignment for DAC channel2. * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data : Data to be loaded in the selected data holding register. * @retval None */ @@ -381,11 +382,11 @@ void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) /** * @brief Set the specified data holding register value for dual channel * DAC. - * @param DAC_Align: Specifies the data alignement for dual channel DAC. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data2: Data for DAC Channel2 to be loaded in the selected data * holding register. * @param Data1: Data for DAC Channel1 to be loaded in the selected data @@ -419,7 +420,7 @@ void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) } /** - * @brief Returns the last data output value of the selected DAC cahnnel. + * @brief Returns the last data output value of the selected DAC channel. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected @@ -534,7 +535,7 @@ ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) } /** - * @brief Clears the DAC channelx’s interrupt pending bits. + * @brief Clears the DAC channelx's interrupt pending bits. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected @@ -567,4 +568,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c index 3f4e6272703ce63e52c31c8461d56e9f969f36b4..d34307b05821b7484a8ef1dc2f87f8c4e035e436 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_dbgmcu.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the DBGMCU firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_dbgmcu.h" @@ -158,4 +159,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c index 7f72b54cfcaff895b0128ba0de83e1ff919628be..0c86f9018b0966bd20fd92907211b9f74c325320 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_dma.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the DMA firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_dma.h" @@ -99,7 +100,7 @@ /** * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. + * values. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @retval None @@ -191,11 +192,11 @@ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) /** * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. + * parameters in the DMA_InitStruct. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that - * contains the configuration information for the specified DMA Channel. + * contains the configuration information for the specified DMA Channel. * @retval None */ void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) @@ -252,7 +253,7 @@ void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruc /** * @brief Fills each DMA_InitStruct member with its default value. * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. + * be initialized. * @retval None */ void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) @@ -361,11 +362,11 @@ void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNum /** * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. + * DMAy Channelx transfer. * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. * @retval The number of remaining data units in the current DMAy Channelx - * transfer. + * transfer. */ uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) { @@ -377,7 +378,7 @@ uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) /** * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMA_FLAG: specifies the flag to check. + * @param DMAy_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. @@ -427,17 +428,18 @@ uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval The new state of DMA_FLAG (SET or RESET). + * @retval The new state of DMAy_FLAG (SET or RESET). */ -FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) { FlagStatus bitstatus = RESET; uint32_t tmpreg = 0; + /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); - /* Calculate the used DMA */ - if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) { /* Get DMA2 ISR register value */ tmpreg = DMA2->ISR ; @@ -448,25 +450,25 @@ FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) tmpreg = DMA1->ISR ; } - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + /* Check the status of the specified DMAy flag */ + if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) { - /* DMA_FLAG is set */ + /* DMAy_FLAG is set */ bitstatus = SET; } else { - /* DMA_FLAG is reset */ + /* DMAy_FLAG is reset */ bitstatus = RESET; } - /* Return the DMA_FLAG status */ + /* Return the DMAy_FLAG status */ return bitstatus; } /** * @brief Clears the DMAy Channelx's pending flags. - * @param DMA_FLAG: specifies the flag to clear. + * @param DMAy_FLAG: specifies the flag to clear. * This parameter can be any combination (for the same DMA) of the following values: * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. @@ -518,27 +520,27 @@ FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. * @retval None */ -void DMA_ClearFlag(uint32_t DMA_FLAG) +void DMA_ClearFlag(uint32_t DMAy_FLAG) { /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - /* Calculate the used DMA */ + assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); - if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) { - /* Clear the selected DMA flags */ - DMA2->IFCR = DMA_FLAG; + /* Clear the selected DMAy flags */ + DMA2->IFCR = DMAy_FLAG; } else { - /* Clear the selected DMA flags */ - DMA1->IFCR = DMA_FLAG; + /* Clear the selected DMAy flags */ + DMA1->IFCR = DMAy_FLAG; } } /** * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMA_IT: specifies the DMA interrupt source to check. + * @param DMAy_IT: specifies the DMAy interrupt source to check. * This parameter can be one of the following values: * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. @@ -588,36 +590,37 @@ void DMA_ClearFlag(uint32_t DMA_FLAG) * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval The new state of DMA_IT (SET or RESET). + * @retval The new state of DMAy_IT (SET or RESET). */ -ITStatus DMA_GetITStatus(uint32_t DMA_IT) +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) { ITStatus bitstatus = RESET; uint32_t tmpreg = 0; + /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMA_IT)); + assert_param(IS_DMA_GET_IT(DMAy_IT)); /* Calculate the used DMA */ - if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) { /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; + tmpreg = DMA2->ISR; } else { /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; + tmpreg = DMA1->ISR; } - /* Check the status of the specified DMA interrupt */ - if ((tmpreg & DMA_IT) != (uint32_t)RESET) + /* Check the status of the specified DMAy interrupt */ + if ((tmpreg & DMAy_IT) != (uint32_t)RESET) { - /* DMA_IT is set */ + /* DMAy_IT is set */ bitstatus = SET; } else { - /* DMA_IT is reset */ + /* DMAy_IT is reset */ bitstatus = RESET; } /* Return the DMA_IT status */ @@ -625,8 +628,8 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT) } /** - * @brief Clears the DMAy Channelx’s interrupt pending bits. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * @brief Clears the DMAy Channelx's interrupt pending bits. + * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. * This parameter can be any combination (for the same DMA) of the following values: * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. @@ -678,21 +681,21 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT) * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. * @retval None */ -void DMA_ClearITPendingBit(uint32_t DMA_IT) +void DMA_ClearITPendingBit(uint32_t DMAy_IT) { /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); - /* Calculate the used DMA */ - if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + /* Calculate the used DMAy */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) { - /* Clear the selected DMA interrupt pending bits */ - DMA2->IFCR = DMA_IT; + /* Clear the selected DMAy interrupt pending bits */ + DMA2->IFCR = DMAy_IT; } else { - /* Clear the selected DMA interrupt pending bits */ - DMA1->IFCR = DMA_IT; + /* Clear the selected DMAy interrupt pending bits */ + DMA1->IFCR = DMAy_IT; } } @@ -708,4 +711,4 @@ void DMA_ClearITPendingBit(uint32_t DMA_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c index f9467d0dc48ac11c826b408df4f8256d0d94fca9..ab7346276cdeaebc3a0aeb3792334ed1ffb8257c 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_exti.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the EXTI firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_exti.h" @@ -92,9 +93,9 @@ void EXTI_DeInit(void) /** * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. + * parameters in the EXTI_InitStruct. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. + * that contains the configuration information for the EXTI peripheral. * @retval None */ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) @@ -150,7 +151,7 @@ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) /** * @brief Fills each EXTI_InitStruct member with its reset value. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. + * be initialized. * @retval None */ void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) @@ -200,7 +201,7 @@ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) } /** - * @brief Clears the EXTI’s line pending flags. + * @brief Clears the EXTI's line pending flags. * @param EXTI_Line: specifies the EXTI lines flags to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..19). * @retval None @@ -240,7 +241,7 @@ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) } /** - * @brief Clears the EXTI’s line pending bits. + * @brief Clears the EXTI's line pending bits. * @param EXTI_Line: specifies the EXTI lines to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..19). * @retval None @@ -265,4 +266,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c index 57bb715c85d720aca1f59157fa6797af5dd4fe69..f6c7bf172dba62f761303558fb921849f7642d33 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_flash.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the FLASH firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_flash.h" @@ -413,7 +414,7 @@ void FLASH_LockBank2(void) * @note This function can be used for all STM32F10x devices. * @param Page_Address: The page address to be erased. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_ErasePage(uint32_t Page_Address) { @@ -486,7 +487,7 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address) * @note This function can be used for all STM32F10x devices. * @param None * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_EraseAllPages(void) { @@ -549,7 +550,7 @@ FLASH_Status FLASH_EraseAllPages(void) * to FLASH_EraseAllPages function. * @param None * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_EraseAllBank1Pages(void) { @@ -579,7 +580,7 @@ FLASH_Status FLASH_EraseAllBank1Pages(void) * @note This function can be used only for STM32F10x_XL density devices. * @param None * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_EraseAllBank2Pages(void) { @@ -610,7 +611,7 @@ FLASH_Status FLASH_EraseAllBank2Pages(void) * @note This function can be used for all STM32F10x devices. * @param None * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_EraseOptionBytes(void) { @@ -675,7 +676,7 @@ FLASH_Status FLASH_EraseOptionBytes(void) * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) { @@ -852,7 +853,7 @@ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) { @@ -923,7 +924,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) * This parameter can be 0x1FFFF804 or 0x1FFFF806. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) { @@ -969,7 +970,7 @@ FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 * @arg FLASH_WRProt_AllPages * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) { @@ -1043,7 +1044,7 @@ FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) * @param Newstate: new state of the ReadOut Protection. * This parameter can be: ENABLE or DISABLE. * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) { @@ -1112,7 +1113,7 @@ FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) { @@ -1166,7 +1167,7 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint * in the interrupt vector table). * For more information, please refer to AN2606 from www.st.com. * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) { @@ -1210,7 +1211,7 @@ FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) * @note This function can be used for all STM32F10x devices. * @param None * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). + * and RST_STDBY(Bit2). */ uint32_t FLASH_GetUserOptionByte(void) { @@ -1226,7 +1227,7 @@ uint32_t FLASH_GetUserOptionByte(void) */ uint32_t FLASH_GetWriteProtectionOptionByte(void) { - /* Return the Falsh write protection Register value */ + /* Return the Flash write protection Register value */ return (uint32_t)(FLASH->WRPR); } @@ -1428,7 +1429,7 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) } /** - * @brief Clears the FLASH’s pending flags. + * @brief Clears the FLASH's pending flags. * @note This function can be used for all STM32F10x devices. * - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags * - For other devices, it clears Bank1’s pending flags. @@ -1468,10 +1469,10 @@ void FLASH_ClearFlag(uint32_t FLASH_FLAG) /** * @brief Returns the FLASH Status. * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetBank1Status function. + * to FLASH_GetBank1Status function. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE + * FLASH_ERROR_WRP or FLASH_COMPLETE */ FLASH_Status FLASH_GetStatus(void) { @@ -1506,10 +1507,10 @@ FLASH_Status FLASH_GetStatus(void) /** * @brief Returns the FLASH Bank1 Status. * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetStatus function. + * to FLASH_GetStatus function. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE + * FLASH_ERROR_WRP or FLASH_COMPLETE */ FLASH_Status FLASH_GetBank1Status(void) { @@ -1547,7 +1548,7 @@ FLASH_Status FLASH_GetBank1Status(void) * @note This function can be used for STM32F10x_XL density devices. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE + * FLASH_ERROR_WRP or FLASH_COMPLETE */ FLASH_Status FLASH_GetBank2Status(void) { @@ -1587,9 +1588,9 @@ FLASH_Status FLASH_GetBank2Status(void) * to complete or a TIMEOUT to occur. * - For all other devices it waits for a Flash operation to complete * or a TIMEOUT to occur. - * @param Timeout: FLASH progamming Timeout + * @param Timeout: FLASH programming Timeout * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) { @@ -1615,9 +1616,9 @@ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. * @note This function can be used for all STM32F10x devices, * it is equivalent to FLASH_WaitForLastOperation. - * @param Timeout: FLASH progamming Timeout + * @param Timeout: FLASH programming Timeout * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) { @@ -1643,9 +1644,9 @@ FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) /** * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. * @note This function can be used only for STM32F10x_XL density devices. - * @param Timeout: FLASH progamming Timeout + * @param Timeout: FLASH programming Timeout * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. */ FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) { @@ -1680,4 +1681,4 @@ FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c index db9a5aad119fc5d7ddd584296218d189e4e4c912..c75137cacbaa04d0586f2167fc681916cc53606b 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_fsmc.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the FSMC firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_fsmc.h" @@ -89,7 +90,7 @@ /** * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. + * reset values. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 @@ -166,10 +167,10 @@ void FSMC_PCCARDDeInit(void) /** * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. + * parameters in the FSMC_NORSRAMInitStruct. * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef - * structure that contains the configuration information for - * the FSMC NOR/SRAM specified Banks. + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. * @retval None */ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) @@ -252,9 +253,10 @@ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) /** * @brief Initializes the FSMC NAND Banks according to the specified - * parameters in the FSMC_NANDInitStruct. + * parameters in the FSMC_NANDInitStruct. * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef - * structure that contains the configuration information for the FSMC NAND specified Banks. + * structure that contains the configuration information for the FSMC + * NAND specified Banks. * @retval None */ void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) @@ -317,9 +319,10 @@ void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) /** * @brief Initializes the FSMC PCCARD Bank according to the specified - * parameters in the FSMC_PCCARDInitStruct. + * parameters in the FSMC_PCCARDInitStruct. * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef - * structure that contains the configuration information for the FSMC PCCARD Bank. + * structure that contains the configuration information for the FSMC + * PCCARD Bank. * @retval None */ void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) @@ -371,7 +374,7 @@ void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) /** * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef - * structure which will be initialized. + * structure which will be initialized. * @retval None */ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) @@ -409,7 +412,7 @@ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) /** * @brief Fills each FSMC_NANDInitStruct member with its default value. * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef - * structure which will be initialized. + * structure which will be initialized. * @retval None */ void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) @@ -435,7 +438,7 @@ void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) /** * @brief Fills each FSMC_PCCARDInitStruct member with its default value. * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef - * structure which will be initialized. + * structure which will be initialized. * @retval None */ void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) @@ -728,7 +731,7 @@ FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) } /** - * @brief Clears the FSMC’s pending flags. + * @brief Clears the FSMC's pending flags. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND @@ -814,7 +817,7 @@ ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) } /** - * @brief Clears the FSMC’s interrupt pending bits. + * @brief Clears the FSMC's interrupt pending bits. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND @@ -860,4 +863,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c index 4ec05094ed3784495f5ce3fd5c28c7f8670b4499..93dbcd7cafb9d9ed858e678b7e25092e4a2d30f1 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_gpio.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the GPIO firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_gpio.h" @@ -163,10 +164,10 @@ void GPIO_AFIODeInit(void) /** * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. + * parameters in the GPIO_InitStruct. * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. + * contains the configuration information for the specified GPIO peripheral. * @retval None */ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) @@ -259,7 +260,7 @@ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) /** * @brief Fills each GPIO_InitStruct member with its default value. * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - * be initialized. + * be initialized. * @retval None */ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) @@ -519,6 +520,8 @@ void GPIO_EventOutputCmd(FunctionalState NewState) * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) + * When the SPI3/I2S3 is remapped using this function, the SWJ is configured + * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST. * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to @@ -644,4 +647,4 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c index 5a2521c2ca64c18efd2a83c24a0e078344b0ca88..889672683fa9646c11ce36fbc51dbdc9f97f6b0a 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_i2c.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the I2C firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_i2c.h" @@ -671,6 +672,46 @@ void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) } } +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACKPosition_Next) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_NACKPosition: specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last + * received byte. + * @arg I2C_NACKPosition_Current: indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @retval None + */ +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACKPosition_Next) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CR1 |= I2C_NACKPosition_Next; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CR1 &= I2C_NACKPosition_Current; + } +} + /** * @brief Drives the SMBusAlert pin high or low for the specified I2C. * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. @@ -728,6 +769,11 @@ void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) * This parameter can be one of the following values: * @arg I2C_PECPosition_Next: indicates that the next byte is PEC * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() + * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() + * is intended to used in I2C mode. + * * @retval None */ void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) @@ -748,7 +794,7 @@ void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) } /** - * @brief Enables or disables the PEC value calculation of the transfered bytes. + * @brief Enables or disables the PEC value calculation of the transferred bytes. * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. * @param NewState: new state of the I2Cx PEC value calculation. * This parameter can be: ENABLE or DISABLE. @@ -878,7 +924,7 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) * It returns SUCCESS if the current status includes the given flags * and returns ERROR if one or more flags are missing in the current status. * - When to use: - * - This function is suitable for most applciations as well as for startup + * - This function is suitable for most applications as well as for startup * activity since the events are fully described in the product reference manual * (RM0008). * - It is also suitable for users who need to define their own events. @@ -892,7 +938,7 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) * @note * For error management, it is advised to use the following functions: * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. * Where x is the peripheral instance (I2C1, I2C2 ...) * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() * in order to determine which error occured. @@ -907,9 +953,9 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) * by 16 bits and concatenated to Status Register 1). * - When to use: * - This function is suitable for the same applications above but it allows to - * overcome the mentionned limitation of I2C_GetFlagStatus() function. + * overcome the mentioned limitation of I2C_GetFlagStatus() function. * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defiend by user. + * library (stm32f10x_i2c.h) or to custom values defined by user. * - This function is suitable when multiple flags are monitored at the same time. * - At the opposite of I2C_CheckEvent() function, this function allows user to * choose when an event is accepted (when all events flags are set and no @@ -977,7 +1023,7 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) * @note: For detailed description of Events, please refer to section * I2C_Events in stm32f10x_i2c.h file. * - * @retval An ErrorStatus enumuration value: + * @retval An ErrorStatus enumeration value: * - SUCCESS: Last event is equal to the I2C_EVENT * - ERROR: Last event is different from the I2C_EVENT */ @@ -1079,8 +1125,8 @@ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL” - * Address matched flag (Slave mode)”ENDAD” + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA" * @arg I2C_FLAG_SB: Start bit flag (Master mode) * @retval The new state of I2C_FLAG (SET or RESET). */ @@ -1192,8 +1238,8 @@ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) “ADSL” - * Address matched flag (Slave mode)”ENDAD” + * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" * @arg I2C_IT_SB: Start bit flag (Master mode) * @retval The new state of I2C_IT (SET or RESET). */ @@ -1282,4 +1328,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c index 7738cf3c48186e96a7c26c6bc689c8d1fd6aa49a..9d3b0e855a13e9e6ce1b400604bc321a3dd10a96 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_iwdg.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the IWDG firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_iwdg.h" @@ -186,4 +187,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c index 8eeeec200eb3fff1fd8742547b9ac02f068553b7..147bf0f8d6affd110dd1d564fa18152ac1dc4629 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_pwr.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the PWR firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_pwr.h" @@ -303,4 +304,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c index 9a0b7ca1e0b6d99b130516d7deeede9029d7cdb4..4b2ec1f10440ec2b59eef483cbe6d4dac74adcaf 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_rcc.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the RCC firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_rcc.h" @@ -867,7 +868,7 @@ void RCC_LSICmd(FunctionalState NewState) /** * @brief Configures the RTC clock (RTCCLK). - * @note Once the RTC clock is selected it can’t be changed unless the Backup domain is reset. + * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. * @param RCC_RTCCLKSource: specifies the RTC clock source. * This parameter can be one of the following values: * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock @@ -1419,7 +1420,7 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT) } /** - * @brief Clears the RCC’s interrupt pending bits. + * @brief Clears the RCC's interrupt pending bits. * @param RCC_IT: specifies the interrupt pending bit to clear. * * For @b STM32_Connectivity_line_devices, this parameter can be any combination @@ -1466,4 +1467,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c index dc69f64bf155f1d1fb133642e7bbe1a864325b3a..f798d2bd6f2bd8cc282142dc0b66a466c4669a0f 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_rtc.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the RTC firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_rtc.h" @@ -259,7 +260,7 @@ FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) } /** - * @brief Clears the RTC’s pending flags. + * @brief Clears the RTC's pending flags. * @param RTC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after @@ -274,12 +275,12 @@ void RTC_ClearFlag(uint16_t RTC_FLAG) /* Check the parameters */ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - /* Clear the coressponding RTC flag */ + /* Clear the corresponding RTC flag */ RTC->CRL &= (uint16_t)~RTC_FLAG; } /** - * @brief Checks whether the specified RTC interrupt has occured or not. + * @brief Checks whether the specified RTC interrupt has occurred or not. * @param RTC_IT: specifies the RTC interrupts sources to check. * This parameter can be one of the following values: * @arg RTC_IT_OW: Overflow interrupt @@ -306,7 +307,7 @@ ITStatus RTC_GetITStatus(uint16_t RTC_IT) } /** - * @brief Clears the RTC’s interrupt pending bits. + * @brief Clears the RTC's interrupt pending bits. * @param RTC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RTC_IT_OW: Overflow interrupt @@ -319,7 +320,7 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT) /* Check the parameters */ assert_param(IS_RTC_IT(RTC_IT)); - /* Clear the coressponding RTC pending bit */ + /* Clear the corresponding RTC pending bit */ RTC->CRL &= (uint16_t)~RTC_IT; } @@ -335,4 +336,4 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c index 732cad53b34d08815ab32ccc4f02f862e97cf541..d1870cef153ff7cfcdb3ad7d9d5dd19481153c8b 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_sdio.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the SDIO firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_sdio.h" @@ -172,9 +173,9 @@ void SDIO_DeInit(void) /** * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. + * parameters in the SDIO_InitStruct. * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. + * that contains the configuration information for the SDIO peripheral. * @retval None */ void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) @@ -337,9 +338,9 @@ void SDIO_DMACmd(FunctionalState NewState) /** * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. + * parameters in the SDIO_CmdInitStruct and send the command. * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO command. + * structure that contains the configuration information for the SDIO command. * @retval None */ void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) @@ -375,7 +376,7 @@ void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) /** * @brief Fills each SDIO_CmdInitStruct member with its default value. * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. + * structure which will be initialized. * @retval None */ void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) @@ -465,7 +466,7 @@ void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) /** * @brief Fills each SDIO_DataInitStruct member with its default value. * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which - * will be initialized. + * will be initialized. * @retval None */ void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) @@ -550,7 +551,7 @@ void SDIO_StopSDIOReadWait(FunctionalState NewState) /** * @brief Sets one of the two options of inserting read wait interval. * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parametre can be: + * This parameter can be: * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 * @retval None @@ -757,7 +758,7 @@ ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) } /** - * @brief Clears the SDIO’s interrupt pending bits. + * @brief Clears the SDIO's interrupt pending bits. * @param SDIO_IT: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt @@ -795,4 +796,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c index badd23d66239814e0d156aff8de34a8dbe43833f..51a9cce7736fa1243cc433ac8364f74493f489cd 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_spi.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the SPI firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_spi.h" @@ -111,7 +112,7 @@ /** * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). + * reset values (Affects also the I2Ss). * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @retval None */ @@ -148,10 +149,10 @@ void SPI_I2S_DeInit(SPI_TypeDef* SPIx) /** * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. + * parameters in the SPI_InitStruct. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. + * contains the configuration information for the specified SPI peripheral. * @retval None */ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) @@ -202,12 +203,12 @@ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) /** * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. + * parameters in the I2S_InitStruct. * @param SPIx: where x can be 2 or 3 to select the SPI peripheral - * (configured in I2S mode). + * (configured in I2S mode). * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. * @note * The function calculates the optimal prescaler needed to obtain the most * accurate audio frequency (depending on the I2S clock source, the PLL values @@ -283,7 +284,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) /* Get the value of the PLL3 multiplier */ if((tmp > 5) && (tmp < 15)) { - /* Multplier is between 8 and 14 (value 15 is forbidden) */ + /* Multiplier is between 8 and 14 (value 15 is forbidden) */ tmp += 2; } else @@ -316,7 +317,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) sourceclock = RCC_Clocks.SYSCLK_Frequency; #endif /* STM32F10X_CL */ - /* Compute the Real divider depending on the MCLK output state with a flaoting point */ + /* Compute the Real divider depending on the MCLK output state with a floating point */ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) { /* MCLK output is enabled */ @@ -328,7 +329,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); } - /* Remove the flaoting point */ + /* Remove the floating point */ tmp = tmp / 10; /* Check the parity of the divider */ @@ -653,7 +654,7 @@ void SPI_TransmitCRC(SPI_TypeDef* SPIx) } /** - * @brief Enables or disables the CRC value calculation of the transfered bytes. + * @brief Enables or disables the CRC value calculation of the transferred bytes. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param NewState: new state of the SPIx CRC value calculation. * This parameter can be: ENABLE or DISABLE. @@ -866,7 +867,7 @@ ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) * @param SPIx: where x can be * - 1, 2 or 3 in SPI mode * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR intetrrupt pending bit. + * This function clears only CRCERR interrupt pending bit. * @note * - OVR (OverRun Error) interrupt pending bit is cleared by software * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) @@ -904,4 +905,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c index 780105589a99ec4e56d0a93e0469672089703ec6..81c8484e398966de93a41eba3b57b0329b780e81 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_tim.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the TIM firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_tim.h" @@ -215,10 +216,11 @@ void TIM_DeInit(TIM_TypeDef* TIMx) /** * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. + * the specified parameters in the TIM_TimeBaseInitStruct. * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for the specified TIM peripheral. + * structure that contains the configuration information for the + * specified TIM peripheral. * @retval None */ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) @@ -268,10 +270,10 @@ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseIn /** * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. + * parameters in the TIM_OCInitStruct. * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. + * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) @@ -326,7 +328,7 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Set the Output N State */ tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Ouput Compare and Output Compare N IDLE State */ + /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); @@ -350,11 +352,11 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /** * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. + * parameters in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. + * the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. + * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) @@ -409,7 +411,7 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Set the Output N State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Ouput Compare and Output Compare N IDLE State */ + /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); @@ -433,10 +435,10 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /** * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. + * parameters in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. + * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) @@ -489,7 +491,7 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Set the Output N State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Ouput Compare and Output Compare N IDLE State */ + /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); /* Set the Output Idle state */ @@ -512,10 +514,10 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /** * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. + * parameters in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. + * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) @@ -556,7 +558,7 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Ouput Compare IDLE State */ + /* Reset the Output Compare IDLE State */ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); @@ -576,10 +578,10 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /** * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. + * parameters in the TIM_ICInitStruct. * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. + * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) @@ -643,10 +645,10 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) /** * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * parameters in the TIM_ICInitStruct to measure an external PWM signal. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. + * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) @@ -701,10 +703,10 @@ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) /** * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). + * the OSSR State and the AOE(automatic output enable). * @param TIMx: where x can be 1 or 8 to select the TIM * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. + * contains the BDTR Register configuration information for the TIM peripheral. * @retval None */ void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) @@ -728,7 +730,7 @@ void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) /** * @brief Fills each TIM_TimeBaseInitStruct member with its default value. * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. + * structure which will be initialized. * @retval None */ void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) @@ -744,7 +746,7 @@ void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) /** * @brief Fills each TIM_OCInitStruct member with its default value. * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will - * be initialized. + * be initialized. * @retval None */ void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) @@ -762,8 +764,8 @@ void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) /** * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will - * be initialized. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. * @retval None */ void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) @@ -779,7 +781,7 @@ void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) /** * @brief Fills each TIM_BDTRInitStruct member with its default value. * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. + * will be initialized. * @retval None */ void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) @@ -915,21 +917,21 @@ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) } /** - * @brief Configures the TIMx’s DMA interface. + * @brief Configures the TIMx's DMA interface. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select * the TIM peripheral. * @param TIM_DMABase: DMA Base address. * This parameter can be one of the following values: * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, - * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, - * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, - * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, - * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, - * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, - * TIM_DMABase_DCR. + * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, + * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, + * TIM_DMABase_DCR. * @param TIM_DMABurstLength: DMA Burst length. * This parameter can be one value between: - * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. + * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval None */ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) @@ -943,7 +945,7 @@ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurs } /** - * @brief Enables or disables the TIMx’s DMA Requests. + * @brief Enables or disables the TIMx's DMA Requests. * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 * to select the TIM peripheral. * @param TIM_DMASource: specifies the DMA Request sources. @@ -979,9 +981,9 @@ void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewSt } /** - * @brief Configures the TIMx interrnal Clock + * @brief Configures the TIMx internal Clock * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 - * to select the TIM peripheral. + * to select the TIM peripheral. * @retval None */ void TIM_InternalClockConfig(TIM_TypeDef* TIMx) @@ -1250,11 +1252,11 @@ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending * on the level of the other input. * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_ICPolarity_Falling: IC Falling edge. * @arg TIM_ICPolarity_Rising: IC Rising edge. * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_ICPolarity_Falling: IC Falling edge. * @arg TIM_ICPolarity_Rising: IC Rising edge. * @retval None @@ -1448,7 +1450,7 @@ void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) /** * @brief Selects the TIMx peripheral Capture Compare DMA source. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. + * the TIM peripheral. * @param NewState: new state of the Capture Compare DMA source * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1473,7 +1475,7 @@ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) /** * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 - * to select the TIMx peripheral + * to select the TIMx peripheral * @param NewState: new state of the Capture Compare Preload Control bit * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1522,7 +1524,7 @@ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) /** * @brief Enables or disables the TIMx peripheral Preload register on CCR2. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. + * the TIM peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable @@ -1620,7 +1622,7 @@ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) /** * @brief Configures the TIMx Output Compare 2 Fast feature. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. + * the TIM peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable @@ -1795,7 +1797,7 @@ void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) * @brief Configures the TIMx channel 1 polarity. * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None @@ -1818,7 +1820,7 @@ void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) * @brief Configures the TIMx Channel 1N polarity. * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None @@ -1842,7 +1844,7 @@ void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) * @brief Configures the TIMx channel 2 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None @@ -1865,7 +1867,7 @@ void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) * @brief Configures the TIMx Channel 2N polarity. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None @@ -1889,7 +1891,7 @@ void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) * @brief Configures the TIMx channel 3 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None @@ -1912,7 +1914,7 @@ void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) * @brief Configures the TIMx Channel 3N polarity. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None @@ -1937,7 +1939,7 @@ void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) * @brief Configures the TIMx channel 4 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None @@ -1960,7 +1962,7 @@ void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 @@ -1991,7 +1993,7 @@ void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 @@ -2018,19 +2020,19 @@ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) } /** - * @brief Selects the TIM Ouput Compare Mode. - * @note This function disables the selected channel before changing the Ouput + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output * Compare Mode. * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This paramter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_OCMode_Timing * @arg TIM_OCMode_Active * @arg TIM_OCMode_Toggle @@ -2133,7 +2135,7 @@ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) } /** - * @brief Enables or disables the TIMx’s Hall sensor interface. + * @brief Enables or disables the TIMx's Hall sensor interface. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param NewState: new state of the TIMx Hall sensor interface. * This parameter can be: ENABLE or DISABLE. @@ -2157,7 +2159,7 @@ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) } /** - * @brief Selects the TIMx’s One Pulse Mode. + * @brief Selects the TIMx's One Pulse Mode. * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. * @param TIM_OPMode: specifies the OPM Mode to be used. * This parameter can be one of the following values: @@ -2212,7 +2214,7 @@ void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) * @brief Selects the TIMx Slave Mode. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This paramter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes * the counter and triggers an update of the registers. * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. @@ -2235,7 +2237,7 @@ void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) * @brief Sets or Resets the TIMx Master/Slave Mode. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This paramter can be one of the following values: + * This parameter can be one of the following values: * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer * and its slaves (through TRGO). * @arg TIM_MasterSlaveMode_Disable: No action @@ -2885,4 +2887,4 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c index eb84d977f23f6825a9299350b09a32d3282f5d62..a3f16f15ea60731c5b287983637e53f3c8f30681 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_usart.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the USART firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_usart.h" @@ -122,7 +123,8 @@ /** * @brief Deinitializes the USARTx peripheral registers to their default reset values. * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. * @retval None */ void USART_DeInit(USART_TypeDef* USARTx) @@ -162,12 +164,13 @@ void USART_DeInit(USART_TypeDef* USARTx) /** * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . + * parameters in the USART_InitStruct . * @param USARTx: Select the USART or the UART peripheral. * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified USART peripheral. + * that contains the configuration information for the specified USART + * peripheral. * @retval None */ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) @@ -272,7 +275,7 @@ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) /** * @brief Fills each USART_InitStruct member with its default value. * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. + * which will be initialized. * @retval None */ void USART_StructInit(USART_InitTypeDef* USART_InitStruct) @@ -288,12 +291,12 @@ void USART_StructInit(USART_InitTypeDef* USART_InitStruct) /** * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . + * specified parameters in the USART_ClockInitStruct . * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @note The Smart Card mode is not available for UART4 and UART5. + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. * @retval None */ void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) @@ -324,7 +327,7 @@ void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockI /** * @brief Fills each USART_ClockInitStruct member with its default value. * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. + * structure which will be initialized. * @retval None */ void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) @@ -339,10 +342,10 @@ void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) /** * @brief Enables or disables the specified USART peripheral. * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. + * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) @@ -372,7 +375,7 @@ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) * This parameter can be one of the following values: * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt * @arg USART_IT_RXNE: Receive Data register not empty interrupt * @arg USART_IT_IDLE: Idle line detection interrupt @@ -749,7 +752,7 @@ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) * @param USARTx: Select the USART or the UART peripheral. * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling methode. + * @param NewState: new state of the USART one bit sampling method. * This parameter can be: ENABLE or DISABLE. * @note * This function has to be called before calling USART_Init() @@ -775,11 +778,11 @@ void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) } /** - * @brief Enables or disables the USART's one bit sampling methode. + * @brief Enables or disables the USART's one bit sampling method. * @param USARTx: Select the USART or the UART peripheral. * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling methode. + * @param NewState: new state of the USART one bit sampling method. * This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -802,7 +805,7 @@ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) } /** - * @brief Configures the USART’s IrDA interface. + * @brief Configures the USART's IrDA interface. * @param USARTx: Select the USART or the UART peripheral. * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. @@ -823,7 +826,7 @@ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) } /** - * @brief Enables or disables the USART’s IrDA interface. + * @brief Enables or disables the USART's IrDA interface. * @param USARTx: Select the USART or the UART peripheral. * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. @@ -998,7 +1001,7 @@ ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) } /** - * @brief Clears the USARTx’s interrupt pending bits. + * @brief Clears the USARTx's interrupt pending bits. * @param USARTx: Select the USART or the UART peripheral. * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. @@ -1052,4 +1055,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c index 753a710cda35c761c2f41aa2613a0a83b8b23e5c..77a7ce517d5c4e42ee7fa752e161ae0c110a78e3 100644 --- a/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c +++ b/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f10x_wwdg.c * @author MCD Application Team - * @version V3.4.0 - * @date 10/15/2010 + * @version V3.5.0 + * @date 11-March-2011 * @brief This file provides all the WWDG firmware functions. ****************************************************************************** - * @copy + * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * - *

© COPYRIGHT 2010 STMicroelectronics

- */ + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_wwdg.h" @@ -220,4 +221,4 @@ void WWDG_ClearFlag(void) * @} */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/