diff --git a/bsp/rm48x50/HALCoGen/HALCoGen.dil b/bsp/rm48x50/HALCoGen/HALCoGen.dil
new file mode 100644
index 0000000000000000000000000000000000000000..de07408b11d3a198dd4b6e49a533524bba6009b0
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/HALCoGen.dil
@@ -0,0 +1,8718 @@
+# RM48L950ZWT 05/29/13 16:40:00
+# 
+ARCH=RM48L950ZWT
+# 
+DRIVER.TOOLS.VAR.ARM.VALUE=0
+DRIVER.TOOLS.VAR.IAR.VALUE=0
+DRIVER.TOOLS.VAR.GHS.VALUE=0
+DRIVER.TOOLS.VAR.TI.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_NAME.VALUE=het2LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_NAME.VALUE=adc2Group2Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_NAME.VALUE=spi4HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_MAPPING.VALUE=2
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.EQEP2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MEMINIT_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_DATA_3_WAIT_STATE_FREQ.VALUE=200.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_MAPPING.VALUE=96
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_MAPPING.VALUE=88
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0xFCFFFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SPI3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_BYPASS_ON_SLIP.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=256_KB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=200.000
+DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=200.00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_MAPPING.VALUE=65
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_MAPPING.VALUE=57
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_MAPPING.VALUE=49
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_NAME.VALUE=het1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CCM_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.CLKT_PLL2_OUTPUT_DIV.VALUE=2
+DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x63FFFFFF
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_DP_PBISTCHECK_ENA.VALUE=0x00040000
+DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_MAPPING.VALUE=50
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_MAPPING.VALUE=42
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_MAPPING.VALUE=34
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_MAPPING.VALUE=26
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18
+DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=IRQ_Handler
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0600
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_MAPPING.VALUE=11
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.LBIST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x003FFFFF
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=100.0
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08001200
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_NAME.VALUE=dcc1DoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_NAME.VALUE=sciLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_NAME.VALUE=i2cInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_GLOBAL_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0xFF000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_DP_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=rtiCompare0Interrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER0_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENTRY.VALUE=_c_int00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x0A
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_MAPPING.VALUE=102
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_LENGTH.VALUE=0x3FFFF
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=64_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=spi2HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x203FFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE_VALUE.VALUE=0x0000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_MAPPING.VALUE=95
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_MAPPING.VALUE=87
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_MAPPING.VALUE=79
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_DP_PBISTCHECK_ENA.VALUE=0x00000040
+DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.USB_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SCI_ALL_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0
+DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=24
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16
+DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=200.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x1000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_MAPPING.VALUE=64
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_MAPPING.VALUE=56
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_MAPPING.VALUE=48
+DRIVER.SYSTEM.VAR.CLKT_PLL1_REF_CLOCK_DIV.VALUE=6
+DRIVER.SYSTEM.VAR.FLASHW_BASE_ADDRESS.VALUE=0xFFF87000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_FIQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]"
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001
+DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_FREQ.VALUE=16.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_NAME.VALUE=dcc2DoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_MAPPING.VALUE=41
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_MAPPING.VALUE=33
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_MAPPING.VALUE=25
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=rtiCompare1Interrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=2
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CLKT_PLL2_FM_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0x08400000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_CPUSELFTEST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.HET1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI1_PRE_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.FLASH_MODE_VALUE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE_VALUE.VALUE=0x19
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_MAPPING.VALUE=10
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE.VALUE=128_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_DP_PBISTCHECK_ENA.VALUE=0x00001000
+DRIVER.SYSTEM.VAR.ECAP4_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_MAPPING.VALUE=124
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_MAPPING.VALUE=116
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_MAPPING.VALUE=108
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_NAME.VALUE=adc2Group0Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_NAME.VALUE=can2LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_NAME.VALUE=mibspi1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3
+DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_SP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_MAPPING.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_DIV.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_PLL2_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.RAM_BASE_ADDRESS.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.CORE_PMU_EVENT_EXPORT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x17
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_MAPPING.VALUE=94
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_MAPPING.VALUE=86
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_MAPPING.VALUE=78
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE.VALUE=STRONGLYORDERED_SHAREABLE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08001300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD3_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EFUSE_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_GHV_WAKUP_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE_VALUE.VALUE=0x0000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_MAPPING.VALUE=71
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_MAPPING.VALUE=63
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_MAPPING.VALUE=55
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_MAPPING.VALUE=47
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_MAPPING.VALUE=39
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_NAME.VALUE=rtiCompare2Interrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08001500
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE.VALUE=8_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=120.0
+DRIVER.SYSTEM.VAR.RAM_STACK_BASE.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_NAME.VALUE=adc2Group1Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_MAPPING.VALUE=40
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_NAME.VALUE=can2HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_MAPPING.VALUE=32
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_NAME.VALUE=linLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_MAPPING.VALUE=24
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_NAME.VALUE=crcInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xF07FFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_2.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_3.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_4.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_5.VALUE=1
+DRIVER.SYSTEM.VAR.LBIST_STT.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_6.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_7.VALUE=1
+DRIVER.SYSTEM.VAR.ECAP2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_8.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_MAPPING.VALUE=123
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_MAPPING.VALUE=115
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_MAPPING.VALUE=107
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00001000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0x0843FFFF
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_SP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x11
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x08001000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=STRONGLYORDERED_SHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_DP_PBISTCHECK_ENA.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=12.500
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=rtiCompare3Interrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00001500
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC
+DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0xFFFFFFFF
+DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=PLL2_ODCLK_8
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=100.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_MAPPING.VALUE=69
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ2.VALUE=100.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE.VALUE=16_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_BASE_ADDRESS.VALUE=0xFC000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_2_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=150
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_NAME.VALUE=adc1Group2Interrupt
+DRIVER.SYSTEM.VAR.CLKT_OSC_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE.VALUE=16_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_MAPPING.VALUE=70
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_MAPPING.VALUE=62
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_MAPPING.VALUE=54
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_MAPPING.VALUE=46
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_MAPPING.VALUE=38
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_SOURCE_ENABLE.VALUE=0x00000080
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_DP_PBISTCHECK_ENA.VALUE=0x00080000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0003eaff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x080017FF
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_MAPPING.VALUE=31
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_MAPPING.VALUE=23
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_MAPPING.VALUE=15
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_5_6.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=150
+DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENTRY.VALUE=_prefetch
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_FREQ.VALUE=100.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_BASE_ADDRESS.VALUE=0x60000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_AUTO_CLK_WAKE_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_7_8.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_0.VALUE=0x00000020
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_1.VALUE=0x00180000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE_VALUE.VALUE=0x08
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_MAPPING.VALUE=122
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_MAPPING.VALUE=114
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_MAPPING.VALUE=106
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_NAME.VALUE=rtiOverflow0Interrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER2_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.FLASH_DATA_WAIT_STATES.VALUE=3
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=150.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5
+DRIVER.SYSTEM.VAR.VIM_PARITY_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE
+DRIVER.SYSTEM.VAR.VIM_CHANNELS.VALUE=96
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_7.VALUE=0xF0200000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE.VALUE=512_BYTES
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD1_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_DP_PBISTCHECK_ENA.VALUE=0x00000010
+DRIVER.SYSTEM.VAR.ESM_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_MAPPING.VALUE=99
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_NAME.VALUE=mibspi5HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_NAME.VALUE=can3HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_NAME.VALUE=mibspi3HighInterruptLevel
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_NAME.VALUE=can1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=2_KB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.EQEP1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_FREQ.VALUE=10.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE_VALUE.VALUE=0x11
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]"
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_MAPPING.VALUE=92
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_MAPPING.VALUE=84
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_MAPPING.VALUE=76
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_MAPPING.VALUE=68
+DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_DP_PBISTCHECK_ENA.VALUE=0x00020000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SYSTEM_INIT.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_NAME.VALUE=esmLowInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_NAME.VALUE=mibspi1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION.VALUE=PRIV_NA_USER_NA_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_TYPE.VALUE=FIQ
+DRIVER.SYSTEM.VAR.DMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION_VALUE.VALUE=0x1100
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION_VALUE.VALUE=0x1200
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_MAPPING.VALUE=61
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_MAPPING.VALUE=53
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_MAPPING.VALUE=45
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_MAPPING.VALUE=37
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00300000
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=50.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_MAPPING.VALUE=30
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_MAPPING.VALUE=22
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_MAPPING.VALUE=14
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_NAME.VALUE=rtiOverflow1Interrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_2.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_ESRAM_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=100.0
+DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0xFE0001FF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00002000
+DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_NAME.VALUE=spi4LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_NAME.VALUE=mibspi3LowLevelInterrupt
+DRIVER.SYSTEM.VAR.FEE_FLASH_ECC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE.VALUE=4_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE_AVAIL.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATE_AVAIL.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87FFFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_GB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE_VALUE.VALUE=0x17
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_MAPPING.VALUE=98
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_NAME.VALUE=linHighLevelInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_FUN.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_BASE_ADDRESS.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000800
+DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08001400
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08001000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.PMM_PMCTRL_PWRDN.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_MAPPING.VALUE=83
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_MAPPING.VALUE=75
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_MAPPING.VALUE=67
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_MAPPING.VALUE=59
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_2.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803FFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD5_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_DP_PBISTCHECK_ENA.VALUE=0x00000008
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_4.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_5.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE_VALUE.VALUE=0x15
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_NAME.VALUE=rtiTimebaseInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PRESCALER.VALUE=8
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_6.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0xFE000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=100.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_MAPPING.VALUE=36
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_MAPPING.VALUE=28
+DRIVER.SYSTEM.VAR.CLKT_PLL1_BAND_WIDTH_ADJUSTMENT.VALUE=7
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CLKT_RTI1_POST_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_NAME.VALUE=het2HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_NAME.VALUE=can3LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_DP_PBISTCHECK_ENA.VALUE=0x00000400
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_DP_PBISTCHECK_ENA.VALUE=0x00000080
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_MAPPING.VALUE=13
+DRIVER.SYSTEM.VAR.CLKT_PLL2_REF_CLOCK_DIV.VALUE=6
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_RATE.VALUE=255
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_SLIP.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_MAPPING.VALUE=127
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_MAPPING.VALUE=119
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION.VALUE=PRIV_RW_USER_NA_NOEXEC
+DRIVER.SYSTEM.VAR.CLKT_PLL1_FM_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE.VALUE=4_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.ECAP3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_NAME.VALUE=spi2LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_NAME.VALUE=adc1Group0Interrupt
+DRIVER.SYSTEM.VAR.CLKT_LPOLO_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PSL.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0xFFFFFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=_svc
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FLASHECC_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_MAPPING.VALUE=3
+DRIVER.SYSTEM.VAR.CLKT_LPOHI_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RTP_DP_PBISTCHECK_ENA.VALUE=0x00004000
+DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIV_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_MAPPING.VALUE=97
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_MAPPING.VALUE=89
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_NAME.VALUE=gioHighLevelInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL1_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.FLASH_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_ENA.VALUE=0x08300020
+DRIVER.SYSTEM.VAR.SPI5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x0017FFE0
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00180000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_MAPPING.VALUE=90
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_MAPPING.VALUE=82
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_MAPPING.VALUE=74
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_MAPPING.VALUE=66
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_NAME.VALUE=sciHighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_MAPPING.VALUE=58
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_NAME.VALUE=mibspi5LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08001100
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.FEE_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_10.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM_VALUE.VALUE=8
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_MAPPING.VALUE=51
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_MAPPING.VALUE=43
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_MAPPING.VALUE=35
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_MAPPING.VALUE=27
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_MAPPING.VALUE=19
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_11.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_12.VALUE=1
+DRIVER.SYSTEM.VAR.CCM_MENU.VALUE=NONE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=256_KB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_13.VALUE=1
+DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_14.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=200.00
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x1F
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_DP_PBISTCHECK_ENA.VALUE=0x00000004
+DRIVER.SYSTEM.VAR.ETPWM6_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_ENDIAN_LITTLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_SP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE_VALUE.VALUE=0x15
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_MAPPING.VALUE=126
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_MAPPING.VALUE=118
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULL.VALUE=2
+DRIVER.SYSTEM.VAR.ECLK_SUSPEND.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_AMOUNT.VALUE=61
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_VFP_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_DP_PBISTCHECK_ENA.VALUE=0x00000200
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FMCBUS2_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ECAP1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECLK_OSCILLATOR_FREQ.VALUE=16.000
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM.VALUE=100.00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CLKT_CRYSTAL_FREQ.VALUE=16.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_MAPPING.VALUE=111
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_MAPPING.VALUE=103
+DRIVER.SYSTEM.VAR.VIM_PHANTOM_NAME.VALUE=phantomInterrupt
+DRIVER.OS.VAR.OS_USERECERSIVEMUTEXES.VALUE=0
+DRIVER.OS.VAR.OS_USETIMERS.VALUE=0
+DRIVER.OS.VAR.OS_USECNTSEMAPHORE.VALUE=0
+DRIVER.OS.VAR.OS_GENERATERUNTIMESTATS.VALUE=0
+DRIVER.OS.VAR.OS_USEMPU.VALUE=0
+DRIVER.OS.VAR.OS_TOTALHEAPSIZE.VALUE=8192
+DRIVER.OS.VAR.OS_USEVERBOSESTACK.VALUE=2
+DRIVER.OS.VAR.OS_TIMERPRIORITY.VALUE=0
+DRIVER.OS.VAR.OS_SVCENABLE.VALUE=0
+DRIVER.OS.VAR.OS_MAXTASKNAMELEN.VALUE=16
+DRIVER.OS.VAR.OS_MAXPRIORITIES.VALUE=5
+DRIVER.OS.VAR.OS_TIMERTASKSTACKDEPTH.VALUE=0
+DRIVER.OS.VAR.OS_COROUTINEPRIORITIES.VALUE=2
+DRIVER.OS.VAR.OS_USECOROUTINES.VALUE=0
+DRIVER.OS.VAR.OS_USEMUTEXES.VALUE=0
+DRIVER.OS.VAR.OS_CPUCLOCKHZ.VALUE=80000000
+DRIVER.OS.VAR.OS_USEMALLOCFAILEDHOOK.VALUE=0
+DRIVER.OS.VAR.OS_MINSTACKSIZE.VALUE=128
+DRIVER.OS.VAR.OS_SYSTEM_MODE.VALUE=0x1F
+DRIVER.OS.VAR.OS_USEPREEMPTION.VALUE=1
+DRIVER.OS.VAR.OS_IDLESHOULDYIELD.VALUE=1
+DRIVER.OS.VAR.OS_USEIDLEHOOK.VALUE=0
+DRIVER.OS.VAR.OS_TICKRATEHZ.VALUE=1000
+DRIVER.OS.VAR.OS_TIMERPQUEUELENGTH.VALUE=0
+DRIVER.OS.VAR.OS_USETRACE.VALUE=0
+DRIVER.OS.VAR.OS_USESTACK.VALUE=0
+DRIVER.OS.VAR.OS_USETICKHOOK.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL21_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL13_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL57_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_ENABLE.VALUE=0
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+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULL.VALUE=1
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+DRIVER.GIO.VAR.GIO_PORT1_BIT5_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORTB_ENABLE.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PSL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_TIMMINGMODE.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DIR.VALUE=0
+DRIVER.SCI.VAR.SCI_TIMMINGMODE.VALUE=1
+DRIVER.SCI.VAR.SCILIN_WAKEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PULL.VALUE=2
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DIR.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT0_DIR.VALUE=0
+DRIVER.SCI.VAR.SCI_ACTUALBAUDRATE.VALUE=115741
+DRIVER.SCI.VAR.SCI_EVENPARITY.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_FUN.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DIR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_RXINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_DIR.VALUE=0
+DRIVER.SCI.VAR.SCI_BASE_PORT.VALUE=0xFFF7E540
+DRIVER.SCI.VAR.SCILIN_PRESCALE.VALUE=53
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PDR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_FUN.VALUE=1
+DRIVER.SCI.VAR.SCI_PORT_BIT0_FUN.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_DIR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PDR.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PDR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_FUN.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_FUN.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PSL.VALUE=1
+DRIVER.SCI.VAR.SCI_OEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PDR.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PDR.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_FUN.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PSL.VALUE=1
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PSL.VALUE=1
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PDR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PSL.VALUE=1
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PSL.VALUE=1
+DRIVER.SCI.VAR.SCILIN_BREAKINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_WAKEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_BREAKINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PSL.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_FEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_OEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_TXINTENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PARITYENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT0_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_BAUDRATE.VALUE=115200
+DRIVER.SCI.VAR.SCILIN_BREAKINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_WAKEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_BREAKINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_STOPBITS.VALUE=1
+DRIVER.SCI.VAR.SCI_RXINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_FEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_EVENPARITY.VALUE=0
+DRIVER.SCI.VAR.SCI_TXINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_OEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_PEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_CLKMODE.VALUE=1
+DRIVER.SCI.VAR.SCI_PARITYENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PULL.VALUE=2
+DRIVER.SCI.VAR.SCI_PORT_BIT2_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCILIN_BASE.VALUE=0xFFF7E400
+DRIVER.SCI.VAR.SCI_RXINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_FEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_PRESCALE.VALUE=53
+DRIVER.SCI.VAR.SCILIN_OEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_TXINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULL.VALUE=2
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PULL.VALUE=2
+DRIVER.SCI.VAR.SCI_PEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_WAKEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_LENGTH.VALUE=8
+DRIVER.SCI.VAR.SCILIN_CLKMODE.VALUE=1
+DRIVER.SCI.VAR.SCILIN_BASE_PORT.VALUE=0xFFF7E440
+DRIVER.SCI.VAR.SCILIN_BAUDRATE.VALUE=115200
+DRIVER.SCI.VAR.SCILIN_STOPBITS.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULL.VALUE=2
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PULL.VALUE=2
+DRIVER.SCI.VAR.SCILIN_RXINTENA.VALUE=1
+DRIVER.SCI.VAR.SCILIN_LENGTH.VALUE=8
+DRIVER.SCI.VAR.SCILIN_FEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_ACTUALBAUDRATE.VALUE=115741
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_BASE.VALUE=0xFFF7E500
+DRIVER.SCI.VAR.SCILIN_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_CLKMOD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE.VALUE=0xFFF7FC00
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE_RAM.VALUE=0xFF0A0000
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE_PORT.VALUE=0xFFF7F418
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE.VALUE=0xFFF7F400
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ENABLE.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE.VALUE=0xFFF7F800
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.SPI.VAR.SPI3_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI2_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI1_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI1_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI1_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618
+DRIVER.SPI.VAR.SPI5_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI4_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI3_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI1_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI1_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI4_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI4_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI1_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI1_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI1_BASE.VALUE=0xFFF7F400
+DRIVER.SPI.VAR.SPI3_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI5_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI4_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI5_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI1_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_BASE_PORT.VALUE=0xFFF7FC18
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_BASE.VALUE=0xFFF7F600
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI3_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI5_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI3_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI5_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_BASE.VALUE=0xFFF7F800
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI3_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI3_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI3_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_BASE_PORT.VALUE=0xFFF7F818
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI2_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_BASE_RAM.VALUE=0xFF0C0000
+DRIVER.SPI.VAR.SPI3_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI3_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI1_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI1_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00
+DRIVER.SPI.VAR.SPI3_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI3_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI3_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI2_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI3_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI1_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_BASE_PORT.VALUE=0xFFF7F418
+DRIVER.SPI.VAR.SPI5_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_BASE.VALUE=0xFFF7FC00
+DRIVER.SPI.VAR.SPI2_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI2_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI5_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI5_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI2_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI1_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI1_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI4_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI2_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI2_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI2_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI3_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI1_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_BASE_PORT.VALUE=0xFFF7FA18
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_BASE_RAM.VALUE=0xFF0A0000
+DRIVER.SPI.VAR.SPI5_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI2_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI5_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI4_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI3_PHASE1.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=500
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ID.VALUE=9
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_RAMBASE.VALUE=0xFF1C0000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_RATE.VALUE=500.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_RATE.VALUE=500.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=75.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ID.VALUE=3
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_BASE.VALUE=0xFFF7DE00
+DRIVER.CAN.VAR.CAN_1_RAMBASE.VALUE=0xFF1E0000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ID.VALUE=4
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=500.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ID.VALUE=6
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7
+DRIVER.CAN.VAR.CAN_3_BASE.VALUE=0xFFF7E000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ID.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=10
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ID.VALUE=9
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=11
+DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=12
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_BAUDRATE.VALUE=500
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=75.000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_BRP.VALUE=24
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ID.VALUE=10
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=2
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=3
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_BRP.VALUE=24
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ID.VALUE=12
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=4
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=5
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_BRP.VALUE=24
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=6
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=7
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=9
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_SJW.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_BAUDRATE.VALUE=500
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_2_SJW.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_1_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SJW.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=75.000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ID.VALUE=3
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_RAMBASE.VALUE=0xFF1A0000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ID.VALUE=4
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ID.VALUE=10
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ID.VALUE=5
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ID.VALUE=11
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ID.VALUE=6
+DRIVER.CAN.VAR.CAN_3_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_PARITY_ENABLE.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_ALT_TRIG.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_GROUP2_LENGTH.VALUE=32
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_BND.VALUE=2
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_BND.VALUE=2
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC2_GROUP1_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_LENGTH.VALUE=64
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000
+DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8
+DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_BND.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_ALT_TRIG_COMP.VALUE=1
+DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000
+DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000
+DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32
+DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=9
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN16_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1
+DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=9
+DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.LIN.VAR.LIN_PORT_BIT0_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_PEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOAWUSINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOA3WUSINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_MAXPRESCALE.VALUE=4507
+DRIVER.LIN.VAR.LIN_LENGTH.VALUE=8
+DRIVER.LIN.VAR.LIN_PARITYENA.VALUE=0
+DRIVER.LIN.VAR.LIN_BREAKINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TX_MASK.VALUE=0xFF
+DRIVER.LIN.VAR.LIN_MSTMOD.VALUE=1
+DRIVER.LIN.VAR.LIN_SDEL.VALUE=1
+DRIVER.LIN.VAR.LIN_PORT_BIT2_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_TOAWUSINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_WAKEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_HGENCTRL.VALUE=1
+DRIVER.LIN.VAR.LIN_TOA3WUSINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PULL.VALUE=2
+DRIVER.LIN.VAR.LIN_CEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BREAKINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PBEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT0_FUN.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT2_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PULL.VALUE=2
+DRIVER.LIN.VAR.LIN_WAKEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_OEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_FUN.VALUE=2
+DRIVER.LIN.VAR.LIN_NREINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT2_FUN.VALUE=4
+DRIVER.LIN.VAR.LIN_CEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PSL.VALUE=1
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PULL.VALUE=2
+DRIVER.LIN.VAR.LIN_PBEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_BASE_PORT.VALUE=0xFFF7E440
+DRIVER.LIN.VAR.LIN_ACTUALBAUDRATE.VALUE=19.968
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PSL.VALUE=2
+DRIVER.LIN.VAR.LIN_ISFEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_FEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PSL.VALUE=4
+DRIVER.LIN.VAR.LIN_OEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TXINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_NREINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_IDINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_SBREAK.VALUE=13
+DRIVER.LIN.VAR.LIN_TOINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BAUDRATE.VALUE=20.000
+DRIVER.LIN.VAR.LIN_RX_MASK.VALUE=0xFF
+DRIVER.LIN.VAR.LIN_ISFEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_RXINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BASE.VALUE=0xFFF7E400
+DRIVER.LIN.VAR.LIN_FEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TXINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.LIN.VAR.LIN_IDINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_MAXBAUDRATE.VALUE=22.188
+DRIVER.LIN.VAR.LIN_BEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_RXINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PRESCALE.VALUE=312
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_HRSHARE.VALUE=0x00000008
+DRIVER.HET.VAR.HET2_INT_X1.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT29_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_PWM1_PIN_SELECT.VALUE=10
+DRIVER.HET.VAR.HET2_BIT12_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT3_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X2.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X3.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_INT_X4.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_PWM0_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT4_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM3_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT4_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X5.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT30_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT26_HRSHARE.VALUE=0x00002000
+DRIVER.HET.VAR.HET1_BIT22_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT18_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT3_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X6.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=9
+DRIVER.HET.VAR.HET1_BIT28_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT7_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X7.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT7_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X8.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT18_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT10_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X9.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM4_PIN_SELECT.VALUE=16
+DRIVER.HET.VAR.HET2_PWM4_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET1_RAM_BASE.VALUE=0xFF460000
+DRIVER.HET.VAR.HET2_EDGE6_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_PWM2_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE2_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_BIT11_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT24_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT16_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT19_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE6_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT24_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT16_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT2_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE5_PIN_SELECT.VALUE=21
+DRIVER.HET.VAR.HET2_BIT13_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT27_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT19_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_CAP5_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_PWM4_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT8_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_CAP2_PIN_SELECT.VALUE=4
+DRIVER.HET.VAR.HET2_BIT4_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT29_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT8_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_BIT1_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM7_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_BIT18_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_BIT16_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_BIT0_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT6_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP5_PIN_SELECT.VALUE=26
+DRIVER.HET.VAR.HET1_BIT28_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE7_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT1_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE5_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_PWM5_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_BIT3_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE7_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE1_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE4_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_BIT5_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_EDGE5_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_BIT8_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_LR_ACTUALTIME.VALUE=1280.000
+DRIVER.HET.VAR.HET1_PWM5_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM4_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET2_BIT9_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT5_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_PIN_SELECT.VALUE=18
+DRIVER.HET.VAR.HET2_BIT13_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE7_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_BIT17_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT30_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT19_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_BIT7_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE5_PIN_SELECT.VALUE=21
+DRIVER.HET.VAR.HET1_BIT29_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET_DIS_BLACKBOX.VALUE=0
+DRIVER.HET.VAR.HET2_PWM7_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_HR_ACTUALFREQUENCY.VALUE=100.000
+DRIVER.HET.VAR.HET2_PWM5_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_BIT25_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT17_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT4_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE0_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_CAP6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT20_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X10.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X11.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X20.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X12.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_PWM6_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT16_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X21.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X13.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_HR_PRESCALE.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_LR_PRESCALE.VALUE=7
+DRIVER.HET.VAR.HET2_PWM0_PIN_SELECT.VALUE=8
+DRIVER.HET.VAR.HET2_BIT6_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X30.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X22.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X14.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X31.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X23.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X15.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_INT_X24.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X16.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BASE_PORT.VALUE=0xFFF7B84C
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X25.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X17.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_PWM3_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X26.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X18.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X27.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X19.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT18_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X28.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET2_PWM0_DUTY.VALUE=50
+DRIVER.HET.VAR.HET2_BIT18_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X29.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_CAP7_PIN_SELECT.VALUE=6
+DRIVER.HET.VAR.HET2_BIT8_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_PWM4_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_PWM3_PIN_SELECT.VALUE=14
+DRIVER.HET.VAR.HET1_BIT11_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_BIT2_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE6_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT5_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_BIT14_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT20_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT16_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM0_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_BIT6_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM7_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_PWM0_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT8_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE4_PIN_SELECT.VALUE=20
+DRIVER.HET.VAR.HET2_BIT7_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT9_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT10_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_CAP1_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE6_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP1_PIN_SELECT.VALUE=2
+DRIVER.HET.VAR.HET2_BIT15_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT13_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE3_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_PWM6_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT9_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE0_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_BIT26_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT18_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT6_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE3_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT16_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP4_PIN_SELECT.VALUE=24
+DRIVER.HET.VAR.HET1_BIT29_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT0_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM2_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_EDGE3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_HRSHARE.VALUE=0x00000002
+DRIVER.HET.VAR.HET2_PWM6_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_BIT8_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_BIT4_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_HRSHARE.VALUE=0x00000004
+DRIVER.HET.VAR.HET1_BIT25_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT17_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT16_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM1_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM7_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_PWM3_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT24_HRSHARE.VALUE=0x00001000
+DRIVER.HET.VAR.HET1_BIT16_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_PIN_SELECT.VALUE=17
+DRIVER.HET.VAR.HET1_BIT20_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT12_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X10.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X11.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT3_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE0_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT7_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X20.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X12.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT10_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X21.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X13.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT18_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE4_PIN_SELECT.VALUE=20
+DRIVER.HET.VAR.HET1_INT_X30.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X22.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X14.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET1_INT_X31.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X23.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X15.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE5_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_PWM1_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_BIT7_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_INT_X24.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X16.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP2_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X25.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X17.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT9_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT5_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X26.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X18.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X27.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X19.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_INT_X28.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM2_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_RAM_SIZE.VALUE=160
+DRIVER.HET.VAR.HET1_EDGE2_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_INT_X29.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM3_PERIOD.VALUE=1000.000
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+DRIVER.HET.VAR.HET1_PWM1_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_BIT10_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP4_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_BIT8_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_PWM0_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_BIT4_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_EDGE1_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT19_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT8_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP6_PIN_SELECT.VALUE=4
+DRIVER.HET.VAR.HET1_PWM2_PIN_SELECT.VALUE=12
+DRIVER.HET.VAR.HET1_BIT1_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM3_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM2_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_EDGE4_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE0_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_PWM5_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT8_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT4_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE3_PIN_SELECT.VALUE=15
+DRIVER.HET.VAR.HET2_PWM2_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT18_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT11_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_EDGE1_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM7_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM2_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM5_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT8_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP0_PIN_SELECT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT21_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT13_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT5_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_BIT4_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE2_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_BIT9_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT1_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM4_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_BIT7_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM7_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_BIT8_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM2_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT31_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT23_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT15_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP3_PIN_SELECT.VALUE=6
+DRIVER.HET.VAR.HET1_BIT7_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_PWM4_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET2_BIT12_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_PWM0_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_CAP5_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT26_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT18_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_EDGE4_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_BIT20_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE5_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT6_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE1_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_PWM3_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE3_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_CAP7_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM3_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_PWM4_PIN_SELECT.VALUE=16
+DRIVER.HET.VAR.HET1_BIT10_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_BIT9_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE3_PIN_SELECT.VALUE=15
+DRIVER.HET.VAR.HET1_PWM1_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT8_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BASE.VALUE=0xFFF7B800
+DRIVER.HET.VAR.HET2_EDGE1_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_BIT12_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_PIN_SELECT.VALUE=19
+DRIVER.HET.VAR.HET1_PWM5_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_LR_ACTUALTIME.VALUE=1280.000
+DRIVER.HET.VAR.HET1_BIT21_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT13_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT11_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM3_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM7_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_HR_PRESCALE.VALUE=0
+DRIVER.HET.VAR.HET1_BIT30_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT22_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT14_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT7_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_HR_ACTUALFREQUENCY.VALUE=100.000
+DRIVER.HET.VAR.HET2_PWM1_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT5_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE4_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP0_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_BIT4_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE2_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM2_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT8_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT11_PDR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_EDGE6_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_PWM5_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT9_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_EDGE6_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT10_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP5_PIN_SELECT.VALUE=2
+DRIVER.HET.VAR.HET1_PWM1_PIN_SELECT.VALUE=10
+DRIVER.HET.VAR.HET1_BIT9_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT13_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_PWM7_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_PWM5_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT24_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT16_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.HET.VAR.HET2_BIT16_DOUT.VALUE=0
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+DRIVER.HET.VAR.HET1_EDGE0_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT30_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X0.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE2_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_HRSHARE.VALUE=0x00000001
+DRIVER.HET.VAR.HET1_INT_X1.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE2_PIN_SELECT.VALUE=13
+DRIVER.HET.VAR.HET2_PWM2_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT8_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X2.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_DIS_BLACKBOX.VALUE=0
+DRIVER.HET.VAR.HET2_LR_TIME.VALUE=800.000
+DRIVER.HET.VAR.HET1_INT_X3.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_EDGE5_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_BIT29_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT0_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_INT_X4.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_HRSHARE.VALUE=0x00000002
+DRIVER.HET.VAR.HET1_BIT21_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_INT_X5.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT20_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT3_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_INT_X6.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET1_INT_X7.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BASE_PORT.VALUE=0xFFF7B94C
+DRIVER.HET.VAR.HET1_INT_X8.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_BIT30_HRSHARE.VALUE=0x00008000
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+DRIVER.HET.VAR.HET1_INT_X9.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BASE.VALUE=0xFFF7B900
+DRIVER.HET.VAR.HET2_EDGE2_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE0_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_BIT10_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP2_PIN_SELECT.VALUE=4
+DRIVER.HET.VAR.HET1_BIT11_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM2_DUTYTIME.VALUE=500.480
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+DRIVER.HET.VAR.HET1_BIT31_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT23_DIR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT15_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_PULL.VALUE=1
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+DRIVER.HET.VAR.HET1_PWM6_PERIOD.VALUE=1000.000
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+DRIVER.HET.VAR.HET1_BIT15_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT9_PSL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT7_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_RAM_SIZE.VALUE=160
+DRIVER.HET.VAR.HET2_BIT9_DOUT.VALUE=0
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+DRIVER.HET.VAR.HET2_BIT0_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT14_PULL.VALUE=1
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+DRIVER.HET.VAR.HET1_BIT20_PSL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_EDGE5_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE1_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_PWM5_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT24_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT16_DIR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT18_ANDSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT0_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_PIN_SELECT.VALUE=18
+DRIVER.HET.VAR.HET2_EDGE2_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_LVL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_EDGE4_INTENA.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_EDGE7_PIN_SELECT.VALUE=23
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+DRIVER.HET.VAR.HET1_LR_TIME.VALUE=800.000
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+DRIVER.HET.VAR.HET1_BIT16_DOUT.VALUE=0
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+DRIVER.HET.VAR.HET2_RAM_BASE.VALUE=0xFF440000
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+DRIVER.HET.VAR.HET1_BIT8_XORSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_CAP7_PIN_SELECT.VALUE=30
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+DRIVER.HET.VAR.HET2_BIT0_PDR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_CAP1_PIN_SELECT.VALUE=2
+DRIVER.HET.VAR.HET1_PWM7_PERIOD_PRESCALER.VALUE=99968
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+DRIVER.HET.VAR.HET2_PWM4_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_BIT10_HRSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT10_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE7_PIN_SELECT.VALUE=23
+DRIVER.HET.VAR.HET1_BIT24_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT16_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT5_DOUT.VALUE=0
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+DRIVER.HET.VAR.HET2_PWM4_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT3_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE5_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_ANDSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_EDGE4_BOTH.VALUE=0
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+DRIVER.HET.VAR.HET2_PWM2_PIN_SELECT.VALUE=12
+DRIVER.HET.VAR.HET2_BIT1_PDR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT27_DIR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_PWM6_DUTY.VALUE=50
+DRIVER.HET.VAR.HET2_BIT8_ANDSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_PWM0_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT14_ANDSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT0_HRSHARE.VALUE=0x00000001
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+DRIVER.HET.VAR.HET1_PWM1_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE6_PIN_SELECT.VALUE=22
+DRIVER.HET.VAR.HET2_BIT2_PDR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_EDGE3_LVL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT13_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT12_HRSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT10_PDR.VALUE=0x00000000
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+DRIVER.DMM.VAR.DMM_PORT_BIT11_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT14_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT14_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT16_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT15_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT15_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT17_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT16_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT18_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT16_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT18_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT0_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT6_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_DIR.VALUE=0
+DRIVER.I2C.VAR.I2C_STOPBITS.VALUE=2
+DRIVER.I2C.VAR.I2C_PORT_BIT1_DIR.VALUE=0
+DRIVER.I2C.VAR.I2C_ICXRDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_BASE_PORT.VALUE=0xFFF7D44C
+DRIVER.I2C.VAR.I2C_DATACOUNT.VALUE=8
+DRIVER.I2C.VAR.I2C_ADDRMODE.VALUE=7BIT_AMODE
+DRIVER.I2C.VAR.I2C_PORT_BIT0_FUN.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PDR.VALUE=0
+DRIVER.I2C.VAR.I2C_BC_VALUE.VALUE=0x0003
+DRIVER.I2C.VAR.I2C_PORT_BIT1_FUN.VALUE=0
+DRIVER.I2C.VAR.I2C_RM_ENA.VALUE=0
+DRIVER.I2C.VAR.I2C_BC.VALUE=2_BIT
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PDR.VALUE=0
+DRIVER.I2C.VAR.I2C_TXRX_VALUE.VALUE=0
+DRIVER.I2C.VAR.I2C_SCDLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PSL.VALUE=1
+DRIVER.I2C.VAR.I2C_STPCND.VALUE=1
+DRIVER.I2C.VAR.I2C_ALINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PRESCALE.VALUE=12
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PSL.VALUE=1
+DRIVER.I2C.VAR.I2C_TXRX.VALUE=TRANSMITTER
+DRIVER.I2C.VAR.I2C_PORT_BIT0_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_ALINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_RXDMA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.I2C.VAR.I2C_BASE.VALUE=0xFFF7D400
+DRIVER.I2C.VAR.I2C_ARDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT1_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_TXDMA.VALUE=0
+DRIVER.I2C.VAR.I2C_MSMODE.VALUE=1
+DRIVER.I2C.VAR.I2C_ICCH.VALUE=33
+DRIVER.I2C.VAR.I2C_AASLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_ICCL.VALUE=33
+DRIVER.I2C.VAR.I2C_AAS.VALUE=0
+DRIVER.I2C.VAR.I2C_ADDRMODE_VALUE.VALUE=0x0001
+DRIVER.I2C.VAR.I2C_ICRRDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_FDF.VALUE=0
+DRIVER.I2C.VAR.I2C_ARDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_PARITYENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PULL.VALUE=2
+DRIVER.I2C.VAR.I2C_LENGTH.VALUE=8
+DRIVER.I2C.VAR.I2C_NACKINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_SCD.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PULL.VALUE=2
+DRIVER.I2C.VAR.I2C_ICRRDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_STACND.VALUE=1
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.I2C.VAR.I2C_ICXRDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_NACKINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_EVENPARITY.VALUE=0
+DRIVER.I2C.VAR.I2C_BAUDRATE.VALUE=100
+DRIVER.I2C.VAR.I2C_MODCLK.VALUE=8
+DRIVER.DCC.VAR.DCC1_ENABLE_KEY.VALUE=10
+DRIVER.DCC.VAR.PINMUX_BASE.VALUE=0xFFFFEA00
+DRIVER.DCC.VAR.DCC1_DETECTION_TIME.VALUE=2500.00
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_VALUE.VALUE=0x0002
+DRIVER.DCC.VAR.DCC1_ENABLE_ERROR_INTERRUPT.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40
+DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0
+DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0
+DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=2500.00
+DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002
+DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1
+DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0
+DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792
+DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00
+DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=200.00
+DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0
+DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5
+DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5
+DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400
+DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0x5
+DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=39204
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1
+DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0
+DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=495000
+DRIVER.PINMUX.VAR.DMA_EIDXS_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_2.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_3.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_4.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_4.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX50_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_5.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_5.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_6.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_6.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_7.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_7.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_8.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX99_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_96_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_88_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_5_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_9.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_57_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_49_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX30_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_18_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_10.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_4.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX10.VALUE="PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18"
+DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_11.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_CHPR_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX11.VALUE="PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24"
+DRIVER.PINMUX.VAR.DMA_PRITY_12.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX20.VALUE="PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11"
+DRIVER.PINMUX.VAR.PINMUX12.VALUE="PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA"
+DRIVER.PINMUX.VAR.DMA_PRITY_13.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX21.VALUE="PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9"
+DRIVER.PINMUX.VAR.PINMUX13.VALUE="PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0"
+DRIVER.PINMUX.VAR.DMA_PRITY_14.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX30.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX22.VALUE="PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11"
+DRIVER.PINMUX.VAR.PINMUX14.VALUE="PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1"
+DRIVER.PINMUX.VAR.MUX92_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_15.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX31.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX23.VALUE=PINMUX_BALL_C6_EMIF_ADDR_8
+DRIVER.PINMUX.VAR.PINMUX15.VALUE="PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18"
+DRIVER.PINMUX.VAR.DMA_PRITY_16.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX32.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX16.VALUE="PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13"
+DRIVER.PINMUX.VAR.PINMUX33.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08"
+DRIVER.PINMUX.VAR.PINMUX34.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX26.VALUE="PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3"
+DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0"
+DRIVER.PINMUX.VAR.DMA_ADDMR_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX35.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX27.VALUE="PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2"
+DRIVER.PINMUX.VAR.PINMUX19.VALUE="PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10"
+DRIVER.PINMUX.VAR.PINMUX28.VALUE="PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3"
+DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX29.VALUE=PINMUX_BALL_D3_SPI2NENA
+DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_10.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX98_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_11.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_PRITY_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX98_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_20.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_12.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX100_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX98_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_21.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_13.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX100_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_30.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_22.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_14.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_0.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX100_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_31.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_23.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_15.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_1.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX100_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_24.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_16.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_2.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX100_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX91_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_25.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_17.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_3.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX91_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_26.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_18.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_4.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX91_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_102_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_27.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_19.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_5.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMR_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX91_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_28.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_6.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX91_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_29.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_7.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_8.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_9.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_10.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_10.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_11.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX60_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_20.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_12.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_21.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_13.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_13.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_30.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_22.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_14.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_14.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_31.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_23.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_15.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_STADD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_24.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_16.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_25.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_17.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_26.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_18.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_4.VALUE=0
+DRIVER.PINMUX.VAR.MUX30_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_71_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_63_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_55_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_47_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_39_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_27.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_19.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX21_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_28.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_28.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_29.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_29.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_0.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_TTYPE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_1.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_2.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_3.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_4.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_5.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_6.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_7.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_8.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_9.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5.VALUE=8BIT
+DRIVER.PINMUX.VAR.GATE_EMIF_CLK.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMW_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX97_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX97_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_107_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX90_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_DEBUGMODE.VALUE=IGNORE_SUSPEND
+DRIVER.PINMUX.VAR.MUX90_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_0.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ERRACT.VALUE=IGNORE
+DRIVER.PINMUX.VAR.MUX90_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_100_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_1.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHPR_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX90_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_2.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_BASE_PORT.VALUE=0xFFFFF040
+DRIVER.PINMUX.VAR.MUX90_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_3.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.MUX58_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_4.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.MUX5_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_5.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX5_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_6.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_7.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_8.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_10.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_9.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.ALT_ADC_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.MUX98_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_92_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_84_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_76_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_68_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_1_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTEN_16.VALUE=1
+DRIVER.PINMUX.VAR.MUX20_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_61_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_53_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_45_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_37_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX20_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX100_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_30_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_22_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_14_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX10_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ENDADD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_4.VALUE=0
+DRIVER.PINMUX.VAR.ETHERNET_SELECT.VALUE=RMII
+DRIVER.PINMUX.VAR.MUX91_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_1.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_INTASS_2.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.CONCOUNT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTASS_3.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_INTASS_4.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_ADDMR_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ACC_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_10.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_4.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_11.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMW_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_INTMP_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX96_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_20.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_12.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_6.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_21.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_13.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_30.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_22.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_14.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_8.VALUE=0
+DRIVER.PINMUX.VAR.GIOB_DISABLE_SELECT.VALUE=OFF
+DRIVER.PINMUX.VAR.PIN_MUX_105_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_31.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_23.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMW_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_15.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMR_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_TRIG_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_24.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_16.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX81_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_25.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_17.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX81_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_26.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_18.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_27.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_19.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENABLE1.VALUE=1
+DRIVER.PINMUX.VAR.MUX81_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_28.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_29.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX4_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX4_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_97_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_89_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_1.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_2.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_3.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_4.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX103_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_90_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_82_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_74_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_66_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_58_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_5.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_PRITY_6.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_7.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_8.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX21_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_51_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_43_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_35_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_27_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_9.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.AD1.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.AD2.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_20_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_12_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX9_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX104_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.ALT_ADC.VALUE=0
+DRIVER.PINMUX.VAR.I2C.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX71_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_DEBUGMODE_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX95_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_10.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_103_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_13.VALUE=0
+DRIVER.PINMUX.VAR.HET1.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_10.VALUE=0
+DRIVER.PINMUX.VAR.HET2.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX80_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX80_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX56_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_10.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX3_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_11.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_AIM_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTASS_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX3_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_20.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_12.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_6.VALUE=1
+DRIVER.PINMUX.VAR.EMIF.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_21.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_13.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_7.VALUE=1
+DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_22.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_14.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_8.VALUE=1
+DRIVER.PINMUX.VAR.MUX41_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX40_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_95_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_87_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_79_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_4_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_31.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_23.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_15.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMR_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX41_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_24.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_16.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_25.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_17.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_13.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_26.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_18.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_80_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_72_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_64_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_56_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_48_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_27.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_19.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMW_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.GIOA.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_28.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12.VALUE=8BIT
+DRIVER.PINMUX.VAR.GIOB.VALUE=0
+DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_29.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13.VALUE=8BIT
+DRIVER.PINMUX.VAR.GIOB_DISABLE.VALUE=0
+DRIVER.PINMUX.VAR.MUX10_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX10_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18.VALUE=8BIT
+DRIVER.PINMUX.VAR.PIN_MUX_10_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_4.VALUE=1
+DRIVER.PINMUX.VAR.DMA_AIM_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_8.VALUE=1
+DRIVER.PINMUX.VAR.MUX90_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_9.VALUE=1
+DRIVER.PINMUX.VAR.MIBSPI1.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MIBSPI3.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.OHCI0.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MIBSPI5.VALUE=0
+DRIVER.PINMUX.VAR.DMM.VALUE=0
+DRIVER.PINMUX.VAR.W2FC.VALUE=0
+DRIVER.PINMUX.VAR.OHCI1.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_108_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX94_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_10.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_101_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_11.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_PRITY_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX9_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_12.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_13.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_10.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_14.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX51_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_11.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_15.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_20.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_12.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_16.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_21.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_13.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_30.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_22.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_14.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_10.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX2_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_31.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_23.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_15.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_11.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX2_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_24.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_16.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_12.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX40_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_25.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_17.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_13.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.ETM.VALUE=0
+DRIVER.PINMUX.VAR.MUX40_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_26.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_18.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_14.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_93_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_85_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_77_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_69_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_2_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_27.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_19.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_15.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_PRITY_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX40_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_28.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_TRIG_16.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_29.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX102_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_70_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_62_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_54_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_46_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_38_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ERRACT_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MII.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.GATE_EMIF_CLK_SELECT.VALUE=OFF
+DRIVER.PINMUX.VAR.MUX20_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_1.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_2.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_CHPR_3.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_INTMP_10.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_4.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX93_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_11.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_5.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_1.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTMP_12.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_6.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_2.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTMP_13.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_7.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_3.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTMP_14.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_8.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_4.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_CHANNEL_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_15.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_9.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_5.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.SCI.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_16.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_TRIG_6.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_7.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_8.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX8_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_9.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_1.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_2.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ENABLEPAR.VALUE=1
+DRIVER.PINMUX.VAR.MUX102_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_3.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX102_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_4.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX102_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_5.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_TRIG_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_1.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_6.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_2.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX102_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX93_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_7.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_3.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX93_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_8.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_4.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX93_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_106_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_9.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX93_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX93_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BASE.VALUE=0xFFFFF000
+DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX70_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_98_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_7_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_75_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_67_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_59_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX31_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_60_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_52_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_44_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_36_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_28_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_0.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_21_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_13_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BASE_RAM.VALUE=0xFFF80000
+DRIVER.PINMUX.VAR.DMA_EIDXS_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_2.VALUE=0
+DRIVER.PINMUX.VAR.RTP.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_2.VALUE=1
+DRIVER.PINMUX.VAR.SPI2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_4.VALUE=1
+DRIVER.PINMUX.VAR.SPI4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTASS_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.RMII.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_6.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2"
+DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_7.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21"
+DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_8.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5"
+DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_PRITY_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24"
+DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12.VALUE=8BIT
+DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03"
+DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT
+DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26"
+DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_0.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28"
+DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_1.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHPR_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX7.VALUE="PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30"
+DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_2.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31"
+DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_3.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3"
+DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_4.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX92_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_104_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_5.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX92_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_6.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX92_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_7.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX7_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_8.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_0.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_9.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_1.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_1.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION3.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_PSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_CPB_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_PSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_TRDIR_1.VALUE=HET_TO_MAIN_MEM
+DRIVER.CRC.VAR.CRC_CH1_CCI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPBL_7_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DEBMOD_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_CFI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPAL_1_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ENABUS_1.VALUE=0
+DRIVER.CRC.VAR.HTU_CPA_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_WDTO.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_CCI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP1_ACC_1.VALUE=READ_ONLY
+DRIVER.CRC.VAR.HTU_CONTPAR_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_CFI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPB_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DCP0_EC_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_CPBFULADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPAL_6_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_DTE.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_FC_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_CVH.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PSSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_BASE.VALUE=0xFFF7A400
+DRIVER.CRC.VAR.CRC_CH1_CVL.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PSSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_3_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_DTE.VALUE=1
+DRIVER.CRC.VAR.CRC_CH2_CVH.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_CVL.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPA_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_SCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_DCP0_CPAFULADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPAL_2_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH2_PCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CPA_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_PSA.VALUE=1
+DRIVER.CRC.VAR.CRC_CH1_ORI.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_SCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP1_STADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_TOE.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPAL_7_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH2_PSA.VALUE=1
+DRIVER.CRC.VAR.CRC_CH2_ORI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CPB_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_MP0_ENA_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_MODE_VALUE.VALUE=0x0001
+DRIVER.CRC.VAR.CRC_CH1_URI.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_PSSIH.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_TOE.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_PSSIL.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_BCTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPBL_4_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_PAR_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_URI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CONT_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ENAREQ_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP1_ERRENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_STADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPA_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_3_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_BCTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_DCP0_MMADD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.HTU_ENAINTMAP_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_MODE_VALUE.VALUE=0x0001
+DRIVER.CRC.VAR.HTU_ICPBL_0_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPB_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_MP1_ENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_HETADD.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_5_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPA_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_RES_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_CPATMOD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.HTU_MP1_ENDADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_BASE.VALUE=0xFE000000
+DRIVER.CRC.VAR.HTU_ICPAL_4_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH1_MODE.VALUE=FULL_CPU
+DRIVER.CRC.VAR.HTU_CPA_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_VBHOLD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_ERRENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_1_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPB_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_MODE.VALUE=FULL_CPU
+DRIVER.CRC.VAR.HTU_DCP0_TRDAT_1.VALUE=32BIT
+DRIVER.CRC.VAR.HTU_ICPBL_6_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_0_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DCP0_CPBTMOD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.CRC_CH1_PSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_ACC_1.VALUE=READ_ONLY
+DRIVER.CRC.VAR.CRC_CH1_PSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_5_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_DCP0_ADMOD_1.VALUE=INCREMENT_16BIT
+DRIVER.CRC.VAR.HTU_CPA_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ENA_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_WDTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP0_ENDADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_2_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_0_SEL_1.VALUE=ENABLE
+DRIVER.EMAC.VAR.EMAC_ADD1.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD2.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD3.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD4.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD5.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD6.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_CTRL_BASE.VALUE=0xFCF78800
+DRIVER.EMAC.VAR.MDIO_BASE.VALUE=0xFCF78900
+DRIVER.EMAC.VAR.EMAC_BASE.VALUE=0xFCF78000
+DRIVER.EMAC.VAR.EMAC_BASE_PORT.VALUE=0xFFFFFFFF
+DRIVER.EMAC.VAR.EMAC_PHYADDRESS.VALUE=0
+DRIVER.EMAC.VAR.EMAC_CTRL_RAM_BASE.VALUE=0xFC520000
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TA.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TA.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ENA_SDRAM.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_MAX.VALUE=160
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_MAX.VALUE=160
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_MAX.VALUE=80
+DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC1_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_BANKS.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_BASE.VALUE=0xFCFFE800
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_MAX.VALUE=320
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=100000000
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_SETUP.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_MAX.VALUE=80
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_DEFAULT.VALUE=2500
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_MAX.VALUE=80
+DRIVER.EMIF.VAR.EMIF_CLK.VALUE=100
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_CAS_LATENCY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY0.VALUE=pin_low
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY1.VALUE=pin_high
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_SETUP.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES_MAX.VALUE=0
+DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001
+DRIVER.EMIF.VAR.EMIF_NS.VALUE=0.000000001
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_MAX.VALUE=80
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_MAX.VALUE=320
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD_MAX.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_ASYNC2_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_PAGE_SIZE.VALUE=elements_256
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_IBANK.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TA.VALUE=0
+DRIVER.POM.VAR.POM_OVRLY_START_ADD28.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD29.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_10_ENA.VALUE=0
+DRIVER.POM.VAR.POM_TIMEOUT_ENABLE.VALUE=0
+DRIVER.POM.VAR.POM_REGION_11_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_20_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_12_ENA.VALUE=0
+DRIVER.POM.VAR.POM_NO_OF_REGION.VALUE=1
+DRIVER.POM.VAR.POM_REGION_21_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_13_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_30_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_22_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_14_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_31_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_23_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_15_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_1_ENA.VALUE=1
+DRIVER.POM.VAR.POM_REGION_32_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_24_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_16_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_2_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_25_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_17_ENA.VALUE=0
+DRIVER.POM.VAR.POM_OVRLY_START_ADD1.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD2.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD3.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD4.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD5.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD6.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD7.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD8.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVLY_TRG_REGION.VALUE=INTERNAL_RAM
+DRIVER.POM.VAR.POM_OVRLY_START_ADD9.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_3_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_26_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_18_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_4_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_27_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_19_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_5_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_28_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_6_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_SIZE10.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE11.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE20.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE12.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_29_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_SIZE21.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE13.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE30.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE22.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE14.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE31.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE23.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE15.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE32.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE24.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE16.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE25.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE17.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE26.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE18.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE27.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE19.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE28.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE29.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_7_ENA.VALUE=0
+DRIVER.POM.VAR.POM_BASE.VALUE=0xFFA04000
+DRIVER.POM.VAR.POM_PROG_START_ADD10.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD11.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD20.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD12.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD21.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD13.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_8_ENA.VALUE=0
+DRIVER.POM.VAR.POM_PROG_START_ADD30.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD22.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD14.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD31.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD23.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD15.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD32.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD24.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD16.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD25.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD17.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD26.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD18.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD27.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD19.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE1.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_PROG_START_ADD28.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE2.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_PROG_START_ADD29.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE3.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE4.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE5.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE6.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE7.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE8.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE9.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_9_ENA.VALUE=0
+DRIVER.POM.VAR.POM_PROG_START_ADD1.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD2.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD3.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD4.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD5.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD6.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD7.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD8.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD9.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD10.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD11.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD20.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD12.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD21.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD13.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD30.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD22.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD14.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD31.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD23.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD15.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD32.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD24.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD16.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD25.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD17.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD26.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD18.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD27.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD19.VALUE=0x00000000
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN2_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN5_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN3_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN3_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN1_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0
diff --git a/bsp/rm48x50/HALCoGen/HALCoGen.hcg b/bsp/rm48x50/HALCoGen/HALCoGen.hcg
new file mode 100644
index 0000000000000000000000000000000000000000..e0ada188f817a93aea8a4bf7f84bed59b39ba3c6
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/HALCoGen.hcg
@@ -0,0 +1,730 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<SETTINGS>
+  <DEVICE>
+    <family>RM48x</family>
+    <device>RM48L950ZWT</device>
+    <dilfile>HALCoGen.dil</dilfile>
+    <tools>ti</tools>
+  </DEVICE>
+  <VERSION>
+    <version>03.05.02</version>
+  </VERSION>
+  <HET1>
+    <FILENAME>
+      <HET1ASMHDR>
+        <NAME/>
+      </HET1ASMHDR>
+      <HET1ASMSRC>
+        <NAME/>
+      </HET1ASMSRC>
+    </FILENAME>
+  </HET1>
+  <HET2>
+    <FILENAME>
+      <HET2ASMHDR>
+        <NAME/>
+      </HET2ASMHDR>
+      <HET2ASMSRC>
+        <NAME/>
+      </HET2ASMSRC>
+    </FILENAME>
+  </HET2>
+  <SYSTEM>
+    <FILENAMES>
+      <HDRHAL>
+        <NAME>hal_stdtypes.h</NAME>
+        <PATH>include\hal_stdtypes.h</PATH>
+      </HDRHAL>
+      <HDRCOMMON>
+        <NAME>sys_common.h</NAME>
+        <PATH>include\sys_common.h</PATH>
+      </HDRCOMMON>
+      <HDRSYSTEM_R>
+        <NAME>reg_system.h</NAME>
+        <PATH>include\reg_system.h</PATH>
+      </HDRSYSTEM_R>
+      <HDRFLASH_R>
+        <NAME>reg_flash.h</NAME>
+        <PATH>include\reg_flash.h</PATH>
+      </HDRFLASH_R>
+      <HDRTCRAM_R>
+        <NAME>reg_tcram.h</NAME>
+        <PATH>include\reg_tcram.h</PATH>
+      </HDRTCRAM_R>
+      <HDRVIM_R>
+        <NAME>reg_vim.h</NAME>
+        <PATH>include\reg_vim.h</PATH>
+      </HDRVIM_R>
+      <HDRPBIST_R>
+        <NAME>reg_pbist.h</NAME>
+        <PATH>include\reg_pbist.h</PATH>
+      </HDRPBIST_R>
+      <HDRSTC_R>
+        <NAME>reg_stc.h</NAME>
+        <PATH>include\reg_stc.h</PATH>
+      </HDRSTC_R>
+      <HDREFC_R>
+        <NAME>reg_efc.h</NAME>
+        <PATH>include\reg_efc.h</PATH>
+      </HDREFC_R>
+      <HDRPCR_R>
+        <NAME>reg_pcr.h</NAME>
+        <PATH>include\reg_pcr.h</PATH>
+      </HDRPCR_R>
+      <HDRPMM_R>
+        <NAME>reg_pmm.h</NAME>
+        <PATH>include\reg_pmm.h</PATH>
+      </HDRPMM_R>
+      <HDRDMA_R>
+        <NAME>reg_dma.h</NAME>
+        <PATH>include\reg_dma.h</PATH>
+      </HDRDMA_R>
+      <HDRSYSTEM>
+        <NAME>system.h</NAME>
+        <PATH>include\system.h</PATH>
+      </HDRSYSTEM>
+      <HDRVIM>
+        <NAME>sys_vim.h</NAME>
+        <PATH>include\sys_vim.h</PATH>
+      </HDRVIM>
+      <HDRCORE>
+        <NAME>sys_core.h</NAME>
+        <PATH>include\sys_core.h</PATH>
+      </HDRCORE>
+      <HDRMPU>
+        <NAME>sys_mpu.h</NAME>
+        <PATH>include\sys_mpu.h</PATH>
+      </HDRMPU>
+      <HDRPMU>
+        <NAME>sys_pmu.h</NAME>
+        <PATH>include\sys_pmu.h</PATH>
+      </HDRPMU>
+      <HDRPCR>
+        <NAME>sys_pcr.h</NAME>
+        <PATH>include\sys_pcr.h</PATH>
+      </HDRPCR>
+      <HDRPMM>
+        <NAME>sys_pmm.h</NAME>
+        <PATH>include\sys_pmm.h</PATH>
+      </HDRPMM>
+      <HDRDMA>
+        <NAME>sys_dma.h</NAME>
+        <PATH>include\sys_dma.h</PATH>
+      </HDRDMA>
+      <HDRSLF>
+        <NAME>sys_selftest.h</NAME>
+        <PATH>include\sys_selftest.h</PATH>
+      </HDRSLF>
+      <SRCCORE>
+        <NAME>sys_core.asm</NAME>
+        <PATH>source\sys_core.asm</PATH>
+      </SRCCORE>
+      <SRCINTVECS>
+        <NAME>sys_intvecs.asm</NAME>
+        <PATH>source\sys_intvecs.asm</PATH>
+      </SRCINTVECS>
+      <SRCMPU>
+        <NAME>sys_mpu.asm</NAME>
+        <PATH>source\sys_mpu.asm</PATH>
+      </SRCMPU>
+      <SRCPMU>
+        <NAME>sys_pmu.asm</NAME>
+        <PATH>source\sys_pmu.asm</PATH>
+      </SRCPMU>
+      <SRCDABORT>
+        <NAME>dabort.asm</NAME>
+        <PATH>source\dabort.asm</PATH>
+      </SRCDABORT>
+      <SRCPCR>
+        <NAME>sys_pcr.c</NAME>
+        <PATH>source\sys_pcr.c</PATH>
+      </SRCPCR>
+      <SRCPMM>
+        <NAME>sys_pmm.c</NAME>
+        <PATH>source\sys_pmm.c</PATH>
+      </SRCPMM>
+      <SRCDMA>
+        <NAME>sys_dma.c</NAME>
+        <PATH>source\sys_dma.c</PATH>
+      </SRCDMA>
+      <SRCSYSTEM>
+        <NAME>system.c</NAME>
+        <PATH>source\system.c</PATH>
+      </SRCSYSTEM>
+      <SRCPHANTOM>
+        <NAME>sys_phantom.c</NAME>
+        <PATH>source\sys_phantom.c</PATH>
+      </SRCPHANTOM>
+      <SRCSTARTUP>
+        <NAME>sys_startup.c</NAME>
+        <PATH>source\sys_startup.c</PATH>
+      </SRCSTARTUP>
+      <SRCSLF>
+        <NAME>sys_selftest.c</NAME>
+        <PATH>source\sys_selftest.c</PATH>
+      </SRCSLF>
+      <SRCVIM>
+        <NAME>sys_vim.c</NAME>
+        <PATH>source\sys_vim.c</PATH>
+      </SRCVIM>
+      <SRCMAIN>
+        <NAME>sys_main.c</NAME>
+        <PATH>source\sys_main.c</PATH>
+      </SRCMAIN>
+      <SRCNOTIFY>
+        <NAME>notification.c</NAME>
+        <PATH>source\notification.c</PATH>
+      </SRCNOTIFY>
+      <SRCCMD>
+        <NAME>sys_link.cmd</NAME>
+        <PATH>source\sys_link.cmd</PATH>
+      </SRCCMD>
+      <SRCMISRA-C>
+        <NAME>misra-c.txt</NAME>
+        <PATH>misra-c.txt</PATH>
+      </SRCMISRA-C>
+      <HDRMUX_R>
+        <NAME>reg_pinmux.h</NAME>
+      </HDRMUX_R>
+      <HDRMUX>
+        <NAME>pinmux.h</NAME>
+      </HDRMUX>
+      <SRCMUX>
+        <NAME>pinmux.c</NAME>
+      </SRCMUX>
+      <HDRRTI_R>
+        <NAME>reg_rti.h</NAME>
+      </HDRRTI_R>
+      <HDRRTI>
+        <NAME>rti.h</NAME>
+      </HDRRTI>
+      <SRCRTI>
+        <NAME>rti.c</NAME>
+      </SRCRTI>
+      <HDRGIO_R>
+        <NAME>reg_gio.h</NAME>
+      </HDRGIO_R>
+      <HDRGIO>
+        <NAME>gio.h</NAME>
+      </HDRGIO>
+      <SRCGIO>
+        <NAME>gio.c</NAME>
+      </SRCGIO>
+      <HDRSCI_R>
+        <NAME>reg_sci.h</NAME>
+      </HDRSCI_R>
+      <HDRSCI>
+        <NAME>sci.h</NAME>
+      </HDRSCI>
+      <SRCSCI>
+        <NAME>sci.c</NAME>
+      </SRCSCI>
+      <HDRLIN_R>
+        <NAME>reg_lin.h</NAME>
+      </HDRLIN_R>
+      <HDRLIN>
+        <NAME>lin.h</NAME>
+      </HDRLIN>
+      <SRCLIN/>
+      <HDRMIBSPI_R>
+        <NAME>reg_mibspi.h</NAME>
+      </HDRMIBSPI_R>
+      <HDRMIBSPI>
+        <NAME>mibspi.h</NAME>
+      </HDRMIBSPI>
+      <SRCMIBSPI/>
+      <HDRSPI_R>
+        <NAME>reg_spi.h</NAME>
+      </HDRSPI_R>
+      <HDRSPI>
+        <NAME>spi.h</NAME>
+      </HDRSPI>
+      <SRCSPI/>
+      <HDRCAN_R>
+        <NAME>reg_can.h</NAME>
+      </HDRCAN_R>
+      <HDRCAN>
+        <NAME>can.h</NAME>
+      </HDRCAN>
+      <SRCCAN/>
+      <HDRADC_R>
+        <NAME>reg_adc.h</NAME>
+      </HDRADC_R>
+      <HDRADC>
+        <NAME>adc.h</NAME>
+      </HDRADC>
+      <SRCADC/>
+      <HET1ASMHDR>
+        <NAME/>
+      </HET1ASMHDR>
+      <HET1ASMSRC>
+        <NAME/>
+      </HET1ASMSRC>
+      <STDHDRHET>
+        <NAME>std_nhet.h</NAME>
+      </STDHDRHET>
+      <HDRHET_R>
+        <NAME>reg_het.h</NAME>
+      </HDRHET_R>
+      <HDRHET>
+        <NAME>het.h</NAME>
+      </HDRHET>
+      <HDRHTU_R>
+        <NAME>reg_htu.h</NAME>
+      </HDRHTU_R>
+      <HDRHTU>
+        <NAME>htu.h</NAME>
+      </HDRHTU>
+      <SRCHET/>
+      <HET2ASMHDR>
+        <NAME/>
+      </HET2ASMHDR>
+      <HET2ASMSRC>
+        <NAME/>
+      </HET2ASMSRC>
+      <HDRESM_R>
+        <NAME>reg_esm.h</NAME>
+      </HDRESM_R>
+      <HDRESM>
+        <NAME>esm.h</NAME>
+      </HDRESM>
+      <SRCESM>
+        <NAME>esm.c</NAME>
+      </SRCESM>
+      <HDRI2C_R>
+        <NAME>reg_i2c.h</NAME>
+      </HDRI2C_R>
+      <HDRI2C>
+        <NAME>i2c.h</NAME>
+      </HDRI2C>
+      <SRCI2C/>
+      <HDR1EMAC>
+        <NAME>emac.h</NAME>
+      </HDR1EMAC>
+      <HDR2EMAC>
+        <NAME>hw_emac.h</NAME>
+      </HDR2EMAC>
+      <HDR3EMAC>
+        <NAME>hw_emac_ctrl.h</NAME>
+      </HDR3EMAC>
+      <HDR4EMAC>
+        <NAME>hw_mdio.h</NAME>
+      </HDR4EMAC>
+      <HDR5EMAC>
+        <NAME>hw_reg_access.h</NAME>
+      </HDR5EMAC>
+      <HDR6EMAC>
+        <NAME>mdio.h</NAME>
+      </HDR6EMAC>
+      <SRC1EMAC/>
+      <SRC2EMAC/>
+      <HDRDCC_R>
+        <NAME>reg_dcc.h</NAME>
+      </HDRDCC_R>
+      <HDRDCC>
+        <NAME>dcc.h</NAME>
+      </HDRDCC>
+      <SRCDCC/>
+      <HDRRTP_R>
+        <NAME>reg_rtp.h</NAME>
+      </HDRRTP_R>
+      <HDRRTP>
+        <NAME>rtp.h</NAME>
+      </HDRRTP>
+      <SRCRTP/>
+      <HDRDMM_R>
+        <NAME>reg_dmm.h</NAME>
+      </HDRDMM_R>
+      <HDRDMM>
+        <NAME>dmm.h</NAME>
+      </HDRDMM>
+      <SRCDMM/>
+      <HDREMIF_R>
+        <NAME>reg_emif.h</NAME>
+      </HDREMIF_R>
+      <HDREMIF>
+        <NAME>emif.h</NAME>
+      </HDREMIF>
+      <SRCEMIF/>
+      <HDRPOM_R>
+        <NAME>reg_pom.h</NAME>
+      </HDRPOM_R>
+      <HDRPOM>
+        <NAME>pom.h</NAME>
+      </HDRPOM>
+      <SRCPOM/>
+      <HDR1USB>
+        <NAME>usbcdc.h</NAME>
+      </HDR1USB>
+      <HDR2USB>
+        <NAME>usb_serial_structs.h</NAME>
+      </HDR2USB>
+      <HDR3USB>
+        <NAME>usbdcdc.h</NAME>
+      </HDR3USB>
+      <HDR4USB>
+        <NAME>usbdevice.h</NAME>
+      </HDR4USB>
+      <HDR5USB>
+        <NAME>usbdevicepriv.h</NAME>
+      </HDR5USB>
+      <HDR6USB>
+        <NAME>usb-ids.h</NAME>
+      </HDR6USB>
+      <HDR7USB>
+        <NAME>usblib.h</NAME>
+      </HDR7USB>
+      <HDR8USB>
+        <NAME>usb.h</NAME>
+      </HDR8USB>
+      <HDR9USB>
+        <NAME>hw_usb.h</NAME>
+      </HDR9USB>
+      <SRC1USB/>
+      <SRC2USB/>
+      <SRC3USB/>
+      <SRC5USB/>
+      <SRC6USB/>
+      <SRC7USB/>
+      <SRC8USB/>
+      <SRC9USB/>
+      <SRC10USB/>
+      <HDRCRC_R>
+        <NAME>reg_crc.h</NAME>
+      </HDRCRC_R>
+      <HDRCRC>
+        <NAME>crc.h</NAME>
+      </HDRCRC>
+      <SRCCRC/>
+    </FILENAMES>
+  </SYSTEM>
+  <PINMUX>
+    <FILENAMES>
+      <HDRMUX_R>
+        <PATH>include\reg_pinmux.h</PATH>
+      </HDRMUX_R>
+      <HDRMUX>
+        <PATH>include\pinmux.h</PATH>
+      </HDRMUX>
+      <SRCMUX>
+        <PATH>source\pinmux.c</PATH>
+      </SRCMUX>
+    </FILENAMES>
+  </PINMUX>
+  <RTI>
+    <FILENAMES>
+      <HDRRTI_R>
+        <PATH>include\reg_rti.h</PATH>
+      </HDRRTI_R>
+      <HDRRTI>
+        <PATH>include\rti.h</PATH>
+      </HDRRTI>
+      <SRCRTI>
+        <PATH>source\rti.c</PATH>
+      </SRCRTI>
+    </FILENAMES>
+  </RTI>
+  <GIO>
+    <FILENAMES>
+      <HDRGIO_R>
+        <PATH>include\reg_gio.h</PATH>
+      </HDRGIO_R>
+      <HDRGIO>
+        <PATH>include\gio.h</PATH>
+      </HDRGIO>
+      <SRCGIO>
+        <PATH>source\gio.c</PATH>
+      </SRCGIO>
+    </FILENAMES>
+  </GIO>
+  <SCI>
+    <FILENAMES>
+      <HDRSCI_R>
+        <PATH>include\reg_sci.h</PATH>
+      </HDRSCI_R>
+      <HDRSCI>
+        <PATH>include\sci.h</PATH>
+      </HDRSCI>
+      <SRCSCI>
+        <PATH>source\sci.c</PATH>
+      </SRCSCI>
+    </FILENAMES>
+  </SCI>
+  <LIN>
+    <FILENAMES>
+      <HDRLIN_R>
+        <PATH>include\reg_lin.h</PATH>
+      </HDRLIN_R>
+      <HDRLIN>
+        <PATH>include\lin.h</PATH>
+      </HDRLIN>
+      <SRCLIN>
+        <PATH/>
+      </SRCLIN>
+    </FILENAMES>
+  </LIN>
+  <MIBSPI>
+    <FILENAMES>
+      <HDRMIBSPI_R>
+        <PATH>include\reg_mibspi.h</PATH>
+      </HDRMIBSPI_R>
+      <HDRMIBSPI>
+        <PATH>include\mibspi.h</PATH>
+      </HDRMIBSPI>
+      <SRCMIBSPI>
+        <PATH/>
+      </SRCMIBSPI>
+    </FILENAMES>
+  </MIBSPI>
+  <SPI>
+    <FILENAMES>
+      <HDRSPI_R>
+        <PATH>include\reg_spi.h</PATH>
+      </HDRSPI_R>
+      <HDRSPI>
+        <PATH>include\spi.h</PATH>
+      </HDRSPI>
+      <SRCSPI>
+        <PATH/>
+      </SRCSPI>
+    </FILENAMES>
+  </SPI>
+  <CAN>
+    <FILENAMES>
+      <HDRCAN_R>
+        <PATH>include\reg_can.h</PATH>
+      </HDRCAN_R>
+      <HDRCAN>
+        <PATH>include\can.h</PATH>
+      </HDRCAN>
+      <SRCCAN>
+        <PATH/>
+      </SRCCAN>
+    </FILENAMES>
+  </CAN>
+  <ADC>
+    <FILENAMES>
+      <HDRADC_R>
+        <PATH>include\reg_adc.h</PATH>
+      </HDRADC_R>
+      <HDRADC>
+        <PATH>include\adc.h</PATH>
+      </HDRADC>
+      <SRCADC>
+        <PATH/>
+      </SRCADC>
+    </FILENAMES>
+  </ADC>
+  <HET>
+    <FILENAMES>
+      <STDHDRHET>
+        <PATH>include\std_nhet.h</PATH>
+      </STDHDRHET>
+      <HDRHET_R>
+        <PATH>include\reg_het.h</PATH>
+      </HDRHET_R>
+      <HDRHET>
+        <PATH>include\het.h</PATH>
+      </HDRHET>
+      <HDRHTU_R>
+        <PATH>include\reg_htu.h</PATH>
+      </HDRHTU_R>
+      <HDRHTU>
+        <PATH>include\htu.h</PATH>
+      </HDRHTU>
+      <SRCHET>
+        <PATH/>
+      </SRCHET>
+    </FILENAMES>
+  </HET>
+  <ESM>
+    <FILENAMES>
+      <HDRESM_R>
+        <PATH>include\reg_esm.h</PATH>
+      </HDRESM_R>
+      <HDRESM>
+        <PATH>include\esm.h</PATH>
+      </HDRESM>
+      <SRCESM>
+        <PATH>source\esm.c</PATH>
+      </SRCESM>
+    </FILENAMES>
+  </ESM>
+  <I2C>
+    <FILENAMES>
+      <HDRI2C_R>
+        <PATH>include\reg_i2c.h</PATH>
+      </HDRI2C_R>
+      <HDRI2C>
+        <PATH>include\i2c.h</PATH>
+      </HDRI2C>
+      <SRCI2C>
+        <PATH/>
+      </SRCI2C>
+    </FILENAMES>
+  </I2C>
+  <EMAC>
+    <FILENAMES>
+      <HDR1EMAC>
+        <PATH>include\emac.h</PATH>
+      </HDR1EMAC>
+      <HDR2EMAC>
+        <PATH>include\hw_emac.h</PATH>
+      </HDR2EMAC>
+      <HDR3EMAC>
+        <PATH>include\hw_emac_ctrl.h</PATH>
+      </HDR3EMAC>
+      <HDR4EMAC>
+        <PATH>include\hw_mdio.h</PATH>
+      </HDR4EMAC>
+      <HDR5EMAC>
+        <PATH>include\hw_reg_access.h</PATH>
+      </HDR5EMAC>
+      <HDR6EMAC>
+        <PATH>include\mdio.h</PATH>
+      </HDR6EMAC>
+      <SRC1EMAC>
+        <PATH/>
+      </SRC1EMAC>
+      <SRC2EMAC>
+        <PATH/>
+      </SRC2EMAC>
+    </FILENAMES>
+  </EMAC>
+  <DCC>
+    <FILENAMES>
+      <HDRDCC_R>
+        <PATH>include\reg_dcc.h</PATH>
+      </HDRDCC_R>
+      <HDRDCC>
+        <PATH>include\dcc.h</PATH>
+      </HDRDCC>
+      <SRCDCC>
+        <PATH/>
+      </SRCDCC>
+    </FILENAMES>
+  </DCC>
+  <RTP>
+    <FILENAMES>
+      <HDRRTP_R>
+        <PATH>include\reg_rtp.h</PATH>
+      </HDRRTP_R>
+      <HDRRTP>
+        <PATH>include\rtp.h</PATH>
+      </HDRRTP>
+      <SRCRTP>
+        <PATH/>
+      </SRCRTP>
+    </FILENAMES>
+  </RTP>
+  <DMM>
+    <FILENAMES>
+      <HDRDMM_R>
+        <PATH>include\reg_dmm.h</PATH>
+      </HDRDMM_R>
+      <HDRDMM>
+        <PATH>include\dmm.h</PATH>
+      </HDRDMM>
+      <SRCDMM>
+        <PATH/>
+      </SRCDMM>
+    </FILENAMES>
+  </DMM>
+  <EMIF>
+    <FILENAMES>
+      <HDREMIF_R>
+        <PATH>include\reg_emif.h</PATH>
+      </HDREMIF_R>
+      <HDREMIF>
+        <PATH>include\emif.h</PATH>
+      </HDREMIF>
+      <SRCEMIF>
+        <PATH/>
+      </SRCEMIF>
+    </FILENAMES>
+  </EMIF>
+  <POM>
+    <FILENAMES>
+      <HDRPOM_R>
+        <PATH>include\reg_pom.h</PATH>
+      </HDRPOM_R>
+      <HDRPOM>
+        <PATH>include\pom.h</PATH>
+      </HDRPOM>
+      <SRCPOM>
+        <PATH/>
+      </SRCPOM>
+    </FILENAMES>
+  </POM>
+  <USB>
+    <FILENAMES>
+      <HDR1USB>
+        <PATH>include\usbcdc.h</PATH>
+      </HDR1USB>
+      <HDR2USB>
+        <PATH>include\usb_serial_structs.h</PATH>
+      </HDR2USB>
+      <HDR3USB>
+        <PATH>include\usbdcdc.h</PATH>
+      </HDR3USB>
+      <HDR4USB>
+        <PATH>include\usbdevice.h</PATH>
+      </HDR4USB>
+      <HDR5USB>
+        <PATH>include\usbdevicepriv.h</PATH>
+      </HDR5USB>
+      <HDR6USB>
+        <PATH>include\usb-ids.h</PATH>
+      </HDR6USB>
+      <HDR7USB>
+        <PATH>include\usblib.h</PATH>
+      </HDR7USB>
+      <HDR8USB>
+        <PATH>include\usb.h</PATH>
+      </HDR8USB>
+      <HDR9USB>
+        <PATH>include\hw_usb.h</PATH>
+      </HDR9USB>
+      <SRC1USB>
+        <PATH/>
+      </SRC1USB>
+      <SRC2USB>
+        <PATH/>
+      </SRC2USB>
+      <SRC3USB>
+        <PATH/>
+      </SRC3USB>
+      <SRC5USB>
+        <PATH/>
+      </SRC5USB>
+      <SRC6USB>
+        <PATH/>
+      </SRC6USB>
+      <SRC7USB>
+        <PATH/>
+      </SRC7USB>
+      <SRC8USB>
+        <PATH/>
+      </SRC8USB>
+      <SRC9USB>
+        <PATH/>
+      </SRC9USB>
+      <SRC10USB>
+        <PATH/>
+      </SRC10USB>
+    </FILENAMES>
+  </USB>
+  <CRC>
+    <FILENAMES>
+      <HDRCRC_R>
+        <PATH>include\reg_crc.h</PATH>
+      </HDRCRC_R>
+      <HDRCRC>
+        <PATH>include\crc.h</PATH>
+      </HDRCRC>
+      <SRCCRC>
+        <PATH/>
+      </SRCCRC>
+    </FILENAMES>
+  </CRC>
+</SETTINGS>
diff --git a/bsp/rm48x50/HALCoGen/HALCoGen_bak.dil b/bsp/rm48x50/HALCoGen/HALCoGen_bak.dil
new file mode 100644
index 0000000000000000000000000000000000000000..b4fe67692af1bbcbb162c9762b966eaa20f69ffc
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/HALCoGen_bak.dil
@@ -0,0 +1,8718 @@
+# RM48L950ZWT 05/24/13 22:29:58
+# 
+ARCH=RM48L950ZWT
+# 
+DRIVER.TOOLS.VAR.ARM.VALUE=0
+DRIVER.TOOLS.VAR.IAR.VALUE=0
+DRIVER.TOOLS.VAR.GHS.VALUE=0
+DRIVER.TOOLS.VAR.TI.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_NAME.VALUE=het2LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_NAME.VALUE=adc2Group2Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_NAME.VALUE=spi4HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_MAPPING.VALUE=2
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.EQEP2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MEMINIT_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_DATA_3_WAIT_STATE_FREQ.VALUE=200.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_MAPPING.VALUE=96
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_MAPPING.VALUE=88
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0xFCFFFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SPI3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_BYPASS_ON_SLIP.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=256_KB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=200.000
+DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=200.00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_MAPPING.VALUE=65
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_MAPPING.VALUE=57
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_MAPPING.VALUE=49
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_NAME.VALUE=het1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CCM_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.CLKT_PLL2_OUTPUT_DIV.VALUE=2
+DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x63FFFFFF
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_DP_PBISTCHECK_ENA.VALUE=0x00040000
+DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_MAPPING.VALUE=50
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_MAPPING.VALUE=42
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_MAPPING.VALUE=34
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_MAPPING.VALUE=26
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18
+DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=IRQ_Handler
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0600
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_MAPPING.VALUE=11
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.LBIST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x003FFFFF
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=100.0
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08001200
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_NAME.VALUE=dcc1DoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_NAME.VALUE=sciLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_NAME.VALUE=i2cInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_GLOBAL_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0xFF000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_DP_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=rtiCompare0Interrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER0_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENTRY.VALUE=_c_int00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x0A
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_MAPPING.VALUE=102
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_LENGTH.VALUE=0x3FFFF
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=64_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=spi2HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x203FFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE_VALUE.VALUE=0x0000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_MAPPING.VALUE=95
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_MAPPING.VALUE=87
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_MAPPING.VALUE=79
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_DP_PBISTCHECK_ENA.VALUE=0x00000040
+DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.USB_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SCI_ALL_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0
+DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=24
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16
+DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=200.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x1000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_MAPPING.VALUE=64
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_MAPPING.VALUE=56
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_MAPPING.VALUE=48
+DRIVER.SYSTEM.VAR.CLKT_PLL1_REF_CLOCK_DIV.VALUE=6
+DRIVER.SYSTEM.VAR.FLASHW_BASE_ADDRESS.VALUE=0xFFF87000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_FIQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]"
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001
+DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_FREQ.VALUE=16.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_NAME.VALUE=dcc2DoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_MAPPING.VALUE=41
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_MAPPING.VALUE=33
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_MAPPING.VALUE=25
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=rtiCompare1Interrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=2
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CLKT_PLL2_FM_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0x08400000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_CPUSELFTEST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.HET1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI1_PRE_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.FLASH_MODE_VALUE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE_VALUE.VALUE=0x19
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_MAPPING.VALUE=10
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE.VALUE=128_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_DP_PBISTCHECK_ENA.VALUE=0x00001000
+DRIVER.SYSTEM.VAR.ECAP4_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_MAPPING.VALUE=124
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_MAPPING.VALUE=116
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_MAPPING.VALUE=108
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_NAME.VALUE=adc2Group0Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_NAME.VALUE=can2LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_NAME.VALUE=mibspi1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3
+DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_SP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_MAPPING.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_DIV.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_PLL2_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.RAM_BASE_ADDRESS.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.CORE_PMU_EVENT_EXPORT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x17
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_MAPPING.VALUE=94
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_MAPPING.VALUE=86
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_MAPPING.VALUE=78
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE.VALUE=STRONGLYORDERED_SHAREABLE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08001300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD3_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EFUSE_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_GHV_WAKUP_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE_VALUE.VALUE=0x0000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_MAPPING.VALUE=71
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_MAPPING.VALUE=63
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_MAPPING.VALUE=55
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_MAPPING.VALUE=47
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_MAPPING.VALUE=39
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_NAME.VALUE=rtiCompare2Interrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08001500
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE.VALUE=8_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=120.0
+DRIVER.SYSTEM.VAR.RAM_STACK_BASE.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_NAME.VALUE=adc2Group1Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_MAPPING.VALUE=40
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_NAME.VALUE=can2HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_MAPPING.VALUE=32
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_NAME.VALUE=linLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_MAPPING.VALUE=24
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_NAME.VALUE=crcInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xF07FFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_2.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_3.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_4.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_5.VALUE=1
+DRIVER.SYSTEM.VAR.LBIST_STT.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_6.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_7.VALUE=1
+DRIVER.SYSTEM.VAR.ECAP2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_8.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_MAPPING.VALUE=123
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_MAPPING.VALUE=115
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_MAPPING.VALUE=107
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00001000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0x0843FFFF
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_SP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x11
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x08001000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=STRONGLYORDERED_SHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_DP_PBISTCHECK_ENA.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=12.500
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=rtiCompare3Interrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00001500
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC
+DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0xFFFFFFFF
+DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=PLL2_ODCLK_8
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=100.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_MAPPING.VALUE=69
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ2.VALUE=100.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE.VALUE=16_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_BASE_ADDRESS.VALUE=0xFC000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_2_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=150
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_NAME.VALUE=adc1Group2Interrupt
+DRIVER.SYSTEM.VAR.CLKT_OSC_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE.VALUE=16_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_MAPPING.VALUE=70
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_MAPPING.VALUE=62
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_MAPPING.VALUE=54
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_MAPPING.VALUE=46
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_MAPPING.VALUE=38
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_SOURCE_ENABLE.VALUE=0x00000080
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_DP_PBISTCHECK_ENA.VALUE=0x00080000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0003eaff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x080017FF
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_MAPPING.VALUE=31
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_MAPPING.VALUE=23
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_MAPPING.VALUE=15
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_5_6.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=150
+DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENTRY.VALUE=_prefetch
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_FREQ.VALUE=100.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_BASE_ADDRESS.VALUE=0x60000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_AUTO_CLK_WAKE_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_7_8.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_0.VALUE=0x00000020
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_1.VALUE=0x00180000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE_VALUE.VALUE=0x08
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_MAPPING.VALUE=122
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_MAPPING.VALUE=114
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_MAPPING.VALUE=106
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_NAME.VALUE=rtiOverflow0Interrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER2_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.FLASH_DATA_WAIT_STATES.VALUE=3
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=150.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5
+DRIVER.SYSTEM.VAR.VIM_PARITY_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE
+DRIVER.SYSTEM.VAR.VIM_CHANNELS.VALUE=96
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_7.VALUE=0xF0200000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE.VALUE=512_BYTES
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD1_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_DP_PBISTCHECK_ENA.VALUE=0x00000010
+DRIVER.SYSTEM.VAR.ESM_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_MAPPING.VALUE=99
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_NAME.VALUE=mibspi5HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_NAME.VALUE=can3HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_NAME.VALUE=mibspi3HighInterruptLevel
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_NAME.VALUE=can1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=2_KB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.EQEP1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_FREQ.VALUE=10.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE_VALUE.VALUE=0x11
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]"
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_MAPPING.VALUE=92
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_MAPPING.VALUE=84
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_MAPPING.VALUE=76
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_MAPPING.VALUE=68
+DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_DP_PBISTCHECK_ENA.VALUE=0x00020000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SYSTEM_INIT.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_NAME.VALUE=esmLowInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_NAME.VALUE=mibspi1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION.VALUE=PRIV_NA_USER_NA_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_TYPE.VALUE=FIQ
+DRIVER.SYSTEM.VAR.DMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION_VALUE.VALUE=0x1100
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION_VALUE.VALUE=0x1200
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_MAPPING.VALUE=61
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_MAPPING.VALUE=53
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_MAPPING.VALUE=45
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_MAPPING.VALUE=37
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00300000
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=50.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_MAPPING.VALUE=30
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_MAPPING.VALUE=22
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_MAPPING.VALUE=14
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_NAME.VALUE=rtiOverflow1Interrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_2.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_ESRAM_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=100.0
+DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0xFE0001FF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00002000
+DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_NAME.VALUE=spi4LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_NAME.VALUE=mibspi3LowLevelInterrupt
+DRIVER.SYSTEM.VAR.FEE_FLASH_ECC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE.VALUE=4_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE_AVAIL.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATE_AVAIL.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87FFFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_GB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE_VALUE.VALUE=0x17
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_MAPPING.VALUE=98
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_NAME.VALUE=linHighLevelInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_FUN.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_BASE_ADDRESS.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000800
+DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08001400
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08001000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.PMM_PMCTRL_PWRDN.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_MAPPING.VALUE=83
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_MAPPING.VALUE=75
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_MAPPING.VALUE=67
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_MAPPING.VALUE=59
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_2.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803FFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD5_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_DP_PBISTCHECK_ENA.VALUE=0x00000008
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_4.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_5.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE_VALUE.VALUE=0x15
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_NAME.VALUE=rtiTimebaseInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PRESCALER.VALUE=8
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_6.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0xFE000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=100.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_MAPPING.VALUE=36
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_MAPPING.VALUE=28
+DRIVER.SYSTEM.VAR.CLKT_PLL1_BAND_WIDTH_ADJUSTMENT.VALUE=7
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CLKT_RTI1_POST_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_NAME.VALUE=het2HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_NAME.VALUE=can3LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_DP_PBISTCHECK_ENA.VALUE=0x00000400
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_DP_PBISTCHECK_ENA.VALUE=0x00000080
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_MAPPING.VALUE=13
+DRIVER.SYSTEM.VAR.CLKT_PLL2_REF_CLOCK_DIV.VALUE=6
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_RATE.VALUE=255
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_SLIP.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_MAPPING.VALUE=127
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_MAPPING.VALUE=119
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION.VALUE=PRIV_RW_USER_NA_NOEXEC
+DRIVER.SYSTEM.VAR.CLKT_PLL1_FM_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE.VALUE=4_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.ECAP3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_NAME.VALUE=spi2LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_NAME.VALUE=adc1Group0Interrupt
+DRIVER.SYSTEM.VAR.CLKT_LPOLO_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PSL.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0xFFFFFFFF
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=_svc
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FLASHECC_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_MAPPING.VALUE=3
+DRIVER.SYSTEM.VAR.CLKT_LPOHI_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RTP_DP_PBISTCHECK_ENA.VALUE=0x00004000
+DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIV_FREQ.VALUE=100.000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_MAPPING.VALUE=97
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_MAPPING.VALUE=89
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_NAME.VALUE=gioHighLevelInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL1_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.FLASH_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_ENA.VALUE=0x08300020
+DRIVER.SYSTEM.VAR.SPI5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x0017FFE0
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00180000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_MAPPING.VALUE=90
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_MAPPING.VALUE=82
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_MAPPING.VALUE=74
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_MAPPING.VALUE=66
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_NAME.VALUE=sciHighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_MAPPING.VALUE=58
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_NAME.VALUE=mibspi5LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08001100
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.FEE_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_10.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM_VALUE.VALUE=8
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_MAPPING.VALUE=51
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_MAPPING.VALUE=43
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_MAPPING.VALUE=35
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_MAPPING.VALUE=27
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_MAPPING.VALUE=19
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_11.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_12.VALUE=1
+DRIVER.SYSTEM.VAR.CCM_MENU.VALUE=NONE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=256_KB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_13.VALUE=1
+DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_14.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=200.00
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x1F
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_DP_PBISTCHECK_ENA.VALUE=0x00000004
+DRIVER.SYSTEM.VAR.ETPWM6_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_ENDIAN_LITTLE.VALUE=1
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+DRIVER.GIO.VAR.GIO_PORT0_BIT4_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_BASE_PORTA.VALUE=0xFFF7BC34
+DRIVER.GIO.VAR.GIO_BASE_PORTB.VALUE=0xFFF7BC54
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_BASE.VALUE=0xFFF7BC00
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORTB_ENABLE.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_PDR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_LVL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_ENA.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_POL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PSL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_TIMMINGMODE.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DIR.VALUE=0
+DRIVER.SCI.VAR.SCI_TIMMINGMODE.VALUE=1
+DRIVER.SCI.VAR.SCILIN_WAKEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PULL.VALUE=2
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DIR.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT0_DIR.VALUE=0
+DRIVER.SCI.VAR.SCI_ACTUALBAUDRATE.VALUE=115741
+DRIVER.SCI.VAR.SCI_EVENPARITY.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_FUN.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DIR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_RXINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_DIR.VALUE=0
+DRIVER.SCI.VAR.SCI_BASE_PORT.VALUE=0xFFF7E540
+DRIVER.SCI.VAR.SCILIN_PRESCALE.VALUE=53
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PDR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_FUN.VALUE=1
+DRIVER.SCI.VAR.SCI_PORT_BIT0_FUN.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_DIR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PDR.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PDR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_FUN.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_FUN.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PSL.VALUE=1
+DRIVER.SCI.VAR.SCI_OEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PDR.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PDR.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_FUN.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PSL.VALUE=1
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PSL.VALUE=1
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PDR.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PSL.VALUE=1
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PSL.VALUE=1
+DRIVER.SCI.VAR.SCILIN_BREAKINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_WAKEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_BREAKINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PSL.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_FEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_OEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_TXINTENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PARITYENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT0_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_BAUDRATE.VALUE=115200
+DRIVER.SCI.VAR.SCILIN_BREAKINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_WAKEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_BREAKINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCI_STOPBITS.VALUE=1
+DRIVER.SCI.VAR.SCI_RXINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_FEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_EVENPARITY.VALUE=0
+DRIVER.SCI.VAR.SCI_TXINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_OEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT1_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCI_PEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_CLKMODE.VALUE=1
+DRIVER.SCI.VAR.SCI_PARITYENA.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PULL.VALUE=2
+DRIVER.SCI.VAR.SCI_PORT_BIT2_DOUT.VALUE=0
+DRIVER.SCI.VAR.SCILIN_BASE.VALUE=0xFFF7E400
+DRIVER.SCI.VAR.SCI_RXINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_FEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_PRESCALE.VALUE=53
+DRIVER.SCI.VAR.SCILIN_OEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_TXINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULL.VALUE=2
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PULL.VALUE=2
+DRIVER.SCI.VAR.SCI_PEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_WAKEINTENA.VALUE=0
+DRIVER.SCI.VAR.SCI_LENGTH.VALUE=8
+DRIVER.SCI.VAR.SCILIN_CLKMODE.VALUE=1
+DRIVER.SCI.VAR.SCILIN_BASE_PORT.VALUE=0xFFF7E440
+DRIVER.SCI.VAR.SCILIN_BAUDRATE.VALUE=115200
+DRIVER.SCI.VAR.SCILIN_STOPBITS.VALUE=1
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULL.VALUE=2
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PULL.VALUE=2
+DRIVER.SCI.VAR.SCILIN_RXINTENA.VALUE=1
+DRIVER.SCI.VAR.SCILIN_LENGTH.VALUE=8
+DRIVER.SCI.VAR.SCILIN_FEINTLVL.VALUE=0
+DRIVER.SCI.VAR.SCILIN_ACTUALBAUDRATE.VALUE=115741
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SCI.VAR.SCI_BASE.VALUE=0xFFF7E500
+DRIVER.SCI.VAR.SCILIN_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_CLKMOD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE.VALUE=0xFFF7FC00
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE_RAM.VALUE=0xFF0A0000
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE_PORT.VALUE=0xFFF7F418
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE.VALUE=0xFFF7F400
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ENABLE.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE.VALUE=0xFFF7F800
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=99
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.SPI.VAR.SPI3_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI2_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI1_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI1_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI1_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618
+DRIVER.SPI.VAR.SPI5_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI4_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI3_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI1_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI1_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI4_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI4_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI1_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI1_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI1_BASE.VALUE=0xFFF7F400
+DRIVER.SPI.VAR.SPI3_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI5_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI4_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI5_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI1_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_BASE_PORT.VALUE=0xFFF7FC18
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_BASE.VALUE=0xFFF7F600
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI3_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI5_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI3_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI5_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_BASE.VALUE=0xFFF7F800
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI3_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI3_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI3_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_BASE_PORT.VALUE=0xFFF7F818
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI2_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_BASE_RAM.VALUE=0xFF0C0000
+DRIVER.SPI.VAR.SPI3_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI3_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI1_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI1_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00
+DRIVER.SPI.VAR.SPI3_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI3_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI3_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI2_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI3_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI1_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_BASE_PORT.VALUE=0xFFF7F418
+DRIVER.SPI.VAR.SPI5_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_BASE.VALUE=0xFFF7FC00
+DRIVER.SPI.VAR.SPI2_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI2_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI5_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI5_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI2_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI1_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI1_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=10.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI4_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI2_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI2_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI2_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=20.000
+DRIVER.SPI.VAR.SPI3_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI1_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=99
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=99
+DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=99
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=99
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_BASE_PORT.VALUE=0xFFF7FA18
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_BASE_RAM.VALUE=0xFF0A0000
+DRIVER.SPI.VAR.SPI5_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI2_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI5_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI4_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI3_PHASE1.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=500
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ID.VALUE=9
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_RAMBASE.VALUE=0xFF1C0000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_RATE.VALUE=500.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_RATE.VALUE=500.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=75.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ID.VALUE=3
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_BASE.VALUE=0xFFF7DE00
+DRIVER.CAN.VAR.CAN_1_RAMBASE.VALUE=0xFF1E0000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ID.VALUE=4
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=500.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ID.VALUE=6
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7
+DRIVER.CAN.VAR.CAN_3_BASE.VALUE=0xFFF7E000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ID.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=10
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ID.VALUE=9
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=11
+DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=12
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_BAUDRATE.VALUE=500
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=75.000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_BRP.VALUE=24
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ID.VALUE=10
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=2
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=3
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_BRP.VALUE=24
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ID.VALUE=12
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=4
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=5
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_BRP.VALUE=24
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=6
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=7
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=9
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_SJW.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_BAUDRATE.VALUE=500
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_2_SJW.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_1_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SJW.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=75.000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ID.VALUE=3
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_RAMBASE.VALUE=0xFF1A0000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ID.VALUE=4
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ID.VALUE=10
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ID.VALUE=5
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ID.VALUE=11
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ID.VALUE=6
+DRIVER.CAN.VAR.CAN_3_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_PARITY_ENABLE.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_ALT_TRIG.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_GROUP2_LENGTH.VALUE=32
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_BND.VALUE=2
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_BND.VALUE=2
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC2_GROUP1_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_LENGTH.VALUE=64
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000
+DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8
+DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_BND.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_ALT_TRIG_COMP.VALUE=1
+DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000
+DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000
+DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32
+DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=9
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN16_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1
+DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=9
+DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_TIME.VALUE=200.00
+DRIVER.ADC.VAR.ADC2_GROUP1_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.LIN.VAR.LIN_PORT_BIT0_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_PEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOAWUSINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOA3WUSINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_MAXPRESCALE.VALUE=4507
+DRIVER.LIN.VAR.LIN_LENGTH.VALUE=8
+DRIVER.LIN.VAR.LIN_PARITYENA.VALUE=0
+DRIVER.LIN.VAR.LIN_BREAKINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TX_MASK.VALUE=0xFF
+DRIVER.LIN.VAR.LIN_MSTMOD.VALUE=1
+DRIVER.LIN.VAR.LIN_SDEL.VALUE=1
+DRIVER.LIN.VAR.LIN_PORT_BIT2_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_TOAWUSINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_WAKEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_HGENCTRL.VALUE=1
+DRIVER.LIN.VAR.LIN_TOA3WUSINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PULL.VALUE=2
+DRIVER.LIN.VAR.LIN_CEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BREAKINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PBEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT0_FUN.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT2_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PULL.VALUE=2
+DRIVER.LIN.VAR.LIN_WAKEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_OEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_FUN.VALUE=2
+DRIVER.LIN.VAR.LIN_NREINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT2_FUN.VALUE=4
+DRIVER.LIN.VAR.LIN_CEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PSL.VALUE=1
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PULL.VALUE=2
+DRIVER.LIN.VAR.LIN_PBEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_BASE_PORT.VALUE=0xFFF7E440
+DRIVER.LIN.VAR.LIN_ACTUALBAUDRATE.VALUE=19.968
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PSL.VALUE=2
+DRIVER.LIN.VAR.LIN_ISFEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_FEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PSL.VALUE=4
+DRIVER.LIN.VAR.LIN_OEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TXINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_NREINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_IDINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_SBREAK.VALUE=13
+DRIVER.LIN.VAR.LIN_TOINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BAUDRATE.VALUE=20.000
+DRIVER.LIN.VAR.LIN_RX_MASK.VALUE=0xFF
+DRIVER.LIN.VAR.LIN_ISFEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_RXINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BASE.VALUE=0xFFF7E400
+DRIVER.LIN.VAR.LIN_FEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TXINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.LIN.VAR.LIN_IDINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_MAXBAUDRATE.VALUE=22.188
+DRIVER.LIN.VAR.LIN_BEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_RXINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PRESCALE.VALUE=312
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_HRSHARE.VALUE=0x00000008
+DRIVER.HET.VAR.HET2_INT_X1.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT29_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_PWM1_PIN_SELECT.VALUE=10
+DRIVER.HET.VAR.HET2_BIT12_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT3_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X2.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X3.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_INT_X4.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_PWM0_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT4_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM3_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT4_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X5.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT30_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT26_HRSHARE.VALUE=0x00002000
+DRIVER.HET.VAR.HET1_BIT22_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT18_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT3_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X6.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=9
+DRIVER.HET.VAR.HET1_BIT28_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT7_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X7.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT7_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X8.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT18_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT10_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X9.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM4_PIN_SELECT.VALUE=16
+DRIVER.HET.VAR.HET2_PWM4_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET1_RAM_BASE.VALUE=0xFF460000
+DRIVER.HET.VAR.HET2_EDGE6_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_PWM2_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE2_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_BIT11_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT24_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT16_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT19_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE6_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT24_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT16_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT2_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE5_PIN_SELECT.VALUE=21
+DRIVER.HET.VAR.HET2_BIT13_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT27_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT19_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_CAP5_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_PWM4_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT8_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_CAP2_PIN_SELECT.VALUE=4
+DRIVER.HET.VAR.HET2_BIT4_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT29_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT8_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_BIT1_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM7_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_BIT18_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_BIT16_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_BIT0_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT6_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP5_PIN_SELECT.VALUE=26
+DRIVER.HET.VAR.HET1_BIT28_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE7_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT1_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE5_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_PWM5_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_BIT3_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE7_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE1_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE4_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_BIT5_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_EDGE5_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_BIT8_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_LR_ACTUALTIME.VALUE=1280.000
+DRIVER.HET.VAR.HET1_PWM5_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM4_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET2_BIT9_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT5_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_PIN_SELECT.VALUE=18
+DRIVER.HET.VAR.HET2_BIT13_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE7_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_BIT17_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT30_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT19_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_BIT7_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE5_PIN_SELECT.VALUE=21
+DRIVER.HET.VAR.HET1_BIT29_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET_DIS_BLACKBOX.VALUE=0
+DRIVER.HET.VAR.HET2_PWM7_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_HR_ACTUALFREQUENCY.VALUE=100.000
+DRIVER.HET.VAR.HET2_PWM5_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_BIT25_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT17_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT4_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE0_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_CAP6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT20_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X10.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X11.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X20.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X12.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_PWM6_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT16_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X21.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X13.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_HR_PRESCALE.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_LR_PRESCALE.VALUE=7
+DRIVER.HET.VAR.HET2_PWM0_PIN_SELECT.VALUE=8
+DRIVER.HET.VAR.HET2_BIT6_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X30.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X22.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X14.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X31.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X23.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X15.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_INT_X24.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X16.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BASE_PORT.VALUE=0xFFF7B84C
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X25.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X17.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_PWM3_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X26.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X18.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X27.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X19.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT18_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X28.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET2_PWM0_DUTY.VALUE=50
+DRIVER.HET.VAR.HET2_BIT18_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X29.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_CAP7_PIN_SELECT.VALUE=6
+DRIVER.HET.VAR.HET2_BIT8_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_PWM4_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_PWM3_PIN_SELECT.VALUE=14
+DRIVER.HET.VAR.HET1_BIT11_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_BIT2_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE6_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT5_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_BIT14_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT20_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT16_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_DOUT.VALUE=0
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+DRIVER.HET.VAR.HET1_BIT6_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM7_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_PWM0_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT8_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE4_PIN_SELECT.VALUE=20
+DRIVER.HET.VAR.HET2_BIT7_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT9_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ACTION.VALUE=3
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+DRIVER.HET.VAR.HET1_EDGE6_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP1_PIN_SELECT.VALUE=2
+DRIVER.HET.VAR.HET2_BIT15_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT13_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE3_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_PWM6_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT9_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE0_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_BIT26_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT18_PULL.VALUE=1
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+DRIVER.HET.VAR.HET2_BIT16_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP4_PIN_SELECT.VALUE=24
+DRIVER.HET.VAR.HET1_BIT29_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT0_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM2_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET2_EDGE3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_HRSHARE.VALUE=0x00000002
+DRIVER.HET.VAR.HET2_PWM6_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_BIT8_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_BIT4_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_HRSHARE.VALUE=0x00000004
+DRIVER.HET.VAR.HET1_BIT25_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT17_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_PWM1_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM1_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM7_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_PWM3_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT24_HRSHARE.VALUE=0x00001000
+DRIVER.HET.VAR.HET1_BIT16_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_PIN_SELECT.VALUE=17
+DRIVER.HET.VAR.HET1_BIT20_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT12_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X10.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X11.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT3_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE0_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT7_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X20.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X12.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT10_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X21.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X13.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT18_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE4_PIN_SELECT.VALUE=20
+DRIVER.HET.VAR.HET1_INT_X30.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X22.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X14.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET1_INT_X31.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X23.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X15.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE5_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_PWM1_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_BIT7_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_INT_X24.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X16.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP2_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X25.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X17.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT9_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT5_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X26.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X18.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X27.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X19.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_INT_X28.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM2_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_RAM_SIZE.VALUE=160
+DRIVER.HET.VAR.HET1_EDGE2_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_INT_X29.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM3_PERIOD.VALUE=1000.000
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+DRIVER.HET.VAR.HET1_BIT10_DIR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT8_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_PWM0_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_BIT4_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_EDGE1_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT19_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT8_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP6_PIN_SELECT.VALUE=4
+DRIVER.HET.VAR.HET1_PWM2_PIN_SELECT.VALUE=12
+DRIVER.HET.VAR.HET1_BIT1_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM3_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM2_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_EDGE4_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE0_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_PWM5_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT8_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT4_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE3_PIN_SELECT.VALUE=15
+DRIVER.HET.VAR.HET2_PWM2_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT18_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT11_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_EDGE1_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM7_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM2_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM5_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT8_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP0_PIN_SELECT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT21_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT13_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT5_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_BIT4_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE2_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_BIT9_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT1_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM4_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_BIT7_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM7_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_BIT8_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM2_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT31_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT23_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT15_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP3_PIN_SELECT.VALUE=6
+DRIVER.HET.VAR.HET1_BIT7_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_PWM4_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET2_BIT12_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_PWM0_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_CAP5_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT26_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT18_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_PRESCALER.VALUE=99968
+DRIVER.HET.VAR.HET1_EDGE4_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_BIT20_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE5_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT6_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE1_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_PWM3_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE3_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_CAP7_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM3_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_PWM4_PIN_SELECT.VALUE=16
+DRIVER.HET.VAR.HET1_BIT10_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_BIT9_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE3_PIN_SELECT.VALUE=15
+DRIVER.HET.VAR.HET1_PWM1_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT8_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BASE.VALUE=0xFFF7B800
+DRIVER.HET.VAR.HET2_EDGE1_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_BIT12_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_PIN_SELECT.VALUE=19
+DRIVER.HET.VAR.HET1_PWM5_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_LR_ACTUALTIME.VALUE=1280.000
+DRIVER.HET.VAR.HET1_BIT21_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT13_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT11_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM3_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM7_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_HR_PRESCALE.VALUE=0
+DRIVER.HET.VAR.HET1_BIT30_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT22_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT14_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT7_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_HR_ACTUALFREQUENCY.VALUE=100.000
+DRIVER.HET.VAR.HET2_PWM1_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT5_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE4_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP0_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_BIT4_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE2_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM2_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT8_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT11_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_EDGE6_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_PWM5_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT9_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_EDGE6_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT10_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP5_PIN_SELECT.VALUE=2
+DRIVER.HET.VAR.HET1_PWM1_PIN_SELECT.VALUE=10
+DRIVER.HET.VAR.HET1_BIT9_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT13_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_PWM7_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_PWM5_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT24_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT16_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.HET.VAR.HET2_BIT16_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT10_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM7_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE0_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT30_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X0.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE2_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_HRSHARE.VALUE=0x00000001
+DRIVER.HET.VAR.HET1_INT_X1.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE2_PIN_SELECT.VALUE=13
+DRIVER.HET.VAR.HET2_PWM2_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT8_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X2.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_DIS_BLACKBOX.VALUE=0
+DRIVER.HET.VAR.HET2_LR_TIME.VALUE=800.000
+DRIVER.HET.VAR.HET1_INT_X3.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_EDGE5_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_BIT29_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT0_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_INT_X4.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_HRSHARE.VALUE=0x00000002
+DRIVER.HET.VAR.HET1_BIT21_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT13_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X5.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_BIT20_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT3_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_INT_X6.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET1_INT_X7.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BASE_PORT.VALUE=0xFFF7B94C
+DRIVER.HET.VAR.HET1_INT_X8.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_BIT30_HRSHARE.VALUE=0x00008000
+DRIVER.HET.VAR.HET1_BIT22_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X9.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BASE.VALUE=0xFFF7B900
+DRIVER.HET.VAR.HET2_EDGE2_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE0_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_BIT10_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP2_PIN_SELECT.VALUE=4
+DRIVER.HET.VAR.HET1_BIT11_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM2_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_PWM0_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT31_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT23_DIR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT15_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM4_DUTY.VALUE=50
+DRIVER.HET.VAR.HET2_BIT18_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP1_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT30_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_PWM6_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT31_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT23_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT15_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT9_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE6_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT7_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE1_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_RAM_SIZE.VALUE=160
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+DRIVER.HET.VAR.HET1_BIT13_PDR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT0_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_DUTY_PRESCALER.VALUE=50176
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+DRIVER.HET.VAR.HET2_BIT0_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_PIN_SELECT.VALUE=14
+DRIVER.HET.VAR.HET2_PWM6_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT14_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE2_PIN_SELECT.VALUE=13
+DRIVER.HET.VAR.HET1_BIT20_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_HR_FREQUENCY.VALUE=100.000
+DRIVER.HET.VAR.HET2_PWM2_DUTY_PRESCALER.VALUE=50176
+DRIVER.HET.VAR.HET1_EDGE5_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE1_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_PWM5_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT24_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT16_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_BIT18_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE0_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_PIN_SELECT.VALUE=18
+DRIVER.HET.VAR.HET2_EDGE2_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT1_PULL.VALUE=1
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+DRIVER.HET.VAR.HET2_EDGE4_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_HRSHARE.VALUE=0x00000008
+DRIVER.HET.VAR.HET1_BIT30_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT4_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_BIT1_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM7_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT8_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT4_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE7_PIN_SELECT.VALUE=23
+DRIVER.HET.VAR.HET2_PWM7_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_PWM3_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET1_PWM3_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_EDGE3_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_PWM1_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_HRSHARE.VALUE=0x00004000
+DRIVER.HET.VAR.HET1_BIT26_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT18_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP4_PIN_SELECT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM0_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_PWM0_PIN_SELECT.VALUE=8
+DRIVER.HET.VAR.HET1_BIT21_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT13_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_LR_TIME.VALUE=800.000
+DRIVER.HET.VAR.HET2_EDGE0_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_BIT25_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT21_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT17_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT13_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM5_DUTY.VALUE=50
+DRIVER.HET.VAR.HET2_PWM1_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT20_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT11_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT24_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT16_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM5_DUTYTIME.VALUE=500.480
+DRIVER.HET.VAR.HET2_RAM_BASE.VALUE=0xFF440000
+DRIVER.HET.VAR.HET2_PWM3_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT7_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM4_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP4_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT8_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE1_PIN_SELECT.VALUE=11
+DRIVER.HET.VAR.HET1_CAP7_PIN_SELECT.VALUE=30
+DRIVER.HET.VAR.HET1_BIT31_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT23_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT15_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE7_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_BIT2_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE4_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_BIT15_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_BIT10_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM2_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_BIT18_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_BIT0_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT30_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_PSL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_PWM7_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE2_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT26_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT18_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT16_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.HET.VAR.HET1_PWM7_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_DUTY.VALUE=50
+DRIVER.HET.VAR.HET2_PWM0_ACTUALPERIOD.VALUE=1000.960
+DRIVER.HET.VAR.HET2_BIT1_DOUT.VALUE=0
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+DRIVER.DMM.VAR.DMM_PORT_BIT1_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT0_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT2_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT7_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT18_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT0_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_BASE.VALUE=0xFFFFF700
+DRIVER.DMM.VAR.DMM_PORT_BIT1_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT2_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT0_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT5_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT4_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT3_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_BASE_PORT.VALUE=0xFFFFF738
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT5_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT10_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT6_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT7_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT9_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT0_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT7_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT6_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT4_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT8_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT7_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT10_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT7_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT1_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT9_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT12_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT7_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT10_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT12_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT9_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT7_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT2_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT13_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT9_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT9_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT12_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT14_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT0_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT9_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT14_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT14_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT16_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT15_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT15_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT17_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT16_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT18_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT16_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT18_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT0_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT6_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_DIR.VALUE=0
+DRIVER.I2C.VAR.I2C_STOPBITS.VALUE=2
+DRIVER.I2C.VAR.I2C_PORT_BIT1_DIR.VALUE=0
+DRIVER.I2C.VAR.I2C_ICXRDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_BASE_PORT.VALUE=0xFFF7D44C
+DRIVER.I2C.VAR.I2C_DATACOUNT.VALUE=8
+DRIVER.I2C.VAR.I2C_ADDRMODE.VALUE=7BIT_AMODE
+DRIVER.I2C.VAR.I2C_PORT_BIT0_FUN.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PDR.VALUE=0
+DRIVER.I2C.VAR.I2C_BC_VALUE.VALUE=0x0003
+DRIVER.I2C.VAR.I2C_PORT_BIT1_FUN.VALUE=0
+DRIVER.I2C.VAR.I2C_RM_ENA.VALUE=0
+DRIVER.I2C.VAR.I2C_BC.VALUE=2_BIT
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PDR.VALUE=0
+DRIVER.I2C.VAR.I2C_TXRX_VALUE.VALUE=0
+DRIVER.I2C.VAR.I2C_SCDLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PSL.VALUE=1
+DRIVER.I2C.VAR.I2C_STPCND.VALUE=1
+DRIVER.I2C.VAR.I2C_ALINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PRESCALE.VALUE=12
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PSL.VALUE=1
+DRIVER.I2C.VAR.I2C_TXRX.VALUE=TRANSMITTER
+DRIVER.I2C.VAR.I2C_PORT_BIT0_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_ALINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_RXDMA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.I2C.VAR.I2C_BASE.VALUE=0xFFF7D400
+DRIVER.I2C.VAR.I2C_ARDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT1_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_TXDMA.VALUE=0
+DRIVER.I2C.VAR.I2C_MSMODE.VALUE=1
+DRIVER.I2C.VAR.I2C_ICCH.VALUE=33
+DRIVER.I2C.VAR.I2C_AASLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_ICCL.VALUE=33
+DRIVER.I2C.VAR.I2C_AAS.VALUE=0
+DRIVER.I2C.VAR.I2C_ADDRMODE_VALUE.VALUE=0x0001
+DRIVER.I2C.VAR.I2C_ICRRDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_FDF.VALUE=0
+DRIVER.I2C.VAR.I2C_ARDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_PARITYENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PULL.VALUE=2
+DRIVER.I2C.VAR.I2C_LENGTH.VALUE=8
+DRIVER.I2C.VAR.I2C_NACKINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_SCD.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PULL.VALUE=2
+DRIVER.I2C.VAR.I2C_ICRRDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_STACND.VALUE=1
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.I2C.VAR.I2C_ICXRDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_NACKINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_EVENPARITY.VALUE=0
+DRIVER.I2C.VAR.I2C_BAUDRATE.VALUE=100
+DRIVER.I2C.VAR.I2C_MODCLK.VALUE=8
+DRIVER.DCC.VAR.DCC1_ENABLE_KEY.VALUE=10
+DRIVER.DCC.VAR.PINMUX_BASE.VALUE=0xFFFFEA00
+DRIVER.DCC.VAR.DCC1_DETECTION_TIME.VALUE=2500.00
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_VALUE.VALUE=0x0002
+DRIVER.DCC.VAR.DCC1_ENABLE_ERROR_INTERRUPT.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40
+DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0
+DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0
+DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=2500.00
+DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002
+DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1
+DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0
+DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792
+DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00
+DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=200.00
+DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0
+DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5
+DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5
+DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400
+DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0x5
+DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=39204
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1
+DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0
+DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=495000
+DRIVER.PINMUX.VAR.DMA_EIDXS_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_2.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_3.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_4.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_4.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX50_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_5.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_5.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_6.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_6.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_7.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_7.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_8.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX99_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_96_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_88_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_5_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_9.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_57_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_49_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX30_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_18_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_10.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_4.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX10.VALUE="PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18"
+DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_11.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_CHPR_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX11.VALUE="PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24"
+DRIVER.PINMUX.VAR.DMA_PRITY_12.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX20.VALUE="PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11"
+DRIVER.PINMUX.VAR.PINMUX12.VALUE="PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA"
+DRIVER.PINMUX.VAR.DMA_PRITY_13.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX21.VALUE="PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9"
+DRIVER.PINMUX.VAR.PINMUX13.VALUE="PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0"
+DRIVER.PINMUX.VAR.DMA_PRITY_14.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX30.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX22.VALUE="PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11"
+DRIVER.PINMUX.VAR.PINMUX14.VALUE="PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1"
+DRIVER.PINMUX.VAR.MUX92_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_15.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX31.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX23.VALUE=PINMUX_BALL_C6_EMIF_ADDR_8
+DRIVER.PINMUX.VAR.PINMUX15.VALUE="PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18"
+DRIVER.PINMUX.VAR.DMA_PRITY_16.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX32.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX16.VALUE="PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13"
+DRIVER.PINMUX.VAR.PINMUX33.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08"
+DRIVER.PINMUX.VAR.PINMUX34.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX26.VALUE="PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3"
+DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0"
+DRIVER.PINMUX.VAR.DMA_ADDMR_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX35.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX27.VALUE="PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2"
+DRIVER.PINMUX.VAR.PINMUX19.VALUE="PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10"
+DRIVER.PINMUX.VAR.PINMUX28.VALUE="PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3"
+DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX29.VALUE=PINMUX_BALL_D3_SPI2NENA
+DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_10.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX98_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_11.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_PRITY_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX98_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_20.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_12.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX100_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX98_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_21.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_13.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX100_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_30.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_22.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_14.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_0.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX100_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_31.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_23.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_15.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_1.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX100_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_24.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_16.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_2.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX100_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX91_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_25.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_17.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_3.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX91_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_26.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_18.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_4.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX91_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_102_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_27.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_19.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_5.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMR_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX91_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_28.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_6.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX91_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_29.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_7.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_8.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_9.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_10.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_10.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_11.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX60_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_20.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_12.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_21.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_13.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_13.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_30.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_22.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_14.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_14.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_31.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_23.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_15.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_STADD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_24.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_16.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_25.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_17.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_26.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_18.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_4.VALUE=0
+DRIVER.PINMUX.VAR.MUX30_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_71_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_63_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_55_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_47_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_39_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_27.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_19.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX21_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_28.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_28.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_29.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_29.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_0.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_TTYPE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_1.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_2.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_3.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_4.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_5.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_6.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_7.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_8.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_9.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5.VALUE=8BIT
+DRIVER.PINMUX.VAR.GATE_EMIF_CLK.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMW_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX97_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX97_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_107_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX90_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_DEBUGMODE.VALUE=IGNORE_SUSPEND
+DRIVER.PINMUX.VAR.MUX90_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_0.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ERRACT.VALUE=IGNORE
+DRIVER.PINMUX.VAR.MUX90_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_100_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_1.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHPR_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX90_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_2.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_BASE_PORT.VALUE=0xFFFFF040
+DRIVER.PINMUX.VAR.MUX90_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_3.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.MUX58_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_4.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.MUX5_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_5.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX5_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_6.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_7.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_8.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_10.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_9.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.ALT_ADC_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.MUX98_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_92_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_84_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_76_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_68_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_1_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTEN_16.VALUE=1
+DRIVER.PINMUX.VAR.MUX20_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_61_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_53_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_45_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_37_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX20_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX100_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_30_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_22_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_14_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX10_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ENDADD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_4.VALUE=0
+DRIVER.PINMUX.VAR.ETHERNET_SELECT.VALUE=RMII
+DRIVER.PINMUX.VAR.MUX91_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_1.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_INTASS_2.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.CONCOUNT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTASS_3.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_INTASS_4.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_ADDMR_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ACC_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_10.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_4.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_11.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMW_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_INTMP_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX96_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_20.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_12.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_6.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_21.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_13.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_30.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_22.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_14.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_8.VALUE=0
+DRIVER.PINMUX.VAR.GIOB_DISABLE_SELECT.VALUE=OFF
+DRIVER.PINMUX.VAR.PIN_MUX_105_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_31.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_23.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMW_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_15.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMR_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_TRIG_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_24.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_16.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX81_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_25.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_17.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX81_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_26.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_18.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_27.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_19.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENABLE1.VALUE=1
+DRIVER.PINMUX.VAR.MUX81_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_28.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_29.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX4_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX4_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_97_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_89_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_1.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_2.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_3.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_4.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX103_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_90_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_82_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_74_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_66_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_58_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_5.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_PRITY_6.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_7.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_8.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX21_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_51_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_43_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_35_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_27_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_9.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.AD1.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.AD2.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_20_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_12_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX9_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX104_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.ALT_ADC.VALUE=0
+DRIVER.PINMUX.VAR.I2C.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX71_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_DEBUGMODE_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX95_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_10.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_103_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_13.VALUE=0
+DRIVER.PINMUX.VAR.HET1.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_10.VALUE=0
+DRIVER.PINMUX.VAR.HET2.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX80_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX80_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX56_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_10.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX3_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_11.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_AIM_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTASS_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX3_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_20.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_12.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_6.VALUE=1
+DRIVER.PINMUX.VAR.EMIF.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_21.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_13.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_7.VALUE=1
+DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_22.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_14.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_8.VALUE=1
+DRIVER.PINMUX.VAR.MUX41_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX40_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_95_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_87_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_79_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_4_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_31.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_23.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_15.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMR_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX41_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_24.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_16.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_25.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_17.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_13.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_26.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_18.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_80_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_72_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_64_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_56_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_48_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_27.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_19.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMW_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.GIOA.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_28.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12.VALUE=8BIT
+DRIVER.PINMUX.VAR.GIOB.VALUE=0
+DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_29.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13.VALUE=8BIT
+DRIVER.PINMUX.VAR.GIOB_DISABLE.VALUE=0
+DRIVER.PINMUX.VAR.MUX10_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX10_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18.VALUE=8BIT
+DRIVER.PINMUX.VAR.PIN_MUX_10_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_4.VALUE=1
+DRIVER.PINMUX.VAR.DMA_AIM_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_8.VALUE=1
+DRIVER.PINMUX.VAR.MUX90_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_9.VALUE=1
+DRIVER.PINMUX.VAR.MIBSPI1.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MIBSPI3.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.OHCI0.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MIBSPI5.VALUE=0
+DRIVER.PINMUX.VAR.DMM.VALUE=0
+DRIVER.PINMUX.VAR.W2FC.VALUE=0
+DRIVER.PINMUX.VAR.OHCI1.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_108_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX94_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_10.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_101_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_11.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_PRITY_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX9_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_12.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_13.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_10.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_14.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX51_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_11.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_15.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_20.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_12.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_16.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_21.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_13.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_30.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_22.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_14.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_10.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX2_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_31.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_23.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_15.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_11.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX2_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_24.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_16.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_12.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX40_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_25.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_17.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_13.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.ETM.VALUE=0
+DRIVER.PINMUX.VAR.MUX40_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_26.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_18.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_14.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_93_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_85_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_77_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_69_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_2_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_27.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_19.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_15.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_PRITY_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX40_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_28.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_TRIG_16.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_29.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX102_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_70_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_62_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_54_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_46_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_38_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ERRACT_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MII.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.GATE_EMIF_CLK_SELECT.VALUE=OFF
+DRIVER.PINMUX.VAR.MUX20_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_1.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_2.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_CHPR_3.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_INTMP_10.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_4.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX93_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_11.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_5.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_1.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTMP_12.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_6.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_2.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTMP_13.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_7.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_3.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTMP_14.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_8.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_4.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_CHANNEL_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_15.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_9.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_5.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.SCI.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_16.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_TRIG_6.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_7.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_8.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX8_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_9.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_1.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_2.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ENABLEPAR.VALUE=1
+DRIVER.PINMUX.VAR.MUX102_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_3.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX102_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_4.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX102_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_5.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_TRIG_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_1.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_6.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_2.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX102_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX93_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_7.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_3.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX93_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_8.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_4.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX93_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_106_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_9.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX93_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX93_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BASE.VALUE=0xFFFFF000
+DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX70_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_98_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_7_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_75_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_67_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_59_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX31_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_60_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_52_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_44_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_36_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_28_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_0.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_21_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_13_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BASE_RAM.VALUE=0xFFF80000
+DRIVER.PINMUX.VAR.DMA_EIDXS_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_2.VALUE=0
+DRIVER.PINMUX.VAR.RTP.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_2.VALUE=1
+DRIVER.PINMUX.VAR.SPI2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_4.VALUE=1
+DRIVER.PINMUX.VAR.SPI4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTASS_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.RMII.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_6.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2"
+DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_7.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21"
+DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_8.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5"
+DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_PRITY_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24"
+DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12.VALUE=8BIT
+DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03"
+DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT
+DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26"
+DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_0.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28"
+DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_1.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHPR_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX7.VALUE="PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30"
+DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_2.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31"
+DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_3.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3"
+DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_4.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX92_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_104_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_5.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX92_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_6.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX92_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_7.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX7_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_8.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_0.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_9.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_1.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_1.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION3.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_PSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_CPB_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_PSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_TRDIR_1.VALUE=HET_TO_MAIN_MEM
+DRIVER.CRC.VAR.CRC_CH1_CCI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPBL_7_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DEBMOD_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_CFI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPAL_1_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ENABUS_1.VALUE=0
+DRIVER.CRC.VAR.HTU_CPA_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_WDTO.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_CCI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP1_ACC_1.VALUE=READ_ONLY
+DRIVER.CRC.VAR.HTU_CONTPAR_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_CFI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPB_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DCP0_EC_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_CPBFULADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPAL_6_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_DTE.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_FC_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_CVH.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PSSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_BASE.VALUE=0xFFF7A400
+DRIVER.CRC.VAR.CRC_CH1_CVL.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PSSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_3_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_DTE.VALUE=1
+DRIVER.CRC.VAR.CRC_CH2_CVH.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_CVL.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPA_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_SCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_DCP0_CPAFULADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPAL_2_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH2_PCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CPA_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_PSA.VALUE=1
+DRIVER.CRC.VAR.CRC_CH1_ORI.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_SCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP1_STADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_TOE.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPAL_7_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH2_PSA.VALUE=1
+DRIVER.CRC.VAR.CRC_CH2_ORI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CPB_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_MP0_ENA_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_MODE_VALUE.VALUE=0x0001
+DRIVER.CRC.VAR.CRC_CH1_URI.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_PSSIH.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_TOE.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_PSSIL.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_BCTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPBL_4_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_PAR_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_URI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CONT_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ENAREQ_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP1_ERRENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_STADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPA_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_3_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_BCTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_DCP0_MMADD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.HTU_ENAINTMAP_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_MODE_VALUE.VALUE=0x0001
+DRIVER.CRC.VAR.HTU_ICPBL_0_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPB_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_MP1_ENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_HETADD.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_5_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPA_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_RES_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_CPATMOD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.HTU_MP1_ENDADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_BASE.VALUE=0xFE000000
+DRIVER.CRC.VAR.HTU_ICPAL_4_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH1_MODE.VALUE=FULL_CPU
+DRIVER.CRC.VAR.HTU_CPA_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_VBHOLD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_ERRENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_1_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPB_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_MODE.VALUE=FULL_CPU
+DRIVER.CRC.VAR.HTU_DCP0_TRDAT_1.VALUE=32BIT
+DRIVER.CRC.VAR.HTU_ICPBL_6_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_0_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DCP0_CPBTMOD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.CRC_CH1_PSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_ACC_1.VALUE=READ_ONLY
+DRIVER.CRC.VAR.CRC_CH1_PSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_5_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_DCP0_ADMOD_1.VALUE=INCREMENT_16BIT
+DRIVER.CRC.VAR.HTU_CPA_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ENA_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_WDTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP0_ENDADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_2_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_0_SEL_1.VALUE=ENABLE
+DRIVER.EMAC.VAR.EMAC_ADD1.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD2.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD3.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD4.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD5.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD6.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_CTRL_BASE.VALUE=0xFCF78800
+DRIVER.EMAC.VAR.MDIO_BASE.VALUE=0xFCF78900
+DRIVER.EMAC.VAR.EMAC_BASE.VALUE=0xFCF78000
+DRIVER.EMAC.VAR.EMAC_BASE_PORT.VALUE=0xFFFFFFFF
+DRIVER.EMAC.VAR.EMAC_PHYADDRESS.VALUE=0
+DRIVER.EMAC.VAR.EMAC_CTRL_RAM_BASE.VALUE=0xFC520000
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TA.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TA.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ENA_SDRAM.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_MAX.VALUE=160
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_MAX.VALUE=160
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_MAX.VALUE=80
+DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC1_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_BANKS.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_BASE.VALUE=0xFCFFE800
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_MAX.VALUE=320
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=100000000
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_SETUP.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_MAX.VALUE=80
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_DEFAULT.VALUE=2500
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_MAX.VALUE=80
+DRIVER.EMIF.VAR.EMIF_CLK.VALUE=100
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_CAS_LATENCY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY0.VALUE=pin_low
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY1.VALUE=pin_high
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_SETUP.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES_MAX.VALUE=0
+DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001
+DRIVER.EMIF.VAR.EMIF_NS.VALUE=0.000000001
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_MAX.VALUE=80
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_MAX.VALUE=320
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD_MAX.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_ASYNC2_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_HOLD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_PAGE_SIZE.VALUE=elements_256
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_IBANK.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_STROBE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TA.VALUE=0
+DRIVER.POM.VAR.POM_OVRLY_START_ADD28.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD29.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_10_ENA.VALUE=0
+DRIVER.POM.VAR.POM_TIMEOUT_ENABLE.VALUE=0
+DRIVER.POM.VAR.POM_REGION_11_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_20_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_12_ENA.VALUE=0
+DRIVER.POM.VAR.POM_NO_OF_REGION.VALUE=1
+DRIVER.POM.VAR.POM_REGION_21_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_13_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_30_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_22_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_14_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_31_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_23_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_15_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_1_ENA.VALUE=1
+DRIVER.POM.VAR.POM_REGION_32_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_24_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_16_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_2_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_25_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_17_ENA.VALUE=0
+DRIVER.POM.VAR.POM_OVRLY_START_ADD1.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD2.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD3.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD4.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD5.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD6.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD7.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD8.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVLY_TRG_REGION.VALUE=INTERNAL_RAM
+DRIVER.POM.VAR.POM_OVRLY_START_ADD9.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_3_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_26_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_18_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_4_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_27_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_19_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_5_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_28_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_6_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_SIZE10.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE11.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE20.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE12.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_29_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_SIZE21.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE13.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE30.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE22.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE14.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE31.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE23.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE15.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE32.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE24.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE16.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE25.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE17.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE26.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE18.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE27.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE19.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE28.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE29.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_7_ENA.VALUE=0
+DRIVER.POM.VAR.POM_BASE.VALUE=0xFFA04000
+DRIVER.POM.VAR.POM_PROG_START_ADD10.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD11.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD20.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD12.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD21.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD13.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_8_ENA.VALUE=0
+DRIVER.POM.VAR.POM_PROG_START_ADD30.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD22.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD14.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD31.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD23.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD15.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD32.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD24.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD16.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD25.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD17.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD26.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD18.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD27.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD19.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE1.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_PROG_START_ADD28.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE2.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_PROG_START_ADD29.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE3.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE4.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE5.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE6.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE7.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE8.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE9.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_9_ENA.VALUE=0
+DRIVER.POM.VAR.POM_PROG_START_ADD1.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD2.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD3.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD4.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD5.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD6.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD7.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD8.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD9.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD10.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD11.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD20.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD12.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD21.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD13.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD30.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD22.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD14.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD31.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD23.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD15.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD32.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD24.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD16.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD25.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD17.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD26.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD18.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD27.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD19.VALUE=0x00000000
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN2_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN5_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN3_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN3_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN1_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0
diff --git a/bsp/rm48x50/HALCoGen/HALCoGen_bak.hcg b/bsp/rm48x50/HALCoGen/HALCoGen_bak.hcg
new file mode 100644
index 0000000000000000000000000000000000000000..b305d4a922af58cd5602bb5a8c677747dac63567
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/HALCoGen_bak.hcg
@@ -0,0 +1,730 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<SETTINGS>
+  <DEVICE>
+    <family>RM48x</family>
+    <device>RM48L950ZWT</device>
+    <dilfile>HALCoGen.dil</dilfile>
+    <tools>ti</tools>
+  </DEVICE>
+  <VERSION>
+    <version>03.05.00</version>
+  </VERSION>
+  <HET1>
+    <FILENAME>
+      <HET1ASMHDR>
+        <NAME/>
+      </HET1ASMHDR>
+      <HET1ASMSRC>
+        <NAME/>
+      </HET1ASMSRC>
+    </FILENAME>
+  </HET1>
+  <HET2>
+    <FILENAME>
+      <HET2ASMHDR>
+        <NAME/>
+      </HET2ASMHDR>
+      <HET2ASMSRC>
+        <NAME/>
+      </HET2ASMSRC>
+    </FILENAME>
+  </HET2>
+  <SYSTEM>
+    <FILENAMES>
+      <HDRHAL>
+        <NAME>hal_stdtypes.h</NAME>
+        <PATH>include\hal_stdtypes.h</PATH>
+      </HDRHAL>
+      <HDRCOMMON>
+        <NAME>sys_common.h</NAME>
+        <PATH>include\sys_common.h</PATH>
+      </HDRCOMMON>
+      <HDRSYSTEM_R>
+        <NAME>reg_system.h</NAME>
+        <PATH>include\reg_system.h</PATH>
+      </HDRSYSTEM_R>
+      <HDRFLASH_R>
+        <NAME>reg_flash.h</NAME>
+        <PATH>include\reg_flash.h</PATH>
+      </HDRFLASH_R>
+      <HDRTCRAM_R>
+        <NAME>reg_tcram.h</NAME>
+        <PATH>include\reg_tcram.h</PATH>
+      </HDRTCRAM_R>
+      <HDRVIM_R>
+        <NAME>reg_vim.h</NAME>
+        <PATH>include\reg_vim.h</PATH>
+      </HDRVIM_R>
+      <HDRPBIST_R>
+        <NAME>reg_pbist.h</NAME>
+        <PATH>include\reg_pbist.h</PATH>
+      </HDRPBIST_R>
+      <HDRSTC_R>
+        <NAME>reg_stc.h</NAME>
+        <PATH>include\reg_stc.h</PATH>
+      </HDRSTC_R>
+      <HDREFC_R>
+        <NAME>reg_efc.h</NAME>
+        <PATH>include\reg_efc.h</PATH>
+      </HDREFC_R>
+      <HDRPCR_R>
+        <NAME>reg_pcr.h</NAME>
+        <PATH>include\reg_pcr.h</PATH>
+      </HDRPCR_R>
+      <HDRPMM_R>
+        <NAME>reg_pmm.h</NAME>
+        <PATH>include\reg_pmm.h</PATH>
+      </HDRPMM_R>
+      <HDRDMA_R>
+        <NAME>reg_dma.h</NAME>
+        <PATH>include\reg_dma.h</PATH>
+      </HDRDMA_R>
+      <HDRSYSTEM>
+        <NAME>system.h</NAME>
+        <PATH>include\system.h</PATH>
+      </HDRSYSTEM>
+      <HDRVIM>
+        <NAME>sys_vim.h</NAME>
+        <PATH>include\sys_vim.h</PATH>
+      </HDRVIM>
+      <HDRCORE>
+        <NAME>sys_core.h</NAME>
+        <PATH>include\sys_core.h</PATH>
+      </HDRCORE>
+      <HDRMPU>
+        <NAME>sys_mpu.h</NAME>
+        <PATH>include\sys_mpu.h</PATH>
+      </HDRMPU>
+      <HDRPMU>
+        <NAME>sys_pmu.h</NAME>
+        <PATH>include\sys_pmu.h</PATH>
+      </HDRPMU>
+      <HDRPCR>
+        <NAME>sys_pcr.h</NAME>
+        <PATH>include\sys_pcr.h</PATH>
+      </HDRPCR>
+      <HDRPMM>
+        <NAME>sys_pmm.h</NAME>
+        <PATH>include\sys_pmm.h</PATH>
+      </HDRPMM>
+      <HDRDMA>
+        <NAME>sys_dma.h</NAME>
+        <PATH>include\sys_dma.h</PATH>
+      </HDRDMA>
+      <HDRSLF>
+        <NAME>sys_selftest.h</NAME>
+        <PATH>include\sys_selftest.h</PATH>
+      </HDRSLF>
+      <SRCCORE>
+        <NAME>sys_core.asm</NAME>
+        <PATH>source\sys_core.asm</PATH>
+      </SRCCORE>
+      <SRCINTVECS>
+        <NAME>sys_intvecs.asm</NAME>
+        <PATH>source\sys_intvecs.asm</PATH>
+      </SRCINTVECS>
+      <SRCMPU>
+        <NAME>sys_mpu.asm</NAME>
+        <PATH>source\sys_mpu.asm</PATH>
+      </SRCMPU>
+      <SRCPMU>
+        <NAME>sys_pmu.asm</NAME>
+        <PATH>source\sys_pmu.asm</PATH>
+      </SRCPMU>
+      <SRCDABORT>
+        <NAME>dabort.asm</NAME>
+        <PATH>source\dabort.asm</PATH>
+      </SRCDABORT>
+      <SRCPCR>
+        <NAME>sys_pcr.c</NAME>
+        <PATH>source\sys_pcr.c</PATH>
+      </SRCPCR>
+      <SRCPMM>
+        <NAME>sys_pmm.c</NAME>
+        <PATH>source\sys_pmm.c</PATH>
+      </SRCPMM>
+      <SRCDMA>
+        <NAME>sys_dma.c</NAME>
+        <PATH>source\sys_dma.c</PATH>
+      </SRCDMA>
+      <SRCSYSTEM>
+        <NAME>system.c</NAME>
+        <PATH>source\system.c</PATH>
+      </SRCSYSTEM>
+      <SRCPHANTOM>
+        <NAME>sys_phantom.c</NAME>
+        <PATH>source\sys_phantom.c</PATH>
+      </SRCPHANTOM>
+      <SRCSTARTUP>
+        <NAME>sys_startup.c</NAME>
+        <PATH>source\sys_startup.c</PATH>
+      </SRCSTARTUP>
+      <SRCSLF>
+        <NAME>sys_selftest.c</NAME>
+        <PATH>source\sys_selftest.c</PATH>
+      </SRCSLF>
+      <SRCVIM>
+        <NAME>sys_vim.c</NAME>
+        <PATH>source\sys_vim.c</PATH>
+      </SRCVIM>
+      <SRCMAIN>
+        <NAME>sys_main.c</NAME>
+        <PATH>source\sys_main.c</PATH>
+      </SRCMAIN>
+      <SRCNOTIFY>
+        <NAME>notification.c</NAME>
+        <PATH>source\notification.c</PATH>
+      </SRCNOTIFY>
+      <SRCCMD>
+        <NAME>sys_link.cmd</NAME>
+        <PATH>source\sys_link.cmd</PATH>
+      </SRCCMD>
+      <SRCMISRA-C>
+        <NAME>misra-c.txt</NAME>
+        <PATH>misra-c.txt</PATH>
+      </SRCMISRA-C>
+      <HDRMUX_R>
+        <NAME>reg_pinmux.h</NAME>
+      </HDRMUX_R>
+      <HDRMUX>
+        <NAME>pinmux.h</NAME>
+      </HDRMUX>
+      <SRCMUX>
+        <NAME>pinmux.c</NAME>
+      </SRCMUX>
+      <HDRRTI_R>
+        <NAME>reg_rti.h</NAME>
+      </HDRRTI_R>
+      <HDRRTI>
+        <NAME>rti.h</NAME>
+      </HDRRTI>
+      <SRCRTI>
+        <NAME>rti.c</NAME>
+      </SRCRTI>
+      <HDRGIO_R>
+        <NAME>reg_gio.h</NAME>
+      </HDRGIO_R>
+      <HDRGIO>
+        <NAME>gio.h</NAME>
+      </HDRGIO>
+      <SRCGIO>
+        <NAME>gio.c</NAME>
+      </SRCGIO>
+      <HDRSCI_R>
+        <NAME>reg_sci.h</NAME>
+      </HDRSCI_R>
+      <HDRSCI>
+        <NAME>sci.h</NAME>
+      </HDRSCI>
+      <SRCSCI>
+        <NAME>sci.c</NAME>
+      </SRCSCI>
+      <HDRLIN_R>
+        <NAME>reg_lin.h</NAME>
+      </HDRLIN_R>
+      <HDRLIN>
+        <NAME>lin.h</NAME>
+      </HDRLIN>
+      <SRCLIN/>
+      <HDRMIBSPI_R>
+        <NAME>reg_mibspi.h</NAME>
+      </HDRMIBSPI_R>
+      <HDRMIBSPI>
+        <NAME>mibspi.h</NAME>
+      </HDRMIBSPI>
+      <SRCMIBSPI/>
+      <HDRSPI_R>
+        <NAME>reg_spi.h</NAME>
+      </HDRSPI_R>
+      <HDRSPI>
+        <NAME>spi.h</NAME>
+      </HDRSPI>
+      <SRCSPI/>
+      <HDRCAN_R>
+        <NAME>reg_can.h</NAME>
+      </HDRCAN_R>
+      <HDRCAN>
+        <NAME>can.h</NAME>
+      </HDRCAN>
+      <SRCCAN/>
+      <HDRADC_R>
+        <NAME>reg_adc.h</NAME>
+      </HDRADC_R>
+      <HDRADC>
+        <NAME>adc.h</NAME>
+      </HDRADC>
+      <SRCADC/>
+      <HET1ASMHDR>
+        <NAME/>
+      </HET1ASMHDR>
+      <HET1ASMSRC>
+        <NAME/>
+      </HET1ASMSRC>
+      <STDHDRHET>
+        <NAME>std_nhet.h</NAME>
+      </STDHDRHET>
+      <HDRHET_R>
+        <NAME>reg_het.h</NAME>
+      </HDRHET_R>
+      <HDRHET>
+        <NAME>het.h</NAME>
+      </HDRHET>
+      <HDRHTU_R>
+        <NAME>reg_htu.h</NAME>
+      </HDRHTU_R>
+      <HDRHTU>
+        <NAME>htu.h</NAME>
+      </HDRHTU>
+      <SRCHET/>
+      <HET2ASMHDR>
+        <NAME/>
+      </HET2ASMHDR>
+      <HET2ASMSRC>
+        <NAME/>
+      </HET2ASMSRC>
+      <HDRESM_R>
+        <NAME>reg_esm.h</NAME>
+      </HDRESM_R>
+      <HDRESM>
+        <NAME>esm.h</NAME>
+      </HDRESM>
+      <SRCESM>
+        <NAME>esm.c</NAME>
+      </SRCESM>
+      <HDRI2C_R>
+        <NAME>reg_i2c.h</NAME>
+      </HDRI2C_R>
+      <HDRI2C>
+        <NAME>i2c.h</NAME>
+      </HDRI2C>
+      <SRCI2C/>
+      <HDR1EMAC>
+        <NAME>emac.h</NAME>
+      </HDR1EMAC>
+      <HDR2EMAC>
+        <NAME>hw_emac.h</NAME>
+      </HDR2EMAC>
+      <HDR3EMAC>
+        <NAME>hw_emac_ctrl.h</NAME>
+      </HDR3EMAC>
+      <HDR4EMAC>
+        <NAME>hw_mdio.h</NAME>
+      </HDR4EMAC>
+      <HDR5EMAC>
+        <NAME>hw_reg_access.h</NAME>
+      </HDR5EMAC>
+      <HDR6EMAC>
+        <NAME>mdio.h</NAME>
+      </HDR6EMAC>
+      <SRC1EMAC/>
+      <SRC2EMAC/>
+      <HDRDCC_R>
+        <NAME>reg_dcc.h</NAME>
+      </HDRDCC_R>
+      <HDRDCC>
+        <NAME>dcc.h</NAME>
+      </HDRDCC>
+      <SRCDCC/>
+      <HDRRTP_R>
+        <NAME>reg_rtp.h</NAME>
+      </HDRRTP_R>
+      <HDRRTP>
+        <NAME>rtp.h</NAME>
+      </HDRRTP>
+      <SRCRTP/>
+      <HDRDMM_R>
+        <NAME>reg_dmm.h</NAME>
+      </HDRDMM_R>
+      <HDRDMM>
+        <NAME>dmm.h</NAME>
+      </HDRDMM>
+      <SRCDMM/>
+      <HDREMIF_R>
+        <NAME>reg_emif.h</NAME>
+      </HDREMIF_R>
+      <HDREMIF>
+        <NAME>emif.h</NAME>
+      </HDREMIF>
+      <SRCEMIF/>
+      <HDRPOM_R>
+        <NAME>reg_pom.h</NAME>
+      </HDRPOM_R>
+      <HDRPOM>
+        <NAME>pom.h</NAME>
+      </HDRPOM>
+      <SRCPOM/>
+      <HDR1USB>
+        <NAME>usbcdc.h</NAME>
+      </HDR1USB>
+      <HDR2USB>
+        <NAME>usb_serial_structs.h</NAME>
+      </HDR2USB>
+      <HDR3USB>
+        <NAME>usbdcdc.h</NAME>
+      </HDR3USB>
+      <HDR4USB>
+        <NAME>usbdevice.h</NAME>
+      </HDR4USB>
+      <HDR5USB>
+        <NAME>usbdevicepriv.h</NAME>
+      </HDR5USB>
+      <HDR6USB>
+        <NAME>usb-ids.h</NAME>
+      </HDR6USB>
+      <HDR7USB>
+        <NAME>usblib.h</NAME>
+      </HDR7USB>
+      <HDR8USB>
+        <NAME>usb.h</NAME>
+      </HDR8USB>
+      <HDR9USB>
+        <NAME>hw_usb.h</NAME>
+      </HDR9USB>
+      <SRC1USB/>
+      <SRC2USB/>
+      <SRC3USB/>
+      <SRC5USB/>
+      <SRC6USB/>
+      <SRC7USB/>
+      <SRC8USB/>
+      <SRC9USB/>
+      <SRC10USB/>
+      <HDRCRC_R>
+        <NAME>reg_crc.h</NAME>
+      </HDRCRC_R>
+      <HDRCRC>
+        <NAME>crc.h</NAME>
+      </HDRCRC>
+      <SRCCRC/>
+    </FILENAMES>
+  </SYSTEM>
+  <PINMUX>
+    <FILENAMES>
+      <HDRMUX_R>
+        <PATH>include\reg_pinmux.h</PATH>
+      </HDRMUX_R>
+      <HDRMUX>
+        <PATH>include\pinmux.h</PATH>
+      </HDRMUX>
+      <SRCMUX>
+        <PATH>source\pinmux.c</PATH>
+      </SRCMUX>
+    </FILENAMES>
+  </PINMUX>
+  <RTI>
+    <FILENAMES>
+      <HDRRTI_R>
+        <PATH>include\reg_rti.h</PATH>
+      </HDRRTI_R>
+      <HDRRTI>
+        <PATH>include\rti.h</PATH>
+      </HDRRTI>
+      <SRCRTI>
+        <PATH>source\rti.c</PATH>
+      </SRCRTI>
+    </FILENAMES>
+  </RTI>
+  <GIO>
+    <FILENAMES>
+      <HDRGIO_R>
+        <PATH>include\reg_gio.h</PATH>
+      </HDRGIO_R>
+      <HDRGIO>
+        <PATH>include\gio.h</PATH>
+      </HDRGIO>
+      <SRCGIO>
+        <PATH>source\gio.c</PATH>
+      </SRCGIO>
+    </FILENAMES>
+  </GIO>
+  <SCI>
+    <FILENAMES>
+      <HDRSCI_R>
+        <PATH>include\reg_sci.h</PATH>
+      </HDRSCI_R>
+      <HDRSCI>
+        <PATH>include\sci.h</PATH>
+      </HDRSCI>
+      <SRCSCI>
+        <PATH>source\sci.c</PATH>
+      </SRCSCI>
+    </FILENAMES>
+  </SCI>
+  <LIN>
+    <FILENAMES>
+      <HDRLIN_R>
+        <PATH>include\reg_lin.h</PATH>
+      </HDRLIN_R>
+      <HDRLIN>
+        <PATH>include\lin.h</PATH>
+      </HDRLIN>
+      <SRCLIN>
+        <PATH/>
+      </SRCLIN>
+    </FILENAMES>
+  </LIN>
+  <MIBSPI>
+    <FILENAMES>
+      <HDRMIBSPI_R>
+        <PATH>include\reg_mibspi.h</PATH>
+      </HDRMIBSPI_R>
+      <HDRMIBSPI>
+        <PATH>include\mibspi.h</PATH>
+      </HDRMIBSPI>
+      <SRCMIBSPI>
+        <PATH/>
+      </SRCMIBSPI>
+    </FILENAMES>
+  </MIBSPI>
+  <SPI>
+    <FILENAMES>
+      <HDRSPI_R>
+        <PATH>include\reg_spi.h</PATH>
+      </HDRSPI_R>
+      <HDRSPI>
+        <PATH>include\spi.h</PATH>
+      </HDRSPI>
+      <SRCSPI>
+        <PATH/>
+      </SRCSPI>
+    </FILENAMES>
+  </SPI>
+  <CAN>
+    <FILENAMES>
+      <HDRCAN_R>
+        <PATH>include\reg_can.h</PATH>
+      </HDRCAN_R>
+      <HDRCAN>
+        <PATH>include\can.h</PATH>
+      </HDRCAN>
+      <SRCCAN>
+        <PATH/>
+      </SRCCAN>
+    </FILENAMES>
+  </CAN>
+  <ADC>
+    <FILENAMES>
+      <HDRADC_R>
+        <PATH>include\reg_adc.h</PATH>
+      </HDRADC_R>
+      <HDRADC>
+        <PATH>include\adc.h</PATH>
+      </HDRADC>
+      <SRCADC>
+        <PATH/>
+      </SRCADC>
+    </FILENAMES>
+  </ADC>
+  <HET>
+    <FILENAMES>
+      <STDHDRHET>
+        <PATH>include\std_nhet.h</PATH>
+      </STDHDRHET>
+      <HDRHET_R>
+        <PATH>include\reg_het.h</PATH>
+      </HDRHET_R>
+      <HDRHET>
+        <PATH>include\het.h</PATH>
+      </HDRHET>
+      <HDRHTU_R>
+        <PATH>include\reg_htu.h</PATH>
+      </HDRHTU_R>
+      <HDRHTU>
+        <PATH>include\htu.h</PATH>
+      </HDRHTU>
+      <SRCHET>
+        <PATH/>
+      </SRCHET>
+    </FILENAMES>
+  </HET>
+  <ESM>
+    <FILENAMES>
+      <HDRESM_R>
+        <PATH>include\reg_esm.h</PATH>
+      </HDRESM_R>
+      <HDRESM>
+        <PATH>include\esm.h</PATH>
+      </HDRESM>
+      <SRCESM>
+        <PATH>source\esm.c</PATH>
+      </SRCESM>
+    </FILENAMES>
+  </ESM>
+  <I2C>
+    <FILENAMES>
+      <HDRI2C_R>
+        <PATH>include\reg_i2c.h</PATH>
+      </HDRI2C_R>
+      <HDRI2C>
+        <PATH>include\i2c.h</PATH>
+      </HDRI2C>
+      <SRCI2C>
+        <PATH/>
+      </SRCI2C>
+    </FILENAMES>
+  </I2C>
+  <EMAC>
+    <FILENAMES>
+      <HDR1EMAC>
+        <PATH>include\emac.h</PATH>
+      </HDR1EMAC>
+      <HDR2EMAC>
+        <PATH>include\hw_emac.h</PATH>
+      </HDR2EMAC>
+      <HDR3EMAC>
+        <PATH>include\hw_emac_ctrl.h</PATH>
+      </HDR3EMAC>
+      <HDR4EMAC>
+        <PATH>include\hw_mdio.h</PATH>
+      </HDR4EMAC>
+      <HDR5EMAC>
+        <PATH>include\hw_reg_access.h</PATH>
+      </HDR5EMAC>
+      <HDR6EMAC>
+        <PATH>include\mdio.h</PATH>
+      </HDR6EMAC>
+      <SRC1EMAC>
+        <PATH/>
+      </SRC1EMAC>
+      <SRC2EMAC>
+        <PATH/>
+      </SRC2EMAC>
+    </FILENAMES>
+  </EMAC>
+  <DCC>
+    <FILENAMES>
+      <HDRDCC_R>
+        <PATH>include\reg_dcc.h</PATH>
+      </HDRDCC_R>
+      <HDRDCC>
+        <PATH>include\dcc.h</PATH>
+      </HDRDCC>
+      <SRCDCC>
+        <PATH/>
+      </SRCDCC>
+    </FILENAMES>
+  </DCC>
+  <RTP>
+    <FILENAMES>
+      <HDRRTP_R>
+        <PATH>include\reg_rtp.h</PATH>
+      </HDRRTP_R>
+      <HDRRTP>
+        <PATH>include\rtp.h</PATH>
+      </HDRRTP>
+      <SRCRTP>
+        <PATH/>
+      </SRCRTP>
+    </FILENAMES>
+  </RTP>
+  <DMM>
+    <FILENAMES>
+      <HDRDMM_R>
+        <PATH>include\reg_dmm.h</PATH>
+      </HDRDMM_R>
+      <HDRDMM>
+        <PATH>include\dmm.h</PATH>
+      </HDRDMM>
+      <SRCDMM>
+        <PATH/>
+      </SRCDMM>
+    </FILENAMES>
+  </DMM>
+  <EMIF>
+    <FILENAMES>
+      <HDREMIF_R>
+        <PATH>include\reg_emif.h</PATH>
+      </HDREMIF_R>
+      <HDREMIF>
+        <PATH>include\emif.h</PATH>
+      </HDREMIF>
+      <SRCEMIF>
+        <PATH/>
+      </SRCEMIF>
+    </FILENAMES>
+  </EMIF>
+  <POM>
+    <FILENAMES>
+      <HDRPOM_R>
+        <PATH>include\reg_pom.h</PATH>
+      </HDRPOM_R>
+      <HDRPOM>
+        <PATH>include\pom.h</PATH>
+      </HDRPOM>
+      <SRCPOM>
+        <PATH/>
+      </SRCPOM>
+    </FILENAMES>
+  </POM>
+  <USB>
+    <FILENAMES>
+      <HDR1USB>
+        <PATH>include\usbcdc.h</PATH>
+      </HDR1USB>
+      <HDR2USB>
+        <PATH>include\usb_serial_structs.h</PATH>
+      </HDR2USB>
+      <HDR3USB>
+        <PATH>include\usbdcdc.h</PATH>
+      </HDR3USB>
+      <HDR4USB>
+        <PATH>include\usbdevice.h</PATH>
+      </HDR4USB>
+      <HDR5USB>
+        <PATH>include\usbdevicepriv.h</PATH>
+      </HDR5USB>
+      <HDR6USB>
+        <PATH>include\usb-ids.h</PATH>
+      </HDR6USB>
+      <HDR7USB>
+        <PATH>include\usblib.h</PATH>
+      </HDR7USB>
+      <HDR8USB>
+        <PATH>include\usb.h</PATH>
+      </HDR8USB>
+      <HDR9USB>
+        <PATH>include\hw_usb.h</PATH>
+      </HDR9USB>
+      <SRC1USB>
+        <PATH/>
+      </SRC1USB>
+      <SRC2USB>
+        <PATH/>
+      </SRC2USB>
+      <SRC3USB>
+        <PATH/>
+      </SRC3USB>
+      <SRC5USB>
+        <PATH/>
+      </SRC5USB>
+      <SRC6USB>
+        <PATH/>
+      </SRC6USB>
+      <SRC7USB>
+        <PATH/>
+      </SRC7USB>
+      <SRC8USB>
+        <PATH/>
+      </SRC8USB>
+      <SRC9USB>
+        <PATH/>
+      </SRC9USB>
+      <SRC10USB>
+        <PATH/>
+      </SRC10USB>
+    </FILENAMES>
+  </USB>
+  <CRC>
+    <FILENAMES>
+      <HDRCRC_R>
+        <PATH>include\reg_crc.h</PATH>
+      </HDRCRC_R>
+      <HDRCRC>
+        <PATH>include\crc.h</PATH>
+      </HDRCRC>
+      <SRCCRC>
+        <PATH/>
+      </SRCCRC>
+    </FILENAMES>
+  </CRC>
+</SETTINGS>
diff --git a/bsp/rm48x50/HALCoGen/include/adc.h b/bsp/rm48x50/HALCoGen/include/adc.h
new file mode 100644
index 0000000000000000000000000000000000000000..bbf02e6cf7110386569b4492ee8cc402dca91f78
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/adc.h
@@ -0,0 +1,221 @@
+/** @file adc.h
+*   @brief ADC Driver Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ADC driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+#include "reg_adc.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* ADC General Definitions */
+
+/** @def adcGROUP0
+*   @brief Alias name for ADC event group
+*
+*   @note This value should be used for API argument @a group
+*/
+#define adcGROUP0 0U
+
+/** @def adcGROUP1
+*   @brief Alias name for ADC group 1
+*
+*   @note This value should be used for API argument @a group
+*/
+#define adcGROUP1 1U
+
+/** @def adcGROUP2
+*   @brief Alias name for ADC group 2
+*
+*   @note This value should be used for API argument @a group
+*/
+#define adcGROUP2 2U
+
+/** @enum adcResolution
+*   @brief Alias names for data resolution
+*   This enumeration is used to provide alias names for the data resolution:
+*     - 12 bit resolution
+*     - 10 bit resolution
+*     - 8  bit resolution
+*/
+
+enum adcResolution
+{
+    ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */
+    ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */
+    ADC_8_BIT  = 0x00000200U  /**< Alias for 8 bit data resolution  */
+};
+
+/** @enum adcFiFoStatus
+*   @brief Alias names for FiFo status
+*   This enumeration is used to provide alias names for the current FiFo states:
+*     - FiFo is not full
+*     - FiFo is full
+*     - FiFo overflow occurred
+*/
+
+enum adcFiFoStatus
+{
+    ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full       */
+    ADC_FIFO_IS_FULL     = 1U, /**< Alias for FiFo is full           */
+    ADC_FIFO_OVERFLOW    = 3U  /**< Alias for FiFo overflow occurred  */
+};
+
+/** @enum adcConversionStatus
+*   @brief Alias names for conversion status
+*   This enumeration is used to provide alias names for the current conversion states:
+*     - Conversion is not finished
+*     - Conversion is finished
+*/
+
+enum adcConversionStatus
+{
+    ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished */
+    ADC_CONVERSION_IS_FINISHED     = 8U  /**< Alias for current conversion is  finished    */
+};
+
+/** @enum adc1HwTriggerSource
+*   @brief Alias names for hardware trigger source
+*   This enumeration is used to provide alias names for the hardware trigger sources:
+*/
+
+enum adc1HwTriggerSource
+{
+	ADC1_EVENT = 0U,       /**< Alias for event pin             */
+	ADC1_HET1_8 = 1U,      /**< Alias for HET1 pin 8            */
+	ADC1_HET1_10 = 2U,     /**< Alias for HET1 pin 10           */
+	ADC1_RTI_COMP0 = 3U,   /**< Alias for RTI compare 0 match   */
+	ADC1_HET1_12 = 4U,     /**< Alias for HET1 pin 12           */
+	ADC1_HET1_14 = 5U,     /**< Alias for HET1 pin 14           */
+	ADC1_GIOB0 = 6U,       /**< Alias for GIO port b pin 0      */
+	ADC1_GIOB1 = 7U,       /**< Alias for GIO port b pin 1      */
+
+	ADC1_HET2_5 = 1U,      /**< Alias for HET2 pin 5            */
+	ADC1_HET1_27 = 2U,     /**< Alias for HET1 pin 27           */
+	ADC1_HET1_17 = 4U,     /**< Alias for HET1 pin 17           */
+	ADC1_HET1_19 = 5U,     /**< Alias for HET1 pin 19           */
+	ADC1_HET1_11 = 6U,     /**< Alias for HET1 pin 11           */
+	ADC1_HET2_13 = 7U,     /**< Alias for HET2 pin 13           */
+
+	ADC1_EPWM_B = 1U,      /**< Alias for B Signal EPWM         */
+	ADC1_EPWM_A1 = 3U,     /**< Alias for A1 Signal EPWM        */	
+	ADC1_HET2_1 = 5U,      /**< Alias for HET2 pin 1            */
+	ADC1_EPWM_A2 = 6U,     /**< Alias for A2 Signal EPWM        */
+	ADC1_EPWM_AB = 7U      /**< Alias for AB Signal EPWM        */	
+
+};
+
+/** @enum adc2HwTriggerSource
+*   @brief Alias names for hardware trigger source
+*   This enumeration is used to provide alias names for the hardware trigger sources:
+*/
+
+enum adc2HwTriggerSource
+{
+	ADC2_EVENT = 0U,       /**< Alias for event pin             */
+	ADC2_HET1_8 = 1U,      /**< Alias for HET1 pin 8            */
+	ADC2_HET1_10 = 2U,     /**< Alias for HET1 pin 10           */
+	ADC2_RTI_COMP0 = 3U,   /**< Alias for RTI compare 0 match   */
+	ADC2_HET1_12 = 4U,     /**< Alias for HET1 pin 12           */
+	ADC2_HET1_14 = 5U,     /**< Alias for HET1 pin 14           */
+	ADC2_GIOB0 = 6U,       /**< Alias for GIO port b pin 0      */
+	ADC2_GIOB1 = 7U,       /**< Alias for GIO port b pin 1      */
+	ADC2_HET2_5 = 1U,      /**< Alias for HET2 pin 5            */
+	ADC2_HET1_27 = 2U,     /**< Alias for HET1 pin 27           */
+	ADC2_HET1_17 = 4U,     /**< Alias for HET1 pin 17           */
+	ADC2_HET1_19 = 5U,     /**< Alias for HET1 pin 19           */
+	ADC2_HET1_11 = 6U,     /**< Alias for HET1 pin 11           */
+	ADC2_HET2_13 = 7U,     /**< Alias for HET2 pin 13           */
+	
+	ADC2_EPWM_B = 1U,      /**< Alias for B Signal EPWM         */
+	ADC2_EPWM_A1 = 3U,     /**< Alias for A1 Signal EPWM        */	
+	ADC2_HET2_1 = 5U,      /**< Alias for HET2 pin 1            */
+	ADC2_EPWM_A2 = 6U,     /**< Alias for A2 Signal EPWM        */
+	ADC2_EPWM_AB = 7U      /**< Alias for AB Signal EPWM        */	
+
+};
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @struct adcData
+*   @brief ADC Conversion data structure
+*
+*   This type is used to pass adc conversion data.
+*/
+/** @typedef adcData_t
+*   @brief ADC Data Type Definition
+*/
+typedef struct adcData
+{
+    uint32            id;     /**< Channel/Pin Id        */
+    uint16 value;  /**< Conversion data value */
+} adcData_t;
+
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** 
+ *  @defgroup ADC ADC
+ *  @brief Analog To Digital Converter Module.
+ *  
+ *  The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit resolution
+ *
+ *	Related Files
+ *   - reg_adc.h
+ *   - adc.h
+ *   - adc.c
+ *  @addtogroup ADC
+ *  @{
+ */
+ 
+/* ADC Interface Functions */
+
+void adcInit(void);
+void adcStartConversion(adcBASE_t *adc, uint32 group);
+void adcStopConversion(adcBASE_t *adc, uint32 group);
+void adcResetFiFo(adcBASE_t *adc, uint32 group);
+uint32  adcGetData(adcBASE_t *adc, uint32 group, adcData_t *data);
+uint32  adcIsFifoFull(adcBASE_t *adc, uint32 group);
+uint32  adcIsConversionComplete(adcBASE_t *adc, uint32 group);
+void adcEnableNotification(adcBASE_t *adc, uint32 group);
+void adcDisableNotification(adcBASE_t *adc, uint32 group);
+void adcCalibration(adcBASE_t *adc);
+uint32 adcMidPointCalibration(adcBASE_t *adc);
+
+/** @fn void adcNotification(adcBASE_t *adc, uint32 group)
+*   @brief Group notification
+*   @param[in] adc Pointer to ADC node:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group number of ADC node:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   @note This function has to be provide by the user.
+*/
+void adcNotification(adcBASE_t *adc, uint32 group);
+
+/**@}*/
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/can.h b/bsp/rm48x50/HALCoGen/include/can.h
new file mode 100644
index 0000000000000000000000000000000000000000..37b8709d5b1d889979925b6c0333cf5f48fa1867
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/can.h
@@ -0,0 +1,607 @@
+/** @file can.h
+*   @brief CAN Driver Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the CAN driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __CAN_H__
+#define __CAN_H__
+
+#include "reg_can.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* CAN General Definitions */
+
+/** @def canLEVEL_ACTIVE
+*   @brief Alias name for CAN error operation level active (Error counter 0-95)  
+*/
+#define canLEVEL_ACTIVE 0x00U
+
+/** @def canLEVEL_WARNING
+*   @brief Alias name for CAN error operation level warning (Error counter 96-127)  
+*/
+#define canLEVEL_WARNING 0x40U
+
+/** @def canLEVEL_PASSIVE
+*   @brief Alias name for CAN error operation level passive (Error counter 128-255)  
+*/
+#define canLEVEL_PASSIVE 0x20U
+
+/** @def canLEVEL_BUS_OFF
+*   @brief Alias name for CAN error operation level bus off (Error counter 256)  
+*/
+#define canLEVEL_BUS_OFF 0x80U
+
+/** @def canERROR_NO
+*   @brief Alias name for no CAN error occurred 
+*/
+#define canERROR_OK 0U
+
+/** @def canERROR_STUFF
+*   @brief Alias name for CAN stuff error an RX message 
+*/
+#define canERROR_STUFF 1U
+
+/** @def canERROR_FORMAT
+*   @brief Alias name for CAN form/format error an RX message 
+*/
+#define canERROR_FORMAT 2U
+
+/** @def canERROR_ACKNOWLEDGE
+*   @brief Alias name for CAN TX message wasn't acknowledged  
+*/
+#define canERROR_ACKNOWLEDGE 3U
+
+/** @def canERROR_BIT1
+*   @brief Alias name for CAN TX message sending recessive level but monitoring dominant  
+*/
+#define canERROR_BIT1 4U
+
+/** @def canERROR_BIT0
+*   @brief Alias name for CAN TX message sending dominant level but monitoring recessive  
+*/
+#define canERROR_BIT0 5U
+
+/** @def canERROR_CRC
+*   @brief Alias name for CAN RX message received wrong CRC  
+*/
+#define canERROR_CRC 6U
+
+/** @def canERROR_NO
+*   @brief Alias name for CAN no message has send or received since last call of CANGetLastError  
+*/
+#define canERROR_NO 7U
+
+/** @def canMESSAGE_BOX1
+*   @brief Alias name for CAN message box 1
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX1 1U
+
+/** @def canMESSAGE_BOX2
+*   @brief Alias name for CAN message box 2
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX2 2U
+
+/** @def canMESSAGE_BOX3
+*   @brief Alias name for CAN message box 3
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX3 3U
+
+/** @def canMESSAGE_BOX4
+*   @brief Alias name for CAN message box 4
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX4 4U
+
+/** @def canMESSAGE_BOX5
+*   @brief Alias name for CAN message box 5
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX5 5U
+
+/** @def canMESSAGE_BOX6
+*   @brief Alias name for CAN message box 6
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX6 6U
+
+/** @def canMESSAGE_BOX7
+*   @brief Alias name for CAN message box 7
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX7 7U
+
+/** @def canMESSAGE_BOX8
+*   @brief Alias name for CAN message box 8
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX8 8U
+
+/** @def canMESSAGE_BOX9
+*   @brief Alias name for CAN message box 9
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX9 9U
+
+/** @def canMESSAGE_BOX10
+*   @brief Alias name for CAN message box 10
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX10 10U
+
+/** @def canMESSAGE_BOX11
+*   @brief Alias name for CAN message box 11
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX11 11U
+
+/** @def canMESSAGE_BOX12
+*   @brief Alias name for CAN message box 12
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX12 12U
+
+/** @def canMESSAGE_BOX13
+*   @brief Alias name for CAN message box 13
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX13 13U
+
+/** @def canMESSAGE_BOX14
+*   @brief Alias name for CAN message box 14
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX14 14U
+
+/** @def canMESSAGE_BOX15
+*   @brief Alias name for CAN message box 15
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX15 15U
+
+/** @def canMESSAGE_BOX16
+*   @brief Alias name for CAN message box 16
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX16 16U
+
+/** @def canMESSAGE_BOX17
+*   @brief Alias name for CAN message box 17
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX17 17U
+
+/** @def canMESSAGE_BOX18
+*   @brief Alias name for CAN message box 18
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX18 18U
+
+/** @def canMESSAGE_BOX19
+*   @brief Alias name for CAN message box 19
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX19 19U
+
+/** @def canMESSAGE_BOX20
+*   @brief Alias name for CAN message box 20
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX20 20U
+
+/** @def canMESSAGE_BOX21
+*   @brief Alias name for CAN message box 21
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX21 21U
+
+/** @def canMESSAGE_BOX22
+*   @brief Alias name for CAN message box 22
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX22 22U
+
+/** @def canMESSAGE_BOX23
+*   @brief Alias name for CAN message box 23
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX23 23U
+
+/** @def canMESSAGE_BOX24
+*   @brief Alias name for CAN message box 24
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX24 24U
+
+/** @def canMESSAGE_BOX25
+*   @brief Alias name for CAN message box 25
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX25 25U
+
+/** @def canMESSAGE_BOX26
+*   @brief Alias name for CAN message box 26
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX26 26U
+
+/** @def canMESSAGE_BOX27
+*   @brief Alias name for CAN message box 27
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX27 27U
+
+/** @def canMESSAGE_BOX28
+*   @brief Alias name for CAN message box 28
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX28 28U
+
+/** @def canMESSAGE_BOX29
+*   @brief Alias name for CAN message box 29
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX29 29U
+
+/** @def canMESSAGE_BOX30
+*   @brief Alias name for CAN message box 30
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX30 30U
+
+/** @def canMESSAGE_BOX31
+*   @brief Alias name for CAN message box 31
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX31 31U
+
+/** @def canMESSAGE_BOX32
+*   @brief Alias name for CAN message box 32
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX32 32U
+
+/** @def canMESSAGE_BOX33
+*   @brief Alias name for CAN message box 33
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX33 33U
+
+/** @def canMESSAGE_BOX34
+*   @brief Alias name for CAN message box 34
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX34 34U
+
+/** @def canMESSAGE_BOX35
+*   @brief Alias name for CAN message box 35
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX35 35U
+
+/** @def canMESSAGE_BOX36
+*   @brief Alias name for CAN message box 36
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX36 36U
+
+/** @def canMESSAGE_BOX37
+*   @brief Alias name for CAN message box 37
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX37 37U
+
+/** @def canMESSAGE_BOX38
+*   @brief Alias name for CAN message box 38
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX38 38U
+
+/** @def canMESSAGE_BOX39
+*   @brief Alias name for CAN message box 39
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX39 39U
+
+/** @def canMESSAGE_BOX40
+*   @brief Alias name for CAN message box 40
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX40 40U
+
+/** @def canMESSAGE_BOX41
+*   @brief Alias name for CAN message box 41
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX41 41U
+
+/** @def canMESSAGE_BOX42
+*   @brief Alias name for CAN message box 42
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX42 42U
+
+/** @def canMESSAGE_BOX43
+*   @brief Alias name for CAN message box 43
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX43 43U
+
+/** @def canMESSAGE_BOX44
+*   @brief Alias name for CAN message box 44
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX44 44U
+
+/** @def canMESSAGE_BOX45
+*   @brief Alias name for CAN message box 45
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX45 45U
+
+/** @def canMESSAGE_BOX46
+*   @brief Alias name for CAN message box 46
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX46 46U
+
+/** @def canMESSAGE_BOX47
+*   @brief Alias name for CAN message box 47
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX47 47U
+
+/** @def canMESSAGE_BOX48
+*   @brief Alias name for CAN message box 48
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX48 48U
+
+/** @def canMESSAGE_BOX49
+*   @brief Alias name for CAN message box 49
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX49 49U
+
+/** @def canMESSAGE_BOX50
+*   @brief Alias name for CAN message box 50
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX50 50U
+
+/** @def canMESSAGE_BOX51
+*   @brief Alias name for CAN message box 51
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX51 51U
+
+/** @def canMESSAGE_BOX52
+*   @brief Alias name for CAN message box 52
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX52 52U
+
+/** @def canMESSAGE_BOX53
+*   @brief Alias name for CAN message box 53
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX53 53U
+
+/** @def canMESSAGE_BOX54
+*   @brief Alias name for CAN message box 54
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX54 54U
+
+/** @def canMESSAGE_BOX55
+*   @brief Alias name for CAN message box 55
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX55 55U
+
+/** @def canMESSAGE_BOX56
+*   @brief Alias name for CAN message box 56
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX56 56U
+
+/** @def canMESSAGE_BOX57
+*   @brief Alias name for CAN message box 57
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX57 57U
+
+/** @def canMESSAGE_BOX58
+*   @brief Alias name for CAN message box 58
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX58 58U
+
+/** @def canMESSAGE_BOX59
+*   @brief Alias name for CAN message box 59
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX59 59U
+
+/** @def canMESSAGE_BOX60
+*   @brief Alias name for CAN message box 60
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX60 60U
+
+/** @def canMESSAGE_BOX61
+*   @brief Alias name for CAN message box 61
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX61 61U
+
+/** @def canMESSAGE_BOX62
+*   @brief Alias name for CAN message box 62
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX62 62U
+
+/** @def canMESSAGE_BOX63
+*   @brief Alias name for CAN message box 63
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX63 63U
+
+/** @def canMESSAGE_BOX64
+*   @brief Alias name for CAN message box 64
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX64 64U
+
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** 
+ *  @defgroup CAN CAN
+ *  @brief Controller Area Network Module.
+ *  
+ *  The Controller Area Network is a high-integrity, serial, multi-master communication protocol for distributed
+ *  real-time applications. This CAN module is implemented according to ISO 11898-1 and is suitable for
+ *  industrial, automotive and general embedded communications
+ *
+ *	Related Files
+ *   - reg_can.h
+ *   - can.h
+ *   - can.c
+ *  @addtogroup CAN
+ *  @{
+ */
+ 
+/* CAN Interface Functions */
+
+void     canInit(void);
+uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data);
+uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data);
+uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox);
+uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox);
+uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox);
+uint32 canGetLastError(canBASE_t *node);
+uint32 canGetErrorLevel(canBASE_t *node);
+void     canEnableErrorNotification(canBASE_t *node);
+void     canDisableErrorNotification(canBASE_t *node);
+void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir);
+void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue);
+uint32 canIoTxGetBit(canBASE_t *node);
+uint32 canIoRxGetBit(canBASE_t *node);
+
+/** @fn void canErrorNotification(canBASE_t *node, uint32 notification)
+*   @brief Error notification
+*   @param[in] node Pointer to CAN node:
+*              - canREG1: CAN1 node pointer
+*              - canREG2: CAN2 node pointer
+*              - canREG3: CAN3 node pointer
+*   @param[in] notification Error notification code:
+*           - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127     
+*           - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255     
+*
+*   @note This function has to be provide by the user.
+*/
+void canErrorNotification(canBASE_t *node, uint32 notification);
+
+/** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox)
+*   @brief Message notification
+*   @param[in] node Pointer to CAN node:
+*              - canREG1: CAN1 node pointer
+*              - canREG2: CAN2 node pointer
+*              - canREG3: CAN3 node pointer
+*   @param[in] messageBox Message box number of CAN node:
+*              - canMESSAGE_BOX1: CAN message box 1
+*              - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+*              - canMESSAGE_BOX64: CAN message box 64
+*
+*   @note This function has to be provide by the user.
+*/
+void canMessageNotification(canBASE_t *node, uint32 messageBox);
+
+/**@}*/
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/crc.h b/bsp/rm48x50/HALCoGen/include/crc.h
new file mode 100644
index 0000000000000000000000000000000000000000..152fa5b706cad1ca0aa581b23a239d33a16fc704
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/crc.h
@@ -0,0 +1,240 @@
+/** @file CRC.h
+*   @brief CRC Driver Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the CRC driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#include "reg_crc.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* CRC General Definitions */
+
+/** @def CRCLEVEL_ACTIVE
+*   @brief Alias name for CRC error operation level active 
+*/
+#define CRCLEVEL_ACTIVE 0x00U
+
+
+/** @def CRC_AUTO
+*   @brief Alias name for CRC auto mode
+*/
+#define CRC_AUTO 0x00000001U
+
+
+/** @def CRC_SEMI_CPU
+*   @brief Alias name for semi cpu mode setting
+*/
+#define CRC_SEMI_CPU 0x00000002U
+
+
+/** @def CRC_FULL_CPU
+*   @brief Alias name for CRC cpu full mode
+*/
+#define CRC_FULL_CPU 0x00000003U
+
+
+/** @def CRC_CH4_TO
+*   @brief Alias name for channel1 time out interrupt flag
+*/
+#define CRC_CH4_TO 0x10000000U
+
+/** @def CRC_CH4_UR
+*   @brief Alias name for channel1 underrun interrupt flag
+*/
+#define CRC_CH4_UR 0x08000000U
+
+/** @def CRC_CH4_OR
+*   @brief Alias name for channel1 overrun interrupt flag
+*/
+#define CRC_CH4_OR 0x04000000U
+
+/** @def CRC_CH4_FAIL
+*   @brief Alias name for channel1 crc fail interrupt flag
+*/
+#define CRC_CH4_FAIL 0x02000000U
+
+/** @def CRC_CH4_CC
+*   @brief Alias name for channel1 compression complete interrupt flag
+*/
+#define CRC_CH4_CC 0x01000000U
+
+/** @def CRC_CH3_TO
+*   @brief Alias name for channel2 time out interrupt flag
+*/
+#define CRC_CH3_TO 0x00100000U
+
+/** @def CRC_CH3_UR
+*   @brief Alias name for channel2 underrun interrupt flag
+*/
+#define CRC_CH3_UR 0x00080000U
+
+/** @def CRC_CH3_OR
+*   @brief Alias name for channel2 overrun interrupt flag
+*/
+#define CRC_CH3_OR 0x00040000U
+
+/** @def CRC_CH3_FAIL
+*   @brief Alias name for channel2 crc fail interrupt flag
+*/
+#define CRC_CH3_FAIL 0x00020000U
+
+/** @def CRC_CH3_CC
+*   @brief Alias name for channel2 compression complete interrupt flag
+*/
+#define CRC_CH3_CC 0x00010000U
+
+/** @def CRC_CH2_TO
+*   @brief Alias name for channel3 time out interrupt flag
+*/
+#define CRC_CH2_TO 0x00001000U
+
+/** @def CRC_CH2_UR
+*   @brief Alias name for channel3 underrun interrupt flag
+*/
+#define CRC_CH2_UR 0x00000800U
+
+/** @def CRC_CH2_OR
+*   @brief Alias name for channel3 overrun interrupt flag  
+*/
+#define CRC_CH2_OR 0x00000400U
+
+/** @def CRC_CH2_FAIL
+*   @brief Alias name for channel3 crc fail interrupt flag 
+*/
+#define CRC_CH2_FAIL 0x00000200U
+
+/** @def CRC_CH2_CC
+*   @brief Alias name for channel3 compression complete interrupt flag  
+*/
+#define CRC_CH2_CC 0x00000100U
+
+/** @def CRC_CH1_TO
+*   @brief Alias name for channel4 time out interrupt flag 
+*/
+#define CRC_CH1_TO 0x00000010U
+
+/** @def CRC_CH1_UR
+*   @brief Alias name for channel4 underrun interrupt flag
+*/
+#define CRC_CH1_UR 0x00000008U
+
+
+/** @def CRC_CH1_OR
+*   @brief Alias name for channel4 overrun interrupt flag  
+*/
+#define CRC_CH1_OR 0x00000004U
+
+/** @def CRC_CH1_FAIL
+*   @brief Alias name for channel4 crc fail interrupt flag  
+*/
+#define CRC_CH1_FAIL 0x00000002U
+
+/** @def CRC_CH1_CC
+*   @brief Alias name for channel4 compression complete interrupt flag    
+*/
+#define CRC_CH1_CC 0x00000001U
+
+
+
+/** @struct crcModConfig
+*   @brief CRC mode specific parameters 
+*
+*   This type is used to pass crc mode specific parameters 
+*/
+/** @typedef crcModConfig_t
+*   @brief CRC Data Type Definition
+*/
+typedef struct crcModConfig
+{
+    uint32 mode;     /**< Mode of operation        */
+    uint32 crc_channel;     /**< CRC channel-0,1       */
+    uint32 * src_data_pat;  /**< Pattern data */
+    uint32 data_length;  /**< Pattern data length.Number of 64 bit size word*/
+} crcModConfig_t;
+
+/** @struct crcConfig
+*   @brief CRC configuration for different modes
+*
+*   This type is used to pass crc configuration
+*/
+/** @typedef crcConfig_t
+*   @brief CRC Data Type Definition
+*/
+typedef struct crcConfig
+{
+    uint32 crc_channel;     /**< CRC channel-0,1         */
+    uint32 mode;     /**< Mode of operation        */
+    uint32 pcount;     /**< Pattern count*/
+    uint32 scount;     /**< Sector count  */
+    uint32 wdg_preload;  /**< Watchdog period */
+    uint32 block_preload;  /**< Block period*/
+
+} crcConfig_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** 
+ *  @defgroup CRC CRC
+ *  @brief Cyclic Redundancy Check Controller Module.
+ *  
+ *  The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) to verify the
+ *  integrity of memory system. A signature representing the contents of the memory is obtained when the
+ *  contents of the memory are read into CRC controller. The responsibility of CRC controller is to calculate
+ *  the signature for a set of data and then compare the calculated signature value against a pre-determined
+ *  good signature value. CRC controller supports two channels to perform CRC calculation on multiple
+ *  memories in parallel and can be used on any memory system.
+ *
+ *	Related Files
+ *   - reg_crc.h
+ *   - crc.h
+ *   - crc.c
+ *  @addtogroup CRC
+ *  @{
+ */
+ 
+/* CRC Interface Functions */
+void crcInit(void);
+void crcSendPowerDown(crcBASE_t *crc);
+void crcSignGen(crcBASE_t *crc,crcModConfig_t *param);
+void crcSetConfig(crcBASE_t *crc,crcConfig_t *param);
+uint64 crcGetSectorSig(crcBASE_t *crc,uint32 channel);
+uint32 crcGetFailedSector(crcBASE_t *crc,uint32 channel);
+uint32 crcGetIntrPend(crcBASE_t *crc,uint32 channel);
+void crcChannelReset(crcBASE_t *crc,uint32 channel);
+void crcEnableNotification(crcBASE_t *crc, uint32 flags);
+void crcDisableNotification(crcBASE_t *crc, uint32 flags);
+
+/** @fn void crcNotification(crcBASE_t *crc, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] crc   - crc module base address
+*   @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void crcNotification(crcBASE_t *crc, uint32 flags);
+
+
+/**@}*/
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/dcc.h b/bsp/rm48x50/HALCoGen/include/dcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..23b25178adf64c6098e3d0d6a5e3d8c18d33e7e1
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/dcc.h
@@ -0,0 +1,278 @@
+/** @file dcc.h
+*   @brief DCC Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __DCC_H__
+#define __DCC_H__
+
+#include "reg_dcc.h"
+
+
+
+/* DCC General Definitions */
+
+/** @def dcc1CNT0_CLKSRC_HFLPO
+*   @brief Alias name for DCC1 Counter 0 Clock Source HFLPO
+*
+*   This is an alias name for the Clock Source HFLPO for DCC1 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U
+
+/** @def dcc1CNT0_CLKSRC_TCK
+*   @brief Alias name for DCC1 Counter 0 Clock Source TCK
+*
+*   This is an alias name for the Clock Source TCK for DCC1 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_TCK 0x0000000AU
+
+/** @def dcc1CNT0_CLKSRC_OSCIN
+*   @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
+*
+*   This is an alias name for the Clock Source OSCIN for DCC1 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU
+
+/** @def dcc1CNT1_CLKSRC_PLL1
+*   @brief Alias name for DCC1 Counter 1 Clock Source PLL1
+*
+*   This is an alias name for the Clock Source PLL for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_PLL1 0x0000A0000U
+
+/** @def dcc1CNT1_CLKSRC_PLL2
+*   @brief Alias name for DCC1 Counter 1 Clock Source PLL2
+*
+*   This is an alias name for the Clock Source OSCIN for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_PLL2 0x0000A0001U
+
+/** @def dcc1CNT1_CLKSRC_LFLPO
+*   @brief Alias name for DCC1 Counter 1 Clock Source LFLPO
+*
+*   This is an alias name for the Clock Source LFLPO for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_LFLPO 0x0000A0002U
+
+/** @def dcc1CNT1_CLKSRC_HFLPO
+*   @brief Alias name for DCC1 Counter 1 Clock Source HFLPO
+*
+*   This is an alias name for the Clock Source HFLPO for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_HFLPO 0x0000A0003U
+
+/** @def dcc1CNT1_CLKSRC_EXTCLKIN1
+*   @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1
+*
+*   This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A0005U
+
+/** @def dcc1CNT1_CLKSRC_EXTCLKIN2
+*   @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2
+*
+*   This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A0006U
+
+/** @def dcc1CNT1_CLKSRC_VCLK
+*   @brief Alias name for DCC1 Counter 1 Clock Source VCLK
+*
+*   This is an alias name for the Clock Source VCLK for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_VCLK 0x0000A0008U
+
+/** @def dcc1CNT1_CLKSRC_N2HET1_31
+*   @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31
+*
+*   This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_N2HET1_31 0x00005000FU
+
+/** @def dcc2CNT0_CLKSRC_TCK
+*   @brief Alias name for DCC2 Counter 0 Clock Source TCK
+*
+*   This is an alias name for the Clock Source TCK for DCC2 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc2CNT0_CLKSRC_TCK 0x0000000AU
+
+/** @def dcc1CNT0_CLKSRC_OSCIN
+*   @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
+*
+*   This is an alias name for the Clock Source OSCIN for DCC2 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU
+
+/** @def dcc2CNT1_CLKSRC_VCLK
+*   @brief Alias name for DCC2 Counter 1 Clock Source VCLK
+*
+*   This is an alias name for the Clock Source VCLK for DCC2 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc2CNT1_CLKSRC_VCLK 0x0000A0008U
+
+/** @def dcc2CNT1_CLKSRC_N2HET1_0
+*   @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0
+*
+*   This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc2CNT1_CLKSRC_N2HET1_0 0x00005000FU
+
+/** @def dccNOTIFICATION_DONE
+*   @brief Alias name for DCC Done notification
+*
+*   This is an alias name for the DCC Done notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define dccNOTIFICATION_DONE 0x0000A000U
+
+/** @def dccNOTIFICATION_ERROR
+*   @brief Alias name for DCC Error notification
+*
+*   This is an alias name for the DCC Error notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define dccNOTIFICATION_ERROR 0x000000A0U
+
+
+/** @enum dcc1clocksource
+*   @brief Alias names for dcc clock sources
+*
+*   This enumeration is used to provide alias names for the clock sources:
+*/
+enum dcc1clocksource
+{
+    DCC1_CNT0_HF_LPO	= 0x5U,	/**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
+	DCC1_CNT0_TCK		= 0xAU,	/**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/
+	DCC1_CNT0_OSCIN		= 0xFU,	/**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
+
+    DCC1_CNT1_PLL1		= 0x0U,	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/
+    DCC1_CNT1_PLL2		= 0x1U,	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
+	DCC1_CNT1_LF_LPO	= 0x2U,	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
+	DCC1_CNT1_HF_LPO	= 0x3U,	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/
+	DCC1_CNT1_EXTCLKIN1 = 0x5U,	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/
+	DCC1_CNT1_EXTCLKIN2 = 0x6U,	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/
+	DCC1_CNT1_VCLK		= 0x8U,	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
+	DCC1_CNT1_N2HET1_31	= 0xAU	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
+};
+
+/** @enum dcc2clocksource
+*   @brief Alias names for dcc clock sources
+*
+*   This enumeration is used to provide alias names for the clock sources:
+*/
+enum dcc2clocksource
+{
+    DCC2_CNT0_OSCIN		= 0xFU,	/**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
+    DCC2_CNT0_TCK		= 0xAU,	/**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
+
+   	DCC2_CNT1_VCLK		= 0x8U,	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
+	DCC2_CNT1_N2HET2_0	= 0xAU	/**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
+};
+
+/* Configuration registers */
+typedef struct dcc_config_reg
+{
+    uint32 CONFIG_GCTRL;
+    uint32 CONFIG_CNT0SEED;
+    uint32 CONFIG_VALID0SEED;
+    uint32 CONFIG_CNT1SEED;
+    uint32 CONFIG_CLKSRC1;
+    uint32 CONFIG_CLKSRC0;
+} dcc_config_reg_t;
+
+/* Configuration registers initial value */
+#define DCC1_GCTRL_CONFIGVALUE		0xAU | (0xAU << 4U) | (0x5U << 8U) | (0xAU << 12U)
+#define DCC1_CNT0SEED_CONFIGVALUE	39204U
+#define DCC1_VALID0SEED_CONFIGVALUE	792U
+#define DCC1_CNT1SEED_CONFIGVALUE	495000U
+#define DCC1_CLKSRC1_CONFIGVALUE	(10U << 12U) | DCC1_CNT1_PLL1
+/*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
+#define DCC1_CLKSRC0_CONFIGVALUE	DCC1_CNT0_OSCIN
+
+#define DCC2_GCTRL_CONFIGVALUE		0xAU | (0xAU << 4U) | (0x5U << 8U) | (0xAU << 12U)
+#define DCC2_CNT0SEED_CONFIGVALUE	0U
+#define DCC2_VALID0SEED_CONFIGVALUE	0U
+#define DCC2_CNT1SEED_CONFIGVALUE	0U
+#define DCC2_CLKSRC1_CONFIGVALUE	(0x5U << 12U) | DCC2_CNT1_VCLK
+/*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
+#define DCC2_CLKSRC0_CONFIGVALUE		DCC2_CNT0_OSCIN
+
+/**
+ *  @defgroup DCC DCC
+ *  @brief Dual-Clock Comparator Module
+ *
+ *  The primary purpose of a DCC module is to measure the frequency of a clock signal using a second
+ *  known clock signal as a reference. This capability can be used to ensure the correct frequency range for
+ *  several different device clock sources, thereby enhancing the system safety metrics.
+ *
+ *	Related Files
+ *   - reg_dcc.h
+ *   - dcc.h
+ *   - dcc.c
+ *  @addtogroup DCC
+ *  @{
+ */
+
+/* DCC Interface Functions */
+void dccInit(void);
+void dccSetCounter0Seed(dccBASE_t  *dcc, uint32 cnt0seed);
+void dccSetTolerance(dccBASE_t  *dcc, uint32 valid0seed);
+void dccSetCounter1Seed(dccBASE_t  *dcc, uint32 cnt1seed);
+void dccSetSeed(dccBASE_t  *dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed);
+void dccSelectClockSource(dccBASE_t  *dcc, uint32 cnt0_Clock_Source, uint32 cnt1_Clock_Source);
+void dccEnable(dccBASE_t  *dcc);
+void dccDisable(dccBASE_t  *dcc);
+uint32 dccGetErrStatus(dccBASE_t  *dcc);
+
+void dccEnableNotification(dccBASE_t  *dcc, uint32 notification);
+void dccDisableNotification(dccBASE_t  *dcc, uint32 notification);
+void dcc1GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type);
+void dcc2GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void dccNotification(dccBASE_t  *dcc,uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] dcc   - dcc module base address
+*   @param[in] flags - status flags
+*
+* This is a callback function provided by the application.  It is call when
+* a dcc is complete or detected error.
+*/
+void dccNotification(dccBASE_t  *dcc,uint32 flags);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/dmm.h b/bsp/rm48x50/HALCoGen/include/dmm.h
new file mode 100644
index 0000000000000000000000000000000000000000..53085ceb75ad797c34649ff4b36e68b6d8e59328
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/dmm.h
@@ -0,0 +1,36 @@
+/** @file dmm.h
+*   @brief DMM Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#ifndef __DMM_H__
+#define __DMM_H__
+
+#include "reg_dmm.h"
+
+
+/** 
+ *  @defgroup DMM DMM
+ *  @brief Data Modification Module.
+ *  
+ *  The DMM module provides the capability to modify data in the entire 4 GB address space of the device from an external peripheral,
+ *  with minimal interruption of the application.
+ *
+ *	Related Files
+ *   - reg_dmm.h
+ *   - dmm.h
+ *   - dmm.c
+ *  @addtogroup DMM
+ *  @{
+ */
+/* DMM Interface Functions */
+
+void dmmInit(void);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/emac.h b/bsp/rm48x50/HALCoGen/include/emac.h
new file mode 100644
index 0000000000000000000000000000000000000000..159573cb6246ab8af9e6ada809297554d14a64be
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/emac.h
@@ -0,0 +1,125 @@
+/**
+ *  \file   emac.h
+ *
+ *  \brief  EMAC APIs and macros.
+ *
+ *   This file contains the driver API prototypes and macro definitions.
+ */
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __EMAC_H__
+#define __EMAC_H__
+
+#include "sys_common.h"
+#include "hw_emac.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/*
+** Macros which can be used as speed parameter to the API EMACRMIISpeedSet
+*/
+#define EMAC_RMIISPEED_10MBPS                 (0x00000000U)
+#define EMAC_RMIISPEED_100MBPS                (0x00008000U)
+
+/*
+** Macros which can be used as duplexMode parameter to the API 
+** EMACDuplexSet
+*/
+#define EMAC_DUPLEX_FULL                      (0x00000001U)
+#define EMAC_DUPLEX_HALF                      (0x00000000U)
+
+/*
+** Macros which can be used as matchFilt  parameters to the API 
+** EMACMACAddrSet
+*/
+/* Address not used to match/filter incoming packets */
+#define EMAC_MACADDR_NO_MATCH_NO_FILTER       (0x00000000U)
+
+/* Address will be used to filter incoming packets */
+#define EMAC_MACADDR_FILTER                   (0x00100000U)
+
+/* Address will be used to match incoming packets */
+#define EMAC_MACADDR_MATCH                    (0x00180000U)
+
+/*
+** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API
+*/
+#define EMAC_INT_CORE0_RX                     (0x1U)
+#define EMAC_INT_CORE1_RX                     (0x5U)
+#define EMAC_INT_CORE2_RX                     (0x9U)
+
+/*
+** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API
+*/
+#define EMAC_INT_CORE0_TX                     (0x2U)
+#define EMAC_INT_CORE1_TX                     (0x6U)
+#define EMAC_INT_CORE2_TX                     (0xAU)
+
+/*****************************************************************************/
+/** 
+ *  @defgroup EMACMDIO EMAC/MDIO
+ *  @brief Ethernet Media Access Controller/Management Data Input/Output.
+ *  
+ *  The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY
+ *  configuration and status monitoring.
+ *
+ *  Both the EMAC and the MDIO modules interface to the system core through a custom interface that
+ *  allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
+ *  module and is considered integral to the EMAC/MDIO peripheral
+ *
+ *	Related Files
+ *   - emac.h
+ *   - emac.c
+ *   - hw_emac.h
+ *   - hw_emac_ctrl.h
+ *   - hw_mdio.h
+ *   - hw_reg_access.h	
+ *   - mdio.h
+ *   - mdio.c
+ *  @addtogroup EMACMDIO
+ *  @{
+ */
+/*
+** Prototypes for the APIs
+*/
+extern void EMACTxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase,
+                                 uint32 ctrlCore, uint32 channel);
+extern void EMACTxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase,
+                                  uint32 ctrlCore, uint32 channel);
+extern void EMACRxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase,
+                                 uint32 ctrlCore, uint32 channel);
+extern void EMACRxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase,
+                                   uint32 ctrlCore, uint32 channel);
+extern void EMACRMIISpeedSet(uint32 emacBase, uint32 speed);
+extern void EMACDuplexSet(uint32 emacBase, uint32 duplexMode);
+extern void EMACTxEnable(uint32 emacBase);
+extern void EMACRxEnable(uint32 emacBase);
+extern void EMACTxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
+                                  uint32 channel);
+extern void EMACRxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
+                                  uint32 channel);
+extern void EMACInit(uint32 emacCtrlBase, uint32 emacBase);
+extern void EMACMACSrcAddrSet(uint32 emacBase, uint8 * macAddr);
+extern void EMACMACAddrSet(uint32 emacBase, uint32 channel,
+                           uint8 * macAddr, uint32 matchFilt);
+extern void EMACMIIEnable(uint32 emacBase);
+extern void EMACRxUnicastSet(uint32 emacBase, uint32 channel);
+extern void EMACCoreIntAck(uint32 emacBase, uint32 eoiFlag);
+extern void EMACTxCPWrite(uint32 emacBase, uint32 channel,
+                          uint32 comPtr);
+extern void EMACRxCPWrite(uint32 emacBase, uint32 channel,
+                          uint32 comPtr);
+extern void EMACRxBroadCastEnable(uint32 emacBase, uint32 channel);
+extern void EMACNumFreeBufSet(uint32 emacBase, uint32 channel,
+                              uint32 nBuf);
+extern uint32 EMACIntVectorGet(uint32 emacBase);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* __EMAC_H__ */
diff --git a/bsp/rm48x50/HALCoGen/include/emif.h b/bsp/rm48x50/HALCoGen/include/emif.h
new file mode 100644
index 0000000000000000000000000000000000000000..95b04d24aa010cfec1f765cef73eb49bc6d78033
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/emif.h
@@ -0,0 +1,101 @@
+/** @file emif.h
+*   @brief emif Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+
+#include "reg_emif.h"
+
+
+
+/** @enum emif_pins
+*   @brief Alias for emif pins
+*
+*/
+enum emif_pins
+{
+    emif_wait_pin0 = 0U,
+    emif_wait_pin1 = 1U
+};
+
+
+/** @enum emif_size
+*   @brief Alias for emif page size
+*
+*/
+enum emif_size
+{
+    elements_256 = 0U,
+    elements_512 = 1U,
+    elements_1024 = 2U,
+    elements_2048 = 3U
+};
+
+/** @enum emif_port
+*   @brief Alias for emif port
+*
+*/
+enum emif_port
+{
+    emif_8_bit_port = 0U,
+    emif_16_bit_port = 1U
+};
+
+
+/** @enum emif_pagesize
+*   @brief Alias for emif pagesize
+*
+*/
+enum emif_pagesize
+{
+    emif_4_words = 0U,
+    emif_8_words = 1U
+};
+
+/** @enum emif_wait_polarity
+*   @brief Alias for emif wait polarity
+*
+*/
+enum emif_wait_polarity
+{
+    emif_pin_low = 0U,
+    emif_pin_high = 1U
+};
+
+
+#define PTR (uint32 *)(0x80000000U)
+
+/** 
+ *  @defgroup EMIF EMIF
+ *  @brief Error Signaling Module.
+ *  
+ *  This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 16-bit
+ *  data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of external
+ *  devices including:
+ *  - Single data rate (SDR) SDRAM
+ *  - Asynchronous devices including NOR Flash and SRAM
+ *  The most common use for the EMIF is to interface with both a flash device and an SDRAM device
+ *  simultaneously. contains an example of operating the EMIF in this configuration.
+ *
+ *	Related Files
+ *   - reg_emif.h
+ *   - emif.h
+ *   - emif.c
+ *  @addtogroup EMIF
+ *  @{
+ */
+/* EMIF Interface Functions */
+
+void emif_SDRAMInit(void);
+void emif_ASYNC1Init(void);
+void emif_ASYNC2Init(void);
+void emif_ASYNC3Init(void);
+
+/**@}*/
+#endif /*EMIF_H_*/
diff --git a/bsp/rm48x50/HALCoGen/include/esm.h b/bsp/rm48x50/HALCoGen/include/esm.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b9e5d545c14a44cf63f30ad4735c8216939dd9a
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/esm.h
@@ -0,0 +1,917 @@
+/** @file esm.h
+*   @brief Error Signaling Module Driver Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the Esm driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __ESM_H__
+#define __ESM_H__
+
+#include "reg_esm.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* ESM General Definitions */
+
+/** @def esmGROUP1
+*   @brief Alias name for ESM group 1
+*
+*   This is an alias name for the ESM group 1.
+*
+*   @note This value should be used for API argument @a group
+*/
+#define esmGROUP1 0U
+
+/** @def esmGROUP2
+*   @brief Alias name for ESM group 2
+*
+*   This is an alias name for the ESM group 2.
+*
+*   @note This value should be used for API argument @a group
+*/
+#define esmGROUP2 1U
+
+/** @def esmGROUP3
+*   @brief Alias name for ESM group 3
+*
+*   This is an alias name for the ESM group 3.
+*
+*   @note This value should be used for API argument @a group
+*/
+#define esmGROUP3 2U
+
+/** @def esmCHANNEL0
+*   @brief Alias name for ESM group x channel 0
+*
+*   This is an alias name for the ESM group x channel 0.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL0 0x0000000000000001ULL
+
+/** @def esmCHANNEL1
+*   @brief Alias name for ESM group x channel 1
+*
+*   This is an alias name for the ESM group x channel 1.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL1 0x0000000000000002ULL
+
+/** @def esmCHANNEL2
+*   @brief Alias name for ESM group x channel 2
+*
+*   This is an alias name for the ESM group x channel 2.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL2 0x0000000000000004ULL
+
+/** @def esmCHANNEL3
+*   @brief Alias name for ESM group x channel 3
+*
+*   This is an alias name for the ESM group x channel 3.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL3 0x0000000000000008ULL
+
+/** @def esmCHANNEL4
+*   @brief Alias name for ESM group x channel 4
+*
+*   This is an alias name for the ESM group x channel 4.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL4 0x0000000000000010ULL
+
+/** @def esmCHANNEL5
+*   @brief Alias name for ESM group x channel 5
+*
+*   This is an alias name for the ESM group x channel 5.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL5 0x0000000000000020ULL
+
+/** @def esmCHANNEL6
+*   @brief Alias name for ESM group x channel 6
+*
+*   This is an alias name for the ESM group x channel 6.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL6 0x0000000000000040ULL
+
+/** @def esmCHANNEL7
+*   @brief Alias name for ESM group x channel 7
+*
+*   This is an alias name for the ESM group x channel 7.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL7 0x0000000000000080ULL
+
+/** @def esmCHANNEL8
+*   @brief Alias name for ESM group x channel 8
+*
+*   This is an alias name for the ESM group x channel 8.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL8 0x0000000000000100ULL
+
+/** @def esmCHANNEL9
+*   @brief Alias name for ESM group x channel 9
+*
+*   This is an alias name for the ESM group x channel 9.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL9 0x0000000000000200ULL
+
+/** @def esmCHANNEL10
+*   @brief Alias name for ESM group x channel 10
+*
+*   This is an alias name for the ESM group x channel 10.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL10 0x0000000000000400ULL
+
+/** @def esmCHANNEL11
+*   @brief Alias name for ESM group x channel 11
+*
+*   This is an alias name for the ESM group x channel 11.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL11 0x0000000000000800ULL
+
+/** @def esmCHANNEL12
+*   @brief Alias name for ESM group x channel 12
+*
+*   This is an alias name for the ESM group x channel 12.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL12 0x0000000000001000ULL
+
+/** @def esmCHANNEL13
+*   @brief Alias name for ESM group x channel 13
+*
+*   This is an alias name for the ESM group x channel 13.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL13 0x0000000000002000ULL
+
+/** @def esmCHANNEL14
+*   @brief Alias name for ESM group x channel 14
+*
+*   This is an alias name for the ESM group x channel 14.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL14 0x0000000000004000ULL
+
+/** @def esmCHANNEL15
+*   @brief Alias name for ESM group x channel 15
+*
+*   This is an alias name for the ESM group x channel 15.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL15 0x0000000000008000ULL
+
+/** @def esmCHANNEL16
+*   @brief Alias name for ESM group x channel 16
+*
+*   This is an alias name for the ESM group x channel 16.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL16 0x0000000000010000ULL
+
+/** @def esmCHANNEL17
+*   @brief Alias name for ESM group x channel 17
+*
+*   This is an alias name for the ESM group x channel 17.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL17 0x0000000000020000ULL
+
+/** @def esmCHANNEL18
+*   @brief Alias name for ESM group x channel 18
+*
+*   This is an alias name for the ESM group x channel 18.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL18 0x0000000000040000ULL
+
+/** @def esmCHANNEL19
+*   @brief Alias name for ESM group x channel 19
+*
+*   This is an alias name for the ESM group x channel 19.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL19 0x0000000000080000ULL
+
+/** @def esmCHANNEL20
+*   @brief Alias name for ESM group x channel 20
+*
+*   This is an alias name for the ESM group x channel 20.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL20 0x0000000000100000ULL
+
+/** @def esmCHANNEL21
+*   @brief Alias name for ESM group x channel 21
+*
+*   This is an alias name for the ESM group x channel 21.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL21 0x0000000000200000ULL
+
+/** @def esmCHANNEL22
+*   @brief Alias name for ESM group x channel 22
+*
+*   This is an alias name for the ESM group x channel 22.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL22 0x0000000000400000ULL
+
+/** @def esmCHANNEL23
+*   @brief Alias name for ESM group x channel 23
+*
+*   This is an alias name for the ESM group x channel 23.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL23 0x0000000000800000ULL
+
+/** @def esmCHANNEL24
+*   @brief Alias name for ESM group x channel 24
+*
+*   This is an alias name for the ESM group x channel 24.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL24 0x0000000001000000ULL
+
+/** @def esmCHANNEL25
+*   @brief Alias name for ESM group x channel 25
+*
+*   This is an alias name for the ESM group x channel 25.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL25 0x0000000002000000ULL
+
+/** @def esmCHANNEL26
+*   @brief Alias name for ESM group x channel 26
+*
+*   This is an alias name for the ESM group x channel 26.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL26 0x0000000004000000ULL
+
+/** @def esmCHANNEL27
+*   @brief Alias name for ESM group x channel 27
+*
+*   This is an alias name for the ESM group x channel 27.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL27 0x0000000008000000ULL
+
+/** @def esmCHANNEL28
+*   @brief Alias name for ESM group x channel 28
+*
+*   This is an alias name for the ESM group x channel 28.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL28 0x0000000010000000ULL
+
+/** @def esmCHANNEL29
+*   @brief Alias name for ESM group x channel 29
+*
+*   This is an alias name for the ESM group x channel 29.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL29 0x0000000020000000ULL
+
+/** @def esmCHANNEL30
+*   @brief Alias name for ESM group x channel 30
+*
+*   This is an alias name for the ESM group x channel 30.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL30 0x0000000040000000ULL
+
+/** @def esmCHANNEL31
+*   @brief Alias name for ESM group x channel 31
+*
+*   This is an alias name for the ESM group x channel 31.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL31 0x0000000080000000ULL
+
+/** @def esmCHANNEL32
+*   @brief Alias name for ESM group x channel 32
+*
+*   This is an alias name for the ESM group x channel 32.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL32 0x0000000100000000ULL
+
+/** @def esmCHANNEL33
+*   @brief Alias name for ESM group x channel 33
+*
+*   This is an alias name for the ESM group x channel 33.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL33 0x0000000200000000ULL
+
+/** @def esmCHANNEL34
+*   @brief Alias name for ESM group x channel 34
+*
+*   This is an alias name for the ESM group x channel 34.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL34 0x0000000400000000ULL
+
+/** @def esmCHANNEL35
+*   @brief Alias name for ESM group x channel 35
+*
+*   This is an alias name for the ESM group x channel 35.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL35 0x0000000800000000ULL
+
+/** @def esmCHANNEL36
+*   @brief Alias name for ESM group x channel 36
+*
+*   This is an alias name for the ESM group x channel 36.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL36 0x0000001000000000ULL
+
+/** @def esmCHANNEL37
+*   @brief Alias name for ESM group x channel 37
+*
+*   This is an alias name for the ESM group x channel 37.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL37 0x0000002000000000ULL
+
+/** @def esmCHANNEL38
+*   @brief Alias name for ESM group x channel 38
+*
+*   This is an alias name for the ESM group x channel 38.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL38 0x0000004000000000ULL
+
+/** @def esmCHANNEL39
+*   @brief Alias name for ESM group x channel 39
+*
+*   This is an alias name for the ESM group x channel 39.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL39 0x0000008000000000ULL
+
+/** @def esmCHANNEL40
+*   @brief Alias name for ESM group x channel 40
+*
+*   This is an alias name for the ESM group x channel 40.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL40 0x0000010000000000ULL
+
+/** @def esmCHANNEL41
+*   @brief Alias name for ESM group x channel 41
+*
+*   This is an alias name for the ESM group x channel 41.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL41 0x0000020000000000ULL
+
+/** @def esmCHANNEL42
+*   @brief Alias name for ESM group x channel 42
+*
+*   This is an alias name for the ESM group x channel 42.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL42 0x0000040000000000ULL
+
+/** @def esmCHANNEL43
+*   @brief Alias name for ESM group x channel 43
+*
+*   This is an alias name for the ESM group x channel 43.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL43 0x0000080000000000ULL
+
+/** @def esmCHANNEL44
+*   @brief Alias name for ESM group x channel 44
+*
+*   This is an alias name for the ESM group x channel 44.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL44 0x0000100000000000ULL
+
+/** @def esmCHANNEL45
+*   @brief Alias name for ESM group x channel 45
+*
+*   This is an alias name for the ESM group x channel 45.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL45 0x0000200000000000ULL
+
+/** @def esmCHANNEL46
+*   @brief Alias name for ESM group x channel 46
+*
+*   This is an alias name for the ESM group x channel 46.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL46 0x0000400000000000ULL
+
+/** @def esmCHANNEL47
+*   @brief Alias name for ESM group x channel 47
+*
+*   This is an alias name for the ESM group x channel 47.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL47 0x0000800000000000ULL
+
+/** @def esmCHANNEL48
+*   @brief Alias name for ESM group x channel 48
+*
+*   This is an alias name for the ESM group x channel 48.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL48 0x0001000000000000ULL
+
+/** @def esmCHANNEL49
+*   @brief Alias name for ESM group x channel 49
+*
+*   This is an alias name for the ESM group x channel 49.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL49 0x0002000000000000ULL
+
+/** @def esmCHANNEL50
+*   @brief Alias name for ESM group x channel 50
+*
+*   This is an alias name for the ESM group x channel 50.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL50 0x0004000000000000ULL
+
+/** @def esmCHANNEL51
+*   @brief Alias name for ESM group x channel 51
+*
+*   This is an alias name for the ESM group x channel 51.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL51 0x0008000000000000ULL
+
+/** @def esmCHANNEL52
+*   @brief Alias name for ESM group x channel 52
+*
+*   This is an alias name for the ESM group x channel 52.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL52 0x0010000000000000ULL
+
+/** @def esmCHANNEL53
+*   @brief Alias name for ESM group x channel 53
+*
+*   This is an alias name for the ESM group x channel 53.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL53 0x0020000000000000ULL
+
+/** @def esmCHANNEL54
+*   @brief Alias name for ESM group x channel 54
+*
+*   This is an alias name for the ESM group x channel 54.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL54 0x0040000000000000ULL
+
+/** @def esmCHANNEL55
+*   @brief Alias name for ESM group x channel 55
+*
+*   This is an alias name for the ESM group x channel 55.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL55 0x0080000000000000ULL
+
+/** @def esmCHANNEL56
+*   @brief Alias name for ESM group x channel 56
+*
+*   This is an alias name for the ESM group x channel 56.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL56 0x0100000000000000ULL
+
+/** @def esmCHANNEL57
+*   @brief Alias name for ESM group x channel 57
+*
+*   This is an alias name for the ESM group x channel 57.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL57 0x0200000000000000ULL
+
+/** @def esmCHANNEL58
+*   @brief Alias name for ESM group x channel 58
+*
+*   This is an alias name for the ESM group x channel 58.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL58 0x0400000000000000ULL
+
+/** @def esmCHANNEL59
+*   @brief Alias name for ESM group x channel 59
+*
+*   This is an alias name for the ESM group x channel 59.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL59 0x0800000000000000ULL
+
+/** @def esmCHANNEL60
+*   @brief Alias name for ESM group x channel 60
+*
+*   This is an alias name for the ESM group x channel 60.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL60 0x1000000000000000ULL
+
+/** @def esmCHANNEL61
+*   @brief Alias name for ESM group x channel 61
+*
+*   This is an alias name for the ESM group x channel 61.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL61 0x2000000000000000ULL
+
+/** @def esmCHANNEL62
+*   @brief Alias name for ESM group x channel 62
+*
+*   This is an alias name for the ESM group x channel 62.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL62 0x4000000000000000ULL
+
+/** @def esmCHANNEL63
+*   @brief Alias name for ESM group x channel 63
+*
+*   This is an alias name for the ESM group x channel 63.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL63 0x8000000000000000ULL
+
+/** @typedef esmSelfTestFlag_t
+*   @brief ESM Self-Test Status Type Definition
+*
+*   This type is used to represent ESM Self-Test Status.
+*/
+typedef enum esmSelfTestFlag 
+{
+    esmSelfTest_Passed = 0U,
+	esmSelfTest_Active = 1U,
+	esmSelfTest_NotStarted = 2U,
+    esmSelfTest_Failed = 3U
+}esmSelfTestFlag_t;
+
+/* Configuration registers */
+typedef struct esm_config_reg
+{
+    uint32 CONFIG_EPENASET1;
+    uint32 CONFIG_INTENASET1;
+    uint32 CONFIG_INTLVLSET1;
+    uint32 CONFIG_LTCPRELOAD;
+	uint32 CONFIG_KEY;  
+    uint32 CONFIG_EPENASET4;
+    uint32 CONFIG_INTENASET4;
+    uint32 CONFIG_INTLVLSET4;
+} esm_config_reg_t;
+
+/* Configuration registers initial value */
+#define ESM_EPENASET1_CONFIGVALUE	(0U << 31U)\
+                      | (0U << 30U)\
+                      | (0U << 29U)\
+                      | (0U << 28U)\
+                      | (0U << 27U)\
+                      | (0U << 26U)\
+                      | (0U << 25U)\
+                      | (0U << 24U)\
+                      | (0U << 23U)\
+                      | (0U << 22U)\
+                      | (0U << 21U)\
+                      | (0U << 20U)\
+                      | (0U << 19U)\
+                      | (0U << 18U)\
+                      | (0U << 17U)\
+                      | (0U << 16U)\
+                      | (0U << 15U)\
+                      | (0U << 14U)\
+                      | (0U << 13U)\
+                      | (0U << 12U)\
+                      | (0U << 11U)\
+                      | (0U << 10U)\
+                      | (0U <<  9U)\
+                      | (0U <<  8U)\
+                      | (0U <<  7U)\
+                      | (0U <<  6U)\
+                      | (0U <<  5U)\
+                      | (0U <<  4U)\
+                      | (0U <<  3U)\
+                      | (0U <<  2U)\
+                      | (0U <<  1U)\
+                      | (0U)
+#define ESM_INTENASET1_CONFIGVALUE	(0U << 31U)\
+                       | (0U << 30U)\
+                       | (0U << 29U)\
+                       | (0U << 28U)\
+                       | (0U << 27U)\
+                       | (0U << 26U)\
+                       | (0U << 25U)\
+                       | (0U << 24U)\
+                       | (0U << 23U)\
+                       | (0U << 22U)\
+                       | (0U << 21U)\
+                       | (0U << 20U)\
+                       | (0U << 19U)\
+                       | (0U << 18U)\
+                       | (0U << 17U)\
+                       | (0U << 16U)\
+                       | (0U << 15U)\
+                       | (0U << 14U)\
+                       | (0U << 13U)\
+                       | (0U << 12U)\
+                       | (0U << 11U)\
+                       | (0U << 10U)\
+                       | (0U <<  9U)\
+                       | (0U <<  8U)\
+                       | (0U <<  7U)\
+                       | (0U <<  6U)\
+                       | (0U <<  5U)\
+                       | (0U <<  4U)\
+                       | (0U <<  3U)\
+                       | (0U <<  2U)\
+                       | (0U <<  1U)\
+                       | (0U)
+#define ESM_INTLVLSET1_CONFIGVALUE (0U << 31U)\
+                       | (0U << 30U)\
+                       | (0U << 29U)\
+                       | (0U << 28U)\
+                       | (0U << 27U)\
+                       | (0U << 26U)\
+                       | (0U << 25U)\
+                       | (0U << 24U)\
+                       | (0U << 23U)\
+                       | (0U << 22U)\
+                       | (0U << 21U)\
+                       | (0U << 20U)\
+                       | (0U << 19U)\
+                       | (0U << 18U)\
+                       | (0U << 17U)\
+                       | (0U << 16U)\
+                       | (0U << 15U)\
+                       | (0U << 14U)\
+                       | (0U << 13U)\
+                       | (0U << 12U)\
+                       | (0U << 11U)\
+                       | (0U << 10U)\
+                       | (0U <<  9U)\
+                       | (0U <<  8U)\
+                       | (0U <<  7U)\
+                       | (0U <<  6U)\
+                       | (0U <<  5U)\
+                       | (0U <<  4U)\
+                       | (0U <<  3U)\
+                       | (0U <<  2U)\
+                       | (0U <<  1U)\
+                       | (0U)
+#define ESM_LTCPRELOAD_CONFIGVALUE	16384U - 1U
+#define ESM_KEY_CONFIGVALUE 		0U
+#define ESM_EPENASET4_CONFIGVALUE (0U << 31U)\
+                      | (0U << 30U)\
+                      | (0U << 29U)\
+                      | (0U << 28U)\
+                      | (0U << 27U)\
+                      | (0U << 26U)\
+                      | (0U << 25U)\
+                      | (0U << 24U)\
+                      | (0U << 23U)\
+                      | (0U << 22U)\
+                      | (0U << 21U)\
+                      | (0U << 20U)\
+                      | (0U << 19U)\
+                      | (0U << 18U)\
+                      | (0U << 17U)\
+                      | (0U << 16U)\
+                      | (0U << 15U)\
+                      | (0U << 14U)\
+                      | (0U << 13U)\
+                      | (0U << 12U)\
+                      | (0U << 11U)\
+                      | (0U << 10U)\
+                      | (0U <<  9U)\
+                      | (0U <<  8U)\
+                      | (0U <<  7U)\
+                      | (0U <<  6U)\
+                      | (0U <<  5U)\
+                      | (0U <<  4U)\
+                      | (0U <<  3U)\
+                      | (0U <<  2U)\
+                      | (0U <<  1U)\
+                      | (0U)
+#define ESM_INTENASET4_CONFIGVALUE (0U << 31U)\
+                       | (0U << 30U)\
+                       | (0U << 29U)\
+                       | (0U << 28U)\
+                       | (0U << 27U)\
+                       | (0U << 26U)\
+                       | (0U << 25U)\
+                       | (0U << 24U)\
+                       | (0U << 23U)\
+                       | (0U << 22U)\
+                       | (0U << 21U)\
+                       | (0U << 20U)\
+                       | (0U << 19U)\
+                       | (0U << 18U)\
+                       | (0U << 17U)\
+                       | (0U << 16U)\
+                       | (0U << 15U)\
+                       | (0U << 14U)\
+                       | (0U << 13U)\
+                       | (0U << 12U)\
+                       | (0U << 11U)\
+                       | (0U << 10U)\
+                       | (0U <<  9U)\
+                       | (0U <<  8U)\
+                       | (0U <<  7U)\
+                       | (0U <<  6U)\
+                       | (0U <<  5U)\
+                       | (0U <<  4U)\
+                       | (0U <<  3U)\
+                       | (0U <<  2U)\
+                       | (0U <<  1U)\
+                       | (0U)
+#define ESM_INTLVLSET4_CONFIGVALUE (0U << 31U)\
+                       | (0U << 30U)\
+                       | (0U << 29U)\
+                       | (0U << 28U)\
+                       | (0U << 27U)\
+                       | (0U << 26U)\
+                       | (0U << 25U)\
+                       | (0U << 24U)\
+                       | (0U << 23U)\
+                       | (0U << 22U)\
+                       | (0U << 21U)\
+                       | (0U << 20U)\
+                       | (0U << 19U)\
+                       | (0U << 18U)\
+                       | (0U << 17U)\
+                       | (0U << 16U)\
+                       | (0U << 15U)\
+                       | (0U << 14U)\
+                       | (0U << 13U)\
+                       | (0U << 12U)\
+                       | (0U << 11U)\
+                       | (0U << 10U)\
+                       | (0U <<  9U)\
+                       | (0U <<  8U)\
+                       | (0U <<  7U)\
+                       | (0U <<  6U)\
+                       | (0U <<  5U)\
+                       | (0U <<  4U)\
+                       | (0U <<  3U)\
+                       | (0U <<  2U)\
+                       | (0U <<  1U)\
+                       | (0U)
+
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** 
+ *  @defgroup ESM ESM
+ *  @brief Error Signaling Module.
+ *  
+ *  The ESM module aggregates device errors and provides internal and external error response based on error severity.
+ *
+ *	Related Files
+ *   - reg_esm.h
+ *   - esm.h
+ *   - esm.c
+ *  @addtogroup ESM
+ *  @{
+ */
+ 
+/* Esm Interface Functions */
+void     esmInit(void);
+uint32 esmError(void);
+void     esmEnableError(uint64 channels);
+void     esmDisableError(uint64 channels);
+void     esmTriggerErrorPinReset(void);
+void     esmActivateNormalOperation(void);
+void     esmEnableInterrupt(uint64 channels);
+void     esmDisableInterrupt(uint64 channels);
+void     esmSetInterruptLevel(uint64 channels, uint64 flags);
+void     esmClearStatus(uint32 group, uint64 channels);
+void     esmClearStatusBuffer(uint64 channels);
+void     esmSetCounterPreloadValue(uint32 value);
+
+uint64 esmGetStatus(uint32 group, uint64 channels);
+uint64 esmGetStatusBuffer(uint64 channels);
+
+esmSelfTestFlag_t esmEnterSelfTest(void);
+esmSelfTestFlag_t esmSelfTestStatus(void);
+
+boolean esmSelfTest(void);
+
+void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void esmGroup1Notification(uint32 channel)
+*   @brief Interrupt callback
+*   @param[in] channel - Group 1 channel
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt. The parameter passed to the callback is group 1 channel caused the interrupt.
+*/
+void esmGroup1Notification(uint32 channel);
+
+
+/** @fn void esmGroup2Notification(uint32 channel)
+*   @brief Interrupt callback
+*   @param[in] channel - Group 2 channel
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt. The parameter passed to the callback is group 2 channel caused the interrupt.
+*/
+void esmGroup2Notification(uint32 channel);
+
+/**@}*/
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/gio.h b/bsp/rm48x50/HALCoGen/include/gio.h
new file mode 100644
index 0000000000000000000000000000000000000000..b4df1d6f632d6afcf700440203d824240ecd8788
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/gio.h
@@ -0,0 +1,45 @@
+/** @file gio.h
+*   @brief GIO Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __GIO_H__
+#define __GIO_H__
+
+#include "reg_gio.h"
+
+
+/** 
+ *  @defgroup GIO GIO
+ *  @brief General-Purpose Input/Output Module.
+ *  
+ *  The GIO module provides the family of devices with input/output (I/O) capability. 
+ *  The I/O pins are bidirectional and bit-programmable.
+ *  The GIO module also supports external interrupt capability.
+ *
+ *	Related Files
+ *   - reg_gio.h
+ *   - gio.h
+ *   - gio.c
+ *  @addtogroup GIO
+ *  @{
+ */
+ 
+/* GIO Interface Functions */
+void gioInit(void);
+void gioSetDirection(gioPORT_t *port, uint32 dir);
+void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value);
+void gioSetPort(gioPORT_t *port, uint32 value);
+uint32 gioGetBit(gioPORT_t *port, uint32 bit);
+uint32 gioGetPort(gioPORT_t *port);
+void gioToggleBit(gioPORT_t *port, uint32 bit);
+void gioEnableNotification(gioPORT_t *port, uint32 bit);
+void gioDisableNotification(gioPORT_t *port, uint32 bit);
+void gioNotification(gioPORT_t *port, sint32 bit);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/hal_stdtypes.h b/bsp/rm48x50/HALCoGen/include/hal_stdtypes.h
new file mode 100644
index 0000000000000000000000000000000000000000..161d59cae18cafd864e8a088c14b0232009e1945
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/hal_stdtypes.h
@@ -0,0 +1,104 @@
+/** @file hal_stdtypes.h
+*   @brief HALCoGen standard types header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Type and Global definitions which are relevant for all drivers.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __HAL_STDTYPES_H__
+#define __HAL_STDTYPES_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+/************************************************************/
+/* Type Definitions                                         */
+/************************************************************/
+#ifndef _UINT64_DECLARED
+typedef unsigned long long uint64;
+#define	_UINT64_DECLARED
+#endif
+
+#ifndef _UINT32_DECLARED
+typedef unsigned int uint32;
+#define	_UINT32_DECLARED
+#endif
+
+#ifndef _UINT16_DECLARED
+typedef unsigned short uint16;
+#define	_UINT16_DECLARED
+#endif
+
+#ifndef _UINT8_DECLARED
+typedef unsigned char uint8;
+#define	_UINT8_DECLARED
+#endif
+
+#ifndef _BOOLEAN_DECLARED
+typedef unsigned char boolean;
+typedef unsigned char boolean_t;
+#define	_BOOLEAN_DECLARED
+#endif
+
+#ifndef _SINT64_DECLARED
+typedef signed long long sint64;
+#define	_SINT64_DECLARED
+#endif
+
+#ifndef _SINT32_DECLARED
+typedef signed int sint32;
+#define	_SINT32_DECLARED
+#endif
+
+#ifndef _SINT16_DECLARED
+typedef signed short sint16;
+#define	_SINT16_DECLARED
+#endif
+
+#ifndef _SINT8_DECLARED
+typedef signed char sint8;
+#define	_SINT8_DECLARED
+#endif
+
+#ifndef _FLOAT32_DECLARED
+typedef float float32;
+#define	_FLOAT32_DECLARED
+#endif
+
+#ifndef _FLOAT64_DECLARED
+typedef double float64;
+#define	_FLOAT64_DECLARED
+#endif
+
+
+/************************************************************/
+/* Global Definitions                                       */
+/************************************************************/
+/** @def NULL
+*   @brief NULL definition
+*/
+#ifndef NULL
+    #define NULL ((void *) 0U)
+#endif
+
+/** @def TRUE
+*   @brief definition for TRUE
+*/
+#ifndef TRUE
+    #define TRUE (boolean)1U
+#endif
+
+/** @def FALSE
+*   @brief BOOLEAN definition for FALSE
+*/
+#ifndef FALSE
+    #define FALSE (boolean)0U
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#endif /* __HAL_STDTYPES_H__ */
diff --git a/bsp/rm48x50/HALCoGen/include/het.h b/bsp/rm48x50/HALCoGen/include/het.h
new file mode 100644
index 0000000000000000000000000000000000000000..8edcdd81d87e91c18285570c907894071536b151
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/het.h
@@ -0,0 +1,378 @@
+/** @file het.h
+*   @brief HET Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#ifndef __HET_H__
+#define __HET_H__
+
+#include "reg_het.h"
+#include <string.h>
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def pwm0
+*   @brief Pwm signal 0
+*
+*   Alias for pwm signal 0
+*/
+#define pwm0 0U
+
+/** @def pwm1
+*   @brief Pwm signal 1
+*
+*   Alias for pwm signal 1
+*/
+#define pwm1 1U
+
+/** @def pwm2
+*   @brief Pwm signal 2
+*
+*   Alias for pwm signal 2
+*/
+#define pwm2 2U
+
+/** @def pwm3
+*   @brief Pwm signal 3
+*
+*   Alias for pwm signal 3
+*/
+#define pwm3 3U
+
+/** @def pwm4
+*   @brief Pwm signal 4
+*
+*   Alias for pwm signal 4
+*/
+#define pwm4 4U
+
+/** @def pwm5
+*   @brief Pwm signal 5
+*
+*   Alias for pwm signal 5
+*/
+#define pwm5 5U
+
+/** @def pwm6
+*   @brief Pwm signal 6
+*
+*   Alias for pwm signal 6
+*/
+#define pwm6 6U
+
+/** @def pwm7
+*   @brief Pwm signal 7
+*
+*   Alias for pwm signal 7
+*/
+#define pwm7 7U
+
+
+/** @def edge0
+*   @brief Edge signal 0
+*
+*   Alias for edge signal 0
+*/
+#define edge0 0U
+
+/** @def edge1
+*   @brief Edge signal 1
+*
+*   Alias for edge signal 1
+*/
+#define edge1 1U
+
+/** @def edge2
+*   @brief Edge signal 2
+*
+*   Alias for edge signal 2
+*/
+#define edge2 2U
+
+/** @def edge3
+*   @brief Edge signal 3
+*
+*   Alias for edge signal 3
+*/
+#define edge3 3U
+
+/** @def edge4
+*   @brief Edge signal 4
+*
+*   Alias for edge signal 4
+*/
+#define edge4 4U
+
+/** @def edge5
+*   @brief Edge signal 5
+*
+*   Alias for edge signal 5
+*/
+#define edge5 5U
+
+/** @def edge6
+*   @brief Edge signal 6
+*
+*   Alias for edge signal 6
+*/
+#define edge6 6U
+
+/** @def edge7
+*   @brief Edge signal 7
+*
+*   Alias for edge signal 7
+*/
+#define edge7 7U
+
+
+/** @def cap0
+*   @brief Capture signal 0
+*
+*   Alias for capture signal 0
+*/
+#define cap0 0U
+
+/** @def cap1
+*   @brief Capture signal 1
+*
+*   Alias for capture signal 1
+*/
+#define cap1 1U
+
+/** @def cap2
+*   @brief Capture signal 2
+*
+*   Alias for capture signal 2
+*/
+#define cap2 2U
+
+/** @def cap3
+*   @brief Capture signal 3
+*
+*   Alias for capture signal 3
+*/
+#define cap3 3U
+
+/** @def cap4
+*   @brief Capture signal 4
+*
+*   Alias for capture signal 4
+*/
+#define cap4 4U
+
+/** @def cap5
+*   @brief Capture signal 5
+*
+*   Alias for capture signal 5
+*/
+#define cap5 5U
+
+/** @def cap6
+*   @brief Capture signal 6
+*
+*   Alias for capture signal 6
+*/
+#define cap6 6U
+
+/** @def cap7
+*   @brief Capture signal 7
+*
+*   Alias for capture signal 7
+*/
+#define cap7 7U
+
+/** @def pwmEND_OF_DUTY
+*   @brief Pwm end of duty
+*
+*   Alias for pwm end of duty notification
+*/
+#define pwmEND_OF_DUTY 2U
+
+/** @def pwmEND_OF_PERIOD
+*   @brief Pwm end of period
+*
+*   Alias for pwm end of period notification
+*/
+#define pwmEND_OF_PERIOD 4U
+
+/** @def pwmEND_OF_BOTH
+*   @brief Pwm end of duty and period
+*
+*   Alias for pwm end of duty and period notification
+*/
+#define pwmEND_OF_BOTH 6U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @struct hetBase
+*   @brief HET Register Definition
+*
+*   This structure is used to access the HET module registers.
+*/
+/** @typedef hetBASE_t
+*   @brief HET Register Frame Type Definition
+*
+*   This type is used to access the HET Registers.
+*/
+
+enum hetPinSelect
+{
+    PIN_HET_0 = 0U,
+    PIN_HET_1 = 1U,
+    PIN_HET_2 = 2U,
+    PIN_HET_3 = 3U,
+    PIN_HET_4 = 4U,
+    PIN_HET_5 = 5U,
+    PIN_HET_6 = 6U,
+    PIN_HET_7 = 7U,
+    PIN_HET_8 = 8U,
+    PIN_HET_9 = 9U,
+    PIN_HET_10 = 10U,
+    PIN_HET_11 = 11U,
+    PIN_HET_12 = 12U,
+    PIN_HET_13 = 13U,
+    PIN_HET_14 = 14U,
+    PIN_HET_15 = 15U,
+    PIN_HET_16 = 16U,
+    PIN_HET_17 = 17U,
+    PIN_HET_18 = 18U,
+    PIN_HET_19 = 19U,
+    PIN_HET_20 = 20U,
+    PIN_HET_21 = 21U,
+    PIN_HET_22 = 22U,
+    PIN_HET_23 = 23U,
+    PIN_HET_24 = 24U,
+    PIN_HET_25 = 25U,
+    PIN_HET_26 = 26U,
+    PIN_HET_27 = 27U,
+    PIN_HET_28 = 28U,
+    PIN_HET_29 = 29U,
+    PIN_HET_30 = 30U,
+    PIN_HET_31 = 31U
+};
+
+
+/** @struct hetInstructionBase
+*   @brief HET Instruction Definition
+*
+*   This structure is used to access the HET RAM.
+*/
+/** @typedef hetINSTRUCTION_t
+*   @brief HET Instruction Type Definition
+*
+*   This type is used to access a HET Instruction.
+*/
+typedef volatile struct hetInstructionBase
+{
+    uint32 Program;
+    uint32 Control;
+    uint32 Data;
+    uint32   rsvd1;
+} hetINSTRUCTION_t;
+
+
+/** @struct hetRamBase
+*   @brief HET RAM Definition
+*
+*   This structure is used to access the HET RAM.
+*/
+/** @typedef hetRAMBASE_t
+*   @brief HET RAM Type Definition
+*
+*   This type is used to access the HET RAM.
+*/
+typedef volatile struct het1RamBase
+{
+    hetINSTRUCTION_t Instruction[160U];
+} hetRAMBASE_t;
+
+
+/** @struct hetSignal
+*   @brief HET Signal Definition
+*
+*   This structure is used to define a pwm signal.
+*/
+/** @typedef hetSIGNAL_t
+*   @brief HET Signal Type Definition
+*
+*   This type is used to access HET Signal Information.
+*/
+typedef struct hetSignal
+{
+	uint32 duty;   /**< Duty cycle in % of the period  */
+	float64   period; /**< Period in us                   */
+} hetSIGNAL_t;
+
+/** 
+ *  @defgroup HET HET
+ *  @brief Inter-Integrated Circuit Module.
+ *  
+ *  The HET is a software-controlled timer with a dedicated specialized timer micromachine and a set of 30 instructions.
+ *  The HET micromachine is connected to a port of up to 32 input/output (I/O) pins.
+ *
+ *	Related Files
+ *   - reg_het.h
+ *   - het.h
+ *   - het.c
+ *   - reg_htu.h
+ *   - htu.h
+ *   - std_nhet.h
+ *  @addtogroup HET
+ *  @{
+ */
+ 
+/* HET Interface Functions */
+void hetInit(void);
+
+/* PWM Interface Functions */
+void        pwmStart(hetRAMBASE_t * hetRAM,uint32 pwm);
+void        pwmStop(hetRAMBASE_t * hetRAM,uint32 pwm);
+void        pwmSetDuty(hetRAMBASE_t * hetRAM,uint32 pwm, uint32 pwmDuty);
+void        pwmSetSignal(hetRAMBASE_t * hetRAM,uint32 pwm, hetSIGNAL_t signal);
+hetSIGNAL_t pwmGetSignal(hetRAMBASE_t * hetRAM,uint32 pwm);
+void        pwmEnableNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+void        pwmDisableNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+void        pwmNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+
+/* Edge Interface Functions */
+void     edgeResetCounter(hetRAMBASE_t * hetRAM,uint32 edge);
+uint32 edgeGetCounter(hetRAMBASE_t * hetRAM,uint32 edge);
+void     edgeEnableNotification(hetBASE_t * hetREG,uint32 edge);
+void     edgeDisableNotification(hetBASE_t * hetREG,uint32 edge);
+void     edgeNotification(hetBASE_t * hetREG,uint32 edge);
+
+/* Captured Signal Interface Functions */
+hetSIGNAL_t capGetSignal(hetRAMBASE_t * hetRAM,uint32 cap);
+
+/* Timestamp Interface Functions */
+void     hetResetTimestamp(hetRAMBASE_t * hetRAM);
+uint32 hetGetTimestamp(hetRAMBASE_t * hetRAM);
+
+/** @fn void hetNotification(hetBASE_t *het, uint32 offset)
+*   @brief het interrupt callback
+*   @param[in] het - Het module base address
+*              - hetREG1: HET1 module base address pointer
+*              - hetREG2: HET2 module base address pointer
+*   @param[in] offset - het interrupt offset / Source number
+*
+*   @note This function has to be provide by the user.
+*
+* This is a interrupt callback that is provided by the application and is call upon
+* an het interrupt.  The parameter passed to the callback is a copy of the interrupt 
+* offset register which is used to decode the interrupt source.
+*/
+void hetNotification(hetBASE_t *het, uint32 offset);
+
+/**@}*/
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/htu.h b/bsp/rm48x50/HALCoGen/include/htu.h
new file mode 100644
index 0000000000000000000000000000000000000000..6b4dee5a148285d931fae0ea37eaef4f67a70b2e
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/htu.h
@@ -0,0 +1,25 @@
+/** @file htu.h
+*   @brief HTU Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#ifndef __HTU_H__
+#define __HTU_H__
+
+#include "reg_htu.h"
+
+/* HTU General Definitions */
+
+
+#define HTU1PARLOC		(*(volatile uint32 *)0xFF4E0200U)
+#define HTU2PARLOC		(*(volatile uint32 *)0xFF4C0200U)
+
+#define HTU1RAMLOC		(*(volatile uint32 *)0xFF4E0000U)
+#define HTU2RAMLOC		(*(volatile uint32 *)0xFF4C0000U)
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/hw_emac.h b/bsp/rm48x50/HALCoGen/include/hw_emac.h
new file mode 100644
index 0000000000000000000000000000000000000000..57c34d35099dbc8b6f2ed76e54076925593f36ee
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/hw_emac.h
@@ -0,0 +1,1437 @@
+/*
+ * hw_emac1.h
+ */
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef _HW_EMAC_H_
+#define _HW_EMAC_H_
+
+#define EMAC_BASE               (0xFCF78000U)
+#define EMAC_CTRL_BASE          (0xFCF78800U)
+#define EMAC_CTRL_RAM_BASE      (0xFC520000U)
+
+#define EMAC_TXREVID		    (0x0U)
+#define EMAC_TXCONTROL		    (0x4U)
+#define EMAC_TXTEARDOWN		    (0x8U)
+#define EMAC_RXREVID		    (0x10U)
+#define EMAC_RXCONTROL		    (0x14U)
+#define EMAC_RXTEARDOWN		    (0x18U)
+#define EMAC_TXINTSTATRAW	    (0x80U)
+#define EMAC_TXINTSTATMASKED	(0x84U)
+#define EMAC_TXINTMASKSET	    (0x88U)
+#define EMAC_TXINTMASKCLEAR	    (0x8CU)
+#define EMAC_MACINVECTOR	    (0x90U)
+#define EMAC_MACEOIVECTOR	    (0x94U)
+#define EMAC_RXINTSTATRAW	    (0xA0U)
+#define EMAC_RXINTSTATMASKED	(0xA4U)
+#define EMAC_RXINTMASKSET	    (0xA8U)
+#define EMAC_RXINTMASKCLEAR	    (0xACU)
+#define EMAC_MACINTSTATRAW	    (0xB0U)
+#define EMAC_MACINTSTATMASKED	(0xB4U)
+#define EMAC_MACINTMASKSET	    (0xB8U)
+#define EMAC_MACINTMASKCLEAR	(0xBCU)
+#define EMAC_RXMBPENABLE	    (0x100U)
+#define EMAC_RXUNICASTSET	    (0x104U)
+#define EMAC_RXUNICASTCLEAR   	(0x108U)
+#define EMAC_RXMAXLEN		    (0x10CU)
+#define EMAC_RXBUFFEROFFSET	    (0x110U)
+#define EMAC_RXFILTERLOWTHRESH	(0x114U)
+#define EMAC_RXFLOWTHRESH(n)	(0x120U + ((n) * 4U))
+#define EMAC_RXFREEBUFFER(n)	(0x140U + ((n) * 4U))
+#define EMAC_MACCONTROL		    (0x160U)
+#define EMAC_MACSTATUS		    (0x164U)
+#define EMAC_EMCONTROL		    (0x168U)
+#define EMAC_FIFOCONTROL	    (0x16CU)
+#define EMAC_MACCONFIG		    (0x170U)
+#define EMAC_SOFTRESET		    (0x174U)
+#define EMAC_MACSRCADDRLO	    (0x1D0U)
+#define EMAC_MACSRCADDRHI	    (0x1D4U)
+#define EMAC_MACHASH1		    (0x1D8U)
+#define EMAC_MACHASH2		    (0x1DCU)
+#define EMAC_BOFFTEST		    (0x1E0U)
+#define EMAC_TPACETEST		    (0x1E4U)
+#define EMAC_RXPAUSE		    (0x1E8U)
+#define EMAC_TXPAUSE		    (0x1ECU)
+#define EMAC_RXGOODFRAMES	    (0x200U)
+#define EMAC_RXBCASTFRAMES	    (0x204U)
+#define EMAC_RXMCASTFRAMES	    (0x208U)
+#define EMAC_RXPAUSEFRAMES	    (0x20CU)
+#define EMAC_RXCRCERRORS	    (0x210U)
+#define EMAC_RXALIGNCODEERRORS	(0x214U)
+#define EMAC_RXOVERSIZED	    (0x218U)
+#define EMAC_RXJABBER		    (0x21CU)
+#define EMAC_RXUNDERSIZED	    (0x220U)
+#define EMAC_RXFRAGMENTS	    (0x224U)
+#define EMAC_RXFILTERED		    (0x228U)
+#define EMAC_RXQOSFILTERED	    (0x22CU)
+#define EMAC_RXOCTETS		    (0x230U)
+#define EMAC_TXGOODFRAMES	    (0x234U)
+#define EMAC_TXBCASTFRAMES	    (0x238U)
+#define EMAC_TXMCASTFRAMES	    (0x23CU)
+#define EMAC_TXPAUSEFRAMES	    (0x240U)
+#define EMAC_TXDEFERRED		    (0x244U)
+#define EMAC_TXCOLLISION	    (0x248U)
+#define EMAC_TXSINGLECOLL	    (0x24CU)
+#define EMAC_TXMULTICOLL	    (0x250U)
+#define EMAC_TXEXCESSIVECOLL	(0x254U)
+#define EMAC_TXLATECOLL		    (0x258U)
+#define EMAC_TXUNDERRUN		    (0x25CU)
+#define EMAC_TXCARRIERSENSE   	(0x260U)
+#define EMAC_TXOCTETS		    (0x264U)
+#define EMAC_FRAME64		    (0x268U)
+#define EMAC_FRAME65T127	    (0x26CU)
+#define EMAC_FRAME128T255	    (0x270U)
+#define EMAC_FRAME256T511	    (0x274U)
+#define EMAC_FRAME512T1023	    (0x278U)
+#define EMAC_FRAME1024TUP	    (0x27CU)
+#define EMAC_NETOCTETS		    (0x208U)
+#define EMAC_RXSOFOVERRUNS	    (0x284U)
+#define EMAC_RXMOFOVERRUNS	    (0x288U)
+#define EMAC_RXDMAOVERRUNS	    (0x28CU)
+#define EMAC_MACADDRLO          (0x500U)
+#define EMAC_MACADDRHI          (0x504U)
+#define EMAC_MACINDEX           (0x508U)
+#define EMAC_TXHDP(n)		    (0x600U + ((n) * 4U))
+#define EMAC_RXHDP(n)		    (0x620U + ((n) * 4U))
+#define EMAC_TXCP(n)		    (0x640U + ((n) * 4U))
+#define EMAC_RXCP(n)		    (0x660U + ((n) * 4U))
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* TXREVID */
+
+#define EMAC_TXREVID_TXREV      (0xFFFFFFFFU)
+#define EMAC_TXREVID_TXREV_SHIFT     (0x00000000U)
+
+
+/* TXCONTROL */
+
+
+#define EMAC_TXCONTROL_TXEN     (0x00000001U)
+#define EMAC_TXCONTROL_TXEN_SHIFT    (0x00000000U)
+
+
+/* TXTEARDOWN */
+
+#define EMAC_TXTEARDOWN_TXTDNCH (0x00000007U)
+#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT (0x00000000U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 (0x00000000U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 (0x00000001U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 (0x00000002U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 (0x00000003U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 (0x00000004U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 (0x00000005U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 (0x00000006U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 (0x00000007U)
+
+
+/* RXREVID */
+
+#define EMAC_RXREVID_RXREV      (0xFFFFFFFFU)
+#define EMAC_RXREVID_RXREV_SHIFT     (0x00000000U)
+
+
+/* RXCONTROL */
+
+
+#define EMAC_RXCONTROL_RXEN     (0x00000001U)
+#define EMAC_RXCONTROL_RXEN_SHIFT    (0x00000000U)
+
+/* RXTEARDOWN */
+
+
+
+#define EMAC_RXTEARDOWN_RXTDNCH (0x00000007U)
+#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT (0x00000000U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 (0x00000000U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 (0x00000001U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 (0x00000002U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 (0x00000003U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 (0x00000004U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 (0x00000005U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 (0x00000006U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 (0x00000007U)
+
+
+/* TXINTSTATRAW */
+
+
+#define EMAC_TXINTSTATRAW_TX7PEND (0x00000080U)
+#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_TXINTSTATRAW_TX6PEND (0x00000040U)
+#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_TXINTSTATRAW_TX5PEND (0x00000020U)
+#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_TXINTSTATRAW_TX4PEND (0x00000010U)
+#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_TXINTSTATRAW_TX3PEND (0x00000008U)
+#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_TXINTSTATRAW_TX2PEND (0x00000004U)
+#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_TXINTSTATRAW_TX1PEND (0x00000002U)
+#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_TXINTSTATRAW_TX0PEND (0x00000001U)
+#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT (0x00000000U)
+
+
+/* TXINTSTATMASKED */
+
+
+#define EMAC_TXINTSTATMASKED_TX7PEND (0x00000080U)
+#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_TXINTSTATMASKED_TX6PEND (0x00000040U)
+#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_TXINTSTATMASKED_TX5PEND (0x00000020U)
+#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_TXINTSTATMASKED_TX4PEND (0x00000010U)
+#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_TXINTSTATMASKED_TX3PEND (0x00000008U)
+#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_TXINTSTATMASKED_TX2PEND (0x00000004U)
+#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_TXINTSTATMASKED_TX1PEND (0x00000002U)
+#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_TXINTSTATMASKED_TX0PEND (0x00000001U)
+#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT (0x00000000U)
+
+
+/* TXINTMASKSET */
+
+
+#define EMAC_TXINTMASKSET_TX7MASK (0x00000080U)
+#define EMAC_TXINTMASKSET_TX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_TXINTMASKSET_TX6MASK (0x00000040U)
+#define EMAC_TXINTMASKSET_TX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_TXINTMASKSET_TX5MASK (0x00000020U)
+#define EMAC_TXINTMASKSET_TX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_TXINTMASKSET_TX4MASK (0x00000010U)
+#define EMAC_TXINTMASKSET_TX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_TXINTMASKSET_TX3MASK (0x00000008U)
+#define EMAC_TXINTMASKSET_TX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_TXINTMASKSET_TX2MASK (0x00000004U)
+#define EMAC_TXINTMASKSET_TX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_TXINTMASKSET_TX1MASK (0x00000002U)
+#define EMAC_TXINTMASKSET_TX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_TXINTMASKSET_TX0MASK (0x00000001U)
+#define EMAC_TXINTMASKSET_TX0MASK_SHIFT (0x00000000U)
+
+
+/* TXINTMASKCLEAR */
+
+
+#define EMAC_TXINTMASKCLEAR_TX7MASK (0x00000080U)
+#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_TXINTMASKCLEAR_TX6MASK (0x00000040U)
+#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_TXINTMASKCLEAR_TX5MASK (0x00000020U)
+#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_TXINTMASKCLEAR_TX4MASK (0x00000010U)
+#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_TXINTMASKCLEAR_TX3MASK (0x00000008U)
+#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_TXINTMASKCLEAR_TX2MASK (0x00000004U)
+#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_TXINTMASKCLEAR_TX1MASK (0x00000002U)
+#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_TXINTMASKCLEAR_TX0MASK (0x00000001U)
+#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT (0x00000000U)
+
+
+/* MACINVECTOR */
+
+
+#define EMAC_MACINVECTOR_STATPEND (0x08000000U)
+#define EMAC_MACINVECTOR_STATPEND_SHIFT (0x0000001BU)
+
+#define EMAC_MACINVECTOR_HOSTPEND (0x04000000U)
+#define EMAC_MACINVECTOR_HOSTPEND_SHIFT (0x0000001AU)
+
+#define EMAC_MACINVECTOR_LINKINT0 (0x02000000U)
+#define EMAC_MACINVECTOR_LINKINT0_SHIFT (0x00000019U)
+
+#define EMAC_MACINVECTOR_USERINT0 (0x01000000U)
+#define EMAC_MACINVECTOR_USERINT0_SHIFT (0x00000018U)
+
+#define EMAC_MACINVECTOR_TXPEND (0x00FF0000U)
+#define EMAC_MACINVECTOR_TXPEND_SHIFT (0x00000010U)
+
+#define EMAC_MACINVECTOR_RXTHRESHPEND (0x0000FF00U)
+#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_MACINVECTOR_RXPEND (0x000000FFU)
+#define EMAC_MACINVECTOR_RXPEND_SHIFT (0x00000000U)
+
+
+/* MACEOIVECTOR */
+
+
+#define EMAC_MACEOIVECTOR_INTVECT (0x0000001FU)
+#define EMAC_MACEOIVECTOR_INTVECT_SHIFT (0x00000000U)
+/*----INTVECT Tokens----*/
+#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH (0x00000000U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0RX (0x00000001U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0TX (0x00000002U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0MISC (0x00000003U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH (0x00000004U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1RX (0x00000005U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1TX (0x00000006U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1MISC (0x00000007U)
+
+
+/* RXINTSTATRAW */
+
+
+#define EMAC_RXINTSTATRAW_RX7THRESHPEND (0x00008000U)
+#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTSTATRAW_RX6THRESHPEND (0x00004000U)
+#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTSTATRAW_RX5THRESHPEND (0x00002000U)
+#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTSTATRAW_RX4THRESHPEND (0x00001000U)
+#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTSTATRAW_RX3THRESHPEND (0x00000800U)
+#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTSTATRAW_RX2THRESHPEND (0x00000400U)
+#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTSTATRAW_RX1THRESHPEND (0x00000200U)
+#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT (0x00000009U)
+
+#define EMAC_RXINTSTATRAW_RX0THRESHPEND (0x00000100U)
+#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_RXINTSTATRAW_RX7PEND (0x00000080U)
+#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_RXINTSTATRAW_RX6PEND (0x00000040U)
+#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_RXINTSTATRAW_RX5PEND (0x00000020U)
+#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_RXINTSTATRAW_RX4PEND (0x00000010U)
+#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_RXINTSTATRAW_RX3PEND (0x00000008U)
+#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_RXINTSTATRAW_RX2PEND (0x00000004U)
+#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_RXINTSTATRAW_RX1PEND (0x00000002U)
+#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_RXINTSTATRAW_RX0PEND (0x00000001U)
+#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT (0x00000000U)
+
+
+/* RXINTSTATMASKED */
+
+
+#define EMAC_RXINTSTATMASKED_RX7THRESHPEND (0x00008000U)
+#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTSTATMASKED_RX6THRESHPEND (0x00004000U)
+#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTSTATMASKED_RX5THRESHPEND (0x00002000U)
+#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTSTATMASKED_RX4THRESHPEND (0x00001000U)
+#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTSTATMASKED_RX3THRESHPEND (0x00000800U)
+#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTSTATMASKED_RX2THRESHPEND (0x00000400U)
+#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTSTATMASKED_RX1THRESHPEND (0x00000200U)
+#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT (0x00000009U)
+
+#define EMAC_RXINTSTATMASKED_RX0THRESHPEND (0x00000100U)
+#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_RXINTSTATMASKED_RX7PEND (0x00000080U)
+#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_RXINTSTATMASKED_RX6PEND (0x00000040U)
+#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_RXINTSTATMASKED_RX5PEND (0x00000020U)
+#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_RXINTSTATMASKED_RX4PEND (0x00000010U)
+#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_RXINTSTATMASKED_RX3PEND (0x00000008U)
+#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_RXINTSTATMASKED_RX2PEND (0x00000004U)
+#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_RXINTSTATMASKED_RX1PEND (0x00000002U)
+#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_RXINTSTATMASKED_RX0PEND (0x00000001U)
+#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT (0x00000000U)
+
+
+/* RXINTMASKSET */
+
+
+#define EMAC_RXINTMASKSET_RX7THRESHMASK (0x00008000U)
+#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTMASKSET_RX6THRESHMASK (0x00004000U)
+#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTMASKSET_RX5THRESHMASK (0x00002000U)
+#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTMASKSET_RX4THRESHMASK (0x00001000U)
+#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTMASKSET_RX3THRESHMASK (0x00000800U)
+#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTMASKSET_RX2THRESHMASK (0x00000400U)
+#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTMASKSET_RX1THRESHMASK (0x00000200U)
+#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT (0x00000009U)
+
+#define EMAC_RXINTMASKSET_RX0THRESHMASK (0x00000100U)
+#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT (0x00000008U)
+
+#define EMAC_RXINTMASKSET_RX7MASK (0x00000080U)
+#define EMAC_RXINTMASKSET_RX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_RXINTMASKSET_RX6MASK (0x00000040U)
+#define EMAC_RXINTMASKSET_RX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_RXINTMASKSET_RX5MASK (0x00000020U)
+#define EMAC_RXINTMASKSET_RX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_RXINTMASKSET_RX4MASK (0x00000010U)
+#define EMAC_RXINTMASKSET_RX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_RXINTMASKSET_RX3MASK (0x00000008U)
+#define EMAC_RXINTMASKSET_RX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_RXINTMASKSET_RX2MASK (0x00000004U)
+#define EMAC_RXINTMASKSET_RX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_RXINTMASKSET_RX1MASK (0x00000002U)
+#define EMAC_RXINTMASKSET_RX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_RXINTMASKSET_RX0MASK (0x00000001U)
+#define EMAC_RXINTMASKSET_RX0MASK_SHIFT (0x00000000U)
+
+
+/* RXINTMASKCLEAR */
+
+
+#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK (0x00008000U)
+#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK (0x00004000U)
+#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK (0x00002000U)
+#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK (0x00001000U)
+#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK (0x00000800U)
+#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK (0x00000400U)
+#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK (0x00000200U)
+#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT (0x00000009U)
+
+#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK (0x00000100U)
+#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT (0x00000008U)
+
+#define EMAC_RXINTMASKCLEAR_RX7MASK (0x00000080U)
+#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_RXINTMASKCLEAR_RX6MASK (0x00000040U)
+#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_RXINTMASKCLEAR_RX5MASK (0x00000020U)
+#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_RXINTMASKCLEAR_RX4MASK (0x00000010U)
+#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_RXINTMASKCLEAR_RX3MASK (0x00000008U)
+#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_RXINTMASKCLEAR_RX2MASK (0x00000004U)
+#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_RXINTMASKCLEAR_RX1MASK (0x00000002U)
+#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_RXINTMASKCLEAR_RX0MASK (0x00000001U)
+#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT (0x00000000U)
+
+
+/* MACINTSTATRAW */
+
+
+#define EMAC_MACINTSTATRAW_HOSTPEND (0x00000002U)
+#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT (0x00000001U)
+
+#define EMAC_MACINTSTATRAW_STATPEND (0x00000001U)
+#define EMAC_MACINTSTATRAW_STATPEND_SHIFT (0x00000000U)
+
+
+/* MACINTSTATMASKED */
+
+
+#define EMAC_MACINTSTATMASKED_HOSTPEND (0x00000002U)
+#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT (0x00000001U)
+
+#define EMAC_MACINTSTATMASKED_STATPEND (0x00000001U)
+#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT (0x00000000U)
+
+
+/* MACINTMASKSET */
+
+
+#define EMAC_MACINTMASKSET_HOSTMASK (0x00000002U)
+#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT (0x00000001U)
+
+#define EMAC_MACINTMASKSET_STATMASK (0x00000001U)
+#define EMAC_MACINTMASKSET_STATMASK_SHIFT (0x00000000U)
+
+
+/* MACINTMASKCLEAR */
+
+
+#define EMAC_MACINTMASKCLEAR_HOSTMASK (0x00000002U)
+#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT (0x00000001U)
+
+#define EMAC_MACINTMASKCLEAR_STATMASK (0x00000001U)
+#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT (0x00000000U)
+
+
+/* RXMBPENABLE */
+
+
+#define EMAC_RXMBPENABLE_RXPASSCRC (0x40000000U)
+#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT (0x0000001EU)
+#define EMAC_RXMBPENABLE_RXQOSEN (0x20000000U)
+#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT (0x0000001DU)
+#define EMAC_RXMBPENABLE_RXNOCHAIN (0x10000000U)
+#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT (0x0000001CU)
+#define EMAC_RXMBPENABLE_RXCMFEN (0x01000000U)
+#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT (0x00000018U)
+#define EMAC_RXMBPENABLE_RXCSFEN (0x00800000U)
+#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT (0x00000017U)
+#define EMAC_RXMBPENABLE_RXCEFEN (0x00400000U)
+#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT (0x00000016U)
+#define EMAC_RXMBPENABLE_RXCAFEN (0x00200000U)
+#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT (0x00000015U)
+/*----RXCAFEN Tokens----*/
+#define EMAC_RXMBPENABLE_RXPROMCH (0x00070000U)
+#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT (0x00000010U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 (0x00000007U)
+
+
+#define EMAC_RXMBPENABLE_RXBROADEN (0x00002000U)
+#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT (0x0000000DU)
+#define EMAC_RXMBPENABLE_RXBROADCH (0x00000700U)
+#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT (0x00000008U)
+/*----RXBROADCH Tokens----*/
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 (0x00000007U)
+
+
+#define EMAC_RXMBPENABLE_RXMULTEN (0x00000020U)
+#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT (0x00000005U)
+#define EMAC_RXMBPENABLE_RXMULTCH (0x00000007U)
+#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT (0x00000000U)
+/*----RXMULTCH Tokens----*/
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 (0x00000007U)
+
+
+/* RXUNICASTSET */
+
+
+#define EMAC_RXUNICASTSET_RXCH7EN (0x00000080U)
+#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT (0x00000007U)
+#define EMAC_RXUNICASTSET_RXCH6EN (0x00000040U)
+#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT (0x00000006U)
+#define EMAC_RXUNICASTSET_RXCH5EN (0x00000020U)
+#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT (0x00000005U)
+#define EMAC_RXUNICASTSET_RXCH4EN (0x00000010U)
+#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT (0x00000004U)
+#define EMAC_RXUNICASTSET_RXCH3EN (0x00000008U)
+#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT (0x00000003U)
+#define EMAC_RXUNICASTSET_RXCH2EN (0x00000004U)
+#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT (0x00000002U)
+#define EMAC_RXUNICASTSET_RXCH1EN (0x00000002U)
+#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT (0x00000001U)
+#define EMAC_RXUNICASTSET_RXCH0EN (0x00000001U)
+#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT (0x00000000U)
+
+/* RXUNICASTCLEAR */
+
+
+#define EMAC_RXUNICASTCLEAR_RXCH7EN (0x00000080U)
+#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT (0x00000007U)
+#define EMAC_RXUNICASTCLEAR_RXCH6EN (0x00000040U)
+#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT (0x00000006U)
+#define EMAC_RXUNICASTCLEAR_RXCH5EN (0x00000020U)
+#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT (0x00000005U)
+#define EMAC_RXUNICASTCLEAR_RXCH4EN (0x00000010U)
+#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT (0x00000004U)
+#define EMAC_RXUNICASTCLEAR_RXCH3EN (0x00000008U)
+#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT (0x00000003U)
+#define EMAC_RXUNICASTCLEAR_RXCH2EN (0x00000004U)
+#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT (0x00000002U)
+#define EMAC_RXUNICASTCLEAR_RXCH1EN (0x00000002U)
+#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT (0x00000001U)
+#define EMAC_RXUNICASTCLEAR_RXCH0EN (0x00000001U)
+#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT (0x00000000U)
+
+/* RXMAXLEN */
+
+
+#define EMAC_RXMAXLEN_RXMAXLEN  (0x0000FFFFU)
+#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT (0x00000000U)
+
+
+/* RXBUFFEROFFSET */
+
+
+#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET (0x0000FFFFU)
+#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT (0x00000000U)
+
+
+/* RXFILTERLOWTHRESH */
+
+
+#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH (0x000000FFU)
+#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT (0x00000000U)
+
+
+/* RX0FLOWTHRESH */
+
+
+#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH (0x000000FFU)
+#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX1FLOWTHRESH */
+
+
+#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH (0x000000FFU)
+#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX2FLOWTHRESH */
+
+
+#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH (0x000000FFU)
+#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX3FLOWTHRESH */
+
+
+#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH (0x000000FFU)
+#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX4FLOWTHRESH */
+
+
+#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH (0x000000FFU)
+#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX5FLOWTHRESH */
+
+
+#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH (0x000000FFU)
+#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX6FLOWTHRESH */
+
+
+#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH (0x000000FFU)
+#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX7FLOWTHRESH */
+
+
+#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH (0x000000FFU)
+#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX0FREEBUFFER */
+
+
+#define EMAC_RX0FREEBUFFER_RX0FREEBUF (0x0000FFFFU)
+#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX1FREEBUFFER */
+
+
+#define EMAC_RX1FREEBUFFER_RX1FREEBUF (0x0000FFFFU)
+#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX2FREEBUFFER */
+
+
+#define EMAC_RX2FREEBUFFER_RX2FREEBUF (0x0000FFFFU)
+#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX3FREEBUFFER */
+
+
+#define EMAC_RX3FREEBUFFER_RX3FREEBUF (0x0000FFFFU)
+#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX4FREEBUFFER */
+
+
+#define EMAC_RX4FREEBUFFER_RX4FREEBUF (0x0000FFFFU)
+#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX5FREEBUFFER */
+
+
+#define EMAC_RX5FREEBUFFER_RX5FREEBUF (0x0000FFFFU)
+#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX6FREEBUFFER */
+
+
+#define EMAC_RX6FREEBUFFER_RX6FREEBUF (0x0000FFFFU)
+#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX7FREEBUFFER */
+
+
+#define EMAC_RX7FREEBUFFER_RX7FREEBUF (0x0000FFFFU)
+#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT (0x00000000U)
+
+
+/* MACCONTROL */
+
+
+
+
+
+#define EMAC_MACCONTROL_RMIISPEED (0x00008000U)
+#define EMAC_MACCONTROL_RMIISPEED_SHIFT (0x0000000FU)
+#define EMAC_MACCONTROL_RXOFFLENBLOCK (0x00004000U)
+#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT (0x0000000EU)
+#define EMAC_MACCONTROL_RXOWNERSHIP (0x00002000U)
+#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT (0x0000000DU)
+#define EMAC_MACCONTROL_CMDIDLE (0x00000800U)
+#define EMAC_MACCONTROL_CMDIDLE_SHIFT (0x0000000BU)
+#define EMAC_MACCONTROL_TXSHORTGAPEN (0x00000400U)
+#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT (0x0000000AU)
+#define EMAC_MACCONTROL_TXPTYPE (0x00000200U)
+#define EMAC_MACCONTROL_TXPTYPE_SHIFT (0x00000009U)
+#define EMAC_MACCONTROL_TXPACE  (0x00000040U)
+#define EMAC_MACCONTROL_TXPACE_SHIFT (0x00000006U)
+#define EMAC_MACCONTROL_GMIIEN  (0x00000020U)
+#define EMAC_MACCONTROL_GMIIEN_SHIFT (0x00000005U)
+#define EMAC_MACCONTROL_TXFLOWEN (0x00000010U)
+#define EMAC_MACCONTROL_TXFLOWEN_SHIFT (0x00000004U)
+#define EMAC_MACCONTROL_RXBUFFERFLOWEN (0x00000008U)
+#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT (0x00000003U)
+#define EMAC_MACCONTROL_LOOPBACK (0x00000002U)
+#define EMAC_MACCONTROL_LOOPBACK_SHIFT (0x00000001U)
+#define EMAC_MACCONTROL_FULLDUPLEX (0x00000001U)
+#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT (0x00000000U)
+
+
+/* MACSTATUS */
+
+#define EMAC_MACSTATUS_IDLE     (0x80000000U)
+#define EMAC_MACSTATUS_IDLE_SHIFT    (0x0000001FU)
+#define EMAC_MACSTATUS_TXERRCODE (0x00F00000U)
+#define EMAC_MACSTATUS_TXERRCODE_SHIFT (0x00000014U)
+/*----TXERRCODE Tokens----*/
+#define EMAC_MACSTATUS_TXERRCODE_NOERROR (0x00000000U)
+#define EMAC_MACSTATUS_TXERRCODE_SOPERROR (0x00000001U)
+#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP (0x00000002U)
+#define EMAC_MACSTATUS_TXERRCODE_NOEOP (0x00000003U)
+#define EMAC_MACSTATUS_TXERRCODE_NULLPTR (0x00000004U)
+#define EMAC_MACSTATUS_TXERRCODE_NULLEN (0x00000005U)
+#define EMAC_MACSTATUS_TXERRCODE_LENERROR (0x00000006U)
+
+
+#define EMAC_MACSTATUS_TXERRCH  (0x00070000U)
+#define EMAC_MACSTATUS_TXERRCH_SHIFT (0x00000010U)
+/*----TXERRCH Tokens----*/
+#define EMAC_MACSTATUS_TXERRCH_CHA0  (0x00000000U)
+#define EMAC_MACSTATUS_TXERRCH_CHA1  (0x00000001U)
+#define EMAC_MACSTATUS_TXERRCH_CHA2  (0x00000002U)
+#define EMAC_MACSTATUS_TXERRCH_CHA3  (0x00000003U)
+#define EMAC_MACSTATUS_TXERRCH_CHA4  (0x00000004U)
+#define EMAC_MACSTATUS_TXERRCH_CHA5  (0x00000005U)
+#define EMAC_MACSTATUS_TXERRCH_CHA6  (0x00000006U)
+#define EMAC_MACSTATUS_TXERRCH_CHA7  (0x00000007U)
+
+#define EMAC_MACSTATUS_RXERRCODE (0x0000F000U)
+#define EMAC_MACSTATUS_RXERRCODE_SHIFT (0x0000000CU)
+/*----RXERRCODE Tokens----*/
+#define EMAC_MACSTATUS_RXERRCODE_NOERROR (0x00000000U)
+#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP (0x00000002U)
+#define EMAC_MACSTATUS_RXERRCODE_NULLPTR (0x00000004U)
+
+
+#define EMAC_MACSTATUS_RXERRCH  (0x00000700U)
+#define EMAC_MACSTATUS_RXERRCH_SHIFT (0x00000008U)
+/*----RXERRCH Tokens----*/
+#define EMAC_MACSTATUS_RXERRCH_CHA0  (0x00000000U)
+#define EMAC_MACSTATUS_RXERRCH_CHA1  (0x00000001U)
+#define EMAC_MACSTATUS_RXERRCH_CHA2  (0x00000002U)
+#define EMAC_MACSTATUS_RXERRCH_CHA3  (0x00000003U)
+#define EMAC_MACSTATUS_RXERRCH_CHA4  (0x00000004U)
+#define EMAC_MACSTATUS_RXERRCH_CHA5  (0x00000005U)
+#define EMAC_MACSTATUS_RXERRCH_CHA6  (0x00000006U)
+#define EMAC_MACSTATUS_RXERRCH_CHA7  (0x00000007U)
+
+
+
+
+#define EMAC_MACSTATUS_RXQOSACT (0x00000004U)
+#define EMAC_MACSTATUS_RXQOSACT_SHIFT (0x00000002U)
+#define EMAC_MACSTATUS_RXFLOWACT (0x00000002U)
+#define EMAC_MACSTATUS_RXFLOWACT_SHIFT (0x00000001U)
+#define EMAC_MACSTATUS_TXFLOWACT (0x00000001U)
+#define EMAC_MACSTATUS_TXFLOWACT_SHIFT (0x00000000U)
+
+/* EMCONTROL */
+
+
+#define EMAC_EMCONTROL_SOFT     (0x00000002U)
+#define EMAC_EMCONTROL_SOFT_SHIFT    (0x00000001U)
+
+#define EMAC_EMCONTROL_FREE     (0x00000001U)
+#define EMAC_EMCONTROL_FREE_SHIFT    (0x00000000U)
+
+
+/* FIFOCONTROL */
+
+
+#define EMAC_FIFOCONTROL_TXCELLTHRESH (0x00000003U)
+#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT (0x00000000U)
+
+
+/* MACCONFIG */
+
+#define EMAC_MACCONFIG_TXCELLDEPTH (0xFF000000U)
+#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT (0x00000018U)
+
+#define EMAC_MACCONFIG_RXCELLDEPTH (0x00FF0000U)
+#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT (0x00000010U)
+
+#define EMAC_MACCONFIG_ADDRESSTYPE (0x0000FF00U)
+#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT (0x00000008U)
+
+#define EMAC_MACCONFIG_MACCFIG  (0x000000FFU)
+#define EMAC_MACCONFIG_MACCFIG_SHIFT (0x00000000U)
+
+
+/* SOFTRESET */
+
+
+#define EMAC_SOFTRESET_SOFTRESET (0x00000001U)
+#define EMAC_SOFTRESET_SOFTRESET_SHIFT (0x00000000U)
+
+/* MACSRCADDRLO */
+
+
+#define EMAC_MACSRCADDRLO_MACSRCADDR0 (0x0000FF00U)
+#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT (0x00000008U)
+#define EMAC_MACSRCADDRLO_MACSRCADDR1 (0x000000FFU)
+#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT (0x00000000U)
+
+
+/* MACSRCADDRHI */
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR2 (0xFF000000U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT (0x00000018U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR3 (0x00FF0000U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT (0x00000010U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR4 (0x0000FF00U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT (0x00000008U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR5 (0x000000FFU)
+#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT (0x00000000U)
+
+
+/* MACHASH1 */
+
+#define EMAC_MACHASH1_MACHASH1  (0xFFFFFFFFU)
+#define EMAC_MACHASH1_MACHASH1_SHIFT (0x00000000U)
+
+
+/* MACHASH2 */
+
+#define EMAC_MACHASH2_MACHASH2  (0xFFFFFFFFU)
+#define EMAC_MACHASH2_MACHASH2_SHIFT (0x00000000U)
+
+
+/* BOFFTEST */
+
+
+#define EMAC_BOFFTEST_RNDNUM    (0x03FF0000U)
+#define EMAC_BOFFTEST_RNDNUM_SHIFT   (0x00000010U)
+
+#define EMAC_BOFFTEST_COLLCOUNT (0x0000F000U)
+#define EMAC_BOFFTEST_COLLCOUNT_SHIFT (0x0000000CU)
+
+
+#define EMAC_BOFFTEST_TXBACKOFF (0x000003FFU)
+#define EMAC_BOFFTEST_TXBACKOFF_SHIFT (0x00000000U)
+
+
+/* TPACETEST */
+
+
+#define EMAC_TPACETEST_PACEVAL  (0x0000001FU)
+#define EMAC_TPACETEST_PACEVAL_SHIFT (0x00000000U)
+
+
+/* RXPAUSE */
+
+
+#define EMAC_RXPAUSE_PAUSETIMER (0x0000FFFFU)
+#define EMAC_RXPAUSE_PAUSETIMER_SHIFT (0x00000000U)
+
+
+/* TXPAUSE */
+
+
+#define EMAC_TXPAUSE_PAUSETIMER (0x0000FFFFU)
+#define EMAC_TXPAUSE_PAUSETIMER_SHIFT (0x00000000U)
+
+
+/* RXGOODFRAMES */
+
+#define EMAC_RXGOODFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXGOODFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXBCASTFRAMES */
+
+#define EMAC_RXBCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXBCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXMCASTFRAMES */
+
+#define EMAC_RXMCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXMCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXPAUSEFRAMES */
+
+#define EMAC_RXPAUSEFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXCRCERRORS */
+
+#define EMAC_RXCRCERRORS_COUNT  (0xFFFFFFFFU)
+#define EMAC_RXCRCERRORS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXALIGNCODEERRORS */
+
+#define EMAC_RXALIGNCODEERRORS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXOVERSIZED */
+
+#define EMAC_RXOVERSIZED_COUNT  (0xFFFFFFFFU)
+#define EMAC_RXOVERSIZED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXJABBER */
+
+#define EMAC_RXJABBER_COUNT     (0xFFFFFFFFU)
+#define EMAC_RXJABBER_COUNT_SHIFT    (0x00000000U)
+
+
+/* RXUNDERSIZED */
+
+#define EMAC_RXUNDERSIZED_COUNT (0xFFFFFFFFU)
+#define EMAC_RXUNDERSIZED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXFRAGMENTS */
+
+#define EMAC_RXFRAGMENTS_COUNT  (0xFFFFFFFFU)
+#define EMAC_RXFRAGMENTS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXFILTERED */
+
+#define EMAC_RXFILTERED_COUNT   (0xFFFFFFFFU)
+#define EMAC_RXFILTERED_COUNT_SHIFT  (0x00000000U)
+
+
+/* RXQOSFILTERED */
+
+#define EMAC_RXQOSFILTERED_COUNT (0xFFFFFFFFU)
+#define EMAC_RXQOSFILTERED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXOCTETS */
+
+#define EMAC_RXOCTETS_COUNT     (0xFFFFFFFFU)
+#define EMAC_RXOCTETS_COUNT_SHIFT    (0x00000000U)
+
+
+/* TXGOODFRAMES */
+
+#define EMAC_TXGOODFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXGOODFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXBCASTFRAMES */
+
+#define EMAC_TXBCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXBCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXMCASTFRAMES */
+
+#define EMAC_TXMCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXMCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXPAUSEFRAMES */
+
+#define EMAC_TXPAUSEFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXDEFERRED */
+
+#define EMAC_TXDEFERRED_COUNT   (0xFFFFFFFFU)
+#define EMAC_TXDEFERRED_COUNT_SHIFT  (0x00000000U)
+
+
+/* TXCOLLISION */
+
+#define EMAC_TXCOLLISION_COUNT  (0xFFFFFFFFU)
+#define EMAC_TXCOLLISION_COUNT_SHIFT (0x00000000U)
+
+
+/* TXSINGLECOLL */
+
+#define EMAC_TXSINGLECOLL_COUNT (0xFFFFFFFFU)
+#define EMAC_TXSINGLECOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXMULTICOLL */
+
+#define EMAC_TXMULTICOLL_COUNT  (0xFFFFFFFFU)
+#define EMAC_TXMULTICOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXEXCESSIVECOLL */
+
+#define EMAC_TXEXCESSIVECOLL_COUNT (0xFFFFFFFFU)
+#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXLATECOLL */
+
+#define EMAC_TXLATECOLL_COUNT   (0xFFFFFFFFU)
+#define EMAC_TXLATECOLL_COUNT_SHIFT  (0x00000000U)
+
+
+/* TXUNDERRUN */
+
+#define EMAC_TXUNDERRUN_COUNT   (0xFFFFFFFFU)
+#define EMAC_TXUNDERRUN_COUNT_SHIFT  (0x00000000U)
+
+
+/* TXCARRIERSENSE */
+
+#define EMAC_TXCARRIERSENSE_COUNT (0xFFFFFFFFU)
+#define EMAC_TXCARRIERSENSE_COUNT_SHIFT (0x00000000U)
+
+
+/* TXOCTETS */
+
+#define EMAC_TXOCTETS_COUNT     (0xFFFFFFFFU)
+#define EMAC_TXOCTETS_COUNT_SHIFT    (0x00000000U)
+
+
+/* FRAME64 */
+
+#define EMAC_FRAME64_COUNT      (0xFFFFFFFFU)
+#define EMAC_FRAME64_COUNT_SHIFT     (0x00000000U)
+
+
+/* FRAME65T127 */
+
+#define EMAC_FRAME65T127_COUNT  (0xFFFFFFFFU)
+#define EMAC_FRAME65T127_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME128T255 */
+
+#define EMAC_FRAME128T255_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME128T255_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME256T511 */
+
+#define EMAC_FRAME256T511_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME256T511_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME512T1023 */
+
+#define EMAC_FRAME512T1023_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME512T1023_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME1024TUP */
+
+#define EMAC_FRAME1024TUP_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME1024TUP_COUNT_SHIFT (0x00000000U)
+
+
+/* NETOCTETS */
+
+#define EMAC_NETOCTETS_COUNT    (0xFFFFFFFFU)
+#define EMAC_NETOCTETS_COUNT_SHIFT   (0x00000000U)
+
+
+/* RXSOFOVERRUNS */
+
+#define EMAC_RXSOFOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXMOFOVERRUNS */
+
+#define EMAC_RXMOFOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXDMAOVERRUNS */
+
+#define EMAC_RXDMAOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* MACADDRLO */
+
+
+#define EMAC_MACADDRLO_VALID    (0x00100000U)
+#define EMAC_MACADDRLO_VALID_SHIFT   (0x00000014U)
+#define EMAC_MACADDRLO_MATCHFILT (0x00080000U)
+#define EMAC_MACADDRLO_MATCHFILT_SHIFT (0x00000013U)
+#define EMAC_MACADDRLO_CHANNEL  (0x00070000U)
+#define EMAC_MACADDRLO_CHANNEL_SHIFT (0x00000010U)
+#define EMAC_MACADDRLO_MACADDR0 (0x0000FF00U)
+#define EMAC_MACADDRLO_MACADDR0_SHIFT (0x00000008U)
+#define EMAC_MACADDRLO_MACADDR1 (0x000000FFU)
+#define EMAC_MACADDRLO_MACADDR1_SHIFT (0x00000000U)
+
+
+/* MACADDRHI */
+
+#define EMAC_MACADDRHI_MACADDR2 (0xFF000000U)
+#define EMAC_MACADDRHI_MACADDR2_SHIFT (0x00000018U)
+
+#define EMAC_MACADDRHI_MACADDR3 (0x00FF0000U)
+#define EMAC_MACADDRHI_MACADDR3_SHIFT (0x00000010U)
+
+#define EMAC_MACADDRHI_MACADDR4 (0x0000FF00U)
+#define EMAC_MACADDRHI_MACADDR4_SHIFT (0x00000008U)
+
+#define EMAC_MACADDRHI_MACADDR5 (0x000000FFU)
+#define EMAC_MACADDRHI_MACADDR5_SHIFT (0x00000000U)
+
+
+/* MACINDEX */
+
+
+#define EMAC_MACINDEX_MACINDEX  (0x0000001FU)
+#define EMAC_MACINDEX_MACINDEX_SHIFT (0x00000000U)
+
+
+/* TX0HDP */
+
+#define EMAC_TX0HDP_TX0HDP      (0xFFFFFFFFU)
+#define EMAC_TX0HDP_TX0HDP_SHIFT     (0x00000000U)
+
+
+/* TX1HDP */
+
+#define EMAC_TX1HDP_TX1HDP      (0xFFFFFFFFU)
+#define EMAC_TX1HDP_TX1HDP_SHIFT     (0x00000000U)
+
+
+/* TX2HDP */
+
+#define EMAC_TX2HDP_TX2HDP      (0xFFFFFFFFU)
+#define EMAC_TX2HDP_TX2HDP_SHIFT     (0x00000000U)
+
+
+/* TX3HDP */
+
+#define EMAC_TX3HDP_TX3HDP      (0xFFFFFFFFU)
+#define EMAC_TX3HDP_TX3HDP_SHIFT     (0x00000000U)
+
+
+/* TX4HDP */
+
+#define EMAC_TX4HDP_TX4HDP      (0xFFFFFFFFU)
+#define EMAC_TX4HDP_TX4HDP_SHIFT     (0x00000000U)
+
+
+/* TX5HDP */
+
+#define EMAC_TX5HDP_TX5HDP      (0xFFFFFFFFU)
+#define EMAC_TX5HDP_TX5HDP_SHIFT     (0x00000000U)
+
+
+/* TX6HDP */
+
+#define EMAC_TX6HDP_TX6HDP      (0xFFFFFFFFU)
+#define EMAC_TX6HDP_TX6HDP_SHIFT     (0x00000000U)
+
+
+/* TX7HDP */
+
+#define EMAC_TX7HDP_TX7HDP      (0xFFFFFFFFU)
+#define EMAC_TX7HDP_TX7HDP_SHIFT     (0x00000000U)
+
+
+/* RX0HDP */
+
+#define EMAC_RX0HDP_RX0HDP      (0xFFFFFFFFU)
+#define EMAC_RX0HDP_RX0HDP_SHIFT     (0x00000000U)
+
+
+/* RX1HDP */
+
+#define EMAC_RX1HDP_RX1HDP      (0xFFFFFFFFU)
+#define EMAC_RX1HDP_RX1HDP_SHIFT     (0x00000000U)
+
+
+/* RX2HDP */
+
+#define EMAC_RX2HDP_RX2HDP      (0xFFFFFFFFU)
+#define EMAC_RX2HDP_RX2HDP_SHIFT     (0x00000000U)
+
+
+/* RX3HDP */
+
+#define EMAC_RX3HDP_RX3HDP      (0xFFFFFFFFU)
+#define EMAC_RX3HDP_RX3HDP_SHIFT     (0x00000000U)
+
+
+/* RX4HDP */
+
+#define EMAC_RX4HDP_RX4HDP      (0xFFFFFFFFU)
+#define EMAC_RX4HDP_RX4HDP_SHIFT     (0x00000000U)
+
+
+/* RX5HDP */
+
+#define EMAC_RX5HDP_RX5HDP      (0xFFFFFFFFU)
+#define EMAC_RX5HDP_RX5HDP_SHIFT     (0x00000000U)
+
+
+/* RX6HDP */
+
+#define EMAC_RX6HDP_RX6HDP      (0xFFFFFFFFU)
+#define EMAC_RX6HDP_RX6HDP_SHIFT     (0x00000000U)
+
+
+/* RX7HDP */
+
+#define EMAC_RX7HDP_RX7HDP      (0xFFFFFFFFU)
+#define EMAC_RX7HDP_RX7HDP_SHIFT     (0x00000000U)
+
+
+/* TX0CP */
+
+#define EMAC_TX0CP_TX0CP        (0xFFFFFFFFU)
+#define EMAC_TX0CP_TX0CP_SHIFT       (0x00000000U)
+
+
+/* TX1CP */
+
+#define EMAC_TX1CP_TX1CP        (0xFFFFFFFFU)
+#define EMAC_TX1CP_TX1CP_SHIFT       (0x00000000U)
+
+
+/* TX2CP */
+
+#define EMAC_TX2CP_TX2CP        (0xFFFFFFFFU)
+#define EMAC_TX2CP_TX2CP_SHIFT       (0x00000000U)
+
+
+/* TX3CP */
+
+#define EMAC_TX3CP_TX3CP        (0xFFFFFFFFU)
+#define EMAC_TX3CP_TX3CP_SHIFT       (0x00000000U)
+
+
+/* TX4CP */
+
+#define EMAC_TX4CP_TX4CP        (0xFFFFFFFFU)
+#define EMAC_TX4CP_TX4CP_SHIFT       (0x00000000U)
+
+
+/* TX5CP */
+
+#define EMAC_TX5CP_TX5CP        (0xFFFFFFFFU)
+#define EMAC_TX5CP_TX5CP_SHIFT       (0x00000000U)
+
+
+/* TX6CP */
+
+#define EMAC_TX6CP_TX6CP        (0xFFFFFFFFU)
+#define EMAC_TX6CP_TX6CP_SHIFT       (0x00000000U)
+
+
+/* TX7CP */
+
+#define EMAC_TX7CP_TX7CP        (0xFFFFFFFFU)
+#define EMAC_TX7CP_TX7CP_SHIFT       (0x00000000U)
+
+
+/* RX0CP */
+
+#define EMAC_RX0CP_RX0CP        (0xFFFFFFFFU)
+#define EMAC_RX0CP_RX0CP_SHIFT       (0x00000000U)
+
+
+/* RX1CP */
+
+#define EMAC_RX1CP_RX1CP        (0xFFFFFFFFU)
+#define EMAC_RX1CP_RX1CP_SHIFT       (0x00000000U)
+
+
+/* RX2CP */
+
+#define EMAC_RX2CP_RX2CP        (0xFFFFFFFFU)
+#define EMAC_RX2CP_RX2CP_SHIFT       (0x00000000U)
+
+
+/* RX3CP */
+
+#define EMAC_RX3CP_RX3CP        (0xFFFFFFFFU)
+#define EMAC_RX3CP_RX3CP_SHIFT       (0x00000000U)
+
+
+/* RX4CP */
+
+#define EMAC_RX4CP_RX4CP        (0xFFFFFFFFU)
+#define EMAC_RX4CP_RX4CP_SHIFT       (0x00000000U)
+
+
+/* RX5CP */
+
+#define EMAC_RX5CP_RX5CP        (0xFFFFFFFFU)
+#define EMAC_RX5CP_RX5CP_SHIFT       (0x00000000U)
+
+
+/* RX6CP */
+
+#define EMAC_RX6CP_RX6CP        (0xFFFFFFFFU)
+#define EMAC_RX6CP_RX6CP_SHIFT       (0x00000000U)
+
+
+/* RX7CP */
+
+#define EMAC_RX7CP_RX7CP        (0xFFFFFFFFU)
+#define EMAC_RX7CP_RX7CP_SHIFT       (0x00000000U)
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/hw_emac_ctrl.h b/bsp/rm48x50/HALCoGen/include/hw_emac_ctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..e43a15b4d1b6c7d12733983309d1d7ad65a133c0
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/hw_emac_ctrl.h
@@ -0,0 +1,50 @@
+/*
+ * hw_emac1.h
+ */
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef _HW_EMAC_CTRL_H_
+#define _HW_EMAC_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define EMAC_CTRL_REVID              (0x0U)
+#define EMAC_CTRL_SOFTRESET          (0x4U)
+#define EMAC_CTRL_INTCONTROL         (0xCU)
+#define EMAC_CTRL_C0RXTHRESHEN       (0x10U)
+#define EMAC_CTRL_CnRXEN(n)          (0x14u + ((n) << 4))
+#define EMAC_CTRL_CnTXEN(n)          (0x18u + ((n) << 4))
+#define EMAC_CTRL_CnMISCEN(n)        (0x1Cu + ((n) << 4))
+#define EMAC_CTRL_CnRXTHRESHEN(n)    (0x20u + ((n) << 4))
+#define EMAC_CTRL_C0RXTHRESHSTAT     (0x40U)
+#define EMAC_CTRL_C0RXSTAT           (0x44U)
+#define EMAC_CTRL_C0TXSTAT           (0x48U)
+#define EMAC_CTRL_C0MISCSTAT         (0x4CU)
+#define EMAC_CTRL_C1RXTHRESHSTAT     (0x50U)
+#define EMAC_CTRL_C1RXSTAT           (0x54U)
+#define EMAC_CTRL_C1TXSTAT           (0x58U)
+#define EMAC_CTRL_C1MISCSTAT         (0x5CU)
+#define EMAC_CTRL_C2RXTHRESHSTAT     (0x60U)
+#define EMAC_CTRL_C2RXSTAT           (0x64U)
+#define EMAC_CTRL_C2TXSTAT           (0x68U)
+#define EMAC_CTRL_C2MISCSTAT         (0x6CU)
+#define EMAC_CTRL_C0RXIMAX           (0x70U)
+#define EMAC_CTRL_C0TXIMAX           (0x74U)
+#define EMAC_CTRL_C1RXIMAX           (0x78U)
+#define EMAC_CTRL_C1TXIMAX           (0x7CU)
+#define EMAC_CTRL_C2RXIMAX           (0x80U)
+#define EMAC_CTRL_C2TXIMAX           (0x84U)
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/hw_mdio.h b/bsp/rm48x50/HALCoGen/include/hw_mdio.h
new file mode 100644
index 0000000000000000000000000000000000000000..dfacf2b7f5fbe58ccd681b60792fbbb5e02aa7fd
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/hw_mdio.h
@@ -0,0 +1,223 @@
+/*
+ * hw_mdio.h
+ */
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef _HW_MDIO_H_
+#define _HW_MDIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MDIO_BASE               (0xFCF78900U)
+
+#define MDIO_REVID		        (0x0U)
+#define MDIO_CONTROL		    (0x4U)
+#define MDIO_ALIVE		        (0x8U)
+#define MDIO_LINK		        (0xCU)
+#define MDIO_LINKINTRAW		    (0x10U)
+#define MDIO_LINKINTMASKED	    (0x14U)
+#define MDIO_USERINTRAW		    (0x20U)
+#define MDIO_USERINTMASKED	    (0x24U)
+#define MDIO_USERINTMASKSET	    (0x28U)
+#define MDIO_USERINTMASKCLEAR	(0x2CU)
+#define MDIO_USERACCESS0	    (0x80U)
+#define MDIO_USERPHYSEL0	    (0x84U)
+#define MDIO_USERACCESS1	    (0x88U)
+#define MDIO_USERPHYSEL1	    (0x8CU)
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVID */
+
+#define MDIO_REVID_REV (0xFFFFFFFFU)
+#define MDIO_REVID_REV_SHIFT (0x00000000U)
+
+
+/* CONTROL */
+
+#define MDIO_CONTROL_IDLE (0x80000000U)
+#define MDIO_CONTROL_IDLE_SHIFT (0x0000001FU)
+/*----IDLE Tokens----*/
+#define MDIO_CONTROL_IDLE_NO (0x00000000U)
+#define MDIO_CONTROL_IDLE_YES (0x00000001U)
+
+#define MDIO_CONTROL_ENABLE (0x40000000U)
+#define MDIO_CONTROL_ENABLE_SHIFT (0x0000001EU)
+
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F000000U)
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT (0x00000018U)
+
+
+#define MDIO_CONTROL_PREAMBLE (0x00100000U)
+#define MDIO_CONTROL_PREAMBLE_SHIFT (0x00000014U)
+/*----PREAMBLE Tokens----*/
+
+#define MDIO_CONTROL_FAULT (0x00080000U)
+#define MDIO_CONTROL_FAULT_SHIFT (0x00000013U)
+
+#define MDIO_CONTROL_FAULTENB (0x00040000U)
+#define MDIO_CONTROL_FAULTENB_SHIFT (0x00000012U)
+/*----FAULTENB Tokens----*/
+
+
+
+#define MDIO_CONTROL_CLKDIV (0x0000FFFFU)
+#define MDIO_CONTROL_CLKDIV_SHIFT (0x00000000U)
+/*----CLKDIV Tokens----*/
+
+
+/* ALIVE */
+
+#define MDIO_ALIVE_REGVAL (0xFFFFFFFFU)
+#define MDIO_ALIVE_REGVAL_SHIFT (0x00000000U)
+
+
+/* LINK */
+
+#define MDIO_LINK_REGVAL (0xFFFFFFFFU)
+#define MDIO_LINK_REGVAL_SHIFT (0x00000000U)
+
+
+/* LINKINTRAW */
+
+
+#define MDIO_LINKINTRAW_USERPHY1 (0x00000002U)
+#define MDIO_LINKINTRAW_USERPHY1_SHIFT (0x00000001U)
+
+#define MDIO_LINKINTRAW_USERPHY0 (0x00000001U)
+#define MDIO_LINKINTRAW_USERPHY0_SHIFT (0x00000000U)
+
+
+/* LINKINTMASKED */
+
+
+#define MDIO_LINKINTMASKED_USERPHY1 (0x00000002U)
+#define MDIO_LINKINTMASKED_USERPHY1_SHIFT (0x00000001U)
+
+#define MDIO_LINKINTMASKED_USERPHY0 (0x00000001U)
+#define MDIO_LINKINTMASKED_USERPHY0_SHIFT (0x00000000U)
+
+
+/* USERINTRAW */
+
+
+#define MDIO_USERINTRAW_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTRAW_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTRAW_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTRAW_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKED */
+
+
+#define MDIO_USERINTMASKED_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKED_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKED_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKED_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKSET */
+
+
+#define MDIO_USERINTMASKSET_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKSET_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKCLEAR */
+
+
+#define MDIO_USERINTMASKCLEAR_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKCLEAR_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERACCESS0 */
+
+#define MDIO_USERACCESS0_GO (0x80000000U)
+#define MDIO_USERACCESS0_GO_SHIFT (0x0000001FU)
+
+#define MDIO_USERACCESS0_WRITE (0x40000000U)
+#define MDIO_USERACCESS0_READ  (0x00000000U)
+#define MDIO_USERACCESS0_WRITE_SHIFT (0x0000001EU)
+
+#define MDIO_USERACCESS0_ACK (0x20000000U)
+#define MDIO_USERACCESS0_ACK_SHIFT (0x0000001DU)
+
+
+#define MDIO_USERACCESS0_REGADR (0x03E00000U)
+#define MDIO_USERACCESS0_REGADR_SHIFT (0x00000015U)
+
+#define MDIO_USERACCESS0_PHYADR (0x001F0000U)
+#define MDIO_USERACCESS0_PHYADR_SHIFT (0x00000010U)
+
+#define MDIO_USERACCESS0_DATA (0x0000FFFFU)
+#define MDIO_USERACCESS0_DATA_SHIFT (0x00000000U)
+
+
+/* USERPHYSEL0 */
+
+
+#define MDIO_USERPHYSEL0_LINKSEL (0x00000080U)
+#define MDIO_USERPHYSEL0_LINKSEL_SHIFT (0x00000007U)
+
+#define MDIO_USERPHYSEL0_LINKINTENB (0x00000040U)
+#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT (0x00000006U)
+
+
+#define MDIO_USERPHYSEL0_PHYADRMON (0x0000001FU)
+#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT (0x00000000U)
+
+
+/* USERACCESS1 */
+
+#define MDIO_USERACCESS1_GO (0x80000000U)
+#define MDIO_USERACCESS1_GO_SHIFT (0x0000001FU)
+
+#define MDIO_USERACCESS1_WRITE (0x40000000U)
+#define MDIO_USERACCESS1_WRITE_SHIFT (0x0000001EU)
+
+#define MDIO_USERACCESS1_ACK (0x20000000U)
+#define MDIO_USERACCESS1_ACK_SHIFT (0x0000001DU)
+
+
+#define MDIO_USERACCESS1_REGADR (0x03E00000U)
+#define MDIO_USERACCESS1_REGADR_SHIFT (0x00000015U)
+
+#define MDIO_USERACCESS1_PHYADR (0x001F0000U)
+#define MDIO_USERACCESS1_PHYADR_SHIFT (0x00000010U)
+
+#define MDIO_USERACCESS1_DATA (0x0000FFFFU)
+#define MDIO_USERACCESS1_DATA_SHIFT (0x00000000U)
+
+
+/* USERPHYSEL1 */
+
+
+#define MDIO_USERPHYSEL1_LINKSEL (0x00000080U)
+#define MDIO_USERPHYSEL1_LINKSEL_SHIFT (0x00000007U)
+
+#define MDIO_USERPHYSEL1_LINKINTENB (0x00000040U)
+#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT (0x00000006U)
+
+
+#define MDIO_USERPHYSEL1_PHYADRMON (0x0000001FU)
+#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0x00000000U)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/hw_reg_access.h b/bsp/rm48x50/HALCoGen/include/hw_reg_access.h
new file mode 100644
index 0000000000000000000000000000000000000000..db7c151765a398aa4b0ec11ff84eb9fb7b86759b
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/hw_reg_access.h
@@ -0,0 +1,33 @@
+/*
+ * hw_reg_access.h.h
+ */
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef _HW_REG_ACCESS_H_
+#define _HW_REG_ACCESS_H_
+
+/*******************************************************************************
+*
+* Macros for hardware access, both direct and via the bit-band region.
+*
+*****************************************************************************/
+#define HWREG(x)                                                              \
+        (*((volatile uint32 *)(x)))
+#define HWREGH(x)                                                             \
+        (*((volatile uint16 *)(x)))
+#define HWREGB(x)                                                             \
+        (*((volatile uint8 *)(x)))
+#define HWREGBITW(x, b)                                                       \
+        HWREG(((uint32)(x) & 0xF0000000U) | 0x02000000U |                \
+              (((uint32)(x) & 0x000FFFFFU) << 5U) | ((b) << 2U))
+#define HWREGBITH(x, b)                                                       \
+        HWREGH(((uint32)(x) & 0xF0000000U) | 0x02000000U |               \
+               (((uint32)(x) & 0x000FFFFFU) << 5U) | ((b) << 2U))
+#define HWREGBITB(x, b)                                                       \
+        HWREGB(((uint32)(x) & 0xF0000000U) | 0x02000000U |               \
+               (((uint32)(x) & 0x000FFFFFU) << 5U) | ((b) << 2U))
+
+
+
+#endif /* __HW_TYPES_H__ */
diff --git a/bsp/rm48x50/HALCoGen/include/hw_usb.h b/bsp/rm48x50/HALCoGen/include/hw_usb.h
new file mode 100644
index 0000000000000000000000000000000000000000..d6e7a592451fa11638e07f412ae905d7e80a71ec
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/hw_usb.h
@@ -0,0 +1,259 @@
+//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of Hercules Development Kit software.
+//
+//******************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+/** @brief Base address of memmory mapped Registers                 		  */
+#define USBD_0_BASE			0xFCF78A00u
+#define USB0_BASE			USBD_0_BASE
+
+typedef volatile struct {
+	uint16 rev;			/* Revision 					  		  	  */
+	
+	/** Endpoint registers	***************************************************/
+	uint16 epnum;			/* Endpoint selection 			  		  */
+	uint16 data;			/* Data 						  		  */
+	uint16 ctrl;			/* Control 						  		  */
+	uint16 stat_flag;		/* Status 						  		  */
+	uint16 rxf_stat;		/* RX FIFO Status 				  		  */
+	uint16 syscon1;			/* System configuration 1 		  		  */
+	uint16 syscon2;			/* System configuration 2 		  		  */
+	uint16 dev_stat;		/* Device status 				  		  */
+	uint16 sof;				/* Start of frame 				  		  */
+	uint16 irq_en;			/* Interrupt enable 			  		  */
+	uint16 dma_irqen;		/* DMA Interrupt enable 		  		  */
+	uint16 irqsrc;			/* Interrupt source 			  		  */
+	uint16 epn_stat;		/* Non-ISO EP interrupt enable 	  		  */
+	uint16 dman_stat;		/* Non-ISO DMA interrupt enable   		  */
+	uint16 _rsvd1[1];		/* Reserved for reg holes				  */
+	
+	/** DMA Configuration	***************************************************/
+	uint16 rxdma_cfg; 		/* DMA Rx channels configuration 	      */
+	uint16 txdma_cfg; 		/* DMA Tx channels configuration 	  	  */
+	uint16 data_dma; 		/* DMA FIFO data				  	  	  */
+	uint16 txdma0; 			/* Transmit DMA control 0		  	  	  */
+	uint16 txdma1; 			/* Transmit DMA control 1		  	  	  */
+	uint16 txdma2; 			/* Transmit DMA control 2		  	  	  */
+	uint16 _rsvd2[2];		/* Reserved for reg holes				  */
+	
+	uint16 dman_rxdma0; 	/* Receive DMA control 0		  		  */
+	uint16 dman_rxdma1;		/* Receive DMA control 1		  		  */
+	uint16 dman_rxdma2;		/* Receive DMA control 2		  		  */
+	uint16 _rsvd3[5];		/* Reserved 							  */
+
+	/** Endpoint Configuration	***********************************************/
+	uint16 ep0; 			/* Endpoint 0 Configuration 	  		  */
+
+	uint16 epn_rx[15];		/* RX EP configurations... 				  */
+	uint16 _rsvd4[1];		/* Reserved for reg holes 				  */
+	
+	uint16 epn_tx[15];		/* TX EP configurations...				  */
+} usbdRegs;
+
+/******************************************************************************\
+* Register Bit Masks 
+* (USBD_<Instance ID=0>_<Register Name>_<Bit Field Name> <Mask Value>
+\******************************************************************************/
+
+/* Endpoint selection *********************************************************/
+#define USBD_EP_NUM_SETUP_SEL    				(0x0040u)
+#define USBD_EP_NUM_EP_SEL       				(0x0020u)
+#define USBD_EP_NUM_EP_DIR       				(0x0010u)
+#define USBD_EP_NUM_EP_NUM_MASK     			(0x000Fu)
+
+/* Data ***********************************************************************/
+#define USBD_DATA_DATA          				(0xFFFFu)
+
+/* Control ********************************************************************/
+#define USBD_CTRL_CLR_HALT      				(0x0080u)
+#define USBD_CTRL_SET_HALT      				(0x0040u)
+#define USBD_CTRL_SET_FIFO_EN   				(0x0004u)
+#define USBD_CTRL_CLR_EP        				(0x0002u)
+#define USBD_CTRL_RESET_EP      				(0x0001u)
+
+/* Status *********************************************************************/
+#define USBD_STAT_FLG_NO_RXPACKET 				(0x8000u)
+#define USBD_STAT_FLG_MISS_IN   				(0x4000u)
+#define USBD_STAT_FLG_DATA_FLUSH 				(0x2000u)
+#define USBD_STAT_FLG_ISO_ERR   				(0x1000u)
+#define USBD_STAT_FLG_ISO_FIFO_EMPTY 			(0x0200u)
+#define USBD_STAT_FLG_ISO_FIFO_FULL 			(0x0100u)
+#define USBD_STAT_FLG_EP_HALTED 				(0x0040u)
+#define USBD_STAT_FLG_STALL     				(0x0020u)
+#define USBD_STAT_FLG_NAK       				(0x0010u)
+#define USBD_STAT_FLG_ACK       				(0x0008u)
+#define USBD_STAT_FLG_FIFO_EN   				(0x0004u)
+#define USBD_STAT_FLG_NON_ISO_FIFO_EMPTY 		(0x0002u)
+#define USBD_STAT_FLG_NON_ISO_FIFO_FULL 		(0x0001u)
+
+/* RX FIFO Status 					 */
+#define USBD_RXFSTAT_RXF_COUNT  				(0x03FFu)
+
+/* System configuration 1 *****************************************************/
+#define USBD_SYSCON1_CFG_LOCK   				(0x0100u)
+#define USBD_SYSCON1_DATA_ENDIAN 				(0x0080u)
+#define USBD_SYSCON1_DMA_ENDIAN 				(0x0040u)
+#define USBD_SYSCON1_NAK_EN     				(0x0010u)
+#define USBD_SYSCON1_AUTODEC_DIS 				(0x0008u)
+#define USBD_SYSCON1_SELF_PWR   				(0x0004u)
+#define USBD_SYSCON1_SOFF_DIS   				(0x0002u)
+#define USBD_SYSCON1_PULLUP_EN  				(0x0001u)
+
+/* System configuration 2 *****************************************************/
+#define USBD_SYSCON2_RMT_WKP    				(0x0040u)
+#define USBD_SYSCON2_STALL_CMD  				(0x0020u)
+#define USBD_SYSCON2_DEV_CFG    				(0x0008u)
+#define USBD_SYSCON2_CLR_CFG    				(0x0004u)
+
+/* Device status **************************************************************/
+#define USBD_DEVSTAT_B_HNP_ENABLE 				(0x0200u)
+#define USBD_DEVSTAT_A_HNP_SUPPORT 				(0x0100u)
+#define USBD_DEVSTAT_A_ALT_HNP_SUPPORT 			(0x0080u)
+#define USBD_DEVSTAT_R_WK_OK    				(0x0040u)
+#define USBD_DEVSTAT_USB_RESET  				(0x0020u)
+#define USBD_DEVSTAT_SUS        				(0x0010u)
+#define USBD_DEVSTAT_CFG        				(0x0008u)
+#define USBD_DEVSTAT_ADD        				(0x0004u)
+#define USBD_DEVSTAT_DEF        				(0x0002u)
+#define USBD_DEVSTAT_ATT        				(0x0001u)
+
+
+/* Start of frame *************************************************************/
+#define USBD_SOF_FT_LOCK        				(0x1000u)
+#define USBD_SOF_TS_OK          				(0x0800u)
+#define USBD_SOF_TS            					(0x07FFu)
+
+/* Interrupt enable ***********************************************************/
+#define USBD_IRQ_EN_SOF_IE      				(0x0080u)
+#define USBD_IRQ_EN_EPN_RX_IE   				(0x0020u)
+#define USBD_IRQ_EN_EPN_TX_IE   				(0x0010u)
+#define USBD_IRQ_EN_DS_CHG_IE   				(0x0008u)
+#define USBD_IRQ_EN_EP0_IE      				(0x0001u)
+
+/* DMA Interrupt enable *******************************************************/
+#define USBD_DMA_IRQ_EN_TX2_DONE_IE 			(0x0400u)
+#define USBD_DMA_IRQ_EN_RX2_CNT_IE 				(0x0200u)
+#define USBD_DMA_IRQ_EN_RX2_EOT_IE 				(0x0100u)
+#define USBD_DMA_IRQ_EN_TX1_DONE_IE 			(0x0040u)
+#define USBD_DMA_IRQ_EN_RX1_CNT_IE 				(0x0020u)
+#define USBD_DMA_IRQ_EN_RX1_EOT_IE 				(0x0010u)
+#define USBD_DMA_IRQ_EN_TX0_DONE_IE 			(0x0004u)
+#define USBD_DMA_IRQ_EN_RX0_CNT_IE 				(0x0002u)
+#define USBD_DMA_IRQ_EN_RX0_EOT_IE 				(0x0001u)
+
+/* Interrupt source ***********************************************************/
+#define USBD_IRQ_SRC_TXN_DONE   				(0x0400u)
+#define USBD_IRQ_SRC_RXN_CNT    				(0x0200u)
+#define USBD_IRQ_SRC_RXN_EOT    				(0x0100u)
+#define USBD_IRQ_SRC_SOF        				(0x0080u)
+#define USBD_IRQ_SRC_EPN_RX     				(0x0020u)
+#define USBD_IRQ_SRC_EPN_TX    					(0x0010u)
+#define USBD_IRQ_SRC_DS_CHG     				(0x0008u)
+#define USBD_IRQ_SRC_SETUP      				(0x0004u)
+#define USBD_IRQ_SRC_EP0_RX     				(0x0002u)
+#define USBD_IRQ_SRC_EP0_TX     				(0x0001u)
+
+/* Non-ISO endpoint interrupt enable ******************************************/
+#define USBD_EPN_STAT_RX_IT_SRC 				(0x0F00u)
+#define USBD_EPN_STAT_TX_IT_SRC 				(0x000Fu)
+
+/* Non-ISO DMA interrupt enable ***********************************************/
+#define USBD_DMAN_STAT_RX_SB    				(0x1000u)
+#define USBD_DMAN_STAT_RX_IT_SRC 				(0x0F00u)
+#define USBD_DMAN_STAT_TX_IT_SRC 				(0x000Fu)
+
+/* DMA Receive channels configuration *****************************************/
+#define USBD_RXDMA_CFG_RX_REQ   				(0x1000u)
+#define USBD_RXDMA_CFG_RXDMA2_EP 				(0x0F00u)
+#define USBD_RXDMA_CFG_RXDMA1_EP 				(0x00F0u)
+#define USBD_RXDMA_CFG_RXDMA0_EP 				(0x000Fu)
+
+/* DMA Transmit channels configuration ****************************************/
+#define USBD_TXDMA_CFG_TX_REQ   				(0x1000u)
+#define USBD_TXDMA_CFG_TXDMA2_EP 				(0x0F00u)
+#define USBD_TXDMA_CFG_TXDMA1_EP 				(0x00F0u)
+#define USBD_TXDMA_CFG_TXDMA0_EP 				(0x000Fu)
+
+/* DMA FIFO data **************************************************************/
+#define USBD_DATA_DMA_DATA_DMA  				(0xFFFFu)
+
+/* Transmit DMA control 0 *****************************************************/
+#define USBD_TXDMA0_TX0_EOT     				(0x8000u)
+#define USBD_TXDMA0_TX0_START   				(0x4000u)
+#define USBD_TXDMA0_TX0_TSC     				(0x03FFu)
+
+/* Transmit DMA control 1 *****************************************************/
+#define USBD_TXDMA1_TX1_EOT    					(0x8000u)
+#define USBD_TXDMA1_TX1_START   				(0x4000u)
+#define USBD_TXDMA1_TX1_TSC     				(0x03FFu)
+#define USBD_TXDMA1_TX1_TSC_SHIFT    			(0x0000u)
+
+/* Transmit DMA control 2 *****************************************************/
+#define USBD_TXDMA2_TX2_EOT     				(0x8000u)
+#define USBD_TXDMA2_TX2_START   				(0x4000u)
+#define USBD_TXDMA2_TX2_TSC     				(0x03FFu)
+
+/* Receive DMA control 0 ******************************************************/
+#define USBD_RXDMA0_RX0_STOP    				(0x8000u)
+#define USBD_RXDMA0_RX0_TC      				(0x00FFu)
+
+/* Receive DMA control 1 ******************************************************/
+#define USBD_RXDMA1_RX10_STOP   				(0x8000u)
+#define USBD_RXDMA1_RX1_TC      				(0x00FFu)
+
+/* Receive DMA control 2 ******************************************************/
+#define USBD_RXDMA2_RX2_STOP    				(0x8000u)
+#define USBD_RXDMA2_RX2_TC      				(0x00FFu)
+
+/* Endpoint 0 Configuration ***************************************************/
+#define USBD_EP0_SIZE           				(0x3000u)
+#define USBD_EP0_PTR            				(0x07FFu)
+
+/* Receive endpoint configurations... *****************************************/
+#define USBD_RX_EP_VALID        				(0x8000u)
+#define USBD_RX_EP_SIZEDB       				(0x4000u)
+#define USBD_RX_EP_SIZE         				(0x3000u)
+#define USBD_RX_EP_ISO          				(0x0800u)
+#define USBD_RX_EP_PTR          				(0x07FFu)
+
+/* Transmit endpoint configurations... ****************************************/
+#define USBD_TX_EP_VALID        				(0x8000u)
+#define USBD_TX_EP_SIZEDB       				(0x4000u)
+#define USBD_TX_EP_SIZE         				(0x3000u)
+#define USBD_TX_EP_ISO          				(0x0800u)
+#define USBD_TX_EP_PTR          				(0x07FFu)
+
+#define USBD_MAX_EP0_PTR						(0xFFu)
+#define USBD_EP_RX_MAX							(15u)
+#define USBD_EP_TX_MAX							(15u)
+
+/** @brief Macro for setting a bit/s in a register (read, modify & write)	  */
+#define USBD_REG_BIT_SET(reg,bit) ((reg) |= ((uint16)(bit)))
+/** @brief Macro for clearing a bit/s in a register (read, modify & write)	  */
+#define USBD_REG_BIT_CLR(reg,bit) ((reg) &= ((uint16)~((uint16)bit)))
+/** @brief Macro for setting a bit/s in a register (write)	  				  */
+#define USBD_REG_SET_ONE(reg,value) ((reg) = ((uint16)value))
+
+#endif // __HW_USB_H__
diff --git a/bsp/rm48x50/HALCoGen/include/i2c.h b/bsp/rm48x50/HALCoGen/include/i2c.h
new file mode 100644
index 0000000000000000000000000000000000000000..5f98574c40dad91f3712f91f0ae60ee32174bd29
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/i2c.h
@@ -0,0 +1,156 @@
+/** @file I2C.h
+*   @brief I2C Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "reg_i2c.h"
+
+
+
+/** @enum i2cMode
+*   @brief Alias names for i2c modes
+*   This enumeration is used to provide alias names for I2C modes:
+*/
+
+enum i2cMode
+{
+    I2C_FD_FORMAT   = 0x0008U,  /* Free Data Format    */
+    I2C_START_BYTE  = 0x0010U,
+    I2C_RESET_OUT   = 0x0020U,  I2C_RESET_IN   = 0x0000U,
+    I2C_DLOOPBACK   = 0x0040U,    
+    I2C_REPEATMODE  = 0x0080U,  /* In Master Mode only */ 
+    I2C_10BIT_AMODE = 0x0100U,  I2C_7BIT_AMODE = 0x0000U,
+    I2C_TRANSMITTER = 0x0200U,  I2C_RECEIVER   = 0x0000U,        
+    I2C_MASTER      = 0x0400U,  I2C_SLAVE      = 0x0000U,     
+    I2C_STOP_COND   = 0x0800U,  /* In Master Mode only */
+    I2C_START_COND  = 0x2000U,  /* In Master Mode only */    
+    I2C_FREE_RUN    = 0x4000U,
+    I2C_NACK_MODE   = 0x8000U
+};
+
+
+/** @enum i2cBitCount
+*   @brief Alias names for i2c bit count
+*   This enumeration is used to provide alias names for I2C bit count:
+*/
+
+enum i2cBitCount
+{
+    I2C_2_BIT   = 0x2U, 
+    I2C_3_BIT   = 0x3U, 
+    I2C_4_BIT   = 0x4U, 
+    I2C_5_BIT   = 0x5U, 
+    I2C_6_BIT   = 0x6U, 
+    I2C_7_BIT   = 0x7U,     
+    I2C_8_BIT   = 0x0U  
+};
+
+
+
+/** @enum i2cIntFlags
+*   @brief Interrupt Flag Definitions
+*
+*   Used with I2CEnableNotification, I2CDisableNotification
+*/
+enum i2cIntFlags
+{
+    I2C_AL_INT     = 0x0001U,  /* arbitration lost      */
+    I2C_NACK_INT   = 0x0002U,  /* no acknowledgment    */
+    I2C_ARDY_INT   = 0x0004U,  /* access ready          */
+    I2C_RX_INT     = 0x0008U,  /* receive data ready    */
+    I2C_TX_INT     = 0x0010U,  /* transmit data ready   */
+    I2C_SCD_INT    = 0x0020U,  /* stop condition detect */
+    I2C_AAS_INT    = 0x0040U   /* address as slave      */
+};
+
+
+/** @enum i2cStatFlags
+*   @brief Interrupt Status Definitions
+*
+*/
+enum i2cStatFlags
+{
+    I2C_AL         = 0x0001U,  /* arbitration lost          */
+    I2C_NACK       = 0x0002U,  /* no acknowledgement        */
+    I2C_ARDY       = 0x0004U,  /* access ready              */
+    I2C_RX         = 0x0008U,  /* receive data ready        */
+    I2C_TX         = 0x0010U,  /* transmit data ready       */
+    I2C_SCD        = 0x0020U,  /* stop condition detect     */
+    I2C_AD0        = 0x0100U,  /* address Zero Status       */
+    I2C_AAS        = 0x0200U,  /* address as slave          */
+    I2C_XSMT       = 0x0400U,  /* Transmit shift empty not  */	
+    I2C_RXFULL     = 0x0800U,  /* receive full              */
+    I2C_BUSBUSY    = 0x1000U,  /* bus busy                  */
+    I2C_NACKSNT    = 0x2000U,  /* No Ack Sent               */
+    I2C_SDIR       = 0x4000U   /* Slave Direction           */	
+};
+
+
+/** @enum i2cDMA
+*   @brief I2C DMA definitions 
+*
+*   Used before i2c transfer
+*/
+enum i2cDMA
+{
+    I2C_TXDMA   = 0x20U, 
+    I2C_RXDMA   = 0x10U 
+};
+
+/** 
+ *  @defgroup I2C I2C
+ *  @brief Inter-Integrated Circuit Module.
+ *  
+ *  The I2C is a multi-master communication module providing an interface between the Texas Instruments (TI) microcontroller
+ *  and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2Cbus.
+ *  This module will support any slave or master I2C compatible device.
+ *
+ *	Related Files
+ *   - reg_i2c.h
+ *   - i2c.h
+ *   - i2c.c
+ *  @addtogroup I2C
+ *  @{
+ */
+ 
+/* I2C Interface Functions */
+void i2cInit(void);
+void i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd);
+void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd);
+void i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud);
+uint32  i2cIsTxReady(i2cBASE_t *i2c);
+void i2cSendByte(i2cBASE_t *i2c, uint8 byte);
+void i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data);
+uint32  i2cIsRxReady(i2cBASE_t *i2c);
+void i2cClearSCD(i2cBASE_t *i2c);
+uint32  i2cRxError(i2cBASE_t *i2c);
+uint32  i2cReceiveByte(i2cBASE_t *i2c);
+void i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data);
+void i2cEnableNotification(i2cBASE_t *i2c, uint32 flags);
+void i2cDisableNotification(i2cBASE_t *i2c, uint32 flags);
+void i2cSetStart(i2cBASE_t *i2c);
+void i2cSetStop(i2cBASE_t *i2c);
+void i2cSetCount(i2cBASE_t *i2c ,uint32 cnt);
+void i2cEnableLoopback(i2cBASE_t *i2c);
+void i2cDisableLoopback(i2cBASE_t *i2c);
+
+/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] i2c   - I2C module base address
+*   @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called apon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void i2cNotification(i2cBASE_t *i2c, uint32 flags);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/lin.h b/bsp/rm48x50/HALCoGen/include/lin.h
new file mode 100644
index 0000000000000000000000000000000000000000..07f668cce71e9fcb6fb653828222cfa42314aa35
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/lin.h
@@ -0,0 +1,209 @@
+/** @file lin.h
+*   @brief LIN Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#ifndef __LIN_H__
+#define __LIN_H__
+
+#include "reg_lin.h"
+
+
+/** @def LIN_BREAK_INT
+*   @brief Alias for break detect interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_BREAK_INT 0x00000001U
+
+
+/** @def LIN_WAKEUP_INT
+*   @brief Alias for wakeup interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_WAKEUP_INT 0x00000002U
+
+
+/** @def LIN_TO_INT
+*   @brief Alias for time out interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TO_INT 0x00000010U
+
+
+/** @def LIN_TOAWUS_INT
+*   @brief Alias for time out after wakeup signal interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TOAWUS_INT 0x00000040U
+
+
+/** @def LIN_TOA3WUS_INT
+*   @brief Alias for time out after 3 wakeup signals interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TOA3WUS_INT 0x00000080U
+
+
+/** @def LIN_TX_READY
+*   @brief Alias for transmit buffer ready flag
+*
+*   Used with linIsTxReady.
+*/
+#define LIN_TX_READY 0x00000100U
+
+
+/** @def LIN_RX_INT
+*   @brief Alias for receive buffer ready interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_RX_INT 0x00000200U
+
+
+/** @def LIN_ID_INT
+*   @brief Alias for received matching identifier interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_ID_INT 0x00002000U
+
+
+/** @def LIN_PE_INT
+*   @brief Alias for parity error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_PE_INT 0x01000000U
+
+
+/** @def LIN_OE_INT
+*   @brief Alias for overrun error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_OE_INT 0x02000000U
+
+
+/** @def LIN_FE_INT
+*   @brief Alias for framing error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_FE_INT 0x04000000U
+
+
+/** @def LIN_NRE_INT
+*   @brief Alias for no response error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_NRE_INT 0x08000000U
+
+
+/** @def LIN_ISFE_INT
+*   @brief Alias for inconsistent sync field error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_ISFE_INT 0x10000000U
+
+
+/** @def LIN_CE_INT
+*   @brief Alias for checksum error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_CE_INT 0x20000000U
+
+
+/** @def LIN_PBE_INT
+*   @brief Alias for physical bus error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_PBE_INT 0x40000000U
+
+
+/** @def LIN_BE_INT
+*   @brief Alias for bit error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_BE_INT 0x80000000U
+
+
+/** @struct linBase
+*   @brief LIN Register Definition
+*
+*   This structure is used to access the LIN module registers.
+*/
+/** @typedef linBASE_t
+*   @brief LIN Register Frame Type Definition
+*
+*   This type is used to access the LIN Registers.
+*/
+
+enum linPinSelect
+{
+    PIN_LIN_TX   = 0U,
+    PIN_LIN_RX = 1U
+};
+
+/** 
+ *  @defgroup LIN LIN
+ *  @brief Local Interconnect Network Module.
+ *  
+ *  The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
+ *  single-master/multiple-slave with a message identification for multi-cast transmission between any network
+ *  nodes.
+ *
+ *	Related Files
+ *   - reg_lin.h
+ *   - lin.h
+ *   - lin.c
+ *  @addtogroup LIN
+ *  @{
+ */
+ 
+/* LIN Interface Functions */
+void     linInit(void);
+void     linSetFunctional(linBASE_t *lin, uint32 port);
+void     linSendHeader(linBASE_t *lin, uint8 identifier);
+void     linSendWakupSignal(linBASE_t *lin);
+void     linEnterSleep(linBASE_t *lin);
+void     linSoftwareReset(linBASE_t *lin);
+uint32 linIsTxReady(linBASE_t *lin);
+void     linSetLength(linBASE_t *lin, uint32 length);
+void     linSend(linBASE_t *lin, uint8 * data);
+uint32 linIsRxReady(linBASE_t *lin);
+uint32 linTxRxError(linBASE_t *lin);
+uint32 linGetIdentifier(linBASE_t *lin);
+void     linGetData(linBASE_t *lin, uint8 * const data);
+void     linEnableNotification(linBASE_t *lin, uint32 flags);
+void     linDisableNotification(linBASE_t *lin, uint32 flags);
+void     linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype);
+void     linDisableLoopback(linBASE_t *lin);
+
+/** @fn void linNotification(linBASE_t *lin, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] lin   - lin module base address
+*   @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void linNotification(linBASE_t *lin, uint32 flags);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/mdio.h b/bsp/rm48x50/HALCoGen/include/mdio.h
new file mode 100644
index 0000000000000000000000000000000000000000..f58a913f2706f4183ea7e0ff981f75c3d019ee24
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/mdio.h
@@ -0,0 +1,43 @@
+/**
+ *  \file   mdio.h
+ *
+ *  \brief  MDIO APIs and macros.
+ *
+ *   This file contains the driver API prototypes and macro definitions.
+ */
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __MDIO_H__
+#define __MDIO_H__
+
+#include "sys_common.h"
+#include "hw_mdio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*****************************************************************************/
+
+/**
+ *  @addtogroup EMACMDIO
+ *  @{
+ */
+/*
+** Prototypes for the APIs
+*/
+extern uint32 MDIOPhyAliveStatusGet(uint32 baseAddr);
+extern uint32 MDIOPhyLinkStatusGet(uint32 baseAddr);
+extern void MDIOInit(uint32 baseAddr, uint32 mdioInputFreq,
+                     uint32 mdioOutputFreq);
+extern uint32 MDIOPhyRegRead(uint32 baseAddr, uint32 phyAddr,
+                                   uint32 regNum, volatile uint16 * dataPtr);
+extern void MDIOPhyRegWrite(uint32 baseAddr, uint32 phyAddr,
+                            uint32 regNum, uint16 RegVal);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* __MDIO_H__ */
diff --git a/bsp/rm48x50/HALCoGen/include/mibspi.h b/bsp/rm48x50/HALCoGen/include/mibspi.h
new file mode 100644
index 0000000000000000000000000000000000000000..de424b336ede9ae7d3f124d0c3959d3de043acc1
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/mibspi.h
@@ -0,0 +1,159 @@
+/** @file mibspi.h
+*   @brief MIBSPI Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#ifndef __MIBSPI_H__
+#define __MIBSPI_H__
+
+#include "reg_mibspi.h"
+
+
+/** @enum triggerEvent
+*   @brief Transfer Group Trigger Event
+*/
+enum triggerEvent
+{
+    TRG_NEVER   = 0U,
+    TRG_RISING  = 1U,
+    TRG_FALLING = 2U,
+    TRG_BOTH    = 3U,
+    TRG_HIGH    = 5U,
+    TRG_LOW     = 6U,
+    TRG_ALWAYS  = 7U
+};
+
+/** @enum triggerSource
+*   @brief Transfer Group Trigger Source
+*/
+enum triggerSource
+{
+    TRG_DISABLED,
+    TRG_GIOA0,
+    TRG_GIOA1,
+    TRG_GIOA2,
+    TRG_GIOA3,
+    TRG_GIOA4,
+    TRG_GIOA5,
+    TRG_GIOA6,
+    TRG_GIOA7,
+    TRG_HET1_8,
+    TRG_HET1_10,
+    TRG_HET1_12,
+    TRG_HET1_14,
+    TRG_HET1_16,
+    TRG_HET1_18,
+    TRG_TICK
+};
+
+
+/** @enum mibspiPinSelect
+*   @brief mibspi Pin Select
+*/
+enum mibspiPinSelect
+{
+    PIN_CS0   = 0U,
+    PIN_CS1 = 1U,
+    PIN_CS2 = 2U,
+    PIN_CS3  = 3U,
+    PIN_CS4 = 4U,
+    PIN_CS5    = 5U,
+    PIN_CS6    = 6U,
+    PIN_CS7  = 7U,
+    PIN_ENA = 8U,
+    PIN_CLK = 9U,
+    PIN_SIMO = 10U,
+    PIN_SOMI = 11U,
+   PIN_SIMO_1 = 17U,
+   PIN_SIMO_2 = 18U,
+   PIN_SIMO_3 = 19U,
+   PIN_SIMO_4 = 20U,
+   PIN_SIMO_5 = 21U,
+   PIN_SIMO_6 = 22U,
+   PIN_SIMO_7 = 23U,
+   PIN_SOMI_1 = 25U,
+   PIN_SOMI_2 = 26U,
+   PIN_SOMI_3 = 27U,
+   PIN_SOMI_4 = 28U,
+   PIN_SOMI_5 = 29U,
+   PIN_SOMI_6 = 30U,
+   PIN_SOMI_7 = 31U
+};
+
+
+/** @enum chipSelect
+*   @brief Transfer Group Chip Select
+*/
+enum chipSelect
+{
+    CS_NONE = 0xFFU,
+    CS_0    = 0xFEU,
+    CS_1    = 0xFDU,
+    CS_2    = 0xFBU,
+    CS_3    = 0xF7U,
+    CS_4    = 0xEFU,
+    CS_5    = 0xDFU,
+    CS_6    = 0xBFU,
+    CS_7    = 0x7FU
+};
+
+/** 
+ *  @defgroup MIBSPI MIBSPI
+ *  @brief Multi-Buffered Serial Peripheral Interface Module.
+ *  
+ *  The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a serial bit stream of
+ *  programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
+ *  The MibSPI has a programmable buffer memory that enables programmed transmission to be completed
+ *  without CPU intervention
+ *
+ *	Related Files
+ *   - reg_mibspi.h
+ *   - mibspi.h
+ *   - mibspi.c
+ *  @addtogroup MIBSPI
+ *  @{
+ */
+ 
+/* MIBSPI Interface Functions */
+void mibspiInit(void);
+void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port);
+void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data);
+uint32 mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data);
+void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group);
+boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group);
+void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level);
+void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group);
+void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype);
+void mibspiDisableLoopback(mibspiBASE_t *mibspi);
+
+
+/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
+*   @brief Error interrupt callback
+*   @param[in] mibspi   - mibSpi module base address
+*   @param[in] flags - Copy of error interrupt flags
+*
+* This is a error callback that is provided by the application and is call upon
+* an error interrupt.  The paramer passed to the callback is a copy of the error
+* interrupt flag register.
+*/
+void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags);
+
+
+/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group)
+*   @brief Transfer complete notification callback
+*   @param[in] mibspi   - mibSpi module base address
+*   @param[in] group - Transfer group
+*
+* This is a callback function provided by the application.  It is call when
+* a transfer is complete.  The parameter is the transfer group that triggered
+* the interrupt.
+*/
+void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/pinmux.h b/bsp/rm48x50/HALCoGen/include/pinmux.h
new file mode 100644
index 0000000000000000000000000000000000000000..684d89286884af6646298ca10db5ba646662d4ba
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/pinmux.h
@@ -0,0 +1,625 @@
+/** @file pinmux.h 
+*   @brief PINMUX Driver Implementation File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __PINMUX_H__
+#define __PINMUX_H__
+
+#include "reg_pinmux.h"
+
+
+
+#define PINMUX_BALL_A5_SHIFT	8U
+#define PINMUX_BALL_A11_SHIFT	8U
+#define PINMUX_BALL_A14_SHIFT	0U
+#define PINMUX_BALL_B2_SHIFT	24U
+#define PINMUX_BALL_B3_SHIFT	8U
+#define PINMUX_BALL_B4_SHIFT	16U
+#define PINMUX_BALL_B5_SHIFT	24U
+#define PINMUX_BALL_B6_SHIFT	8U
+#define PINMUX_BALL_B11_SHIFT	8U
+#define PINMUX_BALL_C1_SHIFT	0U
+#define PINMUX_BALL_C2_SHIFT	0U
+#define PINMUX_BALL_C3_SHIFT	16U
+#define PINMUX_BALL_C4_SHIFT	16U
+#define PINMUX_BALL_C5_SHIFT	8U
+#define PINMUX_BALL_C6_SHIFT	0U
+#define PINMUX_BALL_C7_SHIFT	24U
+#define PINMUX_BALL_C8_SHIFT	16U
+#define PINMUX_BALL_C9_SHIFT	24U
+#define PINMUX_BALL_C10_SHIFT	8U
+#define PINMUX_BALL_C11_SHIFT	0U
+#define PINMUX_BALL_C12_SHIFT	16U
+#define PINMUX_BALL_C13_SHIFT	0U
+#define PINMUX_BALL_C14_SHIFT	8U
+#define PINMUX_BALL_C15_SHIFT	16U
+#define PINMUX_BALL_C16_SHIFT	8U
+#define PINMUX_BALL_C17_SHIFT	0U
+#define PINMUX_BALL_D3_SHIFT	0U
+#define PINMUX_BALL_D4_SHIFT	0U
+#define PINMUX_BALL_D5_SHIFT	0U
+#define PINMUX_BALL_D14_SHIFT	16U
+#define PINMUX_BALL_D15_SHIFT	24U
+#define PINMUX_BALL_D16_SHIFT	24U
+#define PINMUX_BALL_D17_SHIFT	16U
+#define PINMUX_BALL_D19_SHIFT	0U
+#define PINMUX_BALL_E1_SHIFT	16U
+#define PINMUX_BALL_E3_SHIFT	8U
+#define PINMUX_BALL_E5_SHIFT	16U
+#define PINMUX_BALL_E6_SHIFT	24U
+#define PINMUX_BALL_E7_SHIFT	24U
+#define PINMUX_BALL_E8_SHIFT	0U
+#define PINMUX_BALL_E9_SHIFT	24U
+#define PINMUX_BALL_E10_SHIFT	16U
+#define PINMUX_BALL_E11_SHIFT	8U
+#define PINMUX_BALL_E12_SHIFT	24U
+#define PINMUX_BALL_E13_SHIFT	0U
+#define PINMUX_BALL_E16_SHIFT	16U
+#define PINMUX_BALL_E17_SHIFT	8U
+#define PINMUX_BALL_E18_SHIFT	0U
+#define PINMUX_BALL_E19_SHIFT	0U
+#define PINMUX_BALL_F3_SHIFT	16U
+#define PINMUX_BALL_F5_SHIFT	24U
+#define PINMUX_BALL_G3_SHIFT	8U
+#define PINMUX_BALL_G5_SHIFT	8U
+#define PINMUX_BALL_G16_SHIFT	24U
+#define PINMUX_BALL_G17_SHIFT	0U
+#define PINMUX_BALL_G19_SHIFT	16U
+#define PINMUX_BALL_H3_SHIFT	16U
+#define PINMUX_BALL_H16_SHIFT	16U
+#define PINMUX_BALL_H17_SHIFT	24U
+#define PINMUX_BALL_H18_SHIFT	24U
+#define PINMUX_BALL_H19_SHIFT	16U
+#define PINMUX_BALL_J3_SHIFT	24U
+#define PINMUX_BALL_J18_SHIFT	0U
+#define PINMUX_BALL_J19_SHIFT	8U
+#define PINMUX_BALL_K2_SHIFT	8U
+#define PINMUX_BALL_K5_SHIFT	0U
+#define PINMUX_BALL_K15_SHIFT	8U
+#define PINMUX_BALL_K17_SHIFT	0U
+#define PINMUX_BALL_K18_SHIFT	0U
+#define PINMUX_BALL_K19_SHIFT	8U
+#define PINMUX_BALL_L5_SHIFT	24U
+#define PINMUX_BALL_L15_SHIFT	16U
+#define PINMUX_BALL_M1_SHIFT	0U
+#define PINMUX_BALL_M2_SHIFT	24U
+#define PINMUX_BALL_M5_SHIFT	8U
+#define PINMUX_BALL_M15_SHIFT	24U
+#define PINMUX_BALL_M17_SHIFT	8U
+#define PINMUX_BALL_N1_SHIFT	16U
+#define PINMUX_BALL_N2_SHIFT	0U
+#define PINMUX_BALL_N5_SHIFT	24U
+#define PINMUX_BALL_N15_SHIFT	8U
+#define PINMUX_BALL_N17_SHIFT	16U
+#define PINMUX_BALL_N19_SHIFT	0U
+#define PINMUX_BALL_P1_SHIFT	24U
+#define PINMUX_BALL_P5_SHIFT	8U
+#define PINMUX_BALL_R2_SHIFT	24U
+#define PINMUX_BALL_R5_SHIFT	24U
+#define PINMUX_BALL_R6_SHIFT	0U
+#define PINMUX_BALL_R7_SHIFT	24U
+#define PINMUX_BALL_R8_SHIFT	24U
+#define PINMUX_BALL_R9_SHIFT	0U
+#define PINMUX_BALL_T1_SHIFT	0U
+#define PINMUX_BALL_T12_SHIFT	24U
+#define PINMUX_BALL_U1_SHIFT	24U
+#define PINMUX_BALL_V2_SHIFT	16U
+#define PINMUX_BALL_V5_SHIFT	8U
+#define PINMUX_BALL_V6_SHIFT	16U
+#define PINMUX_BALL_V7_SHIFT	16U
+#define PINMUX_BALL_V10_SHIFT	16U
+#define PINMUX_BALL_W3_SHIFT	16U
+#define PINMUX_BALL_W5_SHIFT	8U
+#define PINMUX_BALL_W6_SHIFT	16U
+#define PINMUX_BALL_W9_SHIFT	8U
+#define PINMUX_BALL_W10_SHIFT	0U
+
+#define PINMUX_GATE_EMIF_CLK_SHIFT			8U
+#define PINMUX_GIOB_DISABLE_HET2_SHIFT		16U
+#define PINMUX_ALT_ADC_TRIGGER_SHIFT		0U
+#define PINMUX_ETHERNET_SHIFT				24U
+
+#define PINMUX_BALL_A5_MASK		(~(0xFFU << PINMUX_BALL_A5_SHIFT))
+#define PINMUX_BALL_A11_MASK	(~(0xFFU << PINMUX_BALL_A11_SHIFT))
+#define PINMUX_BALL_A14_MASK	(~(0xFFU << PINMUX_BALL_A14_SHIFT))
+#define PINMUX_BALL_B2_MASK		(~(0xFFU << PINMUX_BALL_B2_SHIFT))
+#define PINMUX_BALL_B3_MASK		(~(0xFFU << PINMUX_BALL_B3_SHIFT))
+#define PINMUX_BALL_B4_MASK		(~(0xFFU << PINMUX_BALL_B4_SHIFT))
+#define PINMUX_BALL_B5_MASK		(~(0xFFU << PINMUX_BALL_B5_SHIFT))
+#define PINMUX_BALL_B6_MASK		(~(0xFFU << PINMUX_BALL_B6_SHIFT))
+#define PINMUX_BALL_B11_MASK	(~(0xFFU << PINMUX_BALL_B11_SHIFT))
+#define PINMUX_BALL_C1_MASK		(~(0xFFU << PINMUX_BALL_C1_SHIFT))
+#define PINMUX_BALL_C2_MASK		(~(0xFFU << PINMUX_BALL_C2_SHIFT))
+#define PINMUX_BALL_C3_MASK		(~(0xFFU << PINMUX_BALL_C3_SHIFT))
+#define PINMUX_BALL_C4_MASK		(~(0xFFU << PINMUX_BALL_C4_SHIFT))
+#define PINMUX_BALL_C5_MASK		(~(0xFFU << PINMUX_BALL_C5_SHIFT))
+#define PINMUX_BALL_C6_MASK		(~(0xFFU << PINMUX_BALL_C6_SHIFT))
+#define PINMUX_BALL_C7_MASK		(~(0xFFU << PINMUX_BALL_C7_SHIFT))
+#define PINMUX_BALL_C8_MASK		(~(0xFFU << PINMUX_BALL_C8_SHIFT))
+#define PINMUX_BALL_C9_MASK		(~(0xFFU << PINMUX_BALL_C9_SHIFT))
+#define PINMUX_BALL_C10_MASK	(~(0xFFU << PINMUX_BALL_C10_SHIFT))
+#define PINMUX_BALL_C11_MASK	(~(0xFFU << PINMUX_BALL_C11_SHIFT))
+#define PINMUX_BALL_C12_MASK	(~(0xFFU << PINMUX_BALL_C12_SHIFT))
+#define PINMUX_BALL_C13_MASK	(~(0xFFU << PINMUX_BALL_C13_SHIFT))
+#define PINMUX_BALL_C14_MASK	(~(0xFFU << PINMUX_BALL_C14_SHIFT))
+#define PINMUX_BALL_C15_MASK	(~(0xFFU << PINMUX_BALL_C15_SHIFT))
+#define PINMUX_BALL_C16_MASK	(~(0xFFU << PINMUX_BALL_C16_SHIFT))
+#define PINMUX_BALL_C17_MASK	(~(0xFFU << PINMUX_BALL_C17_SHIFT))
+#define PINMUX_BALL_D3_MASK		(~(0xFFU << PINMUX_BALL_D3_SHIFT))
+#define PINMUX_BALL_D4_MASK		(~(0xFFU << PINMUX_BALL_D4_SHIFT))
+#define PINMUX_BALL_D5_MASK		(~(0xFFU << PINMUX_BALL_D5_SHIFT))
+#define PINMUX_BALL_D14_MASK	(~(0xFFU << PINMUX_BALL_D14_SHIFT))
+#define PINMUX_BALL_D15_MASK	(~(0xFFU << PINMUX_BALL_D15_SHIFT))
+#define PINMUX_BALL_D16_MASK	(~(0xFFU << PINMUX_BALL_D16_SHIFT))
+#define PINMUX_BALL_D17_MASK	(~(0xFFU << PINMUX_BALL_D17_SHIFT))
+#define PINMUX_BALL_D19_MASK	(~(0xFFU << PINMUX_BALL_D19_SHIFT))
+#define PINMUX_BALL_E1_MASK		(~(0xFFU << PINMUX_BALL_E1_SHIFT))
+#define PINMUX_BALL_E3_MASK		(~(0xFFU << PINMUX_BALL_E3_SHIFT))
+#define PINMUX_BALL_E5_MASK		(~(0xFFU << PINMUX_BALL_E5_SHIFT))
+#define PINMUX_BALL_E6_MASK		(~(0xFFU << PINMUX_BALL_E6_SHIFT))
+#define PINMUX_BALL_E7_MASK		(~(0xFFU << PINMUX_BALL_E7_SHIFT))
+#define PINMUX_BALL_E8_MASK		(~(0xFFU << PINMUX_BALL_E8_SHIFT))
+#define PINMUX_BALL_E9_MASK		(~(0xFFU << PINMUX_BALL_E9_SHIFT))
+#define PINMUX_BALL_E10_MASK	(~(0xFFU << PINMUX_BALL_E10_SHIFT))
+#define PINMUX_BALL_E11_MASK	(~(0xFFU << PINMUX_BALL_E11_SHIFT))
+#define PINMUX_BALL_E12_MASK	(~(0xFFU << PINMUX_BALL_E12_SHIFT))
+#define PINMUX_BALL_E13_MASK	(~(0xFFU << PINMUX_BALL_E13_SHIFT))
+#define PINMUX_BALL_E16_MASK	(~(0xFFU << PINMUX_BALL_E16_SHIFT))
+#define PINMUX_BALL_E17_MASK	(~(0xFFU << PINMUX_BALL_E17_SHIFT))
+#define PINMUX_BALL_E18_MASK	(~(0xFFU << PINMUX_BALL_E18_SHIFT))
+#define PINMUX_BALL_E19_MASK	(~(0xFFU << PINMUX_BALL_E19_SHIFT))
+#define PINMUX_BALL_F3_MASK		(~(0xFFU << PINMUX_BALL_F3_SHIFT))
+#define PINMUX_BALL_F5_MASK		(~(0xFFU << PINMUX_BALL_F4_SHIFT))
+#define PINMUX_BALL_G3_MASK		(~(0xFFU << PINMUX_BALL_G3_SHIFT))
+#define PINMUX_BALL_G5_MASK		(~(0xFFU << PINMUX_BALL_G4_SHIFT))
+#define PINMUX_BALL_G16_MASK	(~(0xFFU << PINMUX_BALL_G16_SHIFT))
+#define PINMUX_BALL_G17_MASK	(~(0xFFU << PINMUX_BALL_G17_SHIFT))
+#define PINMUX_BALL_G19_MASK	(~(0xFFU << PINMUX_BALL_G19_SHIFT))
+#define PINMUX_BALL_H3_MASK		(~(0xFFU << PINMUX_BALL_H3_SHIFT))
+#define PINMUX_BALL_H16_MASK	(~(0xFFU << PINMUX_BALL_H16_SHIFT))
+#define PINMUX_BALL_H17_MASK	(~(0xFFU << PINMUX_BALL_H17_SHIFT))
+#define PINMUX_BALL_H18_MASK	(~(0xFFU << PINMUX_BALL_H18_SHIFT))
+#define PINMUX_BALL_H19_MASK	(~(0xFFU << PINMUX_BALL_H19_SHIFT))
+#define PINMUX_BALL_J3_MASK		(~(0xFFU << PINMUX_BALL_J3_SHIFT))
+#define PINMUX_BALL_J18_MASK	(~(0xFFU << PINMUX_BALL_J18_SHIFT))
+#define PINMUX_BALL_J19_MASK	(~(0xFFU << PINMUX_BALL_J19_SHIFT))
+#define PINMUX_BALL_K2_MASK		(~(0xFFU << PINMUX_BALL_K2_SHIFT))
+#define PINMUX_BALL_K5_MASK		(~(0xFFU << PINMUX_BALL_K4_SHIFT))
+#define PINMUX_BALL_K15_MASK	(~(0xFFU << PINMUX_BALL_K15_SHIFT))
+#define PINMUX_BALL_K17_MASK	(~(0xFFU << PINMUX_BALL_K17_SHIFT))
+#define PINMUX_BALL_K18_MASK	(~(0xFFU << PINMUX_BALL_K18_SHIFT))
+#define PINMUX_BALL_K19_MASK	(~(0xFFU << PINMUX_BALL_K19_SHIFT))
+#define PINMUX_BALL_L5_MASK		(~(0xFFU << PINMUX_BALL_L4_SHIFT))
+#define PINMUX_BALL_L15_MASK	(~(0xFFU << PINMUX_BALL_L15_SHIFT))
+#define PINMUX_BALL_M1_MASK		(~(0xFFU << PINMUX_BALL_M1_SHIFT))
+#define PINMUX_BALL_M2_MASK		(~(0xFFU << PINMUX_BALL_M2_SHIFT))
+#define PINMUX_BALL_M5_MASK		(~(0xFFU << PINMUX_BALL_M4_SHIFT))
+#define PINMUX_BALL_M15_MASK	(~(0xFFU << PINMUX_BALL_M15_SHIFT))
+#define PINMUX_BALL_M17_MASK	(~(0xFFU << PINMUX_BALL_M17_SHIFT))
+#define PINMUX_BALL_N1_MASK		(~(0xFFU << PINMUX_BALL_N1_SHIFT))
+#define PINMUX_BALL_N2_MASK		(~(0xFFU << PINMUX_BALL_N2_SHIFT))
+#define PINMUX_BALL_N5_MASK		(~(0xFFU << PINMUX_BALL_N4_SHIFT))
+#define PINMUX_BALL_N15_MASK	(~(0xFFU << PINMUX_BALL_N15_SHIFT))
+#define PINMUX_BALL_N17_MASK	(~(0xFFU << PINMUX_BALL_N17_SHIFT))
+#define PINMUX_BALL_N19_MASK	(~(0xFFU << PINMUX_BALL_N19_SHIFT))
+#define PINMUX_BALL_P1_MASK		(~(0xFFU << PINMUX_BALL_P1_SHIFT))
+#define PINMUX_BALL_P5_MASK		(~(0xFFU << PINMUX_BALL_P4_SHIFT))
+#define PINMUX_BALL_R2_MASK		(~(0xFFU << PINMUX_BALL_R2_SHIFT))
+#define PINMUX_BALL_R5_MASK		(~(0xFFU << PINMUX_BALL_R5_SHIFT))
+#define PINMUX_BALL_R6_MASK		(~(0xFFU << PINMUX_BALL_R6_SHIFT))
+#define PINMUX_BALL_R7_MASK		(~(0xFFU << PINMUX_BALL_R7_SHIFT))
+#define PINMUX_BALL_R8_MASK		(~(0xFFU << PINMUX_BALL_R8_SHIFT))
+#define PINMUX_BALL_R9_MASK		(~(0xFFU << PINMUX_BALL_R9_SHIFT))
+#define PINMUX_BALL_T1_MASK		(~(0xFFU << PINMUX_BALL_T1_SHIFT))
+#define PINMUX_BALL_T12_MASK	(~(0xFFU << PINMUX_BALL_T12_SHIFT))
+#define PINMUX_BALL_U1_MASK		(~(0xFFU << PINMUX_BALL_U1_SHIFT))
+#define PINMUX_BALL_V2_MASK		(~(0xFFU << PINMUX_BALL_V2_SHIFT))
+#define PINMUX_BALL_V5_MASK		(~(0xFFU << PINMUX_BALL_V5_SHIFT))
+#define PINMUX_BALL_V6_MASK		(~(0xFFU << PINMUX_BALL_V6_SHIFT))
+#define PINMUX_BALL_V7_MASK		(~(0xFFU << PINMUX_BALL_V7_SHIFT))
+#define PINMUX_BALL_V10_MASK	(~(0xFFU << PINMUX_BALL_V10_SHIFT))
+#define PINMUX_BALL_W3_MASK		(~(0xFFU << PINMUX_BALL_W3_SHIFT))
+#define PINMUX_BALL_W5_MASK		(~(0xFFU << PINMUX_BALL_W5_SHIFT))
+#define PINMUX_BALL_W6_MASK		(~(0xFFU << PINMUX_BALL_W6_SHIFT))
+#define PINMUX_BALL_W9_MASK		(~(0xFFU << PINMUX_BALL_W9_SHIFT))
+#define PINMUX_BALL_W10_MASK	(~(0xFFU << PINMUX_BALL_W10_SHIFT))
+
+#define PINMUX_GATE_EMIF_CLK_MASK		(~(0xFFU << PINMUX_GATE_EMIF_CLK_SHIFT))
+#define PINMUX_GIOB_DISABLE_HET2_MASK	(~(0xFFU << PINMUX_GIOB_DISABLE_HET2_SHIFT))
+#define PINMUX_ALT_ADC_TRIGGER_MASK		(~(0xFFU << PINMUX_ALT_ADC_TRIGGER_SHIFT))
+#define PINMUX_ETHERNET_MASK			(~(0xFFU << PINMUX_ETHERNET_SHIFT))
+
+
+
+#define PINMUX_BALL_A5_GIOA_0					(0x1U <<  PINMUX_BALL_A5_SHIFT)
+#define PINMUX_BALL_A5_OHCI_PRT_RcvDpls_1		(0x2U <<  PINMUX_BALL_A5_SHIFT)
+#define PINMUX_BALL_A5_W2FC_RXDPI				(0x4U <<  PINMUX_BALL_A5_SHIFT)
+
+#define PINMUX_BALL_A11_HET1_14				(0x1U <<  PINMUX_BALL_A11_SHIFT)
+#define PINMUX_BALL_A11_OHCI_RCFG_txSe0_0		(0x2U <<  PINMUX_BALL_A11_SHIFT)
+
+#define PINMUX_BALL_A14_HET1_26				(0x1U <<  PINMUX_BALL_A14_SHIFT)
+#define PINMUX_BALL_A14_MII_RXD_1				(0x2U <<  PINMUX_BALL_A14_SHIFT)
+#define PINMUX_BALL_A14_RMII_RXD_1				(0x4U <<  PINMUX_BALL_A14_SHIFT)
+
+#define PINMUX_BALL_B2_MIBSPI3NCS_2				(0x1U <<  PINMUX_BALL_B2_SHIFT)
+#define PINMUX_BALL_B2_I2C_SDA					(0x2U <<  PINMUX_BALL_B2_SHIFT)
+#define PINMUX_BALL_B2_HET1_27					(0x4U <<  PINMUX_BALL_B2_SHIFT)
+
+#define PINMUX_BALL_B3_HET1_22					(0x1U <<  PINMUX_BALL_B3_SHIFT)
+#define PINMUX_BALL_B3_OHCI_RCFG_txSe0_1		(0x2U <<  PINMUX_BALL_B3_SHIFT)
+#define PINMUX_BALL_B3_W2FC_SE0O				(0x4U <<  PINMUX_BALL_B3_SHIFT)
+
+#define PINMUX_BALL_B4_HET1_12					(0x1U <<  PINMUX_BALL_B4_SHIFT)
+#define PINMUX_BALL_B4_MII_CRS					(0x2U <<  PINMUX_BALL_B4_SHIFT)
+#define PINMUX_BALL_B4_RMII_CRS_DV				(0x4U <<  PINMUX_BALL_B4_SHIFT)
+
+#define PINMUX_BALL_B5_GIOA_5					(0x1U <<  PINMUX_BALL_B5_SHIFT)
+#define PINMUX_BALL_B5_EXTCLKIN					(0x2U <<  PINMUX_BALL_B5_SHIFT)
+
+#define PINMUX_BALL_B6_MIBSPI5NCS_1				(0x1U <<  PINMUX_BALL_B6_SHIFT)
+#define PINMUX_BALL_B6_DMM_DATA_6				(0x2U <<  PINMUX_BALL_B6_SHIFT)
+
+#define PINMUX_BALL_B11_HET1_30				(0x1U <<  PINMUX_BALL_B11_SHIFT)
+#define PINMUX_BALL_B11_MII_RX_DV				(0x2U <<  PINMUX_BALL_B11_SHIFT)
+#define PINMUX_BALL_B11_OHCI_RCFG_speed_0		(0x4U <<  PINMUX_BALL_B11_SHIFT)
+
+#define PINMUX_BALL_C1_GIOA_2					(0x1U <<  PINMUX_BALL_C1_SHIFT)
+#define PINMUX_BALL_C1_OHCI_RCFG_txdPls_1		(0x2U <<  PINMUX_BALL_C1_SHIFT)
+#define PINMUX_BALL_C1_W2FC_TXDO				(0x4U <<  PINMUX_BALL_C1_SHIFT)
+#define PINMUX_BALL_C1_HET2_0					(0x8U <<  PINMUX_BALL_C1_SHIFT)
+
+#define PINMUX_BALL_C2_GIOA_1					(0x1U <<  PINMUX_BALL_C2_SHIFT)
+#define PINMUX_BALL_C2_OHCI_PRT_RcvDmns_1		(0x2U <<  PINMUX_BALL_C2_SHIFT)
+#define PINMUX_BALL_C2_W2FC_RXDMI				(0x4U <<  PINMUX_BALL_C2_SHIFT)
+
+#define PINMUX_BALL_C3_MIBSPI3NCS_3				(0x1U <<  PINMUX_BALL_C3_SHIFT)
+#define PINMUX_BALL_C3_I2C_SCL					(0x2U <<  PINMUX_BALL_C3_SHIFT)
+#define PINMUX_BALL_C3_HET1_29					(0x4U <<  PINMUX_BALL_C3_SHIFT)
+
+#define PINMUX_BALL_C4_EMIF_ADDR_6				(0x1U <<  PINMUX_BALL_C4_SHIFT)
+#define PINMUX_BALL_C4_RTP_DATA_13				(0x2U <<  PINMUX_BALL_C4_SHIFT)
+#define PINMUX_BALL_C4_HET2_11					(0x4U <<  PINMUX_BALL_C4_SHIFT)
+
+#define PINMUX_BALL_C5_EMIF_ADDR_7				(0x1U <<  PINMUX_BALL_C5_SHIFT)
+#define PINMUX_BALL_C5_RTP_DATA_12				(0x2U <<  PINMUX_BALL_C5_SHIFT)
+#define PINMUX_BALL_C5_HET2_13					(0x4U <<  PINMUX_BALL_C5_SHIFT)
+
+#define PINMUX_BALL_C6_EMIF_ADDR_8				(0x1U <<  PINMUX_BALL_C6_SHIFT)
+#define PINMUX_BALL_C6_RTP_DATA_11				(0x2U <<  PINMUX_BALL_C6_SHIFT)
+#define PINMUX_BALL_C6_HET2_15					(0x4U <<  PINMUX_BALL_C6_SHIFT)
+
+#define PINMUX_BALL_C7_EMIF_ADDR_9				(0x1U <<  PINMUX_BALL_C7_SHIFT)
+#define PINMUX_BALL_C7_RTP_DATA_10				(0x2U <<  PINMUX_BALL_C7_SHIFT)
+
+#define PINMUX_BALL_C8_EMIF_ADDR_10				(0x1U <<  PINMUX_BALL_C8_SHIFT)
+#define PINMUX_BALL_C8_RTP_DATA_09				(0x2U <<  PINMUX_BALL_C8_SHIFT)
+
+#define PINMUX_BALL_C9_EMIF_ADDR_11				(0x1U <<  PINMUX_BALL_C9_SHIFT)
+#define PINMUX_BALL_C9_RTP_DATA_08				(0x2U <<  PINMUX_BALL_C9_SHIFT)
+
+#define PINMUX_BALL_C10_EMIF_ADDR_12			(0x1U <<  PINMUX_BALL_C10_SHIFT)
+#define PINMUX_BALL_C10_RTP_DATA_06				(0x2U <<  PINMUX_BALL_C10_SHIFT)
+
+#define PINMUX_BALL_C11_EMIF_ADDR_13			(0x1U <<  PINMUX_BALL_C11_SHIFT)
+#define PINMUX_BALL_C11_RTP_DATA_05				(0x2U <<  PINMUX_BALL_C11_SHIFT)
+
+#define PINMUX_BALL_C12_EMIF_ADDR_14			(0x1U <<  PINMUX_BALL_C12_SHIFT)
+#define PINMUX_BALL_C12_RTP_DATA_04				(0x2U <<  PINMUX_BALL_C12_SHIFT)
+
+#define PINMUX_BALL_C13_EMIF_ADDR_15			(0x1U <<  PINMUX_BALL_C13_SHIFT)
+#define PINMUX_BALL_C13_RTP_DATA_03				(0x2U <<  PINMUX_BALL_C13_SHIFT)
+
+#define PINMUX_BALL_C14_EMIF_ADDR_17			(0x1U <<  PINMUX_BALL_C14_SHIFT)
+#define PINMUX_BALL_C14_RTP_DATA_01				(0x2U <<  PINMUX_BALL_C14_SHIFT)
+
+#define PINMUX_BALL_C15_EMIF_ADDR_19			(0x1U <<  PINMUX_BALL_C15_SHIFT)
+#define PINMUX_BALL_C15_RTP_nENA				(0x2U <<  PINMUX_BALL_C15_SHIFT)
+
+#define PINMUX_BALL_C16_EMIF_ADDR_20			(0x1U <<  PINMUX_BALL_C16_SHIFT)
+#define PINMUX_BALL_C16_RTP_nSYNC				(0x2U <<  PINMUX_BALL_C16_SHIFT)
+
+#define PINMUX_BALL_C17_EMIF_ADDR_21			(0x1U <<  PINMUX_BALL_C17_SHIFT)
+#define PINMUX_BALL_C17_RTP_CLK					(0x2U <<  PINMUX_BALL_C17_SHIFT)
+
+#define PINMUX_BALL_D3_SPI2NENA					(0x1U <<  PINMUX_BALL_D3_SHIFT)
+#define PINMUX_BALL_D3_SPI2NCS_1				(0x2U <<  PINMUX_BALL_D3_SHIFT)
+
+#define PINMUX_BALL_D4_EMIF_ADDR_0				(0x1U <<  PINMUX_BALL_D4_SHIFT)
+#define PINMUX_BALL_D4_HET2_1					(0x2U <<  PINMUX_BALL_D4_SHIFT)
+
+#define PINMUX_BALL_D5_EMIF_ADDR_1				(0x1U <<  PINMUX_BALL_D5_SHIFT)
+#define PINMUX_BALL_D5_HET2_3					(0x2U <<  PINMUX_BALL_D5_SHIFT)
+
+#define PINMUX_BALL_D14_EMIF_ADDR_16			(0x1U <<  PINMUX_BALL_D14_SHIFT)
+#define PINMUX_BALL_D14_RTP_DATA_02				(0x2U <<  PINMUX_BALL_D14_SHIFT)
+
+#define PINMUX_BALL_D15_EMIF_ADDR_18			(0x1U <<  PINMUX_BALL_D15_SHIFT)
+#define PINMUX_BALL_D15_RTP_DATA_0				(0x2U <<  PINMUX_BALL_D15_SHIFT)
+
+#define PINMUX_BALL_D16_EMIF_BA_1				(0x1U <<  PINMUX_BALL_D16_SHIFT)
+#define PINMUX_BALL_D16_HET2_5					(0x2U <<  PINMUX_BALL_D16_SHIFT)
+
+#define PINMUX_BALL_D17_EMIF_nWE				(0x1U <<  PINMUX_BALL_D17_SHIFT)
+#define PINMUX_BALL_D17_EMIF_RNW				(0x2U <<  PINMUX_BALL_D17_SHIFT)
+
+#define PINMUX_BALL_D19_HET1_10				(0x1U <<  PINMUX_BALL_D19_SHIFT)
+#define PINMUX_BALL_D19_MII_TX_CLK				(0x2U <<  PINMUX_BALL_D19_SHIFT)
+#define PINMUX_BALL_D19_OHCI_RCFG_txEnL_0		(0x4U <<  PINMUX_BALL_D19_SHIFT)
+#define PINMUX_BALL_D19_MII_TX_AVCLK4			(0x8U <<  PINMUX_BALL_D19_SHIFT)
+
+#define PINMUX_BALL_E1_GIOA_3					(0x1U <<  PINMUX_BALL_E1_SHIFT)
+#define PINMUX_BALL_E1_HET2_2					(0x2U <<  PINMUX_BALL_E1_SHIFT)
+
+#define PINMUX_BALL_E3_HET1_11					(0x1U <<  PINMUX_BALL_E3_SHIFT)
+#define PINMUX_BALL_E3_MIBSPI3NCS_4				(0x2U <<  PINMUX_BALL_E3_SHIFT)
+#define PINMUX_BALL_E3_HET2_18					(0x4U <<  PINMUX_BALL_E3_SHIFT)
+#define PINMUX_BALL_E3_OHCI_PRT_OvrCurrent_1	(0x8U <<  PINMUX_BALL_E3_SHIFT)
+#define PINMUX_BALL_E3_W2FC_VBUSI				(0x10U <<  PINMUX_BALL_E3_SHIFT)
+
+#define PINMUX_BALL_E5_ETMDATA_20				(0x1U <<  PINMUX_BALL_E5_SHIFT)
+#define PINMUX_BALL_E5_EMIF_DATA_4				(0x2U <<  PINMUX_BALL_E5_SHIFT)
+
+#define PINMUX_BALL_E6_ETMDATA_11				(0x1U <<  PINMUX_BALL_E6_SHIFT)
+#define PINMUX_BALL_E6_EMIF_ADDR_2				(0x2U <<  PINMUX_BALL_E6_SHIFT)
+
+#define PINMUX_BALL_E7_ETMDATA_10				(0x1U <<  PINMUX_BALL_E7_SHIFT)
+#define PINMUX_BALL_E7_EMIF_ADDR_3				(0x2U <<  PINMUX_BALL_E7_SHIFT)
+
+#define PINMUX_BALL_E8_ETMDATA_09				(0x1U <<  PINMUX_BALL_E8_SHIFT)
+#define PINMUX_BALL_E8_EMIF_ADDR_4				(0x2U <<  PINMUX_BALL_E8_SHIFT)
+
+#define PINMUX_BALL_E9_ETMDATA_08				(0x1U <<  PINMUX_BALL_E9_SHIFT)
+#define PINMUX_BALL_E9_EMIF_ADDR_5				(0x2U <<  PINMUX_BALL_E9_SHIFT)
+
+#define PINMUX_BALL_E10_ETMDATA_15				(0x1U <<  PINMUX_BALL_E10_SHIFT)
+#define PINMUX_BALL_E10_EMIF_nDQM_0				(0x2U <<  PINMUX_BALL_E10_SHIFT)
+
+#define PINMUX_BALL_E11_ETMDATA_14				(0x1U <<  PINMUX_BALL_E11_SHIFT)
+#define PINMUX_BALL_E11_EMIF_nDQM_1				(0x2U <<  PINMUX_BALL_E11_SHIFT)
+
+#define PINMUX_BALL_E12_ETMDATA_13				(0x1U <<  PINMUX_BALL_E12_SHIFT)
+#define PINMUX_BALL_E12_EMIF_nOE				(0x2U <<  PINMUX_BALL_E12_SHIFT)
+
+#define PINMUX_BALL_E13_ETMDATA_12				(0x1U <<  PINMUX_BALL_E13_SHIFT)
+#define PINMUX_BALL_E13_EMIF_BA_0				(0x2U <<  PINMUX_BALL_E13_SHIFT)
+
+#define PINMUX_BALL_E16_MIBSPI5SIMO_1			(0x1U <<  PINMUX_BALL_E16_SHIFT)
+#define PINMUX_BALL_E16_DMM_DATA_9				(0x2U <<  PINMUX_BALL_E16_SHIFT)
+
+#define PINMUX_BALL_E17_MIBSPI5SOMI_1			(0x1U <<  PINMUX_BALL_E17_SHIFT)
+#define PINMUX_BALL_E17_DMM_DATA_13				(0x2U <<  PINMUX_BALL_E17_SHIFT)
+
+#define PINMUX_BALL_E18_HET1_08				(0x1U <<  PINMUX_BALL_E18_SHIFT)
+#define PINMUX_BALL_E18_MIBSPI1SIMO_1			(0x2U <<  PINMUX_BALL_E18_SHIFT)
+#define PINMUX_BALL_E18_MII_TXD_3				(0x4U <<  PINMUX_BALL_E18_SHIFT)
+#define PINMUX_BALL_E18_OHCI_PRT_OvrCurrent_0	(0x8U <<  PINMUX_BALL_E18_SHIFT)
+
+#define PINMUX_BALL_E19_MIBSPI5NCS_0			(0x1U <<  PINMUX_BALL_E19_SHIFT)
+#define PINMUX_BALL_E19_DMM_DATA_5				(0x2U <<  PINMUX_BALL_E19_SHIFT)
+
+#define PINMUX_BALL_F3_MIBSPI1NCS_1				(0x1U <<  PINMUX_BALL_F3_SHIFT)
+#define PINMUX_BALL_F3_HET1_17					(0x2U <<  PINMUX_BALL_F3_SHIFT)
+#define PINMUX_BALL_F3_MII_COL					(0x4U <<  PINMUX_BALL_F3_SHIFT)
+#define PINMUX_BALL_F3_OHCI_RCFG_suspend_0		(0x8U <<  PINMUX_BALL_F3_SHIFT)
+
+#define PINMUX_BALL_F5_ETMDATA_21				(0x1U <<  PINMUX_BALL_F5_SHIFT)
+#define PINMUX_BALL_F5_EMIF_DATA_5				(0x2U <<  PINMUX_BALL_F5_SHIFT)
+
+#define PINMUX_BALL_G3_MIBSPI1NCS_2				(0x1U <<  PINMUX_BALL_G3_SHIFT)
+#define PINMUX_BALL_G3_HET1_19					(0x2U <<  PINMUX_BALL_G3_SHIFT)
+#define PINMUX_BALL_G3_MDIO						(0x4U <<  PINMUX_BALL_G3_SHIFT)
+
+#define PINMUX_BALL_G5_ETMDATA_22				(0x1U <<  PINMUX_BALL_G5_SHIFT)
+#define PINMUX_BALL_G5_EMIF_DATA_6				(0x2U <<  PINMUX_BALL_G5_SHIFT)
+
+#define PINMUX_BALL_G16_MIBSPI5SOMI_3			(0x1U <<  PINMUX_BALL_G16_SHIFT)
+#define PINMUX_BALL_G16_DMM_DATA_15				(0x2U <<  PINMUX_BALL_G16_SHIFT)
+
+#define PINMUX_BALL_G17_MIBSPI5SIMO_3			(0x1U <<  PINMUX_BALL_G17_SHIFT)
+#define PINMUX_BALL_G17_DMM_DATA_11				(0x2U <<  PINMUX_BALL_G17_SHIFT)
+
+#define PINMUX_BALL_G19_MIBSPI1NENA				(0x1U <<  PINMUX_BALL_G19_SHIFT)
+#define PINMUX_BALL_G19_HET1_23				(0x2U <<  PINMUX_BALL_G19_SHIFT)
+#define PINMUX_BALL_G19_MII_RXD_2				(0x4U <<  PINMUX_BALL_G19_SHIFT)
+#define PINMUX_BALL_G19_OHCI_PRT_RcvDpls_0		(0x8U <<  PINMUX_BALL_G19_SHIFT)
+
+#define PINMUX_BALL_H3_GIOA_6					(0x1U <<  PINMUX_BALL_H3_SHIFT)
+#define PINMUX_BALL_H3_HET2_4					(0x2U <<  PINMUX_BALL_H3_SHIFT)
+
+#define PINMUX_BALL_H16_MIBSPI5SOMI_2			(0x1U <<  PINMUX_BALL_H16_SHIFT)
+#define PINMUX_BALL_H16_DMM_DATA_14				(0x2U <<  PINMUX_BALL_H16_SHIFT)
+
+#define PINMUX_BALL_H17_MIBSPI5SIMO_2			(0x1U <<  PINMUX_BALL_H17_SHIFT)
+#define PINMUX_BALL_H17_DMM_DATA_10				(0x2U <<  PINMUX_BALL_H17_SHIFT)
+
+#define PINMUX_BALL_H18_MIBSPI5NENA				(0x1U <<  PINMUX_BALL_H18_SHIFT)
+#define PINMUX_BALL_H18_DMM_DATA_7				(0x2U <<  PINMUX_BALL_H18_SHIFT)
+#define PINMUX_BALL_H18_MII_RXD_3				(0x4U <<  PINMUX_BALL_H18_SHIFT)
+#define PINMUX_BALL_H18_OHCI_PRT_RcvDmns_0		(0x8U <<  PINMUX_BALL_H18_SHIFT)
+
+#define PINMUX_BALL_H19_MIBSPI5CLK				(0x1U <<  PINMUX_BALL_H19_SHIFT)
+#define PINMUX_BALL_H19_DMM_DATA_4				(0x2U <<  PINMUX_BALL_H19_SHIFT)
+#define PINMUX_BALL_H19_MII_TXEN				(0x4U <<  PINMUX_BALL_H19_SHIFT)
+#define PINMUX_BALL_H19_RMII_TXEN				(0x8U <<  PINMUX_BALL_H19_SHIFT)
+
+#define PINMUX_BALL_J3_MIBSPI1NCS_3				(0x1U <<  PINMUX_BALL_J3_SHIFT)
+#define PINMUX_BALL_J3_HET1_21					(0x2U <<  PINMUX_BALL_J3_SHIFT)
+
+#define PINMUX_BALL_J18_MIBSPI5SOMI_0			(0x1U <<  PINMUX_BALL_J18_SHIFT)
+#define PINMUX_BALL_J18_DMM_DATA_12				(0x2U <<  PINMUX_BALL_J18_SHIFT)
+#define PINMUX_BALL_J18_MII_TXD_0				(0x4U <<  PINMUX_BALL_J18_SHIFT)
+#define PINMUX_BALL_J18_RMII_TXD_0				(0x8U <<  PINMUX_BALL_J18_SHIFT)
+
+#define PINMUX_BALL_J19_MIBSPI5SIMO_0			(0x1U <<  PINMUX_BALL_J19_SHIFT)
+#define PINMUX_BALL_J19_DMM_DATA_8				(0x2U <<  PINMUX_BALL_J19_SHIFT)
+#define PINMUX_BALL_J19_MII_TXD_1				(0x4U <<  PINMUX_BALL_J19_SHIFT)
+#define PINMUX_BALL_J19_RMII_TXD_1				(0x8U <<  PINMUX_BALL_J19_SHIFT)
+
+#define PINMUX_BALL_K2_GIOB_1					(0x1U <<  PINMUX_BALL_K2_SHIFT)
+#define PINMUX_BALL_K2_OHCI_RCFG_PrtPower_0		(0x2U <<  PINMUX_BALL_K2_SHIFT)
+
+#define PINMUX_BALL_K5_ETMDATA_23				(0x1U <<  PINMUX_BALL_K5_SHIFT)
+#define PINMUX_BALL_K5_EMIF_DATA_7				(0x2U <<  PINMUX_BALL_K5_SHIFT)
+
+#define PINMUX_BALL_K15_ETMDATA_16				(0x1U <<  PINMUX_BALL_K15_SHIFT)
+#define PINMUX_BALL_K15_EMIF_DATA_0				(0x2U <<  PINMUX_BALL_K15_SHIFT)
+
+#define PINMUX_BALL_K17_EMIF_nCS_3				(0x1U <<  PINMUX_BALL_K17_SHIFT)
+#define PINMUX_BALL_K17_RTP_DATA_14				(0x2U <<  PINMUX_BALL_K17_SHIFT)
+#define PINMUX_BALL_K17_HET2_9					(0x4U <<  PINMUX_BALL_K17_SHIFT)
+
+#define PINMUX_BALL_K18_HET1_0					(0x1U <<  PINMUX_BALL_K18_SHIFT)
+#define PINMUX_BALL_K18_SPI4CLK					(0x2U <<  PINMUX_BALL_K18_SHIFT)
+
+#define PINMUX_BALL_K19_HET1_28				(0x1U <<  PINMUX_BALL_K19_SHIFT)
+#define PINMUX_BALL_K19_MII_RXCLK				(0x2U <<  PINMUX_BALL_K19_SHIFT)
+#define PINMUX_BALL_K19_RMII_REFCLK				(0x4U <<  PINMUX_BALL_K19_SHIFT)
+#define PINMUX_BALL_K19_MII_RX_AVCLK4			(0x8U <<  PINMUX_BALL_K19_SHIFT)
+
+#define PINMUX_BALL_L5_ETMDATA_24				(0x1U <<  PINMUX_BALL_L5_SHIFT)
+#define PINMUX_BALL_L5_EMIF_DATA_8				(0x2U <<  PINMUX_BALL_L5_SHIFT)
+
+#define PINMUX_BALL_L15_ETMDATA_17				(0x1U <<  PINMUX_BALL_L15_SHIFT)
+#define PINMUX_BALL_L15_EMIF_DATA_1				(0x2U <<  PINMUX_BALL_L15_SHIFT)
+
+#define PINMUX_BALL_M1_GIOA_7					(0x1U <<  PINMUX_BALL_M1_SHIFT)
+#define PINMUX_BALL_M1_HET2_6					(0x2U <<  PINMUX_BALL_M1_SHIFT)
+
+#define PINMUX_BALL_M2_GIOB_0					(0x1U <<  PINMUX_BALL_M2_SHIFT)
+#define PINMUX_BALL_M2_OHCI_RCFG_txDpls_0		(0x2U <<  PINMUX_BALL_M2_SHIFT)
+
+#define PINMUX_BALL_M5_ETMDATA_25				(0x1U <<  PINMUX_BALL_M5_SHIFT)
+#define PINMUX_BALL_M5_EMIF_DATA_9				(0x2U <<  PINMUX_BALL_M5_SHIFT)
+
+#define PINMUX_BALL_M15_ETMDATA_18				(0x1U <<  PINMUX_BALL_M15_SHIFT)
+#define PINMUX_BALL_M15_EMIF_DATA_2				(0x2U <<  PINMUX_BALL_M15_SHIFT)
+
+#define PINMUX_BALL_M17_EMIF_nCS_4				(0x1U <<  PINMUX_BALL_M17_SHIFT)
+#define PINMUX_BALL_M17_RTP_DATA_07				(0x2U <<  PINMUX_BALL_M17_SHIFT)
+
+#define PINMUX_BALL_N1_HET1_15					(0x1U <<  PINMUX_BALL_N1_SHIFT)
+#define PINMUX_BALL_N1_MIBSPI1NCS_4				(0x2U <<  PINMUX_BALL_N1_SHIFT)
+
+#define PINMUX_BALL_N2_HET1_13					(0x1U <<  PINMUX_BALL_N2_SHIFT)
+#define PINMUX_BALL_N2_SCITX					(0x2U <<  PINMUX_BALL_N2_SHIFT)
+
+#define PINMUX_BALL_N5_ETMDATA_26				(0x1U <<  PINMUX_BALL_N5_SHIFT)
+#define PINMUX_BALL_N5_EMIF_DATA_10				(0x2U <<  PINMUX_BALL_N5_SHIFT)
+
+#define PINMUX_BALL_N15_ETMDATA_19				(0x1U <<  PINMUX_BALL_N15_SHIFT)
+#define PINMUX_BALL_N15_EMIF_DATA_3				(0x2U <<  PINMUX_BALL_N15_SHIFT)
+
+#define PINMUX_BALL_N17_EMIF_nCS_0				(0x1U <<  PINMUX_BALL_N17_SHIFT)
+#define PINMUX_BALL_N17_RTP_DATA_15				(0x2U <<  PINMUX_BALL_N17_SHIFT)
+#define PINMUX_BALL_N17_HET2_7					(0x4U <<  PINMUX_BALL_N17_SHIFT)
+
+#define PINMUX_BALL_N19_AD1EVT					(0x1U <<  PINMUX_BALL_N19_SHIFT)
+#define PINMUX_BALL_N19_MII_RX_ER				(0x2U <<  PINMUX_BALL_N19_SHIFT)
+#define PINMUX_BALL_N19_RMII_RX_ER				(0x4U <<  PINMUX_BALL_N19_SHIFT)
+
+#define PINMUX_BALL_P1_HET1_24					(0x1U <<  PINMUX_BALL_P1_SHIFT)
+#define PINMUX_BALL_P1_MIBSPI1NCS_5				(0x2U <<  PINMUX_BALL_P1_SHIFT)
+#define PINMUX_BALL_P1_MII_RXD_0				(0x4U <<  PINMUX_BALL_P1_SHIFT)
+#define PINMUX_BALL_P1_RMII_RXD_0				(0x8U <<  PINMUX_BALL_P1_SHIFT)
+
+#define PINMUX_BALL_P5_ETMDATA_27				(0x1U <<  PINMUX_BALL_P5_SHIFT)
+#define PINMUX_BALL_P5_EMIF_DATA_11				(0x2U <<  PINMUX_BALL_P5_SHIFT)
+
+#define PINMUX_BALL_R2_MIBSPI1NCS_0				(0x1U <<  PINMUX_BALL_R2_SHIFT)
+#define PINMUX_BALL_R2_MIBSPI1SOMI_1			(0x2U <<  PINMUX_BALL_R2_SHIFT)
+#define PINMUX_BALL_R2_MII_TXD_2				(0x4U <<  PINMUX_BALL_R2_SHIFT)
+#define PINMUX_BALL_R2_OHCI_PRT_RcvData_0		(0x8U <<  PINMUX_BALL_R2_SHIFT)
+
+#define PINMUX_BALL_R5_ETMDATA_28				(0x1U <<  PINMUX_BALL_R5_SHIFT)
+#define PINMUX_BALL_R5_EMIF_DATA_12				(0x2U <<  PINMUX_BALL_R5_SHIFT)
+
+#define PINMUX_BALL_R6_ETMDATA_29				(0x1U <<  PINMUX_BALL_R6_SHIFT)
+#define PINMUX_BALL_R6_EMIF_DATA_13				(0x2U <<  PINMUX_BALL_R6_SHIFT)
+
+#define PINMUX_BALL_R7_ETMDATA_30				(0x1U <<  PINMUX_BALL_R7_SHIFT)
+#define PINMUX_BALL_R7_EMIF_DATA_14				(0x2U <<  PINMUX_BALL_R7_SHIFT)
+	
+#define PINMUX_BALL_R8_ETMDATA_31				(0x1U <<  PINMUX_BALL_R8_SHIFT)
+#define PINMUX_BALL_R8_EMIF_DATA_15				(0x2U <<  PINMUX_BALL_R8_SHIFT)
+
+#define PINMUX_BALL_R9_ETMTRACECLKIN			(0x1U <<  PINMUX_BALL_R9_SHIFT)
+#define PINMUX_BALL_R9_EXTCLKIN2				(0x2U <<  PINMUX_BALL_R9_SHIFT)
+
+#define PINMUX_BALL_T1_HET1_07					(0x1U <<  PINMUX_BALL_T1_SHIFT)
+#define PINMUX_BALL_T1_OHCI_RCFG_PrtPower_1		(0x2U <<  PINMUX_BALL_T1_SHIFT)
+#define PINMUX_BALL_T1_W2FC_GZO					(0x4U <<  PINMUX_BALL_T1_SHIFT)
+#define PINMUX_BALL_T1_HET2_14					(0x8U <<  PINMUX_BALL_T1_SHIFT)
+
+#define PINMUX_BALL_T12_MIBSPI5NCS_3			(0x1U <<  PINMUX_BALL_T12_SHIFT)
+#define PINMUX_BALL_T12_DMM_DATA_3				(0x2U <<  PINMUX_BALL_T12_SHIFT)
+
+#define PINMUX_BALL_U1_HET1_03					(0x1U <<  PINMUX_BALL_U1_SHIFT)
+#define PINMUX_BALL_U1_SPI4NCS_0				(0x2U <<  PINMUX_BALL_U1_SHIFT)
+#define PINMUX_BALL_U1_OHCI_RCFG_speed_1		(0x4U <<  PINMUX_BALL_U1_SHIFT)
+#define PINMUX_BALL_U1_W2FC_PUENON				(0x8U <<  PINMUX_BALL_U1_SHIFT)
+#define PINMUX_BALL_U1_HET2_10					(0x10U <<  PINMUX_BALL_U1_SHIFT)
+
+#define PINMUX_BALL_V2_HET1_01					(0x1U <<  PINMUX_BALL_V2_SHIFT)
+#define PINMUX_BALL_V2_SPI4NENA					(0x2U <<  PINMUX_BALL_V2_SHIFT)
+#define PINMUX_BALL_V2_OHCI_RCFG_txEnL_1		(0x4U <<  PINMUX_BALL_V2_SHIFT)
+#define PINMUX_BALL_V2_W2FC_PUENO				(0x8U <<  PINMUX_BALL_V2_SHIFT)
+#define PINMUX_BALL_V2_HET2_8					(0x10U <<  PINMUX_BALL_V2_SHIFT)
+
+#define PINMUX_BALL_V5_MIBSPI3NCS_1				(0x1U <<  PINMUX_BALL_V5_SHIFT)
+#define PINMUX_BALL_V5_HET1_25					(0x2U <<  PINMUX_BALL_V5_SHIFT)
+#define PINMUX_BALL_V5_MDCLK					(0x4U <<  PINMUX_BALL_V5_SHIFT)
+
+#define PINMUX_BALL_V6_HET1_05					(0x1U <<  PINMUX_BALL_V6_SHIFT)
+#define PINMUX_BALL_V6_SPI4SOMI					(0x2U <<  PINMUX_BALL_V6_SHIFT)
+#define PINMUX_BALL_V6_HET2_12					(0x4U <<  PINMUX_BALL_V6_SHIFT)
+
+#define PINMUX_BALL_V7_HET1_09					(0x1U <<  PINMUX_BALL_V7_SHIFT)
+#define PINMUX_BALL_V7_HET2_16					(0x2U <<  PINMUX_BALL_V7_SHIFT)
+#define PINMUX_BALL_V7_OHCI_RCFG_suspend_1		(0x4U <<  PINMUX_BALL_V7_SHIFT)
+#define PINMUX_BALL_V7_W2FC_SUSPENDO			(0x8U <<  PINMUX_BALL_V7_SHIFT)
+
+#define PINMUX_BALL_V10_MIBSPI3NCS_0			(0x1U <<  PINMUX_BALL_V10_SHIFT)
+#define PINMUX_BALL_V10_AD2EVT					(0x2U <<  PINMUX_BALL_V10_SHIFT)
+#define PINMUX_BALL_V10_GIOB_2					(0x4U <<  PINMUX_BALL_V10_SHIFT)
+
+#define PINMUX_BALL_W3_HET1_06					(0x1U <<  PINMUX_BALL_W3_SHIFT)
+#define PINMUX_BALL_W3_SCIRX					(0x2U <<  PINMUX_BALL_W3_SHIFT)
+
+#define PINMUX_BALL_W5_HET1_02					(0x1U <<  PINMUX_BALL_W5_SHIFT)
+#define PINMUX_BALL_W5_SPI4SIMO					(0x2U <<  PINMUX_BALL_W5_SHIFT)
+
+#define PINMUX_BALL_W6_MIBSPI5NCS_2				(0x1U <<  PINMUX_BALL_W6_SHIFT)
+#define PINMUX_BALL_W6_DMM_DATA_2				(0x2U <<  PINMUX_BALL_W6_SHIFT)
+
+#define PINMUX_BALL_W9_MIBSPI3NENA				(0x1U <<  PINMUX_BALL_W9_SHIFT)
+#define PINMUX_BALL_W9_MIBSPI3NCS_5				(0x2U <<  PINMUX_BALL_W9_SHIFT)
+#define PINMUX_BALL_W9_HET1_31					(0x4U <<  PINMUX_BALL_W9_SHIFT)
+
+#define PINMUX_BALL_W10_GIOB_3					(0x1U <<  PINMUX_BALL_W10_SHIFT)
+#define PINMUX_BALL_W10_OHCI_PRT_RcvData_1		(0x2U <<  PINMUX_BALL_W10_SHIFT)
+#define PINMUX_BALL_W10_W2FC_RXDI				(0x4U <<  PINMUX_BALL_W10_SHIFT)
+
+#define PINMUX_GATE_EMIF_CLK_ON                                 (0x0 <<  PINMUX_GATE_EMIF_CLK_SHIFT)      /**/ 
+#define PINMUX_GIOB_DISABLE_HET2_ON                             (0x1U <<  PINMUX_GIOB_DISABLE_HET2_SHIFT)
+#define PINMUX_GATE_EMIF_CLK_OFF                                (0x1U <<  PINMUX_GATE_EMIF_CLK_SHIFT)    
+#define PINMUX_GIOB_DISABLE_HET2_OFF                            (0x0 <<  PINMUX_GIOB_DISABLE_HET2_SHIFT)
+#define PINMUX_ALT_ADC_TRIGGER_1				(0x1U <<  PINMUX_ALT_ADC_TRIGGER_SHIFT)
+#define PINMUX_ALT_ADC_TRIGGER_2				(0x2U <<  PINMUX_ALT_ADC_TRIGGER_SHIFT)
+#define PINMUX_ETHERNET_MII						(0x0 <<  PINMUX_ETHERNET_SHIFT)
+#define PINMUX_ETHERNET_RMII					(0x1U <<  PINMUX_ETHERNET_SHIFT)
+
+/** @fn void muxInit(void)
+*   @brief Initializes the PINMUX Driver
+*
+*   This function initializes the PINMUX module and configures the selected 
+*   pinmux settings as per the user selection in the GUI
+*/
+void muxInit(void);
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/pom.h b/bsp/rm48x50/HALCoGen/include/pom.h
new file mode 100644
index 0000000000000000000000000000000000000000..9d1b994ccf9a8aa4f8bd2a289e411edf0ef9ae40
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/pom.h
@@ -0,0 +1,97 @@
+/** @file pom.h
+*   @brief POM Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __POM_H__
+#define __POM_H__
+
+#include "reg_pom.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/** @enum pom_region_size
+*   @brief Alias names for pom region size
+*   This enumeration is used to provide alias names for POM region size:
+*/
+enum pom_region_size
+{
+        SIZE_32BYTES    = 0U,
+        SIZE_64BYTES    = 1U,
+        SIZE_128BYTES   = 2U,
+        SIZE_256BYTES   = 3U,
+        SIZE_512BYTES   = 4U,
+        SIZE_1KB        = 5U,
+        SIZE_2KB        = 6U,
+        SIZE_4KB        = 7U,
+        SIZE_8KB        = 8U,
+        SIZE_16KB       = 9U,
+        SIZE_32KB       = 10U,
+        SIZE_64KB       = 11U,
+        SIZE_128KB      = 12U,
+        SIZE_256KB      = 13U
+};
+
+/** @def INTERNAL_RAM 
+*   @brief Alias name for Internal RAM
+*/   
+#define INTERNAL_RAM    0x08000000U
+
+/** @def SDRAM 
+*   @brief Alias name for SD RAM
+*/   
+#define SDRAM   0x80000000U
+
+/** @def ASYNC_MEMORY 
+*   @brief Alias name for Async RAM
+*/   
+#define ASYNC_MEMORY   0x60000000U
+
+
+typedef uint32 REGION_t;
+
+/** @struct REGION_CONFIG_ST
+*   @brief POM region configuration
+*/
+typedef struct
+{       
+        uint32 Prog_Reg_Sta_Addr;
+        uint32 Ovly_Reg_Sta_Addr;
+        uint32 Reg_Size;
+}REGION_CONFIG_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** 
+ *  @defgroup POM POM
+ *  @brief Parameter Overlay Module.
+ *  
+ *  The POM provides a mechanism to redirect accesses to non-volatile memory into a volatile memory
+ *  internal or external to the device. The data requested by the CPU will be fetched from the overlay memory
+ *  instead of the main non-volatile memory.
+ *
+ *	Related Files
+ *   - reg_pom.h
+ *   - pom.h
+ *   - pom.c
+ *  @addtogroup POM
+ *  @{
+ */
+ 
+/* POM Interface Functions */
+void POM_Region_Config(REGION_CONFIG_t *Reg_Config_Ptr,REGION_t Region_Num);
+void POM_Reset(void);
+void POM_Init(void);
+void POM_Disable(void);
+
+/**@}*/
+#endif /* __POM_H_*/
diff --git a/bsp/rm48x50/HALCoGen/include/reg_adc.h b/bsp/rm48x50/HALCoGen/include/reg_adc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5ce7bded0de56f640a39c7393148bc4284d7771d
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_adc.h
@@ -0,0 +1,162 @@
+/** @file reg_adc.h
+*   @brief ADC Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ADC driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_ADC_H__
+#define __REG_ADC_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Adc Register Frame Definition */
+/** @struct adcBase
+*   @brief ADC Register Frame Definition
+*
+*   This type is used to access the ADC Registers.
+*/
+/** @typedef adcBASE_t
+*   @brief ADC Register Frame Type Definition
+*
+*   This type is used to access the ADC Registers.
+*/
+typedef volatile struct adcBase
+{
+    uint32 RSTCR;              /**< 0x0000: Reset control register                            */
+    uint32 OPMODECR;           /**< 0x0004: Operating mode control register                   */
+    uint32 CLOCKCR;            /**< 0x0008: Clock control register                            */
+    uint32 CALCR;              /**< 0x000C: Calibration control register                      */
+    uint32 GxMODECR[3U];       /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register     */
+    uint32 G0SRC;              /**< 0x001C: Group 0 trigger source control register           */
+    uint32 G1SRC;              /**< 0x0020: Group 1 trigger source control register           */
+    uint32 G2SRC;              /**< 0x0024: Group 2 trigger source control register           */
+    uint32 GxINTENA[3U];       /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register */
+    uint32 GxINTFLG[3U];       /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register   */
+    uint32 GxINTCR[3U];        /**< 0x0040-0x0048: Group 0-2 interrupt threshold register     */
+    uint32 G0DMACR;            /**< 0x004C: Group 0 DMA control register                      */
+    uint32 G1DMACR;            /**< 0x0050: Group 1 DMA control register                      */
+    uint32 G2DMACR;            /**< 0x0054: Group 2 DMA control register                      */
+    uint32 BNDCR;              /**< 0x0058: Buffer boundary control register                  */
+    uint32 BNDEND;             /**< 0x005C: Buffer boundary end register                      */
+    uint32 G0SAMP;             /**< 0x0060: Group 0 sample window register                    */
+    uint32 G1SAMP;             /**< 0x0064: Group 1 sample window register                    */
+    uint32 G2SAMP;             /**< 0x0068: Group 2 sample window register                    */
+    uint32 G0SR;               /**< 0x006C: Group 0 status register                           */
+    uint32 G1SR;               /**< 0x0070: Group 1 status register                           */
+    uint32 G2SR;               /**< 0x0074: Group 2 status register                           */
+    uint32 GxSEL[3U];          /**< 0x0078-0x007C: Group 0-2 channel select register          */
+    uint32 CALR;               /**< 0x0084: Calibration register                              */
+    uint32 SMSTATE;            /**< 0x0088: State machine state register                      */
+    uint32 LASTCONV;           /**< 0x008C: Last conversion register                          */
+    struct
+    {
+        uint32 BUF0;           /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register  */
+        uint32 BUF1;           /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register  */
+        uint32 BUF2;           /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register  */
+        uint32 BUF3;           /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register  */
+        uint32 BUF4;           /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register  */
+        uint32 BUF5;           /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register  */
+        uint32 BUF6;           /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register  */
+        uint32 BUF7;           /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register  */
+    } GxBUF[3U];
+    uint32 G0EMUBUFFER;        /**< 0x00F0: Group 0 emulation result buffer                   */
+    uint32 G1EMUBUFFER;        /**< 0x00F4: Group 1 emulation result buffer                   */
+    uint32 G2EMUBUFFER;        /**< 0x00F8: Group 2 emulation result buffer                   */
+    uint32 EVTDIR;             /**< 0x00FC: Event pin direction register                      */
+    uint32 EVTOUT;             /**< 0x0100: Event pin digital output register                 */
+    uint32 EVTIN;              /**< 0x0104: Event pin digital input register                  */
+    uint32 EVTSET;             /**< 0x0108: Event pin set register                            */
+    uint32 EVTCLR;             /**< 0x010C: Event pin clear register                          */
+    uint32 EVTPDR;             /**< 0x0110: Event pin open drain register                     */
+    uint32 EVTDIS;             /**< 0x0114: Event pin pull disable register                   */
+    uint32 EVTPSEL;            /**< 0x0118: Event pin pull select register                    */
+    uint32 G0SAMPDISEN;        /**< 0x011C: Group 0 sample discharge register                 */
+    uint32 G1SAMPDISEN;        /**< 0x0120: Group 1 sample discharge register                 */
+    uint32 G2SAMPDISEN;        /**< 0x0124: Group 2 sample discharge register                 */
+    uint32 MAGINTCR1;          /**< 0x0128: Magnitude interrupt control register 1            */
+    uint32 MAGINT1MASK;        /**< 0x012C: Magnitude interrupt mask register 1               */
+    uint32 MAGINTCR2;          /**< 0x0130: Magnitude interrupt control register 2            */
+    uint32 MAGINT2MASK;        /**< 0x0134: Magnitude interrupt mask register 2               */
+    uint32 MAGINTCR3;          /**< 0x0138: Magnitude interrupt control register 3            */
+    uint32 MAGINT3MASK;        /**< 0x013C: Magnitude interrupt mask register 3               */
+    uint32 MAGINTCR4;          /**< 0x0140: Magnitude interrupt control register 4            */
+    uint32 MAGINT4MASK;        /**< 0x0144: Magnitude interrupt mask register 4               */
+    uint32 MAGINTCR5;          /**< 0x0148: Magnitude interrupt control register 5            */
+    uint32 MAGINT5MASK;        /**< 0x014C: Magnitude interrupt mask register 5               */
+    uint32 MAGINTCR6;          /**< 0x0150: Magnitude interrupt control register 6            */
+    uint32 MAGINT6MASK;        /**< 0x0154: Magnitude interrupt mask register 6               */
+    uint32 MAGTHRINTENASET;    /**< 0x0158: Magnitude interrupt set register                  */
+    uint32 MAGTHRINTENACLR;    /**< 0x015C: Magnitude interrupt clear register                */
+    uint32 MAGTHRINTFLG;       /**< 0x0160: Magnitude interrupt flag register                 */
+    uint32 MAGTHRINTOFFSET;    /**< 0x0164: Magnitude interrupt offset register               */
+    uint32 GxFIFORESETCR[3U];  /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register       */
+    uint32 G0RAMADDR;          /**< 0x0174: Group 0 RAM pointer register                      */
+    uint32 G1RAMADDR;          /**< 0x0178: Group 1 RAM pointer register                      */
+    uint32 G2RAMADDR;          /**< 0x017C: Group 2 RAM pointer register                      */
+    uint32 PARCR;              /**< 0x0180: Parity control register                           */
+    uint32 PARADDR;            /**< 0x0184: Parity error address register                     */
+    uint32 PWRUPDLYCTRL;       /**< 0x0188: Power-Up delay control register                   */
+} adcBASE_t;
+
+
+/** @def adcREG1
+*   @brief ADC1 Register Frame Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC1 registers.
+*/
+#define adcREG1 ((adcBASE_t *)0xFFF7C000U)
+
+/** @def adcREG2
+*   @brief ADC2 Register Frame Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC2 registers.
+*/
+#define adcREG2 ((adcBASE_t *)0xFFF7C200U)
+
+/** @def adcRAM1
+*   @brief ADC1 RAM Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC1 RAM.
+*/
+#define adcRAM1 (*(volatile uint32 *)0xFF3E0000U)
+
+/** @def adcRAM2
+*   @brief ADC2 RAM Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC2 RAM.
+*/
+#define adcRAM2 (*(volatile uint32 *)0xFF3A0000U)
+
+/** @def adcPARRAM1
+*   @brief ADC1 Parity RAM Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC1 Parity RAM.
+*/
+#define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U))
+
+/** @def adcPARRAM2
+*   @brief ADC2 Parity RAM Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC2 Parity RAM.
+*/
+#define adcPARRAM2 (*(volatile uint32 *)(0xFF3A0000U + 0x1000U))
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_can.h b/bsp/rm48x50/HALCoGen/include/reg_can.h
new file mode 100644
index 0000000000000000000000000000000000000000..2d8176788531618749fcd9393a534da45d4aba5a
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_can.h
@@ -0,0 +1,178 @@
+/** @file reg_can.h
+*   @brief CAN Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the CAN driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_CAN_H__
+#define __REG_CAN_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Can Register Frame Definition */
+/** @struct canBase
+*   @brief CAN Register Frame Definition
+*
+*   This type is used to access the CAN Registers.
+*/
+/** @typedef canBASE_t
+*   @brief CAN Register Frame Type Definition
+*
+*   This type is used to access the CAN Registers.
+*/
+typedef volatile struct canBase
+{
+    uint32      CTL;          /**< 0x0000: Control Register                       */
+    uint32      ES;           /**< 0x0004: Error and Status Register              */
+    uint32      EERC;         /**< 0x0008: Error Counter Register                 */
+    uint32      BTR;          /**< 0x000C: Bit Timing Register                    */
+    uint32      INT;          /**< 0x0010: Interrupt Register                     */
+    uint32      TEST;         /**< 0x0014: Test Register                          */
+    uint32        rsvd1;      /**< 0x0018: Reserved                               */
+    uint32      PERR;         /**< 0x001C: Parity/SECDED Error Code Register      */
+    uint32      REL;          /**< 0x0020: Core Release Register                  */
+    uint32      ECCDIAG;      /**< 0x0024: ECC Diagnostic Register                */
+    uint32      ECCDIADSTAT;  /**< 0x0028: ECC Diagnostic Status Register         */
+    uint32        rsvd2[21];  /**< 0x002C: Reserved                               */
+    uint32      ABOTR;        /**< 0x0080: Auto Bus On Time Register              */
+    uint32      TXRQX;        /**< 0x0084: Transmission Request X Register        */
+    uint32      TXRQx[4U];    /**< 0x0088-0x0094: Transmission Request Registers  */
+    uint32      NWDATX;       /**< 0x0098: New Data X Register                    */
+    uint32      NWDATx[4U];   /**< 0x009C-0x00A8: New Data Registers              */
+    uint32      INTPNDX;      /**< 0x00AC: Interrupt Pending X Register           */
+    uint32      INTPNDx[4U];  /**< 0x00B0-0x00BC: Interrupt Pending Registers     */
+    uint32      MSGVALX;      /**< 0x00C0: Message Valid X Register               */
+    uint32      MSGVALx[4U];  /**< 0x00C4-0x00D0: Message Valid Registers         */
+    uint32        rsvd3;      /**< 0x00D4: Reserved                               */
+    uint32      INTMUXx[4U];  /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */
+    uint32        rsvd4[6];   /**< 0x00E8: Reserved                               */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+    uint8 IF1NO;              /**< 0x0100: IF1 Command Register, Msg Number       */
+    uint8 IF1STAT;            /**< 0x0100: IF1 Command Register, Status           */
+    uint8 IF1CMD;             /**< 0x0100: IF1 Command Register, Command          */
+    uint8   rsvd9;            /**< 0x0100: IF1 Command Register, Reserved         */
+#else
+    uint8   rsvd9;            /**< 0x0100: IF1 Command Register, Reserved         */
+    uint8 IF1CMD;             /**< 0x0100: IF1 Command Register, Command          */
+    uint8 IF1STAT;            /**< 0x0100: IF1 Command Register, Status           */
+    uint8 IF1NO;              /**< 0x0100: IF1 Command Register, Msg Number       */
+#endif
+    uint32      IF1MSK;       /**< 0x0104: IF1 Mask Register                      */
+    uint32      IF1ARB;       /**< 0x0108: IF1 Arbitration Register               */
+    uint32      IF1MCTL;      /**< 0x010C: IF1 Message Control Register           */
+    uint8 IF1DATx[8U];        /**< 0x0110-0x0114: IF1 Data A and B Registers      */
+    uint32        rsvd5[2];   /**< 0x0118: Reserved                               */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+    uint8 IF2NO;              /**< 0x0120: IF2 Command Register, Msg No           */
+    uint8 IF2STAT;            /**< 0x0120: IF2 Command Register, Status           */
+    uint8 IF2CMD;             /**< 0x0120: IF2 Command Register, Command          */
+    uint8   rsvd10;           /**< 0x0120: IF2 Command Register, Reserved         */
+#else
+    uint8   rsvd10;            /**< 0x0120: IF2 Command Register, Reserved         */
+    uint8 IF2CMD;             /**< 0x0120: IF2 Command Register, Command          */
+    uint8 IF2STAT;            /**< 0x0120: IF2 Command Register, Status           */
+    uint8 IF2NO;              /**< 0x0120: IF2 Command Register, Msg Number       */
+#endif
+    uint32      IF2MSK;       /**< 0x0124: IF2 Mask Register                      */
+    uint32      IF2ARB;       /**< 0x0128: IF2 Arbitration Register               */
+    uint32      IF2MCTL;      /**< 0x012C: IF2 Message Control Register           */
+    uint8 IF2DATx[8U];        /**< 0x0130-0x0134: IF2 Data A and B Registers      */
+    uint32        rsvd6[2];   /**< 0x0138: Reserved                               */
+    uint32      IF3OBS;       /**< 0x0140: IF3 Observation Register               */
+    uint32      IF3MSK;       /**< 0x0144: IF3 Mask Register                      */
+    uint32      IF3ARB;       /**< 0x0148: IF3 Arbitration Register               */
+    uint32      IF3MCTL;      /**< 0x014C: IF3 Message Control Register           */
+    uint8 IF3DATx[8U];        /**< 0x0150-0x0154: IF3 Data A and B Registers      */
+    uint32        rsvd7[2];   /**< 0x0158: Reserved                               */
+    uint32      IF3UEy[4U];   /**< 0x0160-0x016C: IF3 Update Enable Registers     */
+    uint32        rsvd8[28];  /**< 0x0170: Reserved                               */
+    uint32      TIOC;         /**< 0x01E0: TX IO Control Register                 */
+    uint32      RIOC;         /**< 0x01E4: RX IO Control Register                 */
+} canBASE_t;
+
+
+/** @def canREG1
+*   @brief CAN1 Register Frame Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN1 registers.
+*/
+#define canREG1 ((canBASE_t *)0xFFF7DC00U)
+
+/** @def canREG2
+*   @brief CAN2 Register Frame Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN2 registers.
+*/
+#define canREG2 ((canBASE_t *)0xFFF7DE00U)
+
+/** @def canREG3
+*   @brief CAN3 Register Frame Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN3 registers.
+*/
+#define canREG3 ((canBASE_t *)0xFFF7E000U)
+
+/** @def canRAM1
+*   @brief CAN1 Mailbox RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN1 RAM.
+*/
+#define canRAM1 (*(volatile uint32 *)0xFF1E0000U)
+
+/** @def canRAM2
+*   @brief CAN2 Mailbox RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN2 RAM.
+*/
+#define canRAM2 (*(volatile uint32 *)0xFF1C0000U)
+
+/** @def canRAM3
+*   @brief CAN3 Mailbox RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN3 RAM.
+*/
+#define canRAM3 (*(volatile uint32 *)0xFF1A0000U)
+
+/** @def canPARRAM1
+*   @brief CAN1 Mailbox Parity RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN1 Parity RAM
+*   for testing RAM parity error detect logic.
+*/
+#define canPARRAM1 (*(volatile uint32 *)(0xFF1E0000U + 0x10U))
+
+/** @def canPARRAM2
+*   @brief CAN2 Mailbox Parity RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN2 Parity RAM
+*   for testing RAM parity error detect logic.
+*/
+#define canPARRAM2 (*(volatile uint32 *)(0xFF1C0000U + 0x10U))
+
+/** @def canPARRAM3
+*   @brief CAN3 Mailbox Parity RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN3 Parity RAM
+*   for testing RAM parity error detect logic.
+*/
+#define canPARRAM3 (*(volatile uint32 *)(0xFF1A0000U + 0x10U))
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_crc.h b/bsp/rm48x50/HALCoGen/include/reg_crc.h
new file mode 100644
index 0000000000000000000000000000000000000000..b1929364bd9cfc8557a52f3242e5c4c94a37272d
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_crc.h
@@ -0,0 +1,96 @@
+/** @file reg_crc.h
+*   @brief CRC Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the CRC driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_CRC_H__
+#define __REG_CRC_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Crc Register Frame Definition */
+/** @struct crcBase
+*   @brief CRC Register Frame Definition
+*
+*   This type is used to access the CRC Registers.
+*/
+/** @typedef crcBASE_t
+*   @brief CRC Register Frame Type Definition
+*
+*   This type is used to access the CRC Registers.
+*/
+typedef volatile struct crcBase
+{
+    uint32      CTRL0;                /**< 0x0000: Global Control Register 0 >**/
+    uint32        rsvd1;              /**< 0x0004: reserved >**/
+    uint32      CTRL1;                /**< 0x0008: Global Control Register 1 >**/
+    uint32        rsvd2;              /**< 0x000C: reserved >**/    
+    uint32      CTRL2;                /**< 0x0010: Global Control Register 2 >**/
+    uint32        rsvd3;              /**< 0x0014: reserved >**/        
+    uint32      INTS;                 /**< 0x0018: Interrupt Enable Set Register >**/
+    uint32        rsvd4;              /**< 0x001C: reserved >**/        
+    uint32      INTR;                 /**< 0x0020: Interrupt Enable Reset Register >**/
+    uint32        rsvd5;              /**< 0x0024: reserved >**/    
+    uint32      STATUS;               /**< 0x0028: Interrupt Status Register >**/
+    uint32        rsvd6;              /**< 0x002C: reserved >**/    
+    uint32      INT_OFFSET_REG;       /**< 0x0030: Interrupt Offset >**/
+    uint32        rsvd7;              /**< 0x0034: reserved >**/    
+    uint32      BUSY;                 /**< 0x0038: CRC Busy Register >**/
+    uint32        rsvd8;              /**< 0x003C: reserved >**/    
+    uint32      PCOUNT_REG1;          /**< 0x0040: Pattern Counter Preload Register1 >**/
+    uint32      SCOUNT_REG1;          /**< 0x0044: Sector Counter Preload Register1 >**/
+    uint32      CURSEC_REG1;          /**< 0x0048: Current Sector Register 1 >**/
+    uint32      WDTOPLD1;             /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/
+    uint32      BCTOPLD1;             /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/
+    uint32        rsvd9[3];           /**< 0x0054: reserved >**/
+    uint32      PSA_SIGREGL1;         /**< 0x0060: Channel 1 PSA signature low register >**/
+    uint32      PSA_SIGREGH1;         /**< 0x0064: Channel 1 PSA signature high register >**/
+    uint32      REGL1;                /**< 0x0068: Channel 1 CRC value low register >**/
+    uint32      REGH1;                /**< 0x006C: Channel 1 CRC value high register >**/
+    uint32      PSA_SECSIGREGL1;      /**< 0x0070: Channel 1 PSA sector signature low register >**/
+    uint32      PSA_SECSIGREGH1;      /**< 0x0074: Channel 1 PSA sector signature high register >**/
+    uint32      RAW_DATAREGL1;        /**< 0x0078: Channel 1 Raw Data Low Register >**/
+    uint32      RAW_DATAREGH1;        /**< 0x007C: Channel 1 Raw Data High Register >**/
+    uint32      PCOUNT_REG2;          /**< 0x0080: CRC Pattern Counter Preload Register2 >**/
+    uint32      SCOUNT_REG2;          /**< 0x0084: Sector Counter Preload Register2 >**/
+    uint32      CURSEC_REG2;          /**< 0x0088: Current Sector Register 2>**/
+    uint32      WDTOPLD2;             /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/
+    uint32      BCTOPLD2;             /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/
+    uint32        rsvd10[3];           /**< 0x0094: reserved >**/
+    uint32      PSA_SIGREGL2;         /**< 0x00A0: Channel 2 PSA signature low register >**/
+    uint32      PSA_SIGREGH2;         /**< 0x00A8: Channel 2 PSA signature high register >**/
+    uint32      REGL2;                /**< 0x00AC: Channel 2 CRC value low register >**/
+    uint32      REGH2;                /**< 0x00AC: Channel 2 CRC value high register >**/
+    uint32      PSA_SECSIGREGL2;      /**< 0x00B0: Channel 2 PSA sector signature low register >**/
+    uint32      PSA_SECSIGREGH2;      /**< 0x00B4: Channel 2 PSA sector signature high register >**/
+    uint32      RAW_DATAREGL2;        /**< 0x00B8: Channel 2 Raw Data Low Register >**/
+    uint32      RAW_DATAREGH2;        /**< 0x00BC: Channel 2 Raw Data High Register >**/
+}crcBASE_t;
+ 
+/** @def crcREG
+*   @brief CRC Register Frame Pointer
+*
+*   This pointer is used by the CRC driver to access the CRC registers.
+*/
+#define crcREG ((crcBASE_t *)0xFE000000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_dcc.h b/bsp/rm48x50/HALCoGen/include/reg_dcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..e03d2a36fc9c80e969150df82bf2275d54638649
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_dcc.h
@@ -0,0 +1,72 @@
+/** @file reg_dcc.h
+*   @brief DCC Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the DCC driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_DCC_H__
+#define __REG_DCC_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Dcc Register Frame Definition */
+/** @struct dccBase
+*   @brief DCC Base Register Definition
+*
+*   This structure is used to access the DCC module registers.
+*/
+/** @typedef dccBASE_t
+*   @brief DCC Register Frame Type Definition
+*
+*   This type is used to access the DCC Registers.
+*/
+typedef volatile struct dccBase
+{
+    uint32 GCTRL;      	/**< 0x0000: DCC Control Register		*/
+    uint32 REV;      		/**< 0x0004: DCC Revision Id Register 	*/
+    uint32 CNT0SEED;    	/**< 0x0008: DCC Counter0 Seed Register	*/
+    uint32 VALID0SEED;    /**< 0x000C: DCC Valid0 Seed Register 	*/
+    uint32 CNT1SEED;		/**< 0x0010: DCC Counter1 Seed Register 	*/
+    uint32 STAT; 			/**< 0x0014: DCC Status Register 		*/
+    uint32 CNT0;    		/**< 0x0018: DCC Counter0 Value Register 	*/
+    uint32 VALID0;    	/**< 0x001C: DCC Valid0 Value Register 	*/
+    uint32 CNT1;      	/**< 0x0020: DCC Counter1 Value Register	*/
+    uint32 CLKSRC1;   	/**< 0x0024: DCC Counter1 Clock Source Selection Register 	*/
+    uint32 CLKSRC0;   	/**< 0x0028: DCC Counter0 Clock Source Selection Register 	*/
+} dccBASE_t;
+
+
+/** @def dccREG1
+*   @brief DCC1 Register Frame Pointer
+*
+*   This pointer is used by the DCC driver to access the dcc2 module registers.
+*/
+#define dccREG1   ((dccBASE_t *)0xFFFFEC00U)
+
+
+/** @def dccREG2
+*   @brief DCC2 Register Frame Pointer
+*
+*   This pointer is used by the DCC driver to access the dcc2 module registers.
+*/
+#define dccREG2   ((dccBASE_t *)0xFFFFF400U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_dma.h b/bsp/rm48x50/HALCoGen/include/reg_dma.h
new file mode 100644
index 0000000000000000000000000000000000000000..255ae7bbaa83c2be96384cebf79429bbdc90d0f8
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_dma.h
@@ -0,0 +1,146 @@
+/** @file reg_dma.h
+*   @brief DMA Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the DMA driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_DMA_H__
+#define __REG_DMA_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* DMA Register Frame Definition */
+/** @struct dmaBase
+*   @brief DMA Register Frame Definition
+*
+*   This type is used to access the DMA Registers.
+*/
+/** @struct dmaBASE_t
+*   @brief DMA Register Definition
+*
+*   This structure is used to access the DMA module egisters.
+*/
+typedef volatile struct dmaBase
+{
+
+    uint32 GCTRL;      /**<  0x0000: Global Control Register                */
+    uint32 PEND;       /**<  0x0004: Channel Pending Register               */
+    uint32 FBREG;      /**<  0x0008: Fall Back Register                     */
+    uint32 DMASTAT;    /**<  0x000C: Status Register                        */
+    uint32  rsvd1;     /**<  0x0010: Reserved                               */
+    uint32 HWCHENAS;   /**<  0x0014: HW Channel Enable Set                  */
+    uint32  rsvd2;     /**<  0x0018: Reserved                               */
+    uint32 HWCHENAR;   /**<  0x001C: HW Channel Enable Reset                */
+    uint32  rsvd3;     /**<  0x0020: Reserved                               */
+    uint32 SWCHENAS;   /**<  0x0024: SW Channel Enable Set                  */
+    uint32  rsvd4;     /**<  0x0028: Reserved                               */
+    uint32 SWCHENAR;   /**<  0x002C: SW Channel Enable Reset                */
+    uint32  rsvd5;     /**<  0x0030: Reserved                               */
+    uint32 CHPRIOS;    /**<  0x0034: Channel Priority Set                   */
+    uint32  rsvd6;     /**<  0x0038: Reserved                               */
+    uint32 CHPRIOR;    /**<  0x003C: Channel Priority Reset                 */
+    uint32  rsvd7;     /**<  0x0040: Reserved                               */
+    uint32 GCHIENAS;   /**<  0x0044: Global Channel Interrupt Enable Set    */
+    uint32  rsvd8;     /**<  0x0048: Reserved                               */
+    uint32 GCHIENAR;   /**<  0x004C: Global Channel Interrupt Enable Set    */
+    uint32  rsvd9;     /**<  0x0050: Reserved                               */
+    uint32 DREQASI[8U];/**<  0x0054 - 0x70: DMA Request Assignment Register */
+    uint32  rsvd10[8U];/**<  0x0074 - 0x90: Reserved                        */
+    uint32 PAR[4U];    /**<  0x0094 - 0xA0: Port Assignment Register        */
+    uint32  rsvd11[4U];/**<  0x00A4 - 0xB0: Reserved                        */
+    uint32 FTCMAP;     /**<  0x00B4: FTC Interrupt Mapping Register         */
+    uint32  rsvd12;    /**<  0x00B8: Reserved                               */
+    uint32 LFSMAP;     /**<  0x00BC: LFS Interrupt Mapping Register         */
+    uint32  rsvd13;    /**<  0x00C0: Reserved                               */
+    uint32 HBCMAP;     /**<  0x00C4: HBC Interrupt Mapping Register         */
+    uint32  rsvd14;    /**<  0x00C8: Reserved                               */
+    uint32 BTCMAP;     /**<  0x00CC: BTC Interrupt Mapping Register         */
+    uint32  rsvd15;    /**<  0x00D0: Reserved                               */
+    uint32 BERMAP;     /**<  0x00D4: BER Interrupt Mapping Register         */
+    uint32  rsvd16;    /**<  0x00D8: Reserved                               */
+    uint32 FTCINTENAS; /**<  0x00DC: FTC Interrupt Enable Set               */
+    uint32  rsvd17;    /**<  0x00E0: Reserved                               */
+    uint32 FTCINTENAR; /**<  0x00E4: FTC Interrupt Enable Reset             */
+    uint32  rsvd18;    /**<  0x00E8: Reserved                               */
+    uint32 LFSINTENAS; /**<  0x00EC: LFS Interrupt Enable Set               */
+    uint32  rsvd19;    /**<  0x00F0: Reserved                               */
+    uint32 LFSINTENAR; /**<  0x00F4: LFS Interrupt Enable Reset             */
+    uint32  rsvd20;    /**<  0x00F8: Reserved                               */
+    uint32 HBCINTENAS; /**<  0x00FC: HBC Interrupt Enable Set               */
+    uint32  rsvd21;    /**<  0x0100: Reserved                               */
+    uint32 HBCINTENAR; /**<  0x0104: HBC Interrupt Enable Reset             */
+    uint32  rsvd22;    /**<  0x0108: Reserved                               */
+    uint32 BTCINTENAS; /**<  0x010C: BTC Interrupt Enable Set               */
+    uint32  rsvd23;    /**<  0x0110: Reserved                               */
+    uint32 BTCINTENAR; /**<  0x0114: BTC Interrupt Enable Reset             */
+    uint32  rsvd24;    /**<  0x0118: Reserved                               */
+    uint32 GINTFLAG;   /**<  0x011C: Global Interrupt Flag Register         */
+    uint32  rsvd25;    /**<  0x0120: Reserved                               */
+    uint32 FTCFLAG;    /**<  0x0124: FTC Interrupt Flag Register            */
+    uint32  rsvd26;    /**<  0x0128: Reserved                               */
+    uint32 LFSFLAG;    /**<  0x012C: LFS Interrupt Flag Register            */
+    uint32  rsvd27;    /**<  0x0130: Reserved                               */
+    uint32 HBCFLAG;    /**<  0x0134: HBC Interrupt Flag Register            */
+    uint32  rsvd28;    /**<  0x0138: Reserved                               */
+    uint32 BTCFLAG;    /**<  0x013C: BTC Interrupt Flag Register            */
+    uint32  rsvd29;    /**<  0x0140: Reserved                               */
+    uint32 BERFLAG;    /**<  0x0144: BER Interrupt Flag Register            */
+    uint32  rsvd30;    /**<  0x0148: Reserved                               */
+    uint32 FTCAOFFSET; /**<  0x014C: FTCA Interrupt Channel Offset Register */
+    uint32 LFSAOFFSET; /**<  0x0150: LFSA Interrupt Channel Offset Register */
+    uint32 HBCAOFFSET; /**<  0x0154: HBCA Interrupt Channel Offset Register */
+    uint32 BTCAOFFSET; /**<  0x0158: BTCA Interrupt Channel Offset Register */
+    uint32 BERAOFFSET; /**<  0x015C: BERA Interrupt Channel Offset Register */
+    uint32 FTCBOFFSET; /**<  0x0160: FTCB Interrupt Channel Offset Register */
+    uint32 LFSBOFFSET; /**<  0x0164: LFSB Interrupt Channel Offset Register */
+    uint32 HBCBOFFSET; /**<  0x0168: HBCB Interrupt Channel Offset Register */
+    uint32 BTCBOFFSET; /**<  0x016C: BTCB Interrupt Channel Offset Register */
+    uint32 BERBOFFSET; /**<  0x0170: BERB Interrupt Channel Offset Register */
+    uint32  rsvd31;    /**<  0x0174: Reserved                               */
+    uint32 PTCRL;      /**<  0x0178: Port Control Register                  */
+    uint32 RTCTRL;     /**<  0x017C: RAM Test Control Register              */
+    uint32 DCTRL;      /**<  0x0180: Debug Control                          */
+    uint32 WPR;        /**<  0x0184: Watch Point Register                   */
+    uint32 WMR;        /**<  0x0188: Watch Mask Register                    */
+    uint32 PAACSADDR;  /**<  0x018C:           */
+    uint32 PAACDADDR;  /**<  0x0190:           */
+    uint32 PAACTC;     /**<  0x0194:           */
+    uint32 PBACSADDR;  /**<  0x0198: Port B Active Channel Source Address Register       */
+    uint32 PBACDADDR;  /**<  0x019C: Port B Active Channel Destination Address Register  */
+    uint32 PBACTC;     /**<  0x01A0: Port B Active Channel Transfer Count Register       */
+    uint32  rsvd32;    /**<  0x01A4: Reserved                               */
+    uint32 DMAPCR;     /**<  0x01A8: Parity Control Register                */
+    uint32 DMAPAR;     /**<  0x01AC: DMA Parity Error Address Register      */
+    uint32 DMAMPCTRL;  /**<  0x01B0: DMA Memory Protection Control Register */
+    uint32 DMAMPST;    /**<  0x01B4: DMA Memory Protection Status Register  */
+    struct
+    {
+    	uint32 STARTADD; /**<  0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register  */
+    	uint32 ENDADD;   /**<  0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register  */
+    }DMAMPR[4U];
+} dmaBASE_t;
+
+
+/** @def dmaREG
+*   @brief DMA1 Register Frame Pointer
+*
+*   This pointer is used by the DMA driver to access the DMA module registers.
+*/
+#define dmaREG ((dmaBASE_t *)0xFFFFF000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_dmm.h b/bsp/rm48x50/HALCoGen/include/reg_dmm.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b283820ad3851e7602d07bd21373973a0fb94c7
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_dmm.h
@@ -0,0 +1,99 @@
+/** @file reg_dmm.h
+*   @brief DMM Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the DMM driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_DMM_H__
+#define __REG_DMM_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Dmm Register Frame Definition */
+/** @struct dmmBase
+*   @brief DMM Base Register Definition
+*
+*   This structure is used to access the DMM module registers.
+*/
+/** @typedef dmmBASE_t
+*   @brief DMM Register Frame Type Definition
+*
+*   This type is used to access the DMM Registers.
+*/
+
+typedef volatile struct dmmBase
+{
+    uint32  GLBCTRL;    /**< 0x0000: Global control register 0         */
+    uint32  INTSET;     /**< 0x0004: DMM Interrupt Set Register        */    
+    uint32  INTCLR;     /**< 0x0008: DMM Interrupt Clear Register      */
+    uint32  INTLVL;     /**< 0x000C: DMM Interrupt Level Register      */    
+    uint32  INTFLG;     /**< 0x0010: DMM Interrupt Flag Register       */
+    uint32  OFF1;       /**< 0x0014: DMM Interrupt Offset 1 Register           */
+    uint32  OFF2;       /**< 0x0018: DMM Interrupt Offset 2 Register           */
+    uint32  DDMDEST;    /**< 0x001C: DMM Direct Data Mode Destination Register                */
+    uint32  DDMBL;      /**< 0x0020: DMM Direct Data Mode Blocksize Register           */
+    uint32  DDMPT;      /**< 0x0024: DMM Direct Data Mode Pointer Register        */
+    uint32  INTPT;      /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register     */
+    uint32  DEST0REG1;  /**< 0x002C: DMM Destination 0 Region 1           */
+    uint32  DEST0BL1;   /**< 0x0030: DMM Destination 0 Blocksize 1                     */
+    uint32  DEST0REG2;  /**< 0x0034: DMM Destination 0 Region 2                  */
+    uint32  DEST0BL2;   /**< 0x0038: DMM Destination 0 Blocksize 2                 */
+    uint32  DEST1REG1;  /**< 0x003C: DMM Destination 1 Region 1                  */
+    uint32  DEST1BL1;   /**< 0x0040: DMM Destination 1 Blocksize 1                 */
+    uint32  DEST1REG2;  /**< 0x0044: DMM Destination 1 Region 2                   */
+    uint32  DEST1BL2;   /**< 0x0048: DMM Destination 1 Blocksize 2                  */
+    uint32  DEST2REG1;  /**< 0x004C: DMM Destination 2 Region 1                  */
+    uint32  DEST2BL1;   /**< 0x0050: DMM Destination 2 Blocksize 1                  */
+    uint32  DEST2REG2;  /**< 0x0054: DMM Destination 2 Region 2  */
+    uint32  DEST2BL2;   /**< 0x0058: DMM Destination 2 Blocksize 2   */
+    uint32  DEST3REG1;  /**< 0x005C: DMM Destination 3 Region 1 */
+    uint32  DEST3BL1;   /**< 0x0060: DMM Destination 3 Blocksize 1                       */
+    uint32  DEST3REG2;  /**< 0x0064: DMM Destination 3 Region 2              */
+    uint32  DEST3BL2;   /**< 0x0068: DMM Destination 3 Blocksize 2              */
+    uint32  PC0;        /**< 0x006C: DMM Pin Control 0                          */
+    uint32  PC1;        /**< 0x0070: DMM Pin Control 1               */     
+    uint32  PC2;        /**< 0x0074: DMM Pin Control 2              */
+    uint32  PC3;        /**< 0x0078: DMM Pin Control 3              */
+    uint32  PC4;        /**< 0x007C: DMM Pin Control 4   */
+    uint32  PC5;        /**< 0x0080: DMM Pin Control 5                 */
+    uint32  PC6;        /**< 0x0084: DMM Pin Control 6                              */
+    uint32  PC7;        /**< 0x0088: DMM Pin Control 7                             */
+    uint32  PC8;        /**< 0x008C: DMM Pin Control 8                              */
+} dmmBASE_t;
+
+
+/** @def dmmREG
+*   @brief DMM Register Frame Pointer
+*
+*   This pointer is used by the DMM driver to access the DMM module registers.
+*/
+#define dmmREG ((dmmBASE_t *)0xFFFFF700U)
+
+/** @def dmmPORT
+*   @brief DMM Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of DMM
+*   (use the GIO drivers to access the port pins).
+*/
+#define dmmPORT ((gioPORT_t *)0xFFFFF738U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_efc.h b/bsp/rm48x50/HALCoGen/include/reg_efc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3387a038544f10c59ee3f47788906f87cfa030b2
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_efc.h
@@ -0,0 +1,63 @@
+/** @file reg_efc.h
+*   @brief EFC Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_EFC_H__
+#define __REG_EFC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Efc Register Frame Definition */
+/** @struct efcBase
+*   @brief Efc Register Frame Definition
+*
+*   This type is used to access the Efc Registers.
+*/
+/** @typedef efcBASE_t
+*   @brief Efc Register Frame Type Definition
+*
+*   This type is used to access the Efc Registers.
+*/
+typedef volatile struct efcBase
+{
+	uint32 INSTRUCTION;    			/* 0x0	INSTRUCTION AN DUMPWORD REGISTER	*/
+	uint32 ADDRESS;			    	/* 0x4 ADDRESS REGISTER    					*/
+	uint32 DATA_UPPER;			    /* 0x8 DATA UPPER REGISTER    				*/
+	uint32 DATA_LOWER;				/* 0xc DATA LOWER REGISTER    				*/
+	uint32 SYSTEM_CONFIG;				/* 0x10 SYSTEM CONFIG REGISTER    			*/
+	uint32 SYSTEM_STATUS;				/* 0x14 SYSTEM STATUS REGISTER    			*/
+	uint32 ACCUMULATOR;				/* 0x18 ACCUMULATOR REGISTER    			*/
+	uint32 BOUNDARY;			    	/* 0x1C BOUNDARY REGISTER 					*/
+	uint32 KEY_FLAG;			    	/* 0x20 KEY FLAG REGISTER    				*/
+	uint32 KEY;			        	/* 0x24	KEY REGISTER 						*/
+	uint32   rsvd1;			        /* 0x28	RESERVED 							*/
+	uint32 PINS;				        /* 0x2C  PINS REGISTER						*/
+	uint32 CRA;				        /* 0x30  CRA								*/
+	uint32 READ;				        /* 0x34 READ REGISTER						*/
+	uint32 PROGRAMME;				    /* 0x38 PROGRAMME REGISTER					*/
+	uint32 ERROR;				        /* 0x3C	ERROR STATUS REGISTER				*/
+	uint32 SINGLE_BIT;				/* 0x40	SINGLE BIT ERROR 					*/
+	uint32 TWO_BIT_ERROR;				/* 0x44	DOUBLE BIT ERROR 					*/
+	uint32 SELF_TEST_CYCLES;			/* 0x48	SELF TEST CYCLEX					*/
+	uint32 SELF_TEST_SIGN;			/* 0x4C SELF TEST SIGNATURE					*/
+} efcBASE_t;
+
+#define efcREG   ((efcBASE_t *)0xFFF8C000U)
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_emif.h b/bsp/rm48x50/HALCoGen/include/reg_emif.h
new file mode 100644
index 0000000000000000000000000000000000000000..4a0c013362342fbde16c6306acddd1b65f146d08
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_emif.h
@@ -0,0 +1,60 @@
+/** @file reg_emif.h
+*   @brief EMIF Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the EMIF driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_EMIF_H__
+#define __REG_EMIF_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Emif Register Frame Definition */
+/** @struct emifBASE_t
+*   @brief emifBASE Register Definition
+*
+*   This structure is used to access the EMIF module registers.
+*/
+typedef volatile struct emifBase
+{
+    uint32 MIDR;          /**< 0x0000 Module ID Register */
+    uint32 AWCC;          /**< 0x0004 Asynchronous wait cycle register*/
+    uint32 SDCR;          /**< 0x0008 SDRAM configuration register */
+    uint32 SDRCR ;        /**< 0x000C Set Interrupt Enable Register */
+    uint32 CE2CFG;        /**< 0x0010 Asynchronous 1 Configuration Register */
+    uint32 CE3CFG;        /**< 0x0014 Asynchronous 2 Configuration Register */
+    uint32 CE4CFG;        /**< 0x0018 Asynchronous 3 Configuration Register */
+    uint32 CE5CFG;        /**< 0x001C Asynchronous 4 Configuration Register */
+    uint32 SDTIMR;        /**< 0x0020 SDRAM Timing Register */
+    uint32 dummy1[6];     /** reserved **/
+    uint32 SDSRETR;       /**< 0x003c SDRAM Self Refresh Exit Timing Register */
+    uint32 INTRAW;        /**< 0x0040 0x0020 Interrupt Vector Offset*/
+    uint32 INTMSK;        /**< 0x0044 EMIF Interrupt Mask Register */
+    uint32 INTMSKSET;     /**< 48 EMIF Interrupt Mask Set Register */
+    uint32 INTMSKCLR;     /**< 0x004c EMIF Interrupt Mask Register */
+    uint32 dummy2[6];     /** reserved **/
+    uint32 PMCR;          /**< 0x0068 Page Mode Control Register*/
+
+} emifBASE_t;
+
+#define emifREG ((emifBASE_t *)0xFCFFE800U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_esm.h b/bsp/rm48x50/HALCoGen/include/reg_esm.h
new file mode 100644
index 0000000000000000000000000000000000000000..39df6773a18a7e162e043f88373450e1df95c519
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_esm.h
@@ -0,0 +1,74 @@
+/** @file reg_esm.h
+*   @brief ESM Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ESM driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_ESM_H__
+#define __REG_ESM_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Esm Register Frame Definition */
+/** @struct esmBase
+*   @brief Esm Register Frame Definition
+*
+*   This type is used to access the Esm Registers.
+*/
+/** @typedef esmBASE_t
+*   @brief Esm Register Frame Type Definition
+*
+*   This type is used to access the Esm Registers.
+*/
+typedef volatile struct esmBase
+{
+    uint32 EPENASET1;              /* 0x0000                 */
+    uint32 EPENACLR1;              /* 0x0004                 */
+    uint32 INTENASET1;             /* 0x0008                 */
+    uint32 INTENACLR1;             /* 0x000C                 */
+    uint32 INTLVLSET1;             /* 0x0010                 */
+    uint32 INTLVLCLR1;             /* 0x0014                 */
+    uint32 ESTATUS1[3U];           /* 0x0018, 0x001C, 0x0020 */
+    uint32 EPSTATUS;               /* 0x0024                 */
+    uint32 INTOFFH;                /* 0x0028                 */
+    uint32 INTOFFL;                /* 0x002C                 */
+    uint32 LTC;                    /* 0x0030                 */
+    uint32 LTCPRELOAD;             /* 0x0034                 */
+    uint32 KEY;                    /* 0x0038                 */
+    uint32 ESTATUS2EMU;            /* 0x003C                 */
+    uint32 EPENASET4;              /* 0x0040                 */
+    uint32 EPENACLR4;              /* 0x0044                 */
+    uint32 INTENASET4;             /* 0x0048                 */
+    uint32 INTENACLR4;             /* 0x004C                 */
+    uint32 INTLVLSET4;             /* 0x0050                 */
+    uint32 INTLVLCLR4;             /* 0x0054                 */
+    uint32 ESTATUS4[3U];           /* 0x0058, 0x005C, 0x0060 */
+    uint32 ESTATUS5EMU;            /* 0x0064                 */
+} esmBASE_t;
+
+/** @def esmREG
+*   @brief Esm Register Frame Pointer
+*
+*   This pointer is used by the Esm driver to access the Esm registers.
+*/
+#define esmREG ((esmBASE_t *)0xFFFFF500U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_flash.h b/bsp/rm48x50/HALCoGen/include/reg_flash.h
new file mode 100644
index 0000000000000000000000000000000000000000..474c81e43c60fcadf84c25b9bce1392adc89fe7d
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_flash.h
@@ -0,0 +1,111 @@
+/** @file reg_flash.h
+*   @brief Flash Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_FLASH_H__
+#define __REG_FLASH_H__
+
+#include "sys_common.h"
+
+/* Flash Register Frame Definition */
+/** @struct flashWBase
+*   @brief Flash Wrapper Register Frame Definition
+*
+*   This type is used to access the Flash Wrapper Registers.
+*/
+/** @typedef flashWBASE_t
+*   @brief Flash Wrapper Register Frame Type Definition
+*
+*   This type is used to access the Flash Wrapper Registers.
+*/
+typedef volatile struct flashWBase
+{
+    uint32 FRDCNTL;     /* 0x0000 */
+    uint32 FSPRD;       /* 0x0004 */
+    uint32 FEDACCTRL1;  /* 0x0008 */
+    uint32 FEDACCTRL2;  /* 0x000C */
+    uint32 FCORERRCNT;  /* 0x0010 */
+    uint32 FCORERRADD;  /* 0x0014 */
+    uint32 FCORERRPOS;  /* 0x0018 */
+    uint32 FEDACSTATUS; /* 0x001C */
+    uint32 FUNCERRADD;  /* 0x0020 */
+    uint32 FEDACSDIS;   /* 0x0024 */
+    uint32 FPRIMADDTAG; /* 0x0028 */
+    uint32 FREDUADDTAG; /* 0x002C */
+    uint32 FBPROT;      /* 0x0030 */
+    uint32 FBSE;        /* 0x0034 */
+    uint32 FBBUSY;      /* 0x0038 */
+    uint32 FBAC;        /* 0x003C */
+    uint32 FBFALLBACK;  /* 0x0040 */
+    uint32 FBPRDY;      /* 0x0044 */
+    uint32 FPAC1;       /* 0x0048 */
+    uint32 FPAC2;       /* 0x004C */
+    uint32 FMAC;        /* 0x0050 */
+    uint32 FMSTAT;      /* 0x0054 */
+    uint32 FEMUDMSW;    /* 0x0058 */
+    uint32 FEMUDLSW;    /* 0x005C */
+    uint32 FEMUECC;     /* 0x0060 */
+    uint32 FLOCK;       /* 0x0064 */
+    uint32 FEMUADDR;    /* 0x0068 */
+    uint32 FDIAGCTRL;   /* 0x006C */
+    uint32 FRAWDATAH;   /* 0x0070 */
+    uint32 FRAWDATAL;   /* 0x0074 */
+    uint32 FRAWECC;     /* 0x0078 */
+    uint32 FPAROVR;     /* 0x007C */
+    uint32 FVREADCT;    /* 0x0080 */
+    uint32 FVHVCT1;     /* 0x0084 */
+    uint32 FVHVCT2;     /* 0x0088 */
+    uint32 FVNVCT;      /* 0x008C */
+    uint32 FVPPCT;      /* 0x0090 */
+    uint32 FVWLCT;      /* 0x0094 */
+    uint32 FEFUSE;      /* 0x0098 */
+    uint32   rsvd1[9U];  /* 0x009C */
+    uint32 FEDACSDIS2;  /* 0x00C0 */
+    uint32   rsvd2[15U]; /* 0x00C4 */
+    uint32 FBSTROBES;   /* 0x0100 */
+    uint32 FPSTROBES;   /* 0x0104 */
+    uint32 FBMODE;      /* 0x0108 */
+    uint32 FTCR;        /* 0x010C */
+    uint32 FADDR;       /* 0x0110 */
+    uint32 FWRITE;      /* 0x0114 */
+    uint32 FCBITSEL;    /* 0x0118 */
+    uint32 FTCTRL;      /* 0x011C */
+    uint32 FWPWRITE0;   /* 0x0120 */
+    uint32 FWPWRITE1;   /* 0x0124 */
+    uint32 FWPWRITE2;   /* 0x0128 */
+    uint32 FWPWRITE3;   /* 0x012C */
+    uint32 FWPWRITE4;   /* 0x0130 */
+    uint32   rsvd3[85U]; /* 0x0134 */
+    uint32 FSMWRENA;    /* 0x0288 */
+    uint32   rsvd4[6U];  /* 0x028C */
+    uint32 FSMSECTOR;   /* 0x02A4 */
+    uint32   rsvd5[4U];  /* 0x02A8 */
+    uint32 EEPROMCONFIG;/* 0x02B8 */
+    uint32   rsvd6[19U]; /* 0x02BC */
+    uint32 EECTRL1;     /* 0x0308 */
+    uint32 EECTRL2;     /* 0x030C */
+    uint32 EECORRERRCNT;/* 0x0310 */
+    uint32 EECORRERRADD;/* 0x0314 */
+    uint32 EECORRERRPOS;/* 0x0318 */
+    uint32 EESTATUS;    /* 0x031C */
+    uint32 EEUNCERRADD; /* 0x0320 */
+} flashWBASE_t;
+
+/** @def flashWREG
+*   @brief Flash Wrapper Register Frame Pointer
+*
+*   This pointer is used by the system driver to access the flash wrapper registers.
+*/
+#define flashWREG ((flashWBASE_t *)(0xFFF87000U))
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_gio.h b/bsp/rm48x50/HALCoGen/include/reg_gio.h
new file mode 100644
index 0000000000000000000000000000000000000000..e371916b0d90c2067d14d322a3a673aaad99b911
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_gio.h
@@ -0,0 +1,99 @@
+/** @file reg_gio.h
+*   @brief GIO Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the GIO driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_GIO_H__
+#define __REG_GIO_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Gio Register Frame Definition */
+/** @struct gioBase
+*   @brief GIO Base Register Definition
+*
+*   This structure is used to access the GIO module registers.
+*/
+/** @typedef gioBASE_t
+*   @brief GIO Register Frame Type Definition
+*
+*   This type is used to access the GIO Registers.
+*/
+typedef volatile struct gioBase
+{
+    uint32 GCR0;      /**< 0x0000: Global Control Register */
+    uint32 PWDN;      /**< 0x0004: Power Down Register */
+    uint32 INTDET;    /**< 0x0008: Interrupt Detect Register*/
+    uint32 POL;       /**< 0x000C: Interrupt Polarity Register */
+    uint32 INTENASET; /**< 0x0010: Interrupt Enable Set Register */
+    uint32 INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */
+    uint32 LVLSET;    /**< 0x0018: Interrupt Priority Set Register */
+    uint32 LVLCLR;    /**< 0x001C: Interrupt Priority Clear Register */
+    uint32 FLG;       /**< 0x0020: Interrupt Flag Register */
+    uint32 OFFSET0;   /**< 0x0024: Interrupt Offset A Register */
+    uint32 OFFSET1;   /**< 0x0028: Interrupt Offset B Register */
+} gioBASE_t;
+
+
+/** @struct gioPort
+*   @brief GIO Port Register Definition
+*/
+/** @typedef gioPORT_t
+*   @brief GIO Port Register Type Definition
+*
+*   This type is used to access the GIO Port Registers.
+*/
+typedef volatile struct gioPort
+{
+    uint32 DIR;    /**< 0x0000: Data Direction Register */
+    uint32 DIN;    /**< 0x0004: Data Input Register */
+    uint32 DOUT;   /**< 0x0008: Data Output Register */
+    uint32 DSET;   /**< 0x000C: Data Output Set Register */
+    uint32 DCLR;   /**< 0x0010: Data Output Clear Register */
+    uint32 PDR;    /**< 0x0014: Open Drain Register */
+    uint32 PULDIS; /**< 0x0018: Pullup Disable Register */
+    uint32 PSL;    /**< 0x001C: Pull Up/Down Selection Register */
+} gioPORT_t;
+
+
+/** @def gioREG
+*   @brief GIO Register Frame Pointer
+*
+*   This pointer is used by the GIO driver to access the gio module registers.
+*/
+#define gioREG   ((gioBASE_t *)0xFFF7BC00U)
+
+/** @def gioPORTA
+*   @brief GIO Port (A) Register Pointer
+*
+*   Pointer used by the GIO driver to access PORTA
+*/
+#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)
+
+/** @def gioPORTB
+*   @brief GIO Port (B) Register Pointer
+*
+*   Pointer used by the GIO driver to access PORTB
+*/
+#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_het.h b/bsp/rm48x50/HALCoGen/include/reg_het.h
new file mode 100644
index 0000000000000000000000000000000000000000..435c65d6d42002c6d9cbdf4bb670a0979f09b038
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_het.h
@@ -0,0 +1,152 @@
+/** @file reg_het.h
+*   @brief HET Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the HET driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_HET_H__
+#define __REG_HET_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Het Register Frame Definition */
+/** @struct hetBase
+*   @brief HET Base Register Definition
+*
+*   This structure is used to access the HET module registers.
+*/
+/** @typedef hetBASE_t
+*   @brief HET Register Frame Type Definition
+*
+*   This type is used to access the HET Registers.
+*/
+
+typedef volatile struct hetBase
+{
+    uint32 GCR;     /**< 0x0000: Global control register              */
+    uint32 PFR;     /**< 0x0004: Prescale factor register             */
+    uint32 ADDR;    /**< 0x0008: Current address register             */
+    uint32 OFF1;    /**< 0x000C: Interrupt offset register 1          */
+    uint32 OFF2;    /**< 0x0010: Interrupt offset register 2          */
+    uint32 INTENAS; /**< 0x0014: Interrupt enable set register        */
+    uint32 INTENAC; /**< 0x0018: Interrupt enable clear register      */
+    uint32 EXC1;    /**< 0x001C: Exception control register 1          */
+    uint32 EXC2;    /**< 0x0020: Exception control register 2          */
+    uint32 PRY;     /**< 0x0024: Interrupt priority register          */
+    uint32 FLG;     /**< 0x0028: Interrupt flag register              */
+    uint32 AND;     /**< 0x002C: AND share control register         */
+    uint32   rsvd1; /**< 0x0030: Reserved                             */
+    uint32 HRSH;    /**< 0x0034: High resolution share register        */
+    uint32 XOR;     /**< 0x0038: XOR share register                   */
+    uint32 REQENS;  /**< 0x003C: Request enable set register          */
+    uint32 REQENC;  /**< 0x0040: Request enable clear register        */
+    uint32 REQDS;   /**< 0x0044: Request destination select register  */
+    uint32   rsvd2; /**< 0x0048: Reserved                             */
+    uint32 DIR;     /**< 0x004C: Direction register                   */
+    uint32 DIN;     /**< 0x0050: Data input register                  */
+    uint32 DOUT;    /**< 0x0054: Data output register                 */
+    uint32 DSET;    /**< 0x0058: Data output set register             */
+    uint32 DCLR;    /**< 0x005C: Data output clear register           */
+    uint32 PDR;     /**< 0x0060: Open drain register                  */
+    uint32 PULDIS;  /**< 0x0064: Pull disable register                */
+    uint32 PSL;     /**< 0x0068: Pull select register                 */
+    uint32   rsvd3; /**< 0x006C: Reserved                             */
+    uint32   rsvd4; /**< 0x0070: Reserved                             */
+    uint32 PCR;   /**< 0x0074: Parity control register              */
+    uint32 PAR;     /**< 0x0078: Parity address register              */
+    uint32 PPR;     /**< 0x007C: Parity pin select register           */
+    uint32 SFPRLD;  /**< 0x0080: Suppression filter preload register  */
+    uint32 SFENA;   /**< 0x0084: Suppression filter enable register   */
+    uint32   rsvd5; /**< 0x0088: Reserved                             */
+    uint32 LBPSEL;  /**< 0x008C: Loop back pair select register       */
+    uint32 LBPDIR;  /**< 0x0090: Loop back pair direction register    */
+    uint32 PINDIS;  /**< 0x0094: Pin disable register                 */
+    uint32   rsvd6; /**< 0x0098: Reserved                             */
+    uint32 HWAPINSEL;/**< 0x009C: HWAG Pin select register            */
+    uint32 HWAGCR0;  /**< 0x00A0: HWAG Global control register 0      */
+    uint32 HWAGCR1;  /**< 0x00A4: HWAG Global control register 1      */
+    uint32 HWAGCR2;  /**< 0x00A8: HWAG Global control register 2      */
+    uint32 HWAENASET;/**< 0x00AC: HWAG Interrupt enable set register  */
+    uint32 HWAENACLR;/**< 0x00B0: HWAG Interrupt enable clear register*/
+    uint32 HWALVLSET;/**< 0x00B4: HWAG Interrupt level set register   */
+    uint32 HWALVLCLR;/**< 0x00B8: HWAG Interrupt level clear register */
+    uint32 HWAFLG;   /**< 0x00BC: HWAG Interrupt flag register        */
+    uint32 HWAOFF1;  /**< 0x00C0: HWAG Interrupt offset 1 register    */
+    uint32 HWAOFF2;  /**< 0x00C4: HWAG Interrupt offset 2 register    */
+    uint32 HWAACNT;  /**< 0x00C8: HWAG Angle value register           */
+    uint32 HWAPCNT1; /**< 0x00CC: HWAG Period value register 1        */
+    uint32 HWAPCNT;  /**< 0x00D0: HWAG Period value register          */
+    uint32 HWASTWD;  /**< 0x00D4: HWAG Step width register            */
+    uint32 HWATHNB;  /**< 0x00D8: HWAG Teeth number register          */
+    uint32 HWATHVL;  /**< 0x00DC: HWAG Teeth Value register           */
+    uint32 HWAFIL;   /**< 0x00E0: HWAG Filter register                */
+    uint32   rsvd7;  /**< 0x00E4: Reserved                            */
+    uint32 HWAFIL2;  /**< 0x00E8: HWAG Second filter register         */
+    uint32   rsvd8;  /**< 0x00EC: Reserved                            */
+    uint32 HWAANGI;  /**< 0x00F0: HWAG Angle increment register       */
+} hetBASE_t;
+
+
+/** @def hetREG1
+*   @brief HET Register Frame Pointer
+*
+*   This pointer is used by the HET driver to access the het module registers.
+*/
+#define hetREG1 ((hetBASE_t *)0xFFF7B800U)
+
+
+/** @def hetPORT1
+*   @brief HET GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of HET1
+*   (use the GIO drivers to access the port pins).
+*/
+#define hetPORT1 ((gioPORT_t *)0xFFF7B84CU)
+
+
+/** @def hetREG2
+*   @brief HET2 Register Frame Pointer
+*
+*   This pointer is used by the HET driver to access the het module registers.
+*/
+#define hetREG2 ((hetBASE_t *)0xFFF7B900U)
+
+
+/** @def hetPORT2
+*   @brief HET2 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of HET2
+*   (use the GIO drivers to access the port pins).
+*/
+#define hetPORT2 ((gioPORT_t *)0xFFF7B94CU)
+
+#define hetRAM1 ((hetRAMBASE_t *)0xFF460000U)
+
+#define hetRAM2 ((hetRAMBASE_t *)0xFF440000U)
+
+#define NHET1RAMPARLOC	(*(volatile uint32 *)0xFF462000U)
+#define NHET1RAMLOC		(*(volatile uint32 *)0xFF460000U)
+
+#define NHET2RAMPARLOC	(*(volatile uint32 *)0xFF442000U)
+#define NHET2RAMLOC		(*(volatile uint32 *)0xFF440000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_htu.h b/bsp/rm48x50/HALCoGen/include/reg_htu.h
new file mode 100644
index 0000000000000000000000000000000000000000..a072b79237c3dff2915a02d38ac1237d06b33146
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_htu.h
@@ -0,0 +1,101 @@
+/** @file reg_htu.h
+*   @brief HTU Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the HTU driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_HTU_H__
+#define __REG_HTU_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* htu Register Frame Definition */
+/** @struct htuBase
+*   @brief HTU Base Register Definition
+*
+*   This structure is used to access the HTU module registers.
+*/
+/** @typedef htuBASE_t
+*   @brief HTU Register Frame Type Definition
+*
+*   This type is used to access the HTU Registers.
+*/
+typedef volatile struct htuBase
+{
+    uint32 GC;				/** 0x00 */ 
+    uint32 CPENA;			/** 0x04 */ 
+    uint32 BUSY0;			/** 0x08 */ 
+    uint32 BUSY1;			/** 0x0C */ 
+    uint32 BUSY2;			/** 0x10 */ 
+    uint32 BUSY3;			/** 0x14 */ 
+	uint32 ACPE;			/** 0x18 */ 
+    uint32 rsvd1;    		/** 0x1C */ 
+    uint32 RLBECTRL;		/** 0x20 */ 
+    uint32 BFINTS;			/** 0x24 */ 
+    uint32 BFINTC;			/** 0x28 */ 
+    uint32 INTMAP;			/** 0x2C */ 
+    uint32 rsvd2;  			/** 0x30 */ 
+    uint32 INTOFF0;			/** 0x34 */ 
+    uint32 INTOFF1;			/** 0x38 */ 
+    uint32 BIM;				/** 0x3C */ 
+    uint32 RLOSTFL;			/** 0x40 */ 
+    uint32 BFINTFL;			/** 0x44 */ 
+    uint32 BERINTFL;		/** 0x48 */ 
+    uint32 MP1S;			/** 0x4C */ 
+    uint32 MP1E;			/** 0x50 */ 
+    uint32 DCTRL;			/** 0x54 */ 
+    uint32 WPR;				/** 0x58 */ 
+    uint32 WMR;				/** 0x5C */ 
+    uint32 ID;				/** 0x60 */ 
+    uint32 PCR;				/** 0x64 */ 
+    uint32 PAR;				/** 0x68 */ 
+    uint32 rsvd3; 			/** 0x6C */ 
+    uint32 MPCS;			/** 0x70 */ 
+    uint32 MP0S;			/** 0x74 */ 
+    uint32 MP0E;			/** 0x78 */ 
+} htuBASE_t;                        
+                                    
+typedef volatile struct htudcp      
+{                                   
+    uint32 IFADDRA;			 
+    uint32 IFADDRB;			
+    uint32 IHADDRCT;		
+    uint32 ITCOUNT;			
+} htudcp_t;                         
+                                    
+typedef volatile struct htucdcp     
+{     
+    uint32 CFADDRA;			
+    uint32 CFADDRB;			
+    uint32 CFCOUNT;			
+    uint32 rsvd4; 			
+} htucdcp_t;
+
+#define htuREG1   ((htuBASE_t *)0xFFF7A400U)
+#define htuREG2   ((htuBASE_t *)0xFFF7A500U)
+
+#define htuDCP1   ((htudcp_t *)0xFF4E0000U)
+#define htuDCP2   ((htudcp_t *)0xFF4C0000U)
+
+#define htuCDCP1   ((htucdcp_t *)0xFF4E0100U)
+#define htuCDCP2   ((htucdcp_t *)0xFF4C0100U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_i2c.h b/bsp/rm48x50/HALCoGen/include/reg_i2c.h
new file mode 100644
index 0000000000000000000000000000000000000000..c3015a19e812ebb3755ae33fd6e0fb9ac71d0649
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_i2c.h
@@ -0,0 +1,94 @@
+/** @file reg_i2c.h
+*   @brief I2C Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the I2C driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_I2C_H__
+#define __REG_I2C_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* I2c Register Frame Definition */
+/** @struct i2cBase
+*   @brief I2C Base Register Definition
+*
+*   This structure is used to access the I2C module registers.
+*/
+/** @typedef i2cBASE_t
+*   @brief I2C Register Frame Type Definition
+*
+*   This type is used to access the I2C Registers.
+*/
+typedef volatile struct i2cBase
+{
+
+    uint32 OAR;           /**<  0x0000 I2C Own Address register               */
+    uint32 IMR;           /**<  0x0004 I2C Interrupt Mask/Status register     */
+    uint32 STR;           /**<  0x0008 I2C Interrupt Status register          */
+    uint32 CLKL;          /**<  0x000C I2C Clock Divider Low register         */
+    uint32 CLKH;          /**<  0x0010 I2C Clock Divider High register        */
+    uint32 CNT;           /**<  0x0014 I2C Data Count register                */
+    uint32 DRR;           /**<  0x0018 I2C Data Receive register              */
+    uint32 SAR;           /**<  0x001C I2C Slave Address register             */
+    uint32 DXR;           /**<  0x0020 I2C Data Transmit register             */
+    uint32 MDR;           /**<  0x0024 I2C Mode register                      */
+    uint32 IVR;           /**<  0x0028 I2C Interrupt Vector register          */
+    uint32 EMDR;          /**<  0x002C I2C Extended Mode register             */
+    uint32 PSC;           /**<  0x0030 I2C Prescaler register                 */
+    uint32 PID11;         /**<  0x0034 I2C Peripheral ID register 1           */
+    uint32 PID12;         /**<  0x0038 I2C Peripheral ID register 2           */
+    uint32 DMAC;          /**<  0x003C I2C DMA Control Register               */
+    uint32   rsvd1;       /**<  0x0040 Reserved                               */
+    uint32   rsvd2;       /**<  0x0044 Reserved                               */
+    uint32 FUN;           /**<  0x0048 Pin Function Register                  */
+    uint32 DIR;           /**<  0x004C Pin Direction Register                 */
+    uint32 DIN;           /**<  0x0050 Pin Data In Register                   */
+    uint32 DOUT;          /**<  0x0054 Pin Data Out Register                  */
+    uint32 SET;           /**<  0x0058 Pin Data Set Register                  */
+    uint32 CLR;           /**<  0x005C Pin Data Clr Register                  */
+    uint32 ODR;           /**<  0x0060 Pin Open Drain Output Enable Register  */
+    uint32 PD;            /**<  0x0064 Pin Pullup/Pulldown Disable Register   */
+    uint32 PSL;           /**<  0x0068 Pin Pullup/Pulldown Selection Register */
+} i2cBASE_t;
+
+
+/** @def i2cREG1
+*   @brief I2C Register Frame Pointer
+*
+*   This pointer is used by the I2C driver to access the I2C module registers.
+*/
+#define i2cREG1 ((i2cBASE_t *)0xFFF7D400U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @def i2cPORT1
+*   @brief I2C GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of I2C
+*   (use the GIO drivers to access the port pins).
+*/
+#define i2cPORT1 ((gioPORT_t *)0xFFF7D44CU)
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_lin.h b/bsp/rm48x50/HALCoGen/include/reg_lin.h
new file mode 100644
index 0000000000000000000000000000000000000000..b1b1f13df09f468ecfcb70369c8f61d9de44a722
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_lin.h
@@ -0,0 +1,97 @@
+/** @file reg_lin.h
+*   @brief LIN Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the LIN driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_LIN_H__
+#define __REG_LIN_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Lin Register Frame Definition */
+/** @struct linBase
+*   @brief LIN Base Register Definition
+*
+*   This structure is used to access the LIN module registers.
+*/
+/** @typedef linBASE_t
+*   @brief LIN  Register Frame Type Definition
+*
+*   This type is used to access the LIN Registers.
+*/
+
+typedef volatile struct linBase
+{
+    uint32      GCR0;         /**< 0x0000: Global control register 0              */
+    uint32      GCR1;         /**< 0x0004: Global control register 1              */
+    uint32      GCR2;         /**< 0x0008: Global control register 2              */
+    uint32      SETINT;       /**< 0x000C: Set interrupt enable register          */
+    uint32      CLRINT;       /**< 0x0010: Clear interrupt enable register        */
+    uint32      SETINTLVL;    /**< 0x0014: Set interrupt level register           */
+    uint32      CLRINTLVL;    /**< 0x0018: Set interrupt level register           */
+    uint32      FLR;          /**< 0x001C: interrupt flag register                */
+    uint32      INTVECT0;     /**< 0x0020: interrupt vector Offset 0              */
+    uint32      INTVECT1;     /**< 0x0024: interrupt vector Offset 1              */
+    uint32      FORMAT;       /**< 0x0028: Format Control Register                */	
+    uint32      BRSR;         /**< 0x002C: Baud rate selection register           */
+    uint32      ED;           /**< 0x0030: Emulation register                     */
+    uint32      RD;           /**< 0x0034: Receive data register                  */
+    uint32      TD;           /**< 0x0038: Transmit data register                 */
+    uint32      FUN;          /**< 0x003C: Pin function register                  */
+    uint32      DIR;          /**< 0x0040: Pin direction register                 */
+    uint32      DIN;          /**< 0x0044: Pin data in register                   */
+    uint32      DOUT;         /**< 0x0048: Pin data out register                  */
+    uint32      SET;          /**< 0x004C: Pin data set register                  */
+    uint32      CLR;          /**< 0x0050: Pin data clr register                  */
+    uint32      ODR;          /**< 0x0054: Pin open drain output enable register  */
+    uint32      PD;           /**< 0x0058: Pin pullup/pulldown disable register   */
+    uint32      PSL;          /**< 0x005C: Pin pullup/pulldown selection register */
+    uint32      COMP;         /**< 0x0060: Compare register                       */
+    uint8       RDx[8U];      /**< 0x0064-0x0068: RX buffer register              */
+    uint32      MASK;         /**< 0x006C: Mask register                          */
+    uint32      ID;           /**< 0x0070: Identification Register                */	
+    uint8       TDx[8U];      /**< 0x0074-0x0078: TX buffer register              */
+    uint32      MBRSR;        /**< 0x007C: Maximum baud rate selection register   */
+    uint32      SL;           /**< 0x0080: Pin slew rate register                 */
+    uint32        rsvd1[3U];   /**< 0x0084: Reserved                               */
+    uint32      IODFTCTRL;    /**< 0x0090: IODFT loopback register                */
+} linBASE_t;
+
+
+/** @def linREG
+*   @brief LIN Register Frame Pointer
+*
+*   This pointer is used by the LIN driver to access the lin module registers.
+*/
+#define linREG ((linBASE_t *)0xFFF7E400U)
+
+
+/** @def linPORT
+*   @brief LIN GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of LIN
+*   (use the GIO drivers to access the port pins).
+*/
+#define linPORT ((gioPORT_t *)0xFFF7E440U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_mibspi.h b/bsp/rm48x50/HALCoGen/include/reg_mibspi.h
new file mode 100644
index 0000000000000000000000000000000000000000..42796f0001e0cfaa04e4d3ae5bf8eb5e41ffb7d3
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_mibspi.h
@@ -0,0 +1,224 @@
+/** @file reg_mibspi.h
+*   @brief MIBSPI Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the MIBSPI driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_MIBSPI_H__
+#define __REG_MIBSPI_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Mibspi Register Frame Definition */
+/** @struct mibspiBase
+*   @brief MIBSPI Register Definition
+*
+*   This structure is used to access the MIBSPI module registers.
+*/
+/** @typedef mibspiBASE_t
+*   @brief MIBSPI Register Frame Type Definition
+*
+*   This type is used to access the MIBSPI Registers.
+*/
+typedef volatile struct mibspiBase
+{
+    uint32  GCR0;                 /**< 0x0000: Global Control 0 */
+    uint32  GCR1;                 /**< 0x0004: Global Control 1 */	
+    uint32  INT0;                 /**< 0x0008: Interrupt Register */	
+    uint32  LVL;                  /**< 0x000C: Interrupt Level */
+    uint32  FLG;                  /**< 0x0010: Interrupt flags */	
+    uint32  PCFUN;                /**< 0x0014: Function Pin Enable */
+    uint32  PCDIR;                /**< 0x0018: Pin Direction */
+    uint32  PCDIN;                /**< 0x001C: Pin Input Latch */
+    uint32  PCDOUT;               /**< 0x0020: Pin Output Latch */
+    uint32  PCSET;                /**< 0x0024: Output Pin Set */
+    uint32  PCCLR;                /**< 0x0028: Output Pin Clr */
+    uint32  PCPDR;                /**< 0x002C: Open Drain Output Enable */
+    uint32  PCDIS;                /**< 0x0030: Pullup/Pulldown Disable */
+    uint32  PCPSL;                /**< 0x0034: Pullup/Pulldown Selection */
+    uint32  DAT0;                 /**< 0x0038: Transmit Data */
+    uint32  DAT1;                 /**< 0x003C: Transmit Data with Format and Chip Select */
+    uint32  BUF;                  /**< 0x0040: Receive Buffer */
+    uint32  EMU;                  /**< 0x0044: Emulation Receive Buffer */
+    uint32  DELAY;                /**< 0x0048: Delays */
+    uint32  CSDEF;                /**< 0x004C: Default Chip Select */
+    uint32  FMT0;                 /**< 0x0050: Data Format 0 */
+    uint32  FMT1;                 /**< 0x0054: Data Format 1 */
+    uint32  FMT2;                 /**< 0x0058: Data Format 2 */
+    uint32  FMT3;                 /**< 0x005C: Data Format 3 */
+    uint32  INTVECT0;             /**< 0x0060: Interrupt Vector 0 */
+    uint32  INTVECT1;             /**< 0x0064: Interrupt Vector 1 */
+    uint32  SRSEL;                /**< 0x0068: Slew Rate Select */
+    uint32  PMCTRL;               /**< 0x006C: Parallel Mode Control */
+    uint32  MIBSPIE;              /**< 0x0070: Multi-buffer Mode Enable  */
+    uint32  TGITENST;             /**< 0x0074: TG Interrupt Enable Set */
+    uint32  TGITENCR;             /**< 0x0078: TG Interrupt Enable Clear */
+    uint32  TGITLVST;             /**< 0x007C: Transfer Group Interrupt Level Set */
+    uint32  TGITLVCR;             /**< 0x0080: Transfer Group Interrupt Level Clear */
+    uint32  TGINTFLG;             /**< 0x0084: Transfer Group Interrupt Flag */	
+    uint32    rsvd1[2U];           /**< 0x0088: Reserved */
+    uint32  TICKCNT;              /**< 0x0090: Tick Counter */
+    uint32  LTGPEND;              /**< 0x0090: Last TG End Pointer */	
+    uint32  TGCTRL[16U];          /**< 0x0098 - 0x00D4: Transfer Group Control */
+    uint32  DMACTRL[8U];          /**< 0x00D8 - 0x00F4: DMA Control */
+    uint32  DMACOUNT[8U];         /**< 0x00F8 - 0x0114: DMA Count */
+    uint32  DMACNTLEN;            /**< 0x0118 - 0x0114: DMA Control length */
+    uint32    rsvd2;              /**< 0x011C: Reserved */
+    uint32  UERRCTRL;             /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control */	
+    uint32  UERRSTAT;             /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */	  
+    uint32  UERRADDRRX;           /**< 0x0128: RXRAM Uncorrectable Parity Error Address */	
+    uint32  UERRADDRTX;           /**< 0x012C: TXRAM Uncorrectable Parity Error Address */	
+    uint32  RXOVRN_BUF_ADDR;      /**< 0x0130: RXRAM Overrun Buffer Address */
+    uint32  IOLPKTSTCR;           /**< 0x0134: IO loopback */
+    uint32  EXT_PRESCALE1;        /**< 0x0138: */
+    uint32  EXT_PRESCALE2;        /**< 0x013C: */
+} mibspiBASE_t;
+
+
+/** @def mibspiREG1
+*   @brief MIBSPI1 Register Frame Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG1 ((mibspiBASE_t *)0xFFF7F400U)
+
+
+/** @def mibspiPORT1
+*   @brief MIBSPI1 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of MIBSPI1
+*   (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT1 ((gioPORT_t *)0xFFF7F418U)
+
+/** @def mibspiREG3
+*   @brief MIBSPI3 Register Frame Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG3 ((mibspiBASE_t *)0xFFF7F800U)
+
+
+/** @def mibspiPORT3
+*   @brief MIBSPI3 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of MIBSPI3
+*   (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT3 ((gioPORT_t *)0xFFF7F818U)
+
+/** @def mibspiREG5
+*   @brief MIBSPI5 Register Frame Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG5 ((mibspiBASE_t *)0xFFF7FC00U)
+
+
+/** @def mibspiPORT5
+*   @brief MIBSPI5 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of MIBSPI5
+*   (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT5 ((gioPORT_t *)0xFFF7FC18U)
+
+
+/** @struct mibspiRamBase
+*   @brief MIBSPI Buffer RAM Definition
+*
+*   This structure is used to access the MIBSPI buffer memory.
+*/
+/** @typedef mibspiRAM_t
+*   @brief MIBSPI RAM Type Definition
+*
+*   This type is used to access the MIBSPI RAM.
+*/
+typedef volatile struct mibspiRamBase
+{
+    struct 
+    {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+     uint16  data;     /**< tx buffer data    */   
+     uint16  control;  /**< tx buffer control */  
+#else
+     uint16  control;  /**< tx buffer control */
+     uint16  data;     /**< tx buffer data    */
+#endif
+    } tx[128];
+    struct
+    {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+     uint16 data;     /**< rx buffer data  */
+	 uint16 flags;    /**< rx buffer flags */
+#else
+	 uint16 flags;    /**< rx buffer flags */
+     uint16 data;     /**< rx buffer data  */
+#endif
+    } rx[128];
+} mibspiRAM_t;
+
+
+/** @def mibspiRAM1
+*   @brief MIBSPI1 Buffer RAM Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM1 ((mibspiRAM_t *)0xFF0E0000U)
+
+/** @def mibspiRAM3
+*   @brief MIBSPI3 Buffer RAM Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM3 ((mibspiRAM_t *)0xFF0C0000U)
+
+/** @def mibspiRAM5
+*   @brief MIBSPI5 Buffer RAM Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM5 ((mibspiRAM_t *)0xFF0A0000U)
+
+/** @def mibspiPARRAM1
+*   @brief MIBSPI1 Buffer RAM PARITY Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM1 (*(volatile uint32 *)(0xFF0E0000U + 0x00000400U))
+
+/** @def mibspiPARRAM3
+*   @brief MIBSPI3 Buffer RAM PARITY Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM3 (*(volatile uint32 *)(0xFF0C0000U + 0x00000400U))
+
+
+/** @def mibspiPARRAM5
+*   @brief MIBSPI5 Buffer RAM PARITY Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM5 (*(volatile uint32 *)(0xFF0A0000U + 0x00000400U))
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_pbist.h b/bsp/rm48x50/HALCoGen/include/reg_pbist.h
new file mode 100644
index 0000000000000000000000000000000000000000..92f29c5414d8fcf244d292dcba0a3bf5a6fbfef4
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_pbist.h
@@ -0,0 +1,65 @@
+/** @file reg_pbist.h
+*   @brief PBIST Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_PBIST_H__
+#define __REG_PBIST_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* PBIST Register Frame Definition */
+/** @struct pbistBase
+*   @brief PBIST Base Register Definition
+*
+*   This structure is used to access the PBIST module registers.
+*/
+/** @typedef pbistBASE_t
+*   @brief PBIST Register Frame Type Definition
+*
+*   This type is used to access the PBIST Registers.
+*/
+typedef volatile struct pbistBase
+{
+    uint32 RAMT;			/* 0x0160: RAM Configuration Register */
+    uint32 DLR;			/* 0x0164: Datalogger Register */
+    uint32   rsvd1[6U];	/* 0x0168 */
+    uint32 PACT;			/* 0x0180: PBIST Activate Register */
+    uint32 PBISTID;		/* 0x0184: PBIST ID Register */
+    uint32 OVER;			/* 0x0188: Override Register */
+    uint32   rsvd2;		/* 0x018C */
+    uint32 FSRF0;			/* 0x0190: Fail Status Fail Register 0 */
+	uint32 FSRF1;			/* 0x0194: Fail Status Fail Register 1 */
+    uint32 FSRC0;			/* 0x0198: Fail Status Count Register 0 */
+    uint32 FSRC1;			/* 0x019C: Fail Status Count Register 1 */
+    uint32 FSRA0;			/* 0x01A0: Fail Status Address 0 Register */
+    uint32 FSRA1;			/* 0x01A4: Fail Status Address 1 Register */
+    uint32 FSRDL0;		/* 0x01A8: Fail Status Data Register 0 */
+    uint32   rsvd3;		/* 0x01AC */
+    uint32 FSRDL1;		/* 0x01B0: Fail Status Data Register 1 */
+    uint32   rsvd4[3U];	/* 0x01B4 */
+    uint32 ROM;			/* 0x01C0: ROM Mask Register */
+    uint32 ALGO;			/* 0x01C4: Algorithm Mask Register */
+    uint32 RINFOL;		/* 0x01C8: RAM Info Mask Lower Register */
+    uint32 RINFOU;		/* 0x01CC: RAM Info Mask Upper Register */
+} pbistBASE_t;
+
+#define pbistREG   ((pbistBASE_t *)0xFFFFE560U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_pcr.h b/bsp/rm48x50/HALCoGen/include/reg_pcr.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac60aebfee718c5e9fe8f08d8f8f891c963cf16c
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_pcr.h
@@ -0,0 +1,80 @@
+/** @file reg_pcr.h
+*   @brief PCR Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_PCR_H__
+#define __REG_PCR_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pcr Register Frame Definition */
+/** @struct pcrBase
+*   @brief Pcr Register Frame Definition
+*
+*   This type is used to access the Pcr Registers.
+*/
+/** @typedef pcrBASE_t
+*   @brief PCR Register Frame Type Definition
+*
+*   This type is used to access the PCR Registers.
+*/
+typedef volatile struct pcrBase
+{
+    uint32 PMPROTSET0;    /* 0x0000 */
+    uint32 PMPROTSET1;    /* 0x0004 */
+    uint32   rsvd1[2U];    /* 0x0008 */
+    uint32 PMPROTCLR0;    /* 0x0010 */
+    uint32 PMPROTCLR1;    /* 0x0014 */
+    uint32   rsvd2[2U];    /* 0x0018 */
+    uint32 PPROTSET0;     /* 0x0020 */
+    uint32 PPROTSET1;     /* 0x0024 */
+    uint32 PPROTSET2;     /* 0x0028 */
+    uint32 PPROTSET3;     /* 0x002C */
+    uint32   rsvd3[4U];    /* 0x0030 */
+    uint32 PPROTCLR0;     /* 0x0040 */
+    uint32 PPROTCLR1;     /* 0x0044 */
+    uint32 PPROTCLR2;     /* 0x0048 */
+    uint32 PPROTCLR3;     /* 0x004C */
+    uint32   rsvd4[4U];    /* 0x0050 */
+    uint32 PCSPWRDWNSET0; /* 0x0060 */
+    uint32 PCSPWRDWNSET1; /* 0x0064 */
+    uint32   rsvd5[2U];    /* 0x0068 */
+    uint32 PCSPWRDWNCLR0; /* 0x0070 */
+    uint32 PCSPWRDWNCLR1; /* 0x0074 */
+    uint32   rsvd6[2U];    /* 0x0078 */
+    uint32 PSPWRDWNSET0;  /* 0x0080 */
+    uint32 PSPWRDWNSET1;  /* 0x0084 */
+    uint32 PSPWRDWNSET2;  /* 0x0088 */
+    uint32 PSPWRDWNSET3;  /* 0x008C */
+    uint32   rsvd7[4U];    /* 0x0090 */
+    uint32 PSPWRDWNCLR0;  /* 0x00A0 */
+    uint32 PSPWRDWNCLR1;  /* 0x00A4 */
+    uint32 PSPWRDWNCLR2;  /* 0x00A8 */
+    uint32 PSPWRDWNCLR3;  /* 0x00AC */
+} pcrBASE_t;
+
+/** @def pcrREG
+*   @brief Pcr Register Frame Pointer
+*
+*   This pointer is used by the system driver to access the Pcr registers.
+*/
+#define pcrREG ((pcrBASE_t *)0xFFFFE000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_pinmux.h b/bsp/rm48x50/HALCoGen/include/reg_pinmux.h
new file mode 100644
index 0000000000000000000000000000000000000000..55385ee8341ef59dcd78db4cb2f24cdbddf1710b
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_pinmux.h
@@ -0,0 +1,129 @@
+/** @file reg_pinmux.h
+*   @brief PINMUX Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the PINMUX driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_PINMUX_H__
+#define __REG_PINMUX_H__
+
+#include "sys_common.h"
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* IOMM Revision and Boot Register */
+#define REVISION_REG		(*(volatile uint32 *)0xFFFFEA00U)
+#define ENDIAN_REG		(*(volatile uint32 *)0xFFFFEA20U)
+
+/* IOMM Error and Fault Registers */
+/** @struct iommErrFault
+*   @brief IOMM Error and Fault Register Definition
+*
+*   This structure is used to access the IOMM Error and Fault registers.
+*/
+typedef volatile struct iommErrFault
+{
+    uint32 ERR_RAW_STATUS_REG;          /* Error Raw Status / Set Register */
+    uint32 ERR_ENABLED_STATUS_REG;      /* Error Enabled Status / Clear Register */
+    uint32 ERR_ENABLE_REG;              /* Error Signaling Enable Register */
+    uint32 ERR_ENABLE_CLR_REG;          /* Error Signaling Enable Clear Register */
+	uint32  rsvd;                       /* Reserved */
+    uint32 FAULT_ADDRESS_REG;           /* Fault Address Register */
+    uint32 FAULT_STATUS_REG;            /* Fault Status Register */
+    uint32 FAULT_CLEAR_REG;             /* Fault Clear Register */	
+} iommErrFault_t;
+/* Pinmux Register Frame Definition */
+/** @struct pinMuxKicker
+*   @brief Pin Muxing Kicker Register Definition
+*
+*   This structure is used to access the Pin Muxing Kicker registers.
+*/
+typedef volatile struct pinMuxKicker
+{
+    uint32 KICKER0;       /* kicker 0 register */
+    uint32 KICKER1;       /* kicker 1 register */
+} pinMuxKICKER_t;
+
+/** @struct pinMuxBase
+*   @brief PINMUX Register Definition
+*
+*   This structure is used to access the PINMUX module registers.
+*/
+/** @typedef pinMuxBASE_t
+*   @brief PINMUX Register Frame Type Definition
+*
+*   This type is used to access the PINMUX Registers.
+*/
+typedef volatile struct pinMuxBase
+{
+    uint32 PINMMR0;		/**< 0xEB10 Pin Mux 0 register*/
+    uint32 PINMMR1;		/**< 0xEB14 Pin Mux 1 register*/
+    uint32 PINMMR2;		/**< 0xEB18 Pin Mux 2 register*/
+    uint32 PINMMR3;		/**< 0xEB1C Pin Mux 3 register*/
+    uint32 PINMMR4;		/**< 0xEB20 Pin Mux 4 register*/
+    uint32 PINMMR5;		/**< 0xEB24 Pin Mux 5 register*/
+    uint32 PINMMR6;		/**< 0xEB28 Pin Mux 6 register*/
+    uint32 PINMMR7;		/**< 0xEB2C Pin Mux 7 register*/
+    uint32 PINMMR8;		/**< 0xEB30 Pin Mux 8 register*/
+    uint32 PINMMR9;		/**< 0xEB34 Pin Mux 9 register*/
+    uint32 PINMMR10;		/**< 0xEB38 Pin Mux 10 register*/
+    uint32 PINMMR11;		/**< 0xEB3C Pin Mux 11 register*/
+    uint32 PINMMR12;		/**< 0xEB40 Pin Mux 12 register*/
+    uint32 PINMMR13;		/**< 0xEB44 Pin Mux 13 register*/
+    uint32 PINMMR14;		/**< 0xEB48 Pin Mux 14 register*/
+    uint32 PINMMR15;		/**< 0xEB4C Pin Mux 15 register*/
+    uint32 PINMMR16;		/**< 0xEB50 Pin Mux 16 register*/
+    uint32 PINMMR17;		/**< 0xEB54 Pin Mux 17 register*/
+    uint32 PINMMR18;		/**< 0xEB58 Pin Mux 18 register*/
+    uint32 PINMMR19;		/**< 0xEB5C Pin Mux 19 register*/
+    uint32 PINMMR20;		/**< 0xEB60 Pin Mux 20 register*/
+    uint32 PINMMR21;		/**< 0xEB64 Pin Mux 21 register*/
+    uint32 PINMMR22;		/**< 0xEB68 Pin Mux 22 register*/
+    uint32 PINMMR23;		/**< 0xEB6C Pin Mux 23 register*/
+    uint32 PINMMR24;		/**< 0xEB70 Pin Mux 24 register*/
+    uint32 PINMMR25;		/**< 0xEB74 Pin Mux 25 register*/
+    uint32 PINMMR26;		/**< 0xEB78 Pin Mux 26 register*/
+    uint32 PINMMR27;		/**< 0xEB7C Pin Mux 27 register*/
+    uint32 PINMMR28;		/**< 0xEB80 Pin Mux 28 register*/
+    uint32 PINMMR29;		/**< 0xEB84 Pin Mux 29 register*/
+    uint32 PINMMR30;		/**< 0xEB88 Pin Mux 30 register*/
+}pinMuxBASE_t;
+
+
+/** @def iommErrFaultReg
+*       @brief IOMM Error Fault Register Frame Pointer
+*
+*               This pointer is used to control IOMM Error and Fault across the device.
+*/      
+#define iommErrFaultReg ((iommErrFault_t *) 0xFFFFEAEOU)
+        
+/** @def kickerReg
+*	@brief Pin Muxing Kicker Register Frame Pointer
+*
+*		This pointer is used to enable and disable muxing accross the device.
+*/	
+#define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38U)
+
+/** @def pinMuxReg
+*	@brief Pin Muxing Control Register Frame Pointer
+*
+*		This pointer is used to set the muxing registers accross the device.
+*/	
+#define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_pmm.h b/bsp/rm48x50/HALCoGen/include/reg_pmm.h
new file mode 100644
index 0000000000000000000000000000000000000000..d92ddfbd55a944856a7fb8ccc6cb207ca505e568
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_pmm.h
@@ -0,0 +1,78 @@
+/** @file reg_pmm.h
+*   @brief PMM Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the PMM driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_PMM_H__
+#define __REG_PMM_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pmm Register Frame Definition */
+/** @struct pmmBase
+*   @brief Pmm Register Frame Definition
+*
+*   This type is used to access the Pmm Registers.
+*/
+/** @typedef pmmBase_t
+*   @brief Pmm Register Frame Type Definition
+*
+*   This type is used to access the Pmm Registers.
+*/
+typedef volatile struct pmmBase
+{
+	uint32 LOGICPDPWRCTRL0;		/**< 0x0000: Logic Power Domain Control Register 0 */	
+    uint32   rsvd1[3U];			/**< 0x0004: Reserved*/
+	uint32 MEMPDPWRCTRL0;		/**< 0x0010: Memory Power Domain Control Register 0 */
+    uint32   rsvd2[3U];			/**< 0x0014: Reserved*/
+    uint32 PDCLKDISREG;			/**< 0x0020: Power Domain Clock Disable Register */
+    uint32 PDCLKDISSETREG;		/**< 0x0024: Power Domain Clock Disable Set Register */
+    uint32 PDCLKDISCLRREG;		/**< 0x0028: Power Domain Clock Disable Clear Register */
+    uint32   rsvd3[5U];			/**< 0x002C: Reserved */
+    uint32 LOGICPDPWRSTAT[4U]; 	/**< 0x0040, 0x0044, 0x0048, 0x004C: Logic Power Domain Power Status Register 
+										- 0: PD2
+										- 1: PD3
+										- 2: PD4
+										- 3: PD5 */
+    uint32   rsvd4[12U];		/**< 0x0050: Reserved*/
+    uint32 MEMPDPWRSTAT[3U];	/**< 0x0080, 0x0084, 0x0088: Memory Power Domain Power Status Register 
+										- 0: RAM_PD1
+										- 1: RAM_PD2
+										- 2: RAM_PD3 */
+    uint32   rsvd5[5U];			/**< 0x008C: Reserved */
+    uint32 GLOBALCTRL1;			/**< 0x00A0: Global Control Register 1 */
+    uint32   rsvd6;				/**< 0x00A4: Reserved */
+    uint32 GLOBALSTAT;			/**< 0x00A8: Global Status Register */
+    uint32 PRCKEYREG;			/**< 0x00AC: PSCON Diagnostic Compare Key Register */
+    uint32 LPDDCSTAT1;			/**< 0x00B0: LogicPD PSCON Diagnostic Compare Status Register 1 */
+    uint32 LPDDCSTAT2;			/**< 0x00B4: LogicPD PSCON Diagnostic Compare Status Register 2 */
+    uint32 MPDDCSTAT1;			/**< 0x00B8: Memory PD PSCON Diagnostic Compare Status Register 1 */
+    uint32 MPDDCSTAT2;			/**< 0x00BC: Memory PD PSCON Diagnostic Compare Status Register 2 */
+    uint32 ISODIAGSTAT;			/**< 0x00C0: Isolation Diagnostic Status Register */
+}pmmBase_t;
+
+
+/** @def pmmREG
+*   @brief Pmm Register Frame Pointer
+*
+*   This pointer is used by the Pmm driver to access the Pmm registers.
+*/
+#define pmmREG ((pmmBase_t *)0xFFFF0000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_pom.h b/bsp/rm48x50/HALCoGen/include/reg_pom.h
new file mode 100644
index 0000000000000000000000000000000000000000..9d0a885acd0a0aecc7f4cb64202e58783747225c
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_pom.h
@@ -0,0 +1,94 @@
+/** @file reg_pom.h
+*   @brief POM Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the POM driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_POM_H__
+#define __REG_POM_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pom Register Frame Definition */
+/** @struct POMBase
+*   @brief POM Register Frame Definition
+*
+*   This structure is used to access the POM module registers(POM Register Map).
+*/
+typedef struct
+{
+  uint32 POMGLBCTRL_UL;   /* 0x00      */
+  uint32 POMREV_UL;       /* 0x04      */
+  uint32 POMCLKCTRL_UL;   /* 0x08      */
+  uint32 POMFLG_UL;       /* 0x0C      */
+  struct
+  {
+    uint32   rsdv1;
+  }RESERVED_REG[124U];
+  struct                    /* 0x200 ...    */
+  {
+    uint32 POMPROGSTART_UL; 
+    uint32 POMOVLSTART_UL; 
+    uint32 POMREGSIZE_UL; 
+    uint32   rsdv2; 
+  }POMRGNCONF_ST[32U];
+}pomBASE_t;
+
+
+/** @struct POM_CORESIGHT_ST
+*   @brief POM_CORESIGHT_ST Register Definition
+*
+*   This structure is used to access the POM module registers(POM CoreSight Registers ).
+*/
+typedef struct
+{
+    uint32 POMITCTRL_UL;                  /* 0xF00            */
+    struct                                  /* 0xF04 to 0xF9C   */                     
+    {
+        uint32 Reserved_Reg_UL;
+    }Reserved1_ST[39U];
+    uint32 POMCLAIMSET_UL;                /* 0xFA0      */
+    uint32 POMCLAIMCLR_UL;                /* 0xFA4      */
+    uint32   rsvd1[2U];                    /* 0xFA8      */
+    uint32 POMLOCKACCESS_UL;              /* 0xFB0      */
+    uint32 POMLOCKSTATUS_UL;              /* 0xFB4      */
+    uint32 POMAUTHSTATUS_UL;              /* 0xFB8      */
+    uint32   rsvd2[3U];                    /* 0xFBC      */
+    uint32 POMDEVID_UL;                   /* 0xFC8      */
+    uint32 POMDEVTYPE_UL;                 /* 0xFCC      */
+    uint32 POMPERIPHERALID4_UL;           /* 0xFD0      */
+    uint32 POMPERIPHERALID5_UL;           /* 0xFD4      */
+    uint32 POMPERIPHERALID6_UL;           /* 0xFD8      */
+    uint32 POMPERIPHERALID7_UL;           /* 0xFDC      */
+    uint32 POMPERIPHERALID0_UL;           /* 0xFE0      */
+    uint32 POMPERIPHERALID1_UL;           /* 0xFE4      */
+    uint32 POMPERIPHERALID2_UL;           /* 0xFE8      */
+    uint32 POMPERIPHERALID3_UL;           /* 0xFEC      */            
+    uint32 POMCOMPONENTID0_UL;            /* 0xFF0      */
+    uint32 POMCOMPONENTID1_UL;            /* 0xFF4      */
+    uint32 POMCOMPONENTID2_UL;            /* 0xFF8      */
+    uint32 POMCOMPONENTID3_UL;            /* 0xFFC      */
+}POM_CORESIGHT_ST;
+
+
+#define pomREG ((pomBASE_t *)0xFFA04000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_rti.h b/bsp/rm48x50/HALCoGen/include/reg_rti.h
new file mode 100644
index 0000000000000000000000000000000000000000..45b455257d04dbeaec198d9d221a5b8eb1d604f2
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_rti.h
@@ -0,0 +1,96 @@
+/** @file reg_rti.h
+*   @brief RTI Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the RTI driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_RTI_H__
+#define __REG_RTI_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Rti Register Frame Definition */
+/** @struct rtiBase
+*   @brief RTI Register Frame Definition
+*
+*   This type is used to access the RTI Registers.
+*/
+/** @typedef rtiBASE_t
+*   @brief RTI Register Frame Type Definition
+*
+*   This type is used to access the RTI Registers.
+*/
+typedef volatile struct rtiBase
+{
+    uint32 GCTRL;          /**< 0x0000: Global Control Register   */
+    uint32 TBCTRL;         /**< 0x0004: Timebase Control Register */
+    uint32 CAPCTRL;        /**< 0x0008: Capture Control Register  */
+    uint32 COMPCTRL;       /**< 0x000C: Compare Control Register  */
+    struct
+    {
+        uint32 FRCx;       /**< 0x0010,0x0030: Free Running Counter x Register         */
+        uint32 UCx;        /**< 0x0014,0x0034: Up Counter x Register                   */
+        uint32 CPUCx;      /**< 0x0018,0x0038: Compare Up Counter x Register           */
+        uint32   rsvd1;    /**< 0x001C,0x003C: Reserved                                */
+        uint32 CAFRCx;     /**< 0x0020,0x0040: Capture Free Running Counter x Register */
+        uint32 CAUCx;      /**< 0x0024,0x0044: Capture Up Counter x Register           */
+        uint32   rsvd2[2U]; /**< 0x0028,0x0048: Reserved                                */
+    } CNT[2U];               /**< Counter x selection:
+                                    - 0: Counter 0
+                                    - 1: Counter 1                                       */
+    struct
+    {
+        uint32 COMPx;      /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register        */
+        uint32 UDCPx;      /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */
+    } CMP[4U];               /**< Compare x selection:
+                                    - 0: Compare 0 
+                                    - 1: Compare 1
+                                    - 2: Compare 2
+                                    - 3: Compare 3                                       */
+    uint32 TBLCOMP;        /**< 0x0070: External Clock Timebase Low Compare Register   */
+    uint32 TBHCOMP;        /**< 0x0074: External Clock Timebase High Compare Register  */
+    uint32   rsvd3[2U];     /**< 0x0078: Reserved                                       */
+    uint32 SETINT;         /**< 0x0080: Set/Status Interrupt Register                  */
+    uint32 CLEARINT;       /**< 0x0084: Clear/Status Interrupt Register                */
+    uint32 INTFLAG;        /**< 0x0088: Interrupt Flag Register                        */
+    uint32   rsvd4;        /**< 0x008C: Reserved                                       */
+    uint32 DWDCTRL;        /**< 0x0090: Digital Watchdog Control Register   */
+    uint32 DWDPRLD;        /**< 0x0094: Digital Watchdog Preload Register */
+    uint32 WDSTATUS;       /**< 0x0098: Watchdog Status Register  */
+    uint32 WDKEY;          /**< 0x009C: Watchdog Key Register  */
+    uint32 DWDCNTR;        /**< 0x00A0: Digital Watchdog Down Counter   */
+    uint32 WWDRXNCTRL;     /**< 0x00A4: Digital Windowed Watchdog Reaction Control */
+    uint32 WWDSIZECTRL;    /**< 0x00A8: Digital Windowed Watchdog Window Size Control  */
+    uint32 INTCLRENABLE;   /**< 0x00AC: RTI Compare Interrupt Clear Enable Register  */
+    uint32 COMP0CLR;       /**< 0x00B0: RTI Compare 0 Clear Register   */
+    uint32 COMP1CLR;       /**< 0x00B4: RTI Compare 1 Clear Register */
+    uint32 COMP2CLR;       /**< 0x00B8: RTI Compare 2 Clear Register  */
+    uint32 COMP3CLR;       /**< 0x00BC: RTI Compare 3 Clear Register  */
+} rtiBASE_t;
+
+/** @def rtiREG1
+*   @brief RTI1 Register Frame Pointer
+*
+*   This pointer is used by the RTI driver to access the RTI1 registers.
+*/
+#define rtiREG1 ((rtiBASE_t *)0xFFFFFC00U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_rtp.h b/bsp/rm48x50/HALCoGen/include/reg_rtp.h
new file mode 100644
index 0000000000000000000000000000000000000000..d9e930232defab824d1fefcf35ecd89d462516c4
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_rtp.h
@@ -0,0 +1,83 @@
+/** @file reg_rtp.h
+*   @brief RTP Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the RTP driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_RTP_H__
+#define __REG_RTP_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Rtp Register Frame Definition */
+/** @struct rtpBase
+*   @brief RTP Base Register Definition
+*
+*   This structure is used to access the RTP module registers.
+*/
+/** @typedef rtpBASE_t
+*   @brief RTP Register Frame Type Definition
+*
+*   This type is used to access the RTP Registers.
+*/
+typedef volatile struct rtpBase
+{
+    uint32  GLBCTRL;   /**< 0x0000: RTP Global Control Register             */
+    uint32  TRENA;     /**< 0x0004: RTP Trace Enable Register               */	
+    uint32  GSR;       /**< 0x0008: RTP Global Status Register              */
+    uint32  RAM1REG1;  /**< 0x000C: RTP RAM 1 Trace Region 1 Register       */
+    uint32  RAM1REG2;  /**< 0x0010: RTP RAM 1 Trace Region 2 Register       */
+    uint32  RAM2REG1;  /**< 0x0014: RTP RAM 2 Trace Region 1  Register      */
+    uint32  RAM2REG2;	 /**< 0x0018: RTP RAM 2 Trace Region 2  Register      */
+    uint32   rsvd1[2U]; /**< 0x001C: Reserved																																*/
+    uint32  ERREG1;    /**< 0x0024: RTP Peripheral Trace Region 1 Register  */
+    uint32  ERREG2;    /**< 0x0028: RTP Peripheral Trace Region 2 Register  */
+    uint32  DDMW;      /**< 0x002C: RTP Direct Data Mode Write Register     */
+    uint32   rsvd2;    /**< 0x0030: Reserved                                */
+    uint32  PC0;       /**< 0x0034: RTP Pin Control 0 Register              */
+    uint32  PC1;       /**< 0x0038: RTP Pin Control 1 Register              */
+    uint32  PC2;       /**< 0x003C: RTP Pin Control 2 Register              */
+    uint32  PC3;       /**< 0x0040: RTP Pin Control 3 Register              */
+    uint32  PC4;       /**< 0x0044: RTP Pin Control 4 Register              */
+    uint32  PC5;       /**< 0x0048: RTP Pin Control 5 Register              */
+    uint32  PC6;       /**< 0x004C: RTP Pin Control 6 Register              */
+    uint32  PC7;       /**< 0x0050: RTP Pin Control 7 Register              */
+    uint32  PC8;       /**< 0x0054: RTP Pin Control 8 Register              */
+} rtpBASE_t;
+
+
+/** @def rtpREG
+*   @brief RTP Register Frame Pointer
+*
+*   This pointer is used by the RTP driver to access the RTP module registers.
+*/
+#define rtpREG ((rtpBASE_t *)0xFFFFFA00U)
+
+/** @def rtpPORT
+*   @brief RTP Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of RTP
+*   (use the GIO drivers to access the port pins).
+*/
+#define rtpPORT ((gioPORT_t *)0xFFFFFA38U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_sci.h b/bsp/rm48x50/HALCoGen/include/reg_sci.h
new file mode 100644
index 0000000000000000000000000000000000000000..0f58a4961a2626693fda3f5ac275c528ed992a58
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_sci.h
@@ -0,0 +1,106 @@
+/** @file reg_sci.h
+*   @brief SCI Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the SCI driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_SCI_H__
+#define __REG_SCI_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Sci Register Frame Definition */
+/** @struct sciBase
+*   @brief SCI Base Register Definition
+*
+*   This structure is used to access the SCI module registers.
+*/
+/** @typedef sciBASE_t
+*   @brief SCI Register Frame Type Definition
+*
+*   This type is used to access the SCI Registers.
+*/
+typedef volatile struct sciBase
+{
+    uint32 GCR0;          /**< 0x0000 Global Control Register 0 */
+    uint32 GCR1;          /**< 0x0004 Global Control Register 1 */
+    uint32 GCR2;          /**< 0x0008 Global Control Register 2 */
+    uint32 SETINT;        /**< 0x000C Set Interrupt Enable Register */
+    uint32 CLRINT;        /**< 0x0010 Clear Interrupt Enable Register */
+    uint32 SETINTLVL;     /**< 0x0014 Set Interrupt Level Register */
+    uint32 CLRINTLVL;     /**< 0x0018 Set Interrupt Level Register */
+    uint32 FLR;           /**< 0x001C Interrupt Flag Register */
+    uint32 INTVECT0;      /**< 0x0020 Interrupt Vector Offset 0 */
+    uint32 INTVECT1;      /**< 0x0024 Interrupt Vector Offset 1 */
+    uint32 FORMAT;        /**< 0x0028 Format Control Register */
+    uint32 BRS;           /**< 0x002C Baud Rate Selection Register */
+    uint32 ED;            /**< 0x0030 Emulation Register */
+    uint32 RD;            /**< 0x0034 Receive Data Buffer */
+    uint32 TD;            /**< 0x0038 Transmit Data Buffer */
+    uint32 FUN;           /**< 0x003C Pin Function Register */
+    uint32 DIR;           /**< 0x0040 Pin Direction Register */
+    uint32 DIN;           /**< 0x0044 Pin Data In Register */
+    uint32 DOUT;          /**< 0x0048 Pin Data Out Register */
+    uint32 SET;           /**< 0x004C Pin Data Set Register */
+    uint32 CLR;           /**< 0x0050 Pin Data Clr Register */
+    uint32 ODR;           /**< 0x0054: Pin Open Drain Output Enable Register */
+    uint32 PD;            /**< 0x0058: Pin Pullup/Pulldown Disable Register */
+    uint32 PSL;           /**< 0x005C: Pin Pullup/Pulldown Selection Register */
+    uint32  rsdv1[12U];    /**< 0x060: Reserved                               */
+    uint32 IODFTCTRL;     /**< 0x0090: I/O Error Enable Register */
+} sciBASE_t;
+
+
+/** @def sciREG
+*   @brief  Register Frame Pointer
+*
+*   This pointer is used by the SCI driver to access the sci module registers.
+*/
+#define sciREG ((sciBASE_t *)0xFFF7E500U)
+
+
+/** @def sciPORT
+*   @brief SCI GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SCI
+*   (use the GIO drivers to access the port pins).
+*/
+#define sciPORT ((gioPORT_t *)0xFFF7E540U)
+
+
+/** @def scilinREG
+*   @brief SCILIN (LIN - Compatibility Mode)  Register Frame Pointer
+*
+*   This pointer is used by the SCI driver to access the sci module registers.
+*/
+#define scilinREG ((sciBASE_t *)0xFFF7E400U)
+
+
+/** @def scilinPORT
+*   @brief SCILIN (LIN - Compatibility Mode)  Register Frame Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of LIN
+*   (use the GIO drivers to access the port pins).
+*/
+#define scilinPORT ((gioPORT_t *)0xFFF7E440U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_spi.h b/bsp/rm48x50/HALCoGen/include/reg_spi.h
new file mode 100644
index 0000000000000000000000000000000000000000..07339e84cb4323a51eca50616b451b2f04718305
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_spi.h
@@ -0,0 +1,155 @@
+/** @file reg_spi.h
+*   @brief SPI Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the SPI driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_SPI_H__
+#define __REG_SPI_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Spi Register Frame Definition */
+/** @struct spiBase
+*   @brief SPI Register Definition
+*
+*   This structure is used to access the SPI module registers.
+*/
+/** @typedef spiBASE_t
+*   @brief SPI Register Frame Type Definition
+*
+*   This type is used to access the SPI Registers.
+*/
+typedef volatile struct spiBase
+{
+    uint32  GCR0;                 /**< 0x0000: Global Control 0 */
+    uint32  GCR1;                  /**< 0x0004: Global Control 1 */	
+    uint32  INT0;                  /**< 0x0008: Interrupt Register */	
+    uint32  LVL;                  /**< 0x000C: Interrupt Level */
+    uint32  FLG;                  /**< 0x0010: Interrupt flags */		
+    uint32  PCFUN;                /**< 0x0014: Function Pin Enable */
+    uint32  PCDIR;                /**< 0x0018: Pin Direction */
+    uint32  PCDIN;                /**< 0x001C: Pin Input Latch */
+    uint32  PCDOUT;               /**< 0x0020: Pin Output Latch */
+    uint32  PCSET;                /**< 0x0024: Output Pin Set */
+    uint32  PCCLR;                /**< 0x0028: Output Pin Clr */
+    uint32  PCPDR;                /**< 0x002C: Open Drain Output Enable */
+    uint32  PCDIS;                /**< 0x0030: Pullup/Pulldown Disable */
+    uint32  PCPSL;                /**< 0x0034: Pullup/Pulldown Selection */
+    uint32  DAT0;                 /**< 0x0038: Transmit Data */
+    uint32  DAT1;                 /**< 0x003C: Transmit Data with Format and Chip Select */
+    uint32  BUF;                  /**< 0x0040: Receive Buffer */
+    uint32  EMU;                  /**< 0x0044: Emulation Receive Buffer */
+    uint32  DELAY;                /**< 0x0048: Delays */
+    uint32  CSDEF;                /**< 0x004C: Default Chip Select */
+    uint32  FMT0;                 /**< 0x0050: Data Format 0 */
+    uint32  FMT1;                 /**< 0x0054: Data Format 1 */
+    uint32  FMT2;                 /**< 0x0058: Data Format 2 */
+    uint32  FMT3;                 /**< 0x005C: Data Format 3 */
+    uint32  INTVECT0;             /**< 0x0060: Interrupt Vector 0 */
+    uint32  INTVECT1;             /**< 0x0064: Interrupt Vector 1 */
+    uint32  SRSEL;                /**< 0x0068: Slew Rate Select */
+    uint32  RESERVED[50U];        /**< 0x006C to 0x0130: Reserved */	
+    uint32  IOLPKTSTCR;           /**< 0x0134: IO loopback */
+} spiBASE_t;
+
+/** @def spiREG1
+*   @brief SPI1 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG1 ((spiBASE_t *)0xFFF7F400U)
+
+
+/** @def spiPORT1
+*   @brief SPI1 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI1
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT1 ((gioPORT_t *)0xFFF7F418U)
+
+/** @def spiREG2
+*   @brief SPI2 Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG2 ((spiBASE_t *)0xFFF7F600U)
+
+
+/** @def spiPORT2
+*   @brief SPI2 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI2
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT2 ((gioPORT_t *)0xFFF7F618U)
+
+/** @def spiREG3
+*   @brief SPI3 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG3 ((spiBASE_t *)0xFFF7F800U)
+
+
+/** @def spiPORT3
+*   @brief SPI3 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI3
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT3 ((gioPORT_t *)0xFFF7F818U)
+
+/** @def spiREG4
+*   @brief SPI4 Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG4 ((spiBASE_t *)0xFFF7FA00U)
+
+
+/** @def spiPORT4
+*   @brief SPI4 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI4
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT4 ((gioPORT_t *)0xFFF7FA18U)
+
+/** @def spiREG5
+*   @brief SPI5 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG5 ((spiBASE_t *)0xFFF7FC00U)
+
+
+/** @def spiPORT5
+*   @brief SPI5 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI5
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT5 ((gioPORT_t *)0xFFF7FC18U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_stc.h b/bsp/rm48x50/HALCoGen/include/reg_stc.h
new file mode 100644
index 0000000000000000000000000000000000000000..2f441cc36dc110f4e706cbbf6a8a70c23001967d
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_stc.h
@@ -0,0 +1,60 @@
+/** @file reg_stc.h
+*   @brief STC Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_STC_H__
+#define __REG_STC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Stc Register Frame Definition */
+/** @struct stcBase
+*   @brief STC Base Register Definition
+*
+*   This structure is used to access the STC module registers.
+*/
+/** @typedef stcBASE_t
+*   @brief STC Register Frame Type Definition
+*
+*   This type is used to access the STC Registers.
+*/
+typedef volatile struct stcBase
+{
+    uint32 STCGCR0;		/**< 0x0000: STC Control Register 0	*/
+    uint32 STCGCR1;		/**< 0x0004: STC Control Register 1 */
+    uint32 STCTPR;		/**< 0x0008: STC Self-Test Run Timeout Counter Preload Register	*/
+    uint32 STCCADDR;		/**< 0x000C: STC Self-Test Current ROM Address Register */
+    uint32 STCCICR;		/**< 0x0010: STC Self-Test Current Interval Count Register */
+    uint32 STCGSTAT;		/**< 0x0014: STC Self-Test Global Status Register */
+	uint32 STCFSTAT;		/**< 0x0018: STC Self-Test Fail Status Register */
+    uint32 CPU1_CURMISR3;	/**< 0x001C: STC CPU1 Current MISR Register */
+    uint32 CPU1_CURMISR2;	/**< 0x0020: STC CPU1 Current MISR Register */
+    uint32 CPU1_CURMISR1;	/**< 0x0024: STC CPU1 Current MISR Register */
+    uint32 CPU1_CURMISR0;	/**< 0x0028: STC CPU1 Current MISR Register */
+    uint32 CPU2_CURMISR3;	/**< 0x002C: STC CPU1 Current MISR Register */
+    uint32 CPU2_CURMISR2;	/**< 0x0030: STC CPU1 Current MISR Register */
+    uint32 CPU2_CURMISR1;	/**< 0x0034: STC CPU1 Current MISR Register */
+    uint32 CPU2_CURMISR0;	/**< 0x0038: STC CPU1 Current MISR Register */
+    uint32 STCSCSCR;		/**< 0x003C: STC Signature Compare Self-Check Register */
+} stcBASE_t;
+
+#define stcREG   ((stcBASE_t *)0xFFFFE600U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_system.h b/bsp/rm48x50/HALCoGen/include/reg_system.h
new file mode 100644
index 0000000000000000000000000000000000000000..72093baf7b7ac8a5828c0c6e5d7593589c33ac53
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_system.h
@@ -0,0 +1,159 @@
+/** @file reg_system.h
+*   @brief System Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_SYSTEM_H__
+#define __REG_SYSTEM_H__
+
+#include "sys_common.h"
+#include "gio.h"
+
+
+/* System Register Frame 1 Definition */
+/** @struct systemBase1
+*   @brief System Register Frame 1 Definition
+*
+*   This type is used to access the System 1 Registers.
+*/
+/** @typedef systemBASE1_t
+*   @brief System Register Frame 1 Type Definition
+*
+*   This type is used to access the System 1 Registers.
+*/
+typedef volatile struct systemBase1
+{
+    uint32 SYSPC1;                 /* 0x0000 */
+    uint32 SYSPC2;                 /* 0x0004 */
+    uint32 SYSPC3;                 /* 0x0008 */
+    uint32 SYSPC4;                 /* 0x000C */
+    uint32 SYSPC5;                 /* 0x0010 */
+    uint32 SYSPC6;                 /* 0x0014 */
+    uint32 SYSPC7;                 /* 0x0018 */
+    uint32 SYSPC8;                 /* 0x001C */
+    uint32 SYSPC9;                 /* 0x0020 */
+    uint32 SSWPLL1;                /* 0x0024 */
+    uint32 SSWPLL2;                /* 0x0028 */
+    uint32 SSWPLL3;                /* 0x002C */
+    uint32 CSDIS;                  /* 0x0030 */
+    uint32 CSDISSET;               /* 0x0034 */
+    uint32 CSDISCLR;               /* 0x0038 */
+    uint32 CDDIS;                  /* 0x003C */
+    uint32 CDDISSET;               /* 0x0040 */
+    uint32 CDDISCLR;               /* 0x0044 */
+    uint32 GHVSRC;                 /* 0x0048 */
+    uint32 VCLKASRC;               /* 0x004C */
+    uint32 RCLKSRC;                /* 0x0050 */
+    uint32 CSVSTAT;                /* 0x0054 */
+    uint32 MSTGCR;                 /* 0x0058 */
+    uint32 MINITGCR;               /* 0x005C */
+    uint32 MSINENA;                /* 0x0060 */
+    uint32 MSTFAIL;                /* 0x0064 */
+    uint32 MSTCGSTAT;              /* 0x0068 */
+    uint32 MINISTAT;               /* 0x006C */
+    uint32 PLLCTL1;                /* 0x0070 */
+    uint32 PLLCTL2;                /* 0x0074 */
+    uint32 UERFLAG;                /* 0x0078 */
+    uint32 DIEIDL;                 /* 0x007C */
+    uint32 DIEIDH;                 /* 0x0080 */
+    uint32 VRCTL;                  /* 0x0084 */
+    uint32 LPOMONCTL;              /* 0x0088 */
+    uint32 CLKTEST;                /* 0x008C */
+    uint32 DFTCTRLREG1;            /* 0x0090 */
+    uint32 DFTCTRLREG2;            /* 0x0094 */
+    uint32   rsvd1;                /* 0x0098 */
+    uint32   rsvd2;                /* 0x009C */
+    uint32 GPREG1;                 /* 0x00A0 */
+    uint32 BTRMSEL;                /* 0x00A4 */
+    uint32 IMPFASTS;               /* 0x00A8 */
+    uint32 IMPFTADD;               /* 0x00AC */
+    uint32 SSISR1;                 /* 0x00B0 */
+    uint32 SSISR2;                 /* 0x00B4 */
+    uint32 SSISR3;                 /* 0x00B8 */
+    uint32 SSISR4;                 /* 0x00BC */
+    uint32 RAMGCR;                 /* 0x00C0 */
+    uint32 BMMCR1;                 /* 0x00C4 */
+    uint32 BMMCR2;                 /* 0x00C8 */
+    uint32 MMUGCR;                 /* 0x00CC */
+	uint32 CLKCNTL;                /* 0x00D0 */
+    uint32 ECPCNTL;                /* 0x00D4 */
+    uint32 DSPGCR;                 /* 0x00D8 */
+    uint32 DEVCR1;                 /* 0x00DC */
+    uint32 SYSECR;                 /* 0x00E0 */
+    uint32 SYSESR;                 /* 0x00E4 */
+    uint32 SYSTASR;                /* 0x00E8 */
+    uint32 GBLSTAT;                /* 0x00EC */
+    uint32 DEV;                    /* 0x00F0 */
+    uint32 SSIVEC;                 /* 0x00F4 */
+    uint32 SSIF;                   /* 0x00F8 */
+    uint32 SSIR1;                  /* 0x00FC */	
+} systemBASE1_t;
+
+
+/** @def systemREG1
+*   @brief System Register Frame 1 Pointer
+*
+*   This pointer is used by the system driver to access the system frame 1 registers.
+*/
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
+
+/** @def systemPORT
+*   @brief ECLK GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of System/Eclk
+*   (use the GIO drivers to access the port pins).
+*/
+#define systemPORT ((gioPORT_t *)0xFFFFFF04U)
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* System Register Frame 2 Definition */
+/** @struct systemBase2
+*   @brief System Register Frame 2 Definition
+*
+*   This type is used to access the System 2 Registers.
+*/
+/** @typedef systemBASE2_t
+*   @brief System Register Frame 2 Type Definition
+*
+*   This type is used to access the System 2 Registers.
+*/
+typedef volatile struct systemBase2
+{
+    uint32 PLLCTL3;        /* 0x0000 */
+    uint32   rsvd1;        /* 0x0004 */
+    uint32 STCCLKDIV;      /* 0x0008 */
+    uint32   rsvd2[6U];     /* 0x000C */
+    uint32 ECPCNTRL0;      /* 0x0024 */
+    uint32   rsvd3[5U];     /* 0x0028 */
+    uint32 CLK2CNTL;       /* 0x003C */	
+    uint32 VCLKACON1;      /* 0x0040 */
+    uint32  rsvd4[11U];     /* 0x0044 */
+    uint32  CLKSLIP;       /* 0x0070 */
+    uint32  rsvd5[30U];   	 /* 0x0074 */
+    uint32  EFC_CTLEN;     /* 0x00EC */
+    uint32  DIEIDL_REG0;   /* 0x00F0 */
+    uint32  DIEIDH_REG1;   /* 0x00F4 */
+    uint32  DIEIDL_REG2;   /* 0x00F8 */
+    uint32  DIEIDH_REG3;   /* 0x00FC */
+} systemBASE2_t;
+
+/** @def systemREG2
+*   @brief System Register Frame 2 Pointer
+*
+*   This pointer is used by the system driver to access the system frame 2 registers.
+*/
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_tcram.h b/bsp/rm48x50/HALCoGen/include/reg_tcram.h
new file mode 100644
index 0000000000000000000000000000000000000000..6838cd06e35e27392e31d5f597b0be0e018b9db1
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_tcram.h
@@ -0,0 +1,52 @@
+/** @file reg_tcram.h
+*   @brief TCRAM Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_TCRAM_H__
+#define __REG_TCRAM_H__
+
+#include "sys_common.h"
+
+/* Tcram Register Frame Definition */
+/** @struct tcramBase
+*   @brief TCRAM Wrapper Register Frame Definition
+*
+*   This type is used to access the TCRAM Wrapper Registers.
+*/
+/** @typedef tcramBASE_t
+*   @brief TCRAM Wrapper Register Frame Type Definition
+*
+*   This type is used to access the TCRAM Wrapper Registers.
+*/
+
+typedef volatile struct tcramBase
+{
+    uint32 RAMCTRL;		    /* 0x0000 */
+    uint32 RAMTHRESHOLD;      /* 0x0004 */
+    uint32 RAMOCCUR;			/* 0x0008 */
+    uint32 RAMINTCTRL;		/* 0x000C */
+    uint32 RAMERRSTATUS;		/* 0x0010 */
+    uint32 RAMSERRADDR;		/* 0x0014 */
+    uint32   rsvd1;			/* 0x0018 */
+    uint32 RAMUERRADDR;		/* 0x001C */
+    uint32   rsvd2[4U];		/* 0x0020 */
+    uint32 RAMTEST;			/* 0x0030 */
+    uint32   rsvd3;			/* 0x0034 */
+    uint32 RAMADDRDECVECT;	/* 0x0038 */
+    uint32 RAMPERADDR;        /* 0x003C */
+} tcramBASE_t;
+
+#define tcram1REG ((tcramBASE_t *)(0xFFFFF800U))
+#define tcram2REG ((tcramBASE_t *)(0xFFFFF900U))
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/reg_vim.h b/bsp/rm48x50/HALCoGen/include/reg_vim.h
new file mode 100644
index 0000000000000000000000000000000000000000..816e5fa50f900664ed992350629ae7ed65a3a564
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/reg_vim.h
@@ -0,0 +1,77 @@
+/** @file reg_vim.h
+*   @brief VIM Register Layer Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __REG_VIM_H__
+#define __REG_VIM_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Vim Register Frame Definition */
+/** @struct vimBase
+*   @brief Vim Register Frame Definition
+*
+*   This type is used to access the Vim Registers.
+*/
+/** @typedef vimBASE_t
+*   @brief VIM Register Frame Type Definition
+*
+*   This type is used to access the VIM Registers.
+*/
+typedef volatile struct vimBase
+{
+    uint32      IRQINDEX;         /* 0x0000        */
+    uint32      FIQINDEX;         /* 0x0004        */	
+    uint32        rsvd1;          /* 0x0008        */
+    uint32        rsvd2;          /* 0x000C        */
+    uint32      FIRQPR0;          /* 0x0010        */
+    uint32      FIRQPR1;          /* 0x0014        */
+    uint32      FIRQPR2;          /* 0x0018        */
+    uint32      FIRQPR3;          /* 0x001C        */
+    uint32      INTREQ0;          /* 0x0020        */
+    uint32      INTREQ1;          /* 0x0024        */
+    uint32      INTREQ2;          /* 0x0028        */
+    uint32      INTREQ3;          /* 0x002C        */
+    uint32      REQMASKSET0;      /* 0x0030        */
+    uint32      REQMASKSET1;      /* 0x0034        */
+    uint32      REQMASKSET2;      /* 0x0038        */
+    uint32      REQMASKSET3;      /* 0x003C        */
+    uint32      REQMASKCLR0;      /* 0x0040        */
+    uint32      REQMASKCLR1;      /* 0x0044        */
+    uint32      REQMASKCLR2;      /* 0x0048        */
+    uint32      REQMASKCLR3;      /* 0x004C        */
+    uint32      WAKEMASKSET0;     /* 0x0050        */
+    uint32      WAKEMASKSET1;     /* 0x0054        */
+    uint32      WAKEMASKSET2;     /* 0x0058        */
+    uint32      WAKEMASKSET3;     /* 0x005C        */
+    uint32      WAKEMASKCLR0;     /* 0x0060        */
+    uint32      WAKEMASKCLR1;     /* 0x0064        */
+    uint32      WAKEMASKCLR2;     /* 0x0068        */
+    uint32      WAKEMASKCLR3;     /* 0x006C        */
+    uint32      IRQVECREG;        /* 0x0070        */
+    uint32      FIQVECREG;        /* 0x0074        */
+    uint32      CAPEVT;           /* 0x0078        */	
+    uint32        rsvd3;          /* 0x007C        */
+    uint32      CHANCTRL[24U];    /* 0x0080-0x017C */
+} vimBASE_t;
+
+#define vimREG ((vimBASE_t *)0xFFFFFE00U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/rti.h b/bsp/rm48x50/HALCoGen/include/rti.h
new file mode 100644
index 0000000000000000000000000000000000000000..57a4bcbcf81deee6e28ac9213acfdd0e0c705979
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/rti.h
@@ -0,0 +1,301 @@
+/** @file rti.h
+*   @brief RTI Driver Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the RTI driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#ifndef __RTI_H__
+#define __RTI_H__
+
+#include "reg_rti.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* RTI General Definitions */
+
+/** @def rtiCOUNTER_BLOCK0
+*   @brief Alias name for RTI counter block 0
+*
+*   This is an alias name for the RTI counter block 0.
+*
+*   @note This value should be used for API argument @a counter
+*/
+#define rtiCOUNTER_BLOCK0 0U
+
+/** @def rtiCOUNTER_BLOCK1
+*   @brief Alias name for RTI counter block 1
+*
+*   This is an alias name for the RTI counter block 1.
+*
+*   @note This value should be used for API argument @a counter
+*/
+#define rtiCOUNTER_BLOCK1 1U
+
+/** @def rtiCOMPARE0
+*   @brief Alias name for RTI compare 0
+*
+*   This is an alias name for the RTI compare 0.
+*
+*   @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE0 0U
+
+/** @def rtiCOMPARE1
+*   @brief Alias name for RTI compare 1
+*
+*   This is an alias name for the RTI compare 1.
+*
+*   @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE1 1U
+
+/** @def rtiCOMPARE2
+*   @brief Alias name for RTI compare 2
+*
+*   This is an alias name for the RTI compare 2.
+*
+*   @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE2 2U
+
+/** @def rtiCOMPARE3
+*   @brief Alias name for RTI compare 3
+*
+*   This is an alias name for the RTI compare 3.
+*
+*   @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE3 3U
+
+/** @def rtiNOTIFICATION_COMPARE0
+*   @brief Alias name for RTI compare 0 notification
+*
+*   This is an alias name for the RTI compare 0 notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE0 1U
+
+/** @def rtiNOTIFICATION_COMPARE1
+*   @brief Alias name for RTI compare 1 notification
+*
+*   This is an alias name for the RTI compare 1 notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE1 2U
+
+/** @def rtiNOTIFICATION_COMPARE2
+*   @brief Alias name for RTI compare 2 notification
+*
+*   This is an alias name for the RTI compare 2 notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE2 4U
+
+/** @def rtiNOTIFICATION_COMPARE3
+*   @brief Alias name for RTI compare 3 notification
+*
+*   This is an alias name for the RTI compare 3 notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE3 8U
+
+/** @def rtiNOTIFICATION_TIMEBASE
+*   @brief Alias name for RTI timebase notification
+*
+*   This is an alias name for the RTI timebase notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_TIMEBASE 0x10000U
+
+/** @def rtiNOTIFICATION_COUNTER0
+*   @brief Alias name for RTI counter block 0 overflow notification
+*
+*   This is an alias name for the RTI counter block 0 overflow notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COUNTER0 0x20000U
+
+/** @def rtiNOTIFICATION_COUNTER1
+*   @brief Alias name for RTI counter block 1 overflow notification
+*
+*   This is an alias name for the RTI counter block 1 overflow notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COUNTER1 0x40000U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @enum dwdViolationTag
+*   @brief DWD Violations
+*/
+typedef enum dwdViolationTag
+{
+	NoTime_Violation = 0U,
+	Time_Window_Violation = 1U,
+	EndTime_Window_Violation = 2U,
+	StartTime_Window_Violation = 3U,
+	Key_Seq_Violation = 4U
+}dwdViolation_t;
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @enum dwdResetStatusTag
+*   @brief DWD Reset status
+*/
+typedef enum dwdResetStatusTag
+{
+	No_Reset_Generated = 0U,
+	Reset_Generated    = 1U
+}dwdResetStatus_t;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/** @enum dwwdReactionTag
+*   @brief DWWD Reaction on vioaltion
+*/
+typedef enum dwwdReactionTag
+{
+	Generate_Reset = 0x00000005U,
+	Generate_NMI   = 0x0000000AU
+}dwwdReaction_t;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @enum dwwdWindowSizeTag
+*   @brief DWWD Window size
+*/
+typedef enum dwwdWindowSizeTag
+{
+	Size_100_Percent   = 0x00000005U,
+	Size_50_Percent    = 0x00000050U,
+	Size_25_Percent    = 0x00000500U,
+	Size_12_5_Percent  = 0x00005000U,
+	Size_6_25_Percent  = 0x00050000U,
+	Size_3_125_Percent = 0x00500000U
+}dwwdWindowSize_t;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+/* Configuration registers */
+typedef struct rti_config_reg
+{
+    uint32 CONFIG_GCTRL;
+    uint32 CONFIG_TBCTRL;
+    uint32 CONFIG_CAPCTRL;
+    uint32 CONFIG_COMPCTRL;
+    uint32 CONFIG_UDCP0;
+    uint32 CONFIG_UDCP1;
+    uint32 CONFIG_UDCP2;
+    uint32 CONFIG_UDCP3;
+    uint32 CONFIG_TBLCOMP;
+    uint32 CONFIG_TBHCOMP;
+    uint32 CONFIG_SETINT;
+    uint32 CONFIG_DWDCTRL;
+    uint32 CONFIG_DWDPRLD;
+    uint32 CONFIG_WWDRXNCTRL;
+    uint32 CONFIG_WWDSIZECTRL;
+} rti_config_reg_t;
+
+
+/* Configuration registers initial value */
+#define RTI_GCTRL_CONFIGVALUE	(1U << 16U) | 0x00000000U
+#define RTI_TBCTRL_CONFIGVALUE  0x00000000U
+#define RTI_CAPCTRL_CONFIGVALUE  0U | 0U
+#define RTI_COMPCTRL_CONFIGVALUE  0x00001000U | 0x00000100U | 0x00000000U | 0x00000000U
+#define RTI_UDCP0_CONFIGVALUE 10000U
+#define RTI_UDCP1_CONFIGVALUE 50000U
+#define RTI_UDCP2_CONFIGVALUE 80000U
+#define RTI_UDCP3_CONFIGVALUE 100000U
+#define RTI_TBLCOMP_CONFIGVALUE 0U
+#define RTI_TBHCOMP_CONFIGVALUE 0U
+#define RTI_SETINT_CONFIGVALUE 0U
+#define RTI_DWDCTRL_CONFIGVALUE 0x5312ACEDU
+#define RTI_DWDPRLD_CONFIGVALUE 0xFFFU
+#define RTI_WWDRXNCTRL_CONFIGVALUE 0x5U
+#define RTI_WWDSIZECTRL_CONFIGVALUE 0x5U
+
+
+/** 
+ *  @defgroup RTI RTI
+ *  @brief Real Time Interrupt Module.
+ *  
+ *  The real-time interrupt (RTI) module provides timer functionality for operating systems and for
+ *  benchmarking code. The RTI module can incorporate several counters that define the timebases needed
+ *  for scheduling in the operating system.
+ *
+ *	Related Files
+ *   - reg_rti.h
+ *   - rti.h
+ *   - rti.c
+ *  @addtogroup RTI
+ *  @{
+ */
+ 
+/* RTI Interface Functions */
+
+void rtiInit(void);
+void rtiStartCounter(uint32 counter);
+void rtiStopCounter(uint32 counter);
+uint32 rtiResetCounter(uint32 counter);
+void rtiSetPeriod(uint32 compare, uint32 period);
+uint32 rtiGetPeriod(uint32 compare);
+uint32 rtiGetCurrentTick(uint32 compare);
+void rtiEnableNotification(uint32 notification);
+void rtiDisableNotification(uint32 notification);
+void dwdInit(uint16 dwdPreload);
+void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size);
+uint32 dwwdGetCurrentDownCounter(void);
+void dwdCounterEnable(void);
+void dwdSetPreload(uint16 dwdPreload);
+void dwdReset(void);
+void dwdGenerateSysReset(void);
+boolean IsdwdKeySequenceCorrect(void);
+dwdResetStatus_t dwdGetStatus(void);
+dwdViolation_t dwdGetViolationStatus(void);
+void dwdClearFlag(void);
+void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void rtiNotification(uint32 notification)
+*   @brief Notification of RTI module
+*   @param[in] notification Select notification of RTI module:
+*              - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification
+*              - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification
+*              - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification
+*              - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification
+*              - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification
+*              - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification
+*              - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification
+*
+*   @note This function has to be provide by the user.
+*/
+void rtiNotification(uint32 notification);
+
+/**@}*/
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/rtp.h b/bsp/rm48x50/HALCoGen/include/rtp.h
new file mode 100644
index 0000000000000000000000000000000000000000..e6981324ae7d498afa275e597607fd23f5516997
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/rtp.h
@@ -0,0 +1,35 @@
+/** @file rtp.h
+*   @brief RTP Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#ifndef __RTP_H__
+#define __RTP_H__
+
+#include "reg_rtp.h"
+
+/** 
+ *  @defgroup RTP RTP
+ *  @brief RAM Trace Port.
+ *  
+ *  RAM Trace Port (RTP) module provides the features to datalog the RAM contents of the devices 
+ *  or accesses to peripherals without program intrusion. It can trace all data write or read accesses to internal RAM.
+ *
+ *	Related Files
+ *   - reg_rtp.h
+ *   - rtp.h
+ *   - rtp.c
+ *  @addtogroup RTP
+ *  @{
+ */
+ 
+/* RTP Interface Functions */
+void rtpInit(void);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/sci.h b/bsp/rm48x50/HALCoGen/include/sci.h
new file mode 100644
index 0000000000000000000000000000000000000000..12e69fc87e9b9405c0e3526cd0fdc0fa09c9b6a0
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sci.h
@@ -0,0 +1,102 @@
+/** @file sci.h
+*   @brief SCI Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#ifndef __SCI_H__
+#define __SCI_H__
+
+#include "reg_sci.h"
+
+
+/** @enum sciIntFlags
+*   @brief Interrupt Flag Definitions
+*
+*   Used with sciEnableNotification, sciDisableNotification
+*/
+enum sciIntFlags
+{
+    SCI_FE_INT    = 0x04000000U,  /* framing error */
+    SCI_OE_INT    = 0x02000000U,  /* overrun error */
+    SCI_PE_INT    = 0x01000000U,  /* parity error */
+    SCI_RX_INT    = 0x00000200U,  /* receive buffer ready */
+    SCI_TX_INT    = 0x00000100U,  /* transmit buffer ready */
+    SCI_WAKE_INT  = 0x00000002U,  /* wakeup */
+    SCI_BREAK_INT = 0x00000001U   /* break detect */
+};
+
+/** @def SCI_IDLE
+*   @brief Alias name for the SCI IDLE Flag
+*
+*   This is an alias name for the SCI IDLE Flag.
+*
+*/
+#define SCI_IDLE 0x00000004U
+
+/** @struct sciBase
+*   @brief SCI Register Definition
+*
+*   This structure is used to access the SCI module registers.
+*/
+/** @typedef sciBASE_t
+*   @brief SCI Register Frame Type Definition
+*
+*   This type is used to access the SCI Registers.
+*/
+
+enum sciPinSelect
+{
+    PIN_SCI_TX = 0U,
+    PIN_SCI_RX = 1U
+};
+
+/** 
+ *  @defgroup SCI SCI
+ *  @brief Serial Communication Interface Module.
+ *  
+ *  The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
+ *  to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-line.
+ *
+ *	Related Files
+ *   - reg_sci.h
+ *   - sci.h
+ *   - sci.c
+ *  @addtogroup SCI
+ *  @{
+ */
+ 
+/* SCI Interface Functions */
+void sciInit(void);
+void sciSetFunctional(sciBASE_t *sci, uint32 port);
+void sciSetBaudrate(sciBASE_t *sci, uint32 baud);
+uint32  sciIsTxReady(sciBASE_t *sci);
+void sciSendByte(sciBASE_t *sci, uint8 byte);
+void sciSend(sciBASE_t *sci, uint32 length, uint8 * data);
+uint32  sciIsRxReady(sciBASE_t *sci);
+uint32  sciIsIdleDetected(sciBASE_t *sci);
+uint32  sciRxError(sciBASE_t *sci);
+uint32  sciReceiveByte(sciBASE_t *sci);
+void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data);
+void sciEnableNotification(sciBASE_t *sci, uint32 flags);
+void sciDisableNotification(sciBASE_t *sci, uint32 flags);
+void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype);
+void sciDisableLoopback(sciBASE_t *sci);
+
+/** @fn void sciNotification(sciBASE_t *sci, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] sci   - sci module base address
+*   @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void sciNotification(sciBASE_t *sci, uint32 flags);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/spi.h b/bsp/rm48x50/HALCoGen/include/spi.h
new file mode 100644
index 0000000000000000000000000000000000000000..f11ef348795f1f55d5ebfaad7fc775e41eda757f
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/spi.h
@@ -0,0 +1,154 @@
+/** @file spi.h
+*   @brief SPI Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   (c) Texas Instruments 2009-2013, All rights reserved.
+*/
+
+
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#include "reg_spi.h"
+
+/** @enum chipSelect
+*   @brief Transfer Group Chip Select
+*/
+enum spiChipSelect
+{
+    SPI_CS_NONE = 0xFFU,
+    SPI_CS_0    = 0xFEU,
+    SPI_CS_1    = 0xFDU,
+    SPI_CS_2    = 0xFBU,
+    SPI_CS_3    = 0xF7U,
+    SPI_CS_4    = 0xEFU,
+    SPI_CS_5    = 0xDFU,
+    SPI_CS_6    = 0xBFU,
+    SPI_CS_7    = 0x7FU
+};
+
+/** @enum spiPinSelect
+*   @brief spi Pin Select
+*/
+enum spiPinSelect
+{
+    SPI_PIN_CS0    = 0U,
+    SPI_PIN_CS1    = 1U,
+    SPI_PIN_CS2    = 2U,
+    SPI_PIN_CS3    = 3U,
+    SPI_PIN_CS4    = 4U,
+    SPI_PIN_CS5    = 5U,
+    SPI_PIN_CS6    = 6U,
+    SPI_PIN_CS7    = 7U,
+    SPI_PIN_ENA    = 8U,
+    SPI_PIN_CLK    = 9U,
+    SPI_PIN_SIMO   = 10U,
+    SPI_PIN_SOMI   = 11U,
+    SPI_PIN_SIMO_1 = 17U,
+    SPI_PIN_SIMO_2 = 18U,
+    SPI_PIN_SIMO_3 = 19U,
+    SPI_PIN_SIMO_4 = 20U,
+    SPI_PIN_SIMO_5 = 21U,
+    SPI_PIN_SIMO_6 = 22U,
+    SPI_PIN_SIMO_7 = 23U,
+    SPI_PIN_SOMI_1 = 25U,
+    SPI_PIN_SOMI_2 = 26U,
+    SPI_PIN_SOMI_3 = 27U,
+    SPI_PIN_SOMI_4 = 28U,
+    SPI_PIN_SOMI_5 = 29U,
+    SPI_PIN_SOMI_6 = 30U,
+    SPI_PIN_SOMI_7 = 31U
+};
+
+/** @enum dataformat
+*   @brief SPI dataformat register select
+*/
+typedef enum dataformat
+{
+    SPI_FMT_0 = 0U,
+    SPI_FMT_1 = 1U,
+    SPI_FMT_2 = 2U,
+    SPI_FMT_3 = 3U
+}SPIDATAFMT_t;
+
+/** @struct spiDAT1RegConfig
+*   @brief SPI data register configuration
+*/
+typedef struct spiDAT1RegConfig
+{
+    boolean CS_HOLD;
+    boolean WDEL;
+    SPIDATAFMT_t DFSEL;
+    uint8 CSNR;
+}spiDAT1_t;
+
+/** @enum SpiTxRxDataStatus
+*   @brief SPI Data Status
+*/
+typedef enum SpiTxRxDataStatus
+{
+    SPI_READY = 0U,
+	SPI_PENDING = 1U,
+    SPI_COMPLETED = 2U
+}SpiDataStatus_t;
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** 
+ *  @defgroup SPI SPI
+ *  @brief Serial Peripheral Interface Module.
+ *  
+ *  SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
+ *  programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
+ *
+ *	Related Files
+ *   - reg_spi.h
+ *   - spi.h
+ *   - spi.c
+ *  @addtogroup SPI
+ *  @{
+ */
+ 
+/* SPI Interface Functions */
+void spiInit(void);
+void spiSetFunctional(spiBASE_t *spi, uint32 port);
+void spiEnableNotification(spiBASE_t *spi, uint32 flags);
+void spiDisableNotification(spiBASE_t *spi, uint32 flags);
+uint32 spiTransmitData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff);
+void spiSendData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff);
+uint32 spiReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * destbuff);
+void spiGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * destbuff);
+uint32 spiTransmitAndReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff, uint16 * destbuff);
+void spiSendAndGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff, uint16 * destbuff);
+void spiEnableLoopback(spiBASE_t *spi, loopBackType_t Loopbacktype);
+void spiDisableLoopback(spiBASE_t *spi);
+SpiDataStatus_t SpiTxStatus(spiBASE_t *spi);
+SpiDataStatus_t SpiRxStatus(spiBASE_t *spi);
+
+/** @fn void spiNotification(spiBASE_t *spi, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] spi   - Spi module base address
+*   @param[in] flags - Copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void spiNotification(spiBASE_t *spi, uint32 flags);
+
+/** @fn void spiEndNotification(spiBASE_t *spi)
+*   @brief Interrupt callback for End of TX or RX data length.
+*   @param[in] spi   - Spi module base address
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt at the End of TX or RX data length.
+*/
+void spiEndNotification(spiBASE_t *spi);
+
+/**@}*/
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/std_nhet.h b/bsp/rm48x50/HALCoGen/include/std_nhet.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe496398ee24cbf1681fe4b3079971ec23353aa6
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/std_nhet.h
@@ -0,0 +1,2427 @@
+/** @file std_nhet.h
+*   @brief NHET Instruction Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   (c) Texas Instruments 2009-2013, All rights reserved.
+*/
+
+#ifndef __STD_NHET_H__
+#define __STD_NHET_H__
+
+#include "sys_common.h"
+
+#if defined(_TMS470_BIG) || defined(__big_endian__)
+
+#ifndef HET_v2
+#   define HET_v2 0
+#endif
+
+#ifndef HETBYTE
+#   define HETBYTE uint8
+#endif
+
+typedef struct memory_format
+{
+  uint32 program_word  ;
+  uint32 control_word  ;
+  uint32 data_word     ;
+  uint32 reserved_word ;
+} HET_MEMORY  ;
+ 
+
+/*---------------------------------------------*/
+/* ACMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct acmp_format
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 9 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 coutprv              : 1 ;
+  uint32                      : 2 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32 ext_reg              : 1 ;
+  uint32                      : 2 ; 
+  uint32 pin_action           : 1 ;
+  uint32                      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  uint32 data                 : 25 ;
+  uint32                      : 7  ;
+ 
+} ACMP_FIELDS;
+ 
+typedef union
+{
+  ACMP_FIELDS  acmp   ;
+  HET_MEMORY   memory ;
+} ACMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct ecmp_format   
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;          
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 hr_lr                : 1 ;
+  uint32 angle_compare        : 1 ;
+  uint32                      : 7 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 sub_opcode           : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+
+} ECMP_FIELDS;
+
+typedef union 
+{
+  ECMP_FIELDS  ecmp   ;
+  HET_MEMORY   memory ;
+} ECMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct scmp_format     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;          
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32                      : 2 ;
+  uint32                      : 2 ;
+  uint32                      : 5 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 coutprv              : 1 ;
+  uint32                      : 2 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32                      : 2 ;
+  uint32 restart_en           : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} SCMP_FIELDS ;
+
+typedef union 
+{
+  SCMP_FIELDS  scmp   ;
+  HET_MEMORY   memory ;
+} SCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MCMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct mcmp_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 hr_lr                : 1 ;
+  uint32 angle_compare        : 1 ;
+  uint32                      : 1 ;
+  uint32 save_subtract        : 1 ;
+  uint32                      : 5 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 sub_opcode           : 1 ; 
+  uint32 order                : 1 ; 
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} MCMP_FIELDS ; 
+
+typedef union 
+{
+  MCMP_FIELDS  mcmp   ;
+  HET_MEMORY   memory ;
+} MCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV64 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct mov64_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+
+} MOV64_FIELDS ; 
+
+typedef union 
+{
+  MOV64_FIELDS  mov64  ;
+  HET_MEMORY    memory ;
+} MOV64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DADM64 INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct dadm64_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} DADM64_FIELDS ; 
+
+typedef union 
+{
+  DADM64_FIELDS  dadm64 ;
+  HET_MEMORY     memory ;
+} DADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* RADM64 INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct RADM64_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} RADM64_FIELDS ; 
+
+
+typedef union 
+{
+  RADM64_FIELDS  radm64 ;
+  HET_MEMORY     memory ;
+} RADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV32 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct MOV32_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 z_flag               : 1 ;
+  uint32                      : 15 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode           : 1 ;   
+  uint32 move_type            : 2 ;     
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} MOV32_FIELDS ; 
+
+
+typedef union 
+{
+  MOV32_FIELDS  mov32  ;
+  HET_MEMORY    memory ;
+} MOV32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADM32 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct ADM32_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 19 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode           : 1 ;
+  uint32 move_type            : 2 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} ADM32_FIELDS ; 
+
+
+typedef union 
+{
+  ADM32_FIELDS  adm32  ;
+  HET_MEMORY    memory ;
+} ADM32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADCNST INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct ADCNST_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1 ;  /* pk */
+  uint32                      : 1 ;
+  uint32 constant             : 25 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} ADCNST_FIELDS ;
+
+
+typedef union 
+{
+  ADCNST_FIELDS  adcnst ;
+  HET_MEMORY     memory ;
+} ADCNST_INSTRUCTION;
+
+
+/*----------------------------------------------*/
+/* ADD INSTRUCTION				  	*/
+/*----------------------------------------------*/
+
+typedef struct ADD_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} ADD_FIELDS ;
+
+
+typedef union 
+{
+  ADD_FIELDS  add ;
+  HET_MEMORY  memory ;
+} ADD_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* ADC INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct ADC_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} ADC_FIELDS ;
+
+
+typedef union 
+{
+  ADC_FIELDS  adc ;
+  HET_MEMORY  memory ;
+} ADC_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* SUB INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct SUB_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} SUB_FIELDS ;
+
+
+typedef union 
+{
+  SUB_FIELDS  sub ;
+  HET_MEMORY  memory ;
+} SUB_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* SBB INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct SBB_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} SBB_FIELDS ;
+
+
+typedef union 
+{
+  SBB_FIELDS  sbb ;
+  HET_MEMORY  memory ;
+} SBB_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* AND INSTRUCTION				      */
+/*----------------------------------------------*/
+
+typedef struct AND_format
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} AND_FIELDS ;
+
+
+typedef union 
+{
+  AND_FIELDS  and ;
+  HET_MEMORY  memory ;
+} AND_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* OR INSTRUCTION					      */
+/*----------------------------------------------*/
+
+
+typedef struct OR_format
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} OR_FIELDS ;
+
+
+typedef union 
+{
+  OR_FIELDS  or ;
+  HET_MEMORY  memory ;
+} OR_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* XOR INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct XOR_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} XOR_FIELDS ;
+
+
+typedef union 
+{
+  XOR_FIELDS  xor ;
+  HET_MEMORY  memory ;
+} XOR_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* CNT INSTRUCTION                             */
+/*---------------------------------------------*/
+typedef struct CNT_format                     
+{
+  uint32                      : 9 ;        
+  uint32 brk                  : 1 ;          
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 angle_cnt            : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32                      : 4 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 1 ;
+  uint32 max                  : 25 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} CNT_FIELDS ; 
+
+typedef union 
+{
+  CNT_FIELDS   cnt    ; 
+  HET_MEMORY   memory ;
+} CNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* APCNT INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct apcnt_format
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 interrupt_enable     : 1 ;
+  uint32 edge_select          : 2 ;
+  uint32                      : 6 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32 count                : 25 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+ 
+} APCNT_FIELDS ;
+ 
+typedef union
+{
+  APCNT_FIELDS  apcnt   ;
+  HET_MEMORY   memory ;
+} APCNT_INSTRUCTION;
+ 
+ 
+
+/*---------------------------------------------*/
+/* PCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct pcnt_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;          
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 interrupt_enable     : 1 ;
+  uint32 period_pulse_select  : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32 count                : 25 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+
+} PCNT_FIELDS ;      
+
+typedef union 
+{
+  PCNT_FIELDS  pcnt   ; 
+  HET_MEMORY   memory ;
+} PCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct scnt_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 count_mode           : 2 ;
+  uint32 step_width           : 2 ;
+  uint32                      : 4 ;
+
+  uint32                      : 5 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 1 ;
+  uint32 gap_start            : 25 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} SCNT_FIELDS ;      
+
+typedef union 
+{
+  SCNT_FIELDS  scnt   ; 
+  HET_MEMORY   memory ;
+} SCNT_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* ACNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct acnt_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 edge_select          : 1 ;
+  uint32                      : 7 ;
+  uint32 interrupt_enable     : 1 ; 
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32 gap_end              : 25 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} ACNT_FIELDS ;      
+
+typedef union 
+{
+  ACNT_FIELDS  acnt   ; 
+  HET_MEMORY   memory ;
+} ACNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct ecnt_format
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 6 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 count_cond           : 3 ;
+  uint32                      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+ 
+} ECNT_FIELDS ;
+ 
+typedef union
+{
+  ECNT_FIELDS  ecnt   ;
+  HET_MEMORY   memory ;
+} ECNT_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* RCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct rcnt_format
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 5 ;
+  uint32 count_mode1          : 1 ;
+ 
+  uint32                      : 3 ;
+  uint32                      : 2 ;
+  uint32 control              : 1 ;
+  uint32                      : 1 ;
+  uint32 divisor              : 25 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+ 
+} RCNT_FIELDS ;
+ 
+typedef union
+{
+  RCNT_FIELDS  rcnt   ;
+  HET_MEMORY   memory ;
+} RCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJNZ INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct djnz_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 6 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 4 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 10 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} DJNZ_FIELDS ;      
+
+typedef union 
+{
+  DJNZ_FIELDS  djnz   ; 
+  HET_MEMORY   memory ;
+} DJNZ_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJZ INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct djz_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 6 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 4 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 10 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} DJZ_FIELDS ;      
+
+typedef union 
+{
+  DJZ_FIELDS  djz   ; 
+  HET_MEMORY   memory ;
+} DJZ_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* PWCNT INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct pwcnt_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 hr_lr                : 1 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 6 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 3 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} PWCNT_FIELDS ;      
+
+typedef union 
+{
+  PWCNT_FIELDS  pwcnt ;
+  HET_MEMORY   memory ;
+} PWCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* WCAP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct wcap_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 hr_lr                : 1 ;
+  uint32                      : 8 ;
+  
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 capture_condition    : 2 ;
+  uint32                      : 2 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+
+} WCAP_FIELDS ;      
+
+typedef union 
+{
+  WCAP_FIELDS  wcap   ; 
+  HET_MEMORY   memory ;
+} WCAP_INSTRUCTION;
+ 
+/*----------------------------------------------*/
+/* WCAPE INSTRUCTION                            */
+/*----------------------------------------------*/
+typedef struct wcape_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 9 ;
+  
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 capture_condition    : 2 ;
+  uint32                      : 2 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 ts_data              : 25 ;
+  uint32 ec_data              : 7 ;
+
+} WCAPE_FIELDS ;      
+
+typedef union 
+{
+  WCAPE_FIELDS  wcape   ; 
+  HET_MEMORY   memory ;
+} WCAPE_INSTRUCTION;
+ 
+
+/*---------------------------------------------*/
+/* BR   INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct br_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 9 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+
+#if HET_v2
+  uint32 branch_condition     : 5 ;
+#else 
+  uint32 branch_condition     : 3 ;
+  uint32                      : 1 ;
+  uint32                      : 1 ;
+#endif 
+
+  uint32                      : 2 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} BR_FIELDS ;      
+
+typedef union 
+{
+  BR_FIELDS  br     ; 
+  HET_MEMORY memory ;
+} BR_INSTRUCTION;
+
+ 
+/*---------------------------------------------*/
+/* SHFT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct shft_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 5 ;
+  uint32 shift_mode           : 4 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 shift_condition      : 2 ;
+  uint32                      : 2 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} SHFT_FIELDS ;      
+
+typedef union 
+{
+  SHFT_FIELDS  shft   ; 
+  HET_MEMORY   memory ;
+} SHFT_INSTRUCTION;
+
+/* ---------------------------------------------------------------------------------------------------- */
+
+#elif defined(_TMS470_LITTLE) || defined(__little_endian__)
+
+#ifndef HETBYTE
+#   define HETBYTE uint8
+#endif
+
+typedef struct memory_format
+{
+  uint32 program_word  ;
+  uint32 control_word  ;
+  uint32 data_word     ;
+  uint32 reserved_word ;
+} HET_MEMORY  ;
+ 
+/*---------------------------------------------*/
+/* ACMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct acmp_format
+{
+  uint32                      : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32                      : 3 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ; 
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 2 ;
+  uint32 coutprv              : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+
+  uint32                      : 7  ;
+  uint32 data                 : 25 ;
+ 
+} ACMP_FIELDS;
+ 
+typedef union
+{
+  ACMP_FIELDS  acmp   ;
+  HET_MEMORY   memory ;
+} ACMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct ecmp_format   
+{
+  uint32                      : 7 ;
+  uint32 angle_compare        : 1 ;
+  uint32 hr_lr                : 1 ;         
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ; 
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ; 
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} ECMP_FIELDS;
+
+typedef union 
+{
+  ECMP_FIELDS  ecmp   ;
+  HET_MEMORY   memory ;
+} ECMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct scmp_format     
+{
+  uint32                      : 5 ;
+  uint32                      : 2 ;
+  uint32                      : 2 ;         
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ; 
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 restart_en           : 1 ;
+  uint32                      : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 2 ;
+  uint32 coutprv              : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} SCMP_FIELDS ;
+
+typedef union 
+{
+  SCMP_FIELDS  scmp   ;
+  HET_MEMORY   memory ;
+} SCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MCMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct mcmp_format                     
+{
+  uint32                      : 5 ;
+  uint32 save_subtract        : 1 ;
+  uint32                      : 1 ;
+  uint32 angle_compare        : 1 ;
+  uint32 hr_lr                : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+ 
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 order                : 1 ; 
+  uint32 sub_opcode           : 1 ;  
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+ 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ; 
+
+} MCMP_FIELDS ; 
+
+typedef union 
+{
+  MCMP_FIELDS  mcmp   ;
+  HET_MEMORY   memory ;
+} MCMP_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* MOV64 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct mov64_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;          
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} MOV64_FIELDS ; 
+
+typedef union 
+{
+  MOV64_FIELDS  mov64  ;
+  HET_MEMORY    memory ;
+} MOV64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DADM64 INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct dadm64_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ; 
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+ 
+} DADM64_FIELDS ; 
+
+typedef union 
+{
+  DADM64_FIELDS  dadm64 ;
+  HET_MEMORY     memory ;
+} DADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* RADM64 INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct RADM64_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ; 
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ; 
+
+} RADM64_FIELDS ; 
+
+
+typedef union 
+{
+  RADM64_FIELDS  radm64 ;
+  HET_MEMORY     memory ;
+} RADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV32 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct MOV32_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ;
+ 
+  uint32                      : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 move_type            : 2 ;
+  uint32 sub_opcode           : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32                      : 15 ;
+  uint32 z_flag               : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 5 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+ 
+} MOV32_FIELDS ; 
+
+
+typedef union 
+{
+  MOV32_FIELDS  mov32  ;
+  HET_MEMORY    memory ;
+} MOV32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADM32 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct ADM32_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ; 
+
+  uint32                      : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 move_type            : 2 ;
+  uint32 sub_opcode           : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32                      : 19 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 5 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+   
+} ADM32_FIELDS ; 
+
+
+typedef union 
+{
+  ADM32_FIELDS  adm32  ;
+  HET_MEMORY    memory ;
+} ADM32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADCNST INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct ADCNST_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ;
+ 
+  uint32 constant             : 25 ;
+  uint32                      : 1 ;
+  uint32                      : 5 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ; 
+
+} ADCNST_FIELDS ;
+
+
+typedef union 
+{
+  ADCNST_FIELDS  adcnst ;
+  HET_MEMORY     memory ;
+} ADCNST_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* ADD INSTRUCTION					*/
+/*----------------------------------------------*/
+typedef struct ADD_format                     
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} ADD_FIELDS ;
+
+
+typedef union 
+{
+  ADD_FIELDS  add ;
+  HET_MEMORY  memory ;
+} ADD_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* ADC INSTRUCTION					*/
+/*----------------------------------------------*/
+
+
+typedef struct ADC_format                     
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} ADC_FIELDS ;
+
+
+typedef union 
+{
+  ADC_FIELDS  adc ;
+  HET_MEMORY  memory ;
+} ADC_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* SUB INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct SUB_format                     
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} SUB_FIELDS ;
+
+
+typedef union 
+{
+  SUB_FIELDS  sub ;
+  HET_MEMORY  memory ;
+} SUB_INSTRUCTION;
+
+
+
+
+
+/*----------------------------------------------*/
+/* SBB INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct SBB_format
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} SBB_FIELDS ;
+
+
+typedef union 
+{
+  SBB_FIELDS  sbb ;
+  HET_MEMORY  memory ;
+} SBB_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* AND INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct AND_format
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} AND_FIELDS ;
+
+
+typedef union 
+{
+  AND_FIELDS  and ;
+  HET_MEMORY  memory ;
+} AND_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* OR INSTRUCTION						*/
+/*----------------------------------------------*/
+
+typedef struct OR_format
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} OR_FIELDS ;
+
+
+typedef union 
+{
+  OR_FIELDS  or ;
+  HET_MEMORY  memory ;
+} OR_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* XOR INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct XOR_format
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} XOR_FIELDS ;
+
+
+typedef union 
+{
+  XOR_FIELDS  xor ;
+  HET_MEMORY  memory ;
+} XOR_INSTRUCTION;
+
+
+
+
+/*---------------------------------------------*/
+/* CNT INSTRUCTION                             */
+/*---------------------------------------------*/
+typedef struct CNT_format                     
+{
+  uint32 interrupt_enable     : 1 ;         
+  uint32                      : 4 ;        
+  uint32 ab_register_select   : 1 ;          
+  uint32 t_register_select    : 1 ;
+  uint32 angle_cnt            : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;  
+  uint32                      : 9 ;  
+
+  uint32 max                  : 25 ;
+  uint32                      : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} CNT_FIELDS ; 
+
+typedef union 
+{
+  CNT_FIELDS   cnt    ; 
+  HET_MEMORY   memory ;
+} CNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* APCNT INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct apcnt_format
+{
+  uint32                      : 6 ;
+  uint32 edge_select          : 2 ;
+  uint32 interrupt_enable     : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 count                : 25 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ; 
+
+} APCNT_FIELDS ;
+ 
+typedef union
+{
+  APCNT_FIELDS  apcnt   ;
+  HET_MEMORY   memory ;
+} APCNT_INSTRUCTION;
+ 
+ 
+
+/*---------------------------------------------*/
+/* PCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct pcnt_format                     
+{
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 period_pulse_select  : 2 ;          
+  uint32 interrupt_enable     : 1 ;          
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 count                : 25 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} PCNT_FIELDS ;      
+
+typedef union 
+{
+  PCNT_FIELDS  pcnt   ; 
+  HET_MEMORY   memory ;
+} PCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct scnt_format                     
+{
+  uint32                      : 4 ;
+  uint32 step_width           : 2 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ;
+
+  uint32 gap_start            : 25 ;
+  uint32                      : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 5 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} SCNT_FIELDS ;      
+
+typedef union 
+{
+  SCNT_FIELDS  scnt   ; 
+  HET_MEMORY   memory ;
+} SCNT_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* ACNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct acnt_format                     
+{
+  uint32 interrupt_enable     : 1 ; 
+  uint32                      : 7 ;
+  uint32 edge_select          : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 gap_end              : 25 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} ACNT_FIELDS ;      
+
+typedef union 
+{
+  ACNT_FIELDS  acnt   ; 
+  HET_MEMORY   memory ;
+} ACNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct ecnt_format
+{
+  uint32                      : 6 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+ 
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 1 ;
+  uint32 count_cond           : 3 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 3 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ; 
+ 
+
+} ECNT_FIELDS ;
+ 
+typedef union
+{
+  ECNT_FIELDS  ecnt   ;
+  HET_MEMORY   memory ;
+} ECNT_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* RCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct rcnt_format
+{
+
+  uint32 count_mode1          : 1 ;
+  uint32                      : 5 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+
+  uint32 divisor              : 25 ;  
+  uint32                      : 1 ;
+  uint32 control              : 1 ;
+  uint32                      : 2 ;
+  uint32                      : 3 ;
+
+  uint32                      : 7 ;  
+  uint32 data                 : 25 ;
+
+ 
+} RCNT_FIELDS ;
+ 
+typedef union
+{
+  RCNT_FIELDS  rcnt   ;
+  HET_MEMORY   memory ;
+} RCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJNZ INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct djnz_format                     
+{
+  uint32                      : 6 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ; 
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 10 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 4 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} DJNZ_FIELDS ;      
+
+typedef union 
+{
+  DJNZ_FIELDS  djnz   ; 
+  HET_MEMORY   memory ;
+} DJNZ_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJZ INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct djz_format                     
+{
+  uint32                      : 6 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ; 
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 10 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 4 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} DJZ_FIELDS ;      
+
+typedef union 
+{
+  DJZ_FIELDS  djz   ; 
+  HET_MEMORY   memory ;
+} DJZ_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* PWCNT INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct pwcnt_format                     
+{
+  uint32                      : 6 ;
+  uint32 count_mode           : 2 ;
+  uint32 hr_lr                : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32                      : 3 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;  
+ 
+} PWCNT_FIELDS ;      
+
+typedef union 
+{
+  PWCNT_FIELDS  pwcnt ;
+  HET_MEMORY   memory ;
+} PWCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* WCAP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct wcap_format                     
+{
+  uint32                      : 8 ;
+  uint32 hr_lr                : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ; 
+  
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 2 ;
+  uint32 capture_condition    : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 3 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} WCAP_FIELDS ;      
+
+typedef union 
+{
+  WCAP_FIELDS  wcap   ; 
+  HET_MEMORY   memory ;
+} WCAP_INSTRUCTION;
+ 
+/*----------------------------------------------*/
+/* WCAPE INSTRUCTION                            */
+/*----------------------------------------------*/
+typedef struct wcape_format                     
+{
+  uint32                      : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;  
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 2 ;
+  uint32 capture_condition    : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32 ec_data              : 7 ;
+  uint32 ts_data              : 25 ;
+
+} WCAPE_FIELDS ;      
+
+typedef union 
+{
+  WCAPE_FIELDS  wcape   ; 
+  HET_MEMORY   memory ;
+} WCAPE_INSTRUCTION;
+ 
+
+/*---------------------------------------------*/
+/* BR   INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct br_format                     
+{
+  uint32                      : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32                      : 2 ;
+  uint32                      : 1 ;
+  uint32                      : 1 ;
+  uint32 branch_condition     : 3 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 3 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} BR_FIELDS ;      
+
+typedef union 
+{
+  BR_FIELDS  br     ; 
+  HET_MEMORY memory ;
+} BR_INSTRUCTION;
+
+ 
+/*---------------------------------------------*/
+/* SHFT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct shft_format                     
+{
+  uint32 shift_mode           : 4 ;
+  uint32                      : 5 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ; 
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 2 ;
+  uint32 shift_condition      : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 3 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} SHFT_FIELDS ;      
+
+typedef union 
+{
+  SHFT_FIELDS  shft   ; 
+  HET_MEMORY   memory ;
+} SHFT_INSTRUCTION;
+
+#endif
+
+#endif
+/*--------------------------- End Of File ----------------------------------*/
diff --git a/bsp/rm48x50/HALCoGen/include/sys_common.h b/bsp/rm48x50/HALCoGen/include/sys_common.h
new file mode 100644
index 0000000000000000000000000000000000000000..d3a84dd156646b24739e1b25c3c3e393cd08a557
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_common.h
@@ -0,0 +1,80 @@
+/** @file sys_common.h
+*   @brief Common Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - General Definitions
+*   .
+*   which are relevant for all drivers.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __SYS_COMMON_H__
+#define __SYS_COMMON_H__
+
+#include "hal_stdtypes.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/************************************************************/
+/* Type Definitions                                         */
+/************************************************************/
+
+#ifndef _TBOOLEAN_DECLARED
+typedef boolean tBoolean;
+#define _TBOOLEAN_DECLARED
+#endif
+
+/** @enum loopBackType
+*   @brief Loopback type definition
+*/
+/** @typedef loopBackType_t
+*   @brief Loopback type Type Definition
+*
+*   This type is used to select the module Loopback type Digital or Analog loopback.
+*/
+typedef enum loopBackType 
+{
+    Digital = 0U, 
+    Analog = 1U
+}loopBackType_t;
+
+/** @enum config_value_type
+*   @brief config type definition
+*/
+/** @typedef config_value_type_t
+*   @brief config type Type Definition
+*
+*   This type is used to specify the Initial and Current value.
+*/
+typedef enum config_value_type
+{
+	InitialValue,
+	CurrentValue
+}config_value_type_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/********************************************************************************/
+/* The ASSERT macro, which does the actual assertion checking.  Typically, this */
+/* will be for procedure arguments.                                             */
+/********************************************************************************/
+#ifdef DEBUG
+#define ASSERT(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define ASSERT(expr)
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/sys_core.h b/bsp/rm48x50/HALCoGen/include/sys_core.h
new file mode 100644
index 0000000000000000000000000000000000000000..357a9757377977e67236c0a99710bf3316dfc81d
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_core.h
@@ -0,0 +1,264 @@
+/** @file sys_core.h
+*   @brief System Core Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Core Interface Functions
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __SYS_CORE_H__
+#define __SYS_CORE_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* System Core Interface Functions */
+
+/** @fn void _coreInitRegisters_(void)
+*   @brief Initialize Core register
+*/
+void _coreInitRegisters_(void);
+
+/** @fn void _coreInitStackPointer_(void)
+*   @brief Initialize Core stack pointer
+*/
+void _coreInitStackPointer_(void);
+
+/** @fn void _getCPSRValue_(void)
+*   @brief Get CPSR Value
+*/
+uint32 _getCPSRValue_(void);
+
+/** @fn void _gotoCPUIdle_(void)
+*   @brief Take CPU to Idle state
+*/
+void _gotoCPUIdle_(void);
+
+/** @fn void _coreEnableIrqVicOffset_(void)
+*   @brief Enable Irq offset propagation via Vic controller
+*/
+void _coreEnableIrqVicOffset_(void);
+
+/** @fn void _coreEnableVfp_(void)
+*   @brief Enable vector floating point unit
+*/
+void _coreEnableVfp_(void);
+
+/** @fn void _coreEnableEventBusExport_(void)
+*   @brief Enable event bus export for external monitoring modules
+*   @note It is required to enable event bus export to process ecc issues.
+*
+*   This function enables event bus exports to external monitoring modules
+*   like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
+*/
+void _coreEnableEventBusExport_(void);
+
+/** @fn void _coreDisableEventBusExport_(void)
+*   @brief Disable event bus export for external monitoring modules
+*
+*   This function disables event bus exports to external monitoring modules
+*   like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
+*/
+void _coreDisableEventBusExport_(void);
+
+/** @fn void _coreEnableRamEcc_(void)
+*   @brief Enable external ecc error for RAM odd and even bank
+*   @note It is required to enable event bus export to process ecc issues.
+*/
+void _coreEnableRamEcc_(void);
+
+/** @fn void _coreDisableRamEcc_(void)
+*   @brief Disable external ecc error for RAM odd and even bank
+*/
+void _coreDisableRamEcc_(void);
+
+/** @fn void _coreEnableFlashEcc_(void)
+*   @brief Enable external ecc error for the Flash
+*   @note It is required to enable event bus export to process ecc issues.
+*/
+void _coreEnableFlashEcc_(void);
+
+/** @fn void _coreDisableFlashEcc_(void)
+*   @brief Disable external ecc error for the Flash
+*/
+void _coreDisableFlashEcc_(void);
+
+/** @fn uint32 _coreGetDataFault_(void)
+*   @brief Get core data fault status register
+*   @return The function will return the data fault status register value:
+*           - bit [10,3..0]: 
+*                            - 0b00001: Alignment                -> address is valid
+*                            - 0b00000: Background               -> address is valid
+*                            - 0b01101: Permission               -> address is valid
+*                            - 0b01000: Precise External Abort   -> address is valid
+*                            - 0b10110: Imprecise External Abort -> address is unpredictable
+*                            - 0b11001: Precise ECC Error        -> address is valid
+*                            - 0b11000: Imprecise ECC Error      -> address is unpredictable
+*                            - 0b00010: Debug                    -> address is unchanged
+*           - bit [11]: 
+*                            - 0: Read
+*                            - 1: Write
+*           - bit [12]: 
+*                            - 0: AXI Decode Error (DECERR)
+*                            - 1: AXI Slave Error (SLVERR)
+*/
+uint32 _coreGetDataFault_(void);
+
+/** @fn void _coreClearDataFault_(void)
+*   @brief Clear core data fault status register
+*/
+void _coreClearDataFault_(void);
+
+/** @fn uint32 _coreGetInstructionFault_(void)
+*   @brief Get core instruction fault status register
+*   @return The function will return the instruction fault status register value:
+*           - bit [10,3..0]: 
+*                            - 0b00001: Alignment                -> address is valid
+*                            - 0b00000: Background               -> address is valid
+*                            - 0b01101: Permission               -> address is valid
+*                            - 0b01000: Precise External Abort   -> address is valid
+*                            - 0b10110: Imprecise External Abort -> address is unpredictable
+*                            - 0b11001: Precise ECC Error        -> address is valid
+*                            - 0b11000: Imprecise ECC Error      -> address is unpredictable
+*                            - 0b00010: Debug                    -> address is unchanged
+*           - bit [12]: 
+*                            - 0: AXI Decode Error (DECERR)
+*                            - 1: AXI Slave Error (SLVERR)
+*/
+uint32 _coreGetInstructionFault_(void);
+
+/** @fn void _coreClearInstructionFault_(void)
+*   @brief Clear core instruction fault status register
+*/
+void _coreClearInstructionFault_(void);
+
+/** @fn uint32 _coreGetDataFaultAddress_(void)
+*   @brief Get core data fault address register
+*   @return The function will return the data fault address:
+*/
+uint32 _coreGetDataFaultAddress_(void);
+
+/** @fn void _coreClearDataFaultAddress_(void)
+*   @brief Clear core data fault address register
+*/
+void _coreClearDataFaultAddress_(void);
+
+/** @fn uint32 _coreGetInstructionFaultAddress_(void)
+*   @brief Get core instruction fault address register
+*   @return The function will return the instruction fault address:
+*/
+uint32 _coreGetInstructionFaultAddress_(void);
+
+/** @fn void _coreClearInstructionFaultAddress_(void)
+*   @brief Clear core instruction fault address register
+*/
+void _coreClearInstructionFaultAddress_(void);
+
+/** @fn uint32 _coreGetAuxiliaryDataFault_(void)
+*   @brief Get core auxiliary data fault status register
+*   @return The function will return the auxiliary data fault status register value:
+*           - bit [13..5]:
+*                            - Index value for access giving error
+*           - bit [21]: 
+*                            - 0: Unrecoverable error
+*                            - 1: Recoverable error
+*           - bit [23..22]:
+*                            - 0: Side cache
+*                            - 1: Side ATCM (Flash)
+*                            - 2: Side BTCM (RAM)
+*                            - 3: Reserved
+*           - bit [27..24]: 
+*                            - Cache way or way in which error occurred
+*/
+uint32 _coreGetAuxiliaryDataFault_(void);
+
+/** @fn void _coreClearAuxiliaryDataFault_(void)
+*   @brief Clear core auxiliary data fault status register
+*/
+void _coreClearAuxiliaryDataFault_(void);
+
+/** @fn uint32 _coreGetAuxiliaryInstructionFault_(void)
+*   @brief Get core auxiliary instruction fault status register
+*   @return The function will return the auxiliary instruction fault status register value:
+*           - bit [13..5]:
+*                            - Index value for access giving error
+*           - bit [21]: 
+*                            - 0: Unrecoverable error
+*                            - 1: Recoverable error
+*           - bit [23..22]:
+*                            - 0: Side cache
+*                            - 1: Side ATCM (Flash)
+*                            - 2: Side BTCM (RAM)
+*                            - 3: Reserved
+*           - bit [27..24]: 
+*                            - Cache way or way in which error occurred
+*/
+uint32 _coreGetAuxiliaryInstructionFault_(void);
+
+/** @fn void _coreClearAuxiliaryInstructionFault_(void)
+*   @brief Clear core auxiliary instruction fault status register
+*/
+void _coreClearAuxiliaryInstructionFault_(void);
+
+/** @fn void _disable_interrupt_(void)
+*   @brief Disable IRQ and FIQ Interrupt mode in CPSR register
+*
+*   This function disables IRQ and FIQ Interrupt mode in CPSR register.
+*/
+void _disable_interrupt_(void);
+
+/** @fn void _disable_IRQ_interrupt_(void)
+*   @brief Disable IRQ Interrupt mode in CPSR register
+*
+*   This function disables IRQ Interrupt mode in CPSR register.
+*/
+void _disable_IRQ_interrupt_(void);
+
+/** @fn void _disable_FIQ_interrupt_(void)
+*   @brief Disable FIQ Interrupt mode in CPSR register
+*
+*   This function disables IRQ Interrupt mode in CPSR register.
+*/
+void _disable_FIQ_interrupt_(void);
+
+/** @fn void _enable_interrupt_(void)
+*   @brief Enable IRQ and FIQ Interrupt mode in CPSR register
+*
+*   This function Enables IRQ and FIQ Interrupt mode in CPSR register.
+*   User must call this function to enable Interrupts in non-OS environments.
+*/
+void _enable_interrupt_(void);
+
+/** @fn void _esmCcmErrorsClear_(void)
+*   @brief Clears ESM Error caused due to CCM Errata in RevA Silicon
+*
+*   This function Clears ESM Error caused due to CCM Errata 
+*   in RevA Silicon immediately after powerup.
+*/
+void _esmCcmErrorsClear_(void);
+
+/** @fn void _errata_CORTEXR4_66_(void)
+*   @brief Work Around for Errata CORTEX-R4#66
+*
+*   This function Disable out-of-order completion for divide 
+*   instructions in Auxiliary Control register.
+*/
+void _errata_CORTEXR4_66_(void);
+
+/** @fn void _errata_CORTEXR4_57_(void)
+*   @brief Work Around for Errata CORTEX-R4#57
+*
+*   Disable out-of-order single-precision floating point  
+*   multiply-accumulate instruction completion.
+*/
+void _errata_CORTEXR4_57_(void);
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/sys_dma.h b/bsp/rm48x50/HALCoGen/include/sys_dma.h
new file mode 100644
index 0000000000000000000000000000000000000000..da1981db1230e463f1775a920c9efb9f414479f9
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_dma.h
@@ -0,0 +1,261 @@
+/** @file dma.h
+*   @brief DMA Driver Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include "reg_dma.h"
+
+/* dma configuration definitions */
+
+#define BLOCK_TRANSFER      1U
+#define FRAME_TRANSFER      0U
+
+#define AUTOINIT_ON         1U
+#define AUTOINIT_OFF        0U
+
+#define ADDR_FIXED          0U
+#define ADDR_INC1           1U
+#define ADDR_RESERVED       2U
+#define ADDR_OFFSET         3U
+
+#define INTERRUPT_ENABLE	1U
+#define INTERRUPT_DISABLE	0U
+
+
+/*Bit Masks*/
+#define DMA_GCTRL_BUSBUSY	(1U << 14U)
+/** @enum dmaREQTYPE
+*   @brief DMA TRANSFER Type definitions 
+*
+*   Used to define DMA transfer type
+*/
+enum dmaREQTYPE
+{
+    DMA_HW = 0x0U,  /**<  Hardware trigger  */
+    DMA_SW = 0x1U   /**<  Software trigger  */
+};
+
+
+/** @enum dmaCHANNEL
+*   @brief DMA CHANNEL definitions 
+*
+*   Used to define DMA Channel Number
+*/
+enum dmaCHANNEL
+{
+    DMA_CH0  = 0x00U,
+    DMA_CH1  = 0x01U,
+    DMA_CH2  = 0x02U,
+    DMA_CH3  = 0x03U,
+    DMA_CH4  = 0x04U,
+    DMA_CH5  = 0x05U,
+    DMA_CH6  = 0x06U,
+    DMA_CH7  = 0x07U,
+    DMA_CH8  = 0x08U,
+    DMA_CH9  = 0x09U,
+    DMA_CH10 = 0x0AU,
+    DMA_CH11 = 0x0BU,
+    DMA_CH12 = 0x0CU,
+    DMA_CH13 = 0x0DU,
+    DMA_CH14 = 0x0EU,
+    DMA_CH15 = 0x0FU,
+    DMA_CH16 = 0x10U,
+    DMA_CH17 = 0x11U,
+    DMA_CH18 = 0x12U,
+    DMA_CH19 = 0x13U,
+    DMA_CH20 = 0x14U,
+    DMA_CH21 = 0x15U,
+    DMA_CH22 = 0x16U,
+    DMA_CH23 = 0x17U,
+    DMA_CH24 = 0x18U,
+    DMA_CH25 = 0x19U,
+    DMA_CH26 = 0x1AU,
+    DMA_CH27 = 0x1BU,
+    DMA_CH28 = 0x1CU,
+    DMA_CH29 = 0x1DU,
+    DMA_CH30 = 0x1EU,
+    DMA_CH31 = 0x1FU,
+    DMA_CH32 = 0x20U
+};
+
+/** @enum dmaACCESS
+*   @brief DMA ACESS WIDTH definitions 
+*
+*   Used to define DMA access width
+*/
+typedef enum dmaACCESS
+{
+ ACCESS_8_BIT   =  0U,
+ ACCESS_16_BIT  =  1U,
+ ACCESS_32_BIT  =  2U,
+ ACCESS_64_BIT  =  3U
+}dmaACCESS_t;
+
+
+/** @enum dmaPRIORITY
+*   @brief DMA Channel Priority
+*
+*   Used to define to which priority queue a DMA channel is assigned to
+*/
+typedef enum dmaPRIORITY
+{
+	LOWPRIORITY = 0U,
+	HIGHPRIORITY = 1U
+}dmaPRIORITY_t;
+
+
+/** @enum dmaREGION
+*   @brief DMA Memory Protection Region
+*
+*   Used to define DMA Memory Protection Region
+*/
+typedef enum dmaREGION
+{
+	DMA_REGION0 = 0U,
+	DMA_REGION1 = 1U,
+	DMA_REGION2 = 2U,
+	DMA_REGION3 = 3U
+}dmaREGION_t;
+
+
+/** @enum dmaRegionAccess
+*   @brief DMA Memory Protection Region Access
+*
+*   Used to define access permission of DMA memory protection regions
+*/
+typedef enum dmaRegionAccess
+{
+	FULLACCESS = 0U,
+	READONLY   = 1U,
+	WRITEONLY  = 2U,
+	NOACCESS   = 3U
+}dmaRegionAccess_t;
+
+
+/** @enum dmaInterrupt
+*   @brief DMA Interrupt
+*
+*   Used to define DMA interrupts
+*/
+typedef enum dmaInterrupt
+{
+	FTC = 1U,   /**<  Frame transfer complete Interrupt      */
+	LFS = 2U,   /**<  Last frame transfer started Interrupt  */
+	HBC = 3U,   /**<  First half of block complete Interrupt */
+	BTC = 4U    /**<  Block transfer complete Interrupt      */
+}dmaInterrupt_t;
+
+/** @struct g_dmaCTRL
+*   @brief Interrupt mode globals
+*
+*/
+typedef struct  dmaCTRLPKT
+{
+    uint32 SADD;       /* initial source address           */
+    uint32 DADD;       /* initial destination address      */
+    uint32 CHCTRL;     /* channel count                    */
+    uint32 FRCNT;      /* frame   count                    */
+    uint32 ELCNT;      /* element count                    */
+    uint32 ELDOFFSET;  /* element destination offset       */
+    uint32 ELSOFFSET;  /* element source offset            */
+    uint32 FRDOFFSET;  /* frame detination offset          */
+    uint32 FRSOFFSET;  /* frame source offset              */
+    uint32 PORTASGN;   /* dma port                         */
+    uint32 RDSIZE;     /* read element size                */
+    uint32 WRSIZE;     /* write element size               */
+    uint32 TTYPE;      /* trigger type - frame/block       */
+    uint32 ADDMODERD;  /* addresssing mode for source      */
+    uint32 ADDMODEWR;  /* addresssing mode for destination */
+    uint32 AUTOINIT;   /* auto-init mode                   */
+    uint32 COMBO;      /* next ctrl packet trigger         */
+} g_dmaCTRL;
+
+typedef volatile struct
+{
+     
+     struct                                     /* 0x000-0x400 */
+     {
+      uint32 ISADDR;
+      uint32 IDADDR;
+      uint32 ITCOUNT; 
+      uint32  rsvd1;    
+      uint32 CHCTRL;
+      uint32 EIOFF;
+      uint32 FIOFF;
+      uint32  rsvd2;  
+     }PCP[32U];
+
+     struct                                     /* 0x400-0x800   */
+     {
+       uint32 res[256U];
+     } RESERVED;
+
+     struct                                     /* 0x800-0xA00 */
+     {
+      uint32 CSADDR;
+      uint32 CDADDR;
+      uint32 CTCOUNT;
+      uint32  rsvd3; 
+     }WCP[32U];
+
+} dmaRAMBASE_t;
+
+#define dmaRAMREG ((dmaRAMBASE_t *)0xFFF80000U)
+
+/**
+ * @defgroup DMA DMA
+ * @brief Direct Memory Access Controller
+ *
+ * The DMA controller is used to transfer data between two locations in the memory map in the background
+ * of CPU operations. Typically, the DMA is used to:
+ * - Transfer blocks of data between external and internal data memories
+ * - Restructure portions of internal data memory
+ * - Continually service a peripheral
+ * - Page program sections to internal program memory
+ *
+ * Related files:
+ * - reg_dma.h
+ * - sys_dma.h
+ * - sys_dma.c
+ *
+ * @addtogroup DMA
+ * @{
+ */
+/* DMA Interface Functions */
+void dmaEnable(void);
+void dmaDisable(void);
+void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT);
+void dmaSetChEnable(uint32 channel,uint32 type);
+void dmaReqAssign(uint32 channel,uint32 reqline);
+uint32 dmaGetReq(uint32 channel);
+void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority);
+void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype);
+void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype);
+void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add);
+void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable);
+void dmaDisableRegion(dmaREGION_t region);
+void dmaEnableParityCheck(void);
+void dmaDisableParityCheck(void);
+/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel)
+*   @brief Interrupt callback
+*   @param[in] inttype  Interrupt type
+*                        - FTC
+*                        - LFS
+*                        - HBC
+*                        - BTC
+*   @param[in] channel  channel number 0..15
+* This is a callback that is provided by the application and is called apon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel);
+
+/**@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/sys_mpu.h b/bsp/rm48x50/HALCoGen/include/sys_mpu.h
new file mode 100644
index 0000000000000000000000000000000000000000..41157f2fc63d72538fb44611850e3c368cf1d14c
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_mpu.h
@@ -0,0 +1,352 @@
+/** @file sys_mpu.h
+*   @brief System Mpu Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Mpu Interface Functions
+*   .
+*   which are relevant for the memory protection unit driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __SYS_MPU_H__
+#define __SYS_MPU_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def mpuREGION1
+*   @brief Mpu region 1
+*
+*   Alias for Mpu region 1
+*/
+#define mpuREGION1 0U
+
+/** @def mpuREGION2
+*   @brief Mpu region 2
+*
+*   Alias for Mpu region 1
+*/
+#define mpuREGION2 1U
+
+/** @def mpuREGION3
+*   @brief Mpu region 3
+*
+*   Alias for Mpu region 3
+*/
+#define mpuREGION3 2U
+
+/** @def mpuREGION4
+*   @brief Mpu region 4
+*
+*   Alias for Mpu region 4
+*/
+#define mpuREGION4 3U
+
+/** @def mpuREGION5
+*   @brief Mpu region 5
+*
+*   Alias for Mpu region 5
+*/
+#define mpuREGION5 4U
+
+/** @def mpuREGION6
+*   @brief Mpu region 6
+*
+*   Alias for Mpu region 6
+*/
+#define mpuREGION6 5U
+
+/** @def mpuREGION7
+*   @brief Mpu region 7
+*
+*   Alias for Mpu region 7
+*/
+#define mpuREGION7 6U
+
+/** @def mpuREGION8
+*   @brief Mpu region 8
+*
+*   Alias for Mpu region 8
+*/
+#define mpuREGION8 7U
+
+/** @def mpuREGION9
+*   @brief Mpu region 9
+*
+*   Alias for Mpu region 9
+*/
+#define mpuREGION9 8U
+
+/** @def mpuREGION10
+*   @brief Mpu region 10
+*
+*   Alias for Mpu region 10
+*/
+#define mpuREGION10 9U
+
+/** @def mpuREGION11
+*   @brief Mpu region 11
+*
+*   Alias for Mpu region 11
+*/
+#define mpuREGION11 10U
+
+/** @def mpuREGION12
+*   @brief Mpu region 12
+*
+*   Alias for Mpu region 12
+*/
+#define mpuREGION12 11U
+
+
+
+
+/** @enum mpuRegionAccessPermission
+*   @brief Alias names for mpu region access permissions
+*
+*   This enumeration is used to provide alias names for the mpu region access permission:
+*     - MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and execute
+*     - MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode and execute
+*     - MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode and execute
+*     - MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode and execute
+*     - MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and execute
+*     - MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and execute
+*     - MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode and no execution
+*     - MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode and no execution
+*     - MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode and no execution
+*     - MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode and no execution
+*     - MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode and no execution
+*     - MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode and no execution
+*
+*/
+enum mpuRegionAccessPermission
+{
+    MPU_PRIV_NA_USER_NA_EXEC   = 0x0000U, /**< Alias no access in privileged mode, no access in user mode and execute */
+    MPU_PRIV_RW_USER_NA_EXEC   = 0x0100U, /**< Alias no read/write in privileged mode, no access in user mode and execute */
+    MPU_PRIV_RW_USER_RO_EXEC   = 0x0200U, /**< Alias no read/write in privileged mode, read only in user mode and execute */
+    MPU_PRIV_RW_USER_RW_EXEC   = 0x0300U, /**< Alias no read/write in privileged mode, read/write in user mode and execute */
+    MPU_PRIV_RO_USER_NA_EXEC   = 0x0500U, /**< Alias no read only in privileged mode, no access in user mode and execute */
+    MPU_PRIV_RO_USER_RO_EXEC   = 0x0600U, /**< Alias no read only in privileged mode, read only in user mode and execute */
+    MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no access in user mode and no execution */
+    MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias no read/write in privileged mode, no access in user mode and no execution */
+    MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias no read/write in privileged mode, read only in user mode and no execution */
+    MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias no read/write in privileged mode, read/write in user mode and no execution */
+    MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias no read only in privileged mode, no access in user mode and no execution */
+    MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U  /**< Alias no read only in privileged mode, read only in user mode and no execution */
+};
+
+/** @enum mpuRegionType
+*   @brief Alias names for mpu region type
+*
+*   This enumeration is used to provide alias names for the mpu region type:
+*     - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable
+*     - MPU_DEVICE_SHAREABLE          Memory type device and sharable
+*     - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, no write allocate and non shared
+*     - MPU_NORMAL_OIWTNOWA_SHARED    Memory type normal outer and inner write-through, no write allocate and shared
+*     - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no write allocate and non shared
+*     - MPU_NORMAL_OIWBNOWA_SHARED    Memory type normal outer and inner write-back, no write allocate and shared
+*     - MPU_NORMAL_OINC_NONSHARED     Memory type normal outer and inner non-cachable and non shared
+*     - MPU_NORMAL_OINC_SHARED        Memory type normal outer and inner non-cachable and shared
+*     - MPU_NORMAL_OIWBWA_NONSHARED   Memory type normal outer and inner write-back, write allocate and non shared
+*     - MPU_NORMAL_OIWBWA_SHARED      Memory type normal outer and inner write-back, write allocate and shared
+*     - MPU_DEVICE_NONSHAREABLE       Memory type device and non sharable
+*/
+enum mpuRegionType
+{
+    MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and sharable */
+    MPU_DEVICE_SHAREABLE          = 0x0001U, /**< Memory type device and sharable */
+    MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner write-through, no write allocate and non shared */
+    MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner write-back, no write allocate and non shared */
+    MPU_NORMAL_OIWTNOWA_SHARED    = 0x0006U, /**< Memory type normal outer and inner write-through, no write allocate and shared */
+    MPU_NORMAL_OIWBNOWA_SHARED    = 0x0007U, /**< Memory type normal outer and inner write-back, no write allocate and shared */
+    MPU_NORMAL_OINC_NONSHARED     = 0x0008U, /**< Memory type normal outer and inner non-cachable and non shared */
+    MPU_NORMAL_OIWBWA_NONSHARED   = 0x000BU, /**< Memory type normal outer and inner write-back, write allocate and non shared */
+    MPU_NORMAL_OINC_SHARED        = 0x000CU, /**< Memory type normal outer and inner non-cachable and shared */
+    MPU_NORMAL_OIWBWA_SHARED      = 0x000FU, /**< Memory type normal outer and inner write-back, write allocate and shared */
+    MPU_DEVICE_NONSHAREABLE       = 0x0010U  /**< Memory type device and non sharable */
+};
+
+/** @enum mpuRegionSize
+*   @brief Alias names for mpu region type
+*
+*   This enumeration is used to provide alias names for the mpu region type:
+*     - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable
+*     - MPU_32_BYTES Memory size in bytes
+*     - MPU_64_BYTES Memory size in bytes
+*     - MPU_128_BYTES Memory size in bytes
+*     - MPU_256_BYTES Memory size in bytes
+*     - MPU_512_BYTES Memory size in bytes
+*     - MPU_1_KB Memory size in kB
+*     - MPU_2_KB Memory size in kB
+*     - MPU_4_KB Memory size in kB
+*     - MPU_8_KB Memory size in kB
+*     - MPU_16_KB Memory size in kB
+*     - MPU_32_KB Memory size in kB
+*     - MPU_64_KB Memory size in kB
+*     - MPU_128_KB Memory size in kB
+*     - MPU_256_KB  Memory size in kB
+*     - MPU_512_KB Memory size in kB
+*     - MPU_1_MB Memory size in MB
+*     - MPU_2_MB Memory size in MB
+*     - MPU_4_MB Memory size in MB
+*     - MPU_8_MBv Memory size in MB
+*     - MPU_16_MB Memory size in MB
+*     - MPU_32_MB Memory size in MB
+*     - MPU_64_MB Memory size in MB
+*     - MPU_128_MB Memory size in MB
+*     - MPU_256_MB Memory size in MB
+*     - MPU_512_MB Memory size in MB
+*     - MPU_1_GB Memory size in GB
+*     - MPU_2_GB Memory size in GB
+*     - MPU_4_GB Memory size in GB
+*/
+enum mpuRegionSize
+{
+    MPU_32_BYTES  = 0x04U, /**< Memory size in bytes */
+    MPU_64_BYTES  = 0x05U, /**< Memory size in bytes */
+    MPU_128_BYTES = 0x06U, /**< Memory size in bytes */
+    MPU_256_BYTES = 0x07U, /**< Memory size in bytes */
+    MPU_512_BYTES = 0x08U, /**< Memory size in bytes */
+    MPU_1_KB      = 0x09U, /**< Memory size in kB */
+    MPU_2_KB      = 0x0AU, /**< Memory size in kB */
+    MPU_4_KB      = 0x0BU, /**< Memory size in kB */
+    MPU_8_KB      = 0x0CU, /**< Memory size in kB */
+    MPU_16_KB     = 0x0DU, /**< Memory size in kB */
+    MPU_32_KB     = 0x0EU, /**< Memory size in kB */
+    MPU_64_KB     = 0x0FU, /**< Memory size in kB */
+    MPU_128_KB    = 0x10U, /**< Memory size in kB */
+    MPU_256_KB    = 0x11U, /**< Memory size in kB */
+    MPU_512_KB    = 0x12U, /**< Memory size in kB */
+    MPU_1_MB      = 0x13U, /**< Memory size in MB */
+    MPU_2_MB      = 0x14U, /**< Memory size in MB */
+    MPU_4_MB      = 0x15U, /**< Memory size in MB */
+    MPU_8_MB      = 0x16U, /**< Memory size in MB */
+    MPU_16_MB     = 0x17U, /**< Memory size in MB */
+    MPU_32_MB     = 0x18U, /**< Memory size in MB */
+    MPU_64_MB     = 0x19U, /**< Memory size in MB */
+    MPU_128_MB    = 0x1AU, /**< Memory size in MB */
+    MPU_256_MB    = 0x1BU, /**< Memory size in MB */
+    MPU_512_MB    = 0x1CU, /**< Memory size in MB */
+    MPU_1_GB      = 0x1DU, /**< Memory size in GB */
+    MPU_2_GB      = 0x1EU, /**< Memory size in GB */
+    MPU_4_GB      = 0x1FU  /**< Memory size in GB */
+};
+
+/** @fn void _mpuInit_(void)
+*   @brief Initialize Mpu
+*
+*   This function initializes memory protection unit.
+*/
+void _mpuInit_(void);
+
+/** @fn void _mpuEnable_(void)
+*   @brief Enable Mpu
+*
+*   This function enables memory protection unit.
+*/
+void _mpuEnable_(void);
+
+/** @fn void _mpuDisable_(void)
+*   @brief Disable Mpu
+*
+*   This function disables memory protection unit.
+*/
+void _mpuDisable_(void);
+
+/** @fn void _mpuEnableBackgroundRegion_(void)
+*   @brief Enable Mpu background region
+*
+*   This function enables background region of the memory protection unit.
+*/
+void _mpuEnableBackgroundRegion_(void);
+
+/** @fn void _mpuDisableBackgroundRegion_(void)
+*   @brief Disable Mpu background region
+*
+*   This function disables background region of the memory protection unit.
+*/
+void _mpuDisableBackgroundRegion_(void);
+
+/** @fn uint32 _mpuGetNumberOfRegions_(void)
+*   @brief Returns number of implemented Mpu regions
+*   @return Number of implemented mpu regions
+*
+*   This function returns the number of implemented mpu regions.
+*/
+uint32 _mpuGetNumberOfRegions_(void);
+
+/** @fn uint32 _mpuAreRegionsSeparate_(void)
+*   @brief Returns the type of the implemented mpu regions
+*   @return Mpu type of regions
+*
+*   This function returns 0 when mpu regions are of type unified otherwise regions are of type separate.
+*/
+uint32 _mpuAreRegionsSeparate_(void);
+
+/** @fn void _mpuSetRegion_(uint32 region)
+*   @brief Set mpu region number
+*
+*   This function selects one of the implemented mpu regions.
+*/
+void _mpuSetRegion_(uint32 region);
+
+/** @fn uint32 _mpuGetRegion_(void)
+*   @brief Returns the currently selected mpu region
+*   @return Mpu region number
+*
+*   This function returns currently selected mpu region number.
+*/
+uint32 _mpuGetRegion_(void);
+
+/** @fn void _mpuSetRegionBaseAddress_(uint32 address)
+*   @brief Set base address of currently selected mpu region
+*   @note The base address must always aligned with region size
+*
+*   This function sets the base address of currently selected mpu region.
+*/
+void _mpuSetRegionBaseAddress_(uint32 address);
+
+/** @fn uint32 _mpuGetRegionBaseAddress_(void)
+*   @brief Returns base address of currently selected mpu region
+*   @return Current base address of selected mpu region
+*
+*   This function returns the base address of currently selected mpu region.
+*/
+uint32 _mpuGetRegionBaseAddress_(void);
+
+/** @fn void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission)
+*   @brief Set type of currently selected mpu region
+*
+*   This function sets the type of currently selected mpu region.
+*/
+void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission);
+
+/** @fn uint32 _mpuGetRegionType_(void)
+*   @brief Returns the type of currently selected mpu region
+*   @return Current type of selected mpu region
+*
+*   This function returns the type of currently selected mpu region.
+*/
+uint32 _mpuGetRegionType_(void);
+
+/** @fn uint32 _mpuGetRegionPermission_(void)
+*   @brief Returns permission of currently selected mpu region
+*   @return Current type of selected mpu region
+*
+*   This function returns permission of currently selected mpu region.
+*/
+uint32 _mpuGetRegionPermission_(void);
+
+/** @fn void _mpuSetRegionSizeRegister_(uint32 value)
+*   @brief Set mpu region size register value
+*
+*   This function sets mpu region size register value.
+*/
+void _mpuSetRegionSizeRegister_(uint32 value);
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/sys_pcr.h b/bsp/rm48x50/HALCoGen/include/sys_pcr.h
new file mode 100644
index 0000000000000000000000000000000000000000..0f034be6f1d81fea9946380978801128eab6f7e8
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_pcr.h
@@ -0,0 +1,238 @@
+/** @file sys_pcr.h
+*   @brief PCR Driver Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __SYS_PCR_H__
+#define __SYS_PCR_H__
+
+#include "reg_pcr.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* PCR General Definitions */
+
+typedef uint32 peripheralFrame_CS_t;
+
+#define PeripheralFrame_CS0 0U
+#define PeripheralFrame_CS1 1U
+#define PeripheralFrame_CS2 2U
+#define PeripheralFrame_CS3 3U
+#define PeripheralFrame_CS4 4U
+#define PeripheralFrame_CS5 5U
+#define PeripheralFrame_CS6 6U
+#define PeripheralFrame_CS7 7U
+#define PeripheralFrame_CS8 8U
+#define PeripheralFrame_CS9 9U
+#define PeripheralFrame_CS10 10U
+#define PeripheralFrame_CS11 11U
+#define PeripheralFrame_CS12 12U
+#define PeripheralFrame_CS13 13U
+#define PeripheralFrame_CS14 14U
+#define PeripheralFrame_CS15 15U
+#define PeripheralFrame_CS16 16U
+#define PeripheralFrame_CS17 17U
+#define PeripheralFrame_CS18 18U
+#define PeripheralFrame_CS19 19U
+#define PeripheralFrame_CS20 20U
+#define PeripheralFrame_CS21 21U
+#define PeripheralFrame_CS22 22U
+#define PeripheralFrame_CS23 23U
+#define PeripheralFrame_CS24 24U
+#define PeripheralFrame_CS25 25U
+#define PeripheralFrame_CS26 26U
+#define PeripheralFrame_CS27 27U
+#define PeripheralFrame_CS28 28U
+#define PeripheralFrame_CS29 29U
+#define PeripheralFrame_CS30 30U
+#define PeripheralFrame_CS31 31U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+typedef uint32 quadrant_Select_t;
+#define Quadrant0 1U
+#define Quadrant1 2U
+#define Quadrant2 4U
+#define Quadrant3 8U
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @typedef peripheral_Frame_Select_t
+*   @brief PCR Peripheral Frame Type Definition
+*
+*   This type is used to access the PCR peripheral Frame configuration register.
+*/
+typedef struct peripheral_Frame_Select
+{
+	peripheralFrame_CS_t Peripheral_CS;
+	quadrant_Select_t Peripheral_Quadrant;
+}peripheral_Frame_Select_t;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/** @typedef peripheral_Quad_ChipSelect_t
+*   @brief PCR Peripheral Frame registers Type Definition
+*
+*   This type is used to access all the PCR peripheral Frame configuration registers.
+*/
+typedef struct peripheral_Quad_ChipSelect
+{
+	uint32 Peripheral_Quad0_3_CS0_7;
+	uint32 Peripheral_Quad4_7_CS8_15;
+	uint32 Peripheral_Quad8_11_CS16_23;
+	uint32 Peripheral_Quad12_15_CS24_31;
+}peripheral_Quad_ChipSelect_t;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @typedef peripheral_Memory_ChipSelect_t
+*   @brief PCR Peripheral Memory Frame registers Type Definition
+*
+*   This type is used to access all the PCR peripheral Memory Frame configuration registers.
+*/
+typedef struct peripheral_Memory_ChipSelect
+{
+	uint32 Peripheral_Mem_CS0_31;
+	uint32 Peripheral_Mem_CS32_63;
+}peripheral_Memory_ChipSelect_t;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+typedef uint32 peripheral_MemoryFrame_CS_t;
+
+#define PeripheralMemoryFrame_CS0 0U
+#define PeripheralMemoryFrame_CS1 1U
+#define PeripheralMemoryFrame_CS2 2U
+#define PeripheralMemoryFrame_CS3 3U
+#define PeripheralMemoryFrame_CS4 4U
+#define PeripheralMemoryFrame_CS5 5U
+#define PeripheralMemoryFrame_CS6 6U
+#define PeripheralMemoryFrame_CS7 7U
+#define PeripheralMemoryFrame_CS8 8U
+#define PeripheralMemoryFrame_CS9 9U
+#define PeripheralMemoryFrame_CS10 10U
+#define PeripheralMemoryFrame_CS11 11U
+#define PeripheralMemoryFrame_CS12 12U
+#define PeripheralMemoryFrame_CS13 13U
+#define PeripheralMemoryFrame_CS14 14U
+#define PeripheralMemoryFrame_CS15 15U
+#define PeripheralMemoryFrame_CS16 16U
+#define PeripheralMemoryFrame_CS17 17U
+#define PeripheralMemoryFrame_CS18 18U
+#define PeripheralMemoryFrame_CS19 19U
+#define PeripheralMemoryFrame_CS20 20U
+#define PeripheralMemoryFrame_CS21 21U
+#define PeripheralMemoryFrame_CS22 22U
+#define PeripheralMemoryFrame_CS23 23U
+#define PeripheralMemoryFrame_CS24 24U
+#define PeripheralMemoryFrame_CS25 25U
+#define PeripheralMemoryFrame_CS26 26U
+#define PeripheralMemoryFrame_CS27 27U
+#define PeripheralMemoryFrame_CS28 28U
+#define PeripheralMemoryFrame_CS29 29U
+#define PeripheralMemoryFrame_CS30 30U
+#define PeripheralMemoryFrame_CS31 31U
+#define PeripheralMemoryFrame_CS32 32U
+#define PeripheralMemoryFrame_CS33 33U
+#define PeripheralMemoryFrame_CS34 34U
+#define PeripheralMemoryFrame_CS35 35U
+#define PeripheralMemoryFrame_CS36 36U
+#define PeripheralMemoryFrame_CS37 37U
+#define PeripheralMemoryFrame_CS38 38U
+#define PeripheralMemoryFrame_CS39 39U
+#define PeripheralMemoryFrame_CS40 40U
+#define PeripheralMemoryFrame_CS41 41U
+#define PeripheralMemoryFrame_CS42 42U
+#define PeripheralMemoryFrame_CS43 43U
+#define PeripheralMemoryFrame_CS44 44U
+#define PeripheralMemoryFrame_CS45 45U
+#define PeripheralMemoryFrame_CS46 46U
+#define PeripheralMemoryFrame_CS47 47U
+#define PeripheralMemoryFrame_CS48 48U
+#define PeripheralMemoryFrame_CS49 49U
+#define PeripheralMemoryFrame_CS50 50U
+#define PeripheralMemoryFrame_CS51 51U
+#define PeripheralMemoryFrame_CS52 52U
+#define PeripheralMemoryFrame_CS53 53U
+#define PeripheralMemoryFrame_CS54 54U
+#define PeripheralMemoryFrame_CS55 55U
+#define PeripheralMemoryFrame_CS56 56U
+#define PeripheralMemoryFrame_CS57 57U
+#define PeripheralMemoryFrame_CS58 58U
+#define PeripheralMemoryFrame_CS59 59U
+#define PeripheralMemoryFrame_CS60 60U
+#define PeripheralMemoryFrame_CS61 61U
+#define PeripheralMemoryFrame_CS62 62U
+#define PeripheralMemoryFrame_CS63 63U
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+/**
+ * @defgroup PCR PCR
+ * @brief Peripheral Central Resource Controller
+ *
+ * The PCR manages the accesses to the peripheral registers and peripheral
+ * memories. It provides a global reset for all the peripherals. It also supports the
+ * capability to selectively enable or disable the clock for each peripheral
+ * individually. The PCR also manages the accesses to the system module
+ * registers required to configure the device’s clocks, interrupts, and so on. The
+ * system module registers also include status flags for indicating exception
+ * conditions – resets, aborts, errors, interrupts.
+ *
+ * Related files:
+ * - reg_pcr.h
+ * - sys_pcr.h
+ * - sys_pcr.c
+ *
+ * @addtogroup PCR
+ * @{
+ */
+ 
+/* PCR Interface Functions */
+
+void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame);
+
+void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+peripheral_Quad_ChipSelect_t peripheral_Protection_Status(void);
+void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+peripheral_Quad_ChipSelect_t peripheral_Powerdown_Status(void);
+
+void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+peripheral_Memory_ChipSelect_t peripheral_Memory_Protection_Status(void);
+void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+peripheral_Memory_ChipSelect_t Periipheral_Memory_Powerdown_Status(void);
+
+void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+
+/**@}*/
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/sys_pmm.h b/bsp/rm48x50/HALCoGen/include/sys_pmm.h
new file mode 100644
index 0000000000000000000000000000000000000000..1e0b791e32ff95c30ac4374f041b70294fce1dc4
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_pmm.h
@@ -0,0 +1,141 @@
+/** @file sys_pmm.h
+*   @brief PMM Driver Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __SYS_PMM_H__
+#define __SYS_PMM_H__
+
+#include "reg_pmm.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Bit Masks */
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON0      (0xFU << 24U)		/*PD2*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON1      (0xFU << 16U)		/*PD3*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON2      (0xFU << 8U)		/*PD4*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON3      (0xFU << 0U)		/*PD5*/
+
+#define PMM_MEMPDPWRCTRL0_MEMPDON0          (0xFU << 24U)		/*RAM_PD1*/
+#define PMM_MEMPDPWRCTRL0_MEMPDON1          (0xFU << 16U)		/*RAM_PD2*/
+#define PMM_MEMPDPWRCTRL0_MEMPDON2          (0xFU << 8U)		/*RAM_PD3*/
+
+#define PMM_LOGICPDPWRSTAT_DOMAINON	        (1U << 8U)
+#define PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT	(0x3U << 0U)
+#define PMM_MEMPDPWRSTAT_DOMAINON	        (1U << 8U)
+#define PMM_MEMPDPWRSTAT_MEMPDPWRSTAT    	(0x3U << 0U)
+#define PMM_GLOBALCTRL1_AUTOCLKWAKEENA	    (1U << 0U)
+
+/* Configuration registers initial value */
+#define PMM_LOGICPDPWRCTRL0_CONFIGVALUE   (((1U)?0x5U:0xAU) << 24U) \
+										| (((1U)?0x5U:0xAU) << 16U) \
+										| (((0U)?0x5U:0xAU) << 8U)  \
+										| (((1U)?0x5U:0xAU) << 0U)
+
+#define PMM_MEMPDPWRCTRL0_CONFIGVALUE 	  (((1U)?0x5U:0xAU) << 24U) \
+										| (((1U)?0x5U:0xAU) << 16U) \
+										| (((1U)?0x5U:0xAU) << 8U)
+
+#define PMM_PDCLKDISREG_CONFIGVALUE		  ((!1U) << 0U)\
+										| ((!1U) << 1U)\
+										| ((!0U) << 2U)\
+										| ((!1U) << 3U)
+
+#define PMM_GLOBALCTRL1_CONFIGVALUE		(0U << 8U) | (0U << 0U)
+
+
+/** @enum pmmLogicPDTag
+*   @brief PMM Logic Power Domain 
+*
+*   Used to define PMM Logic Power Domain
+*/
+typedef enum pmmLogicPDTag
+{
+	PMM_LOGICPD1	= 4U,	/*-- NOT USED*/
+	PMM_LOGICPD2	= 0U,
+	PMM_LOGICPD3	= 1U,
+	PMM_LOGICPD4	= 2U,
+	PMM_LOGICPD5	= 3U
+}pmm_LogicPD_t;
+
+
+/** @enum pmmMemPDTag
+*   @brief PMM Memory-Only Power Domain 
+*
+*   Used to define PMM Memory-Only Power Domain
+*/
+typedef enum pmmMemPDTag
+{
+	PMM_MEMPD1 = 0U,
+	PMM_MEMPD2 = 1U,
+	PMM_MEMPD3 = 2U
+}pmm_MemPD_t;
+
+
+/** @enum pmmModeTag
+*   @brief PSCON operating mode 
+*
+*   Used to define the operating mode of PSCON Compare Block
+*/
+typedef enum pmmModeTag
+{
+	LockStep				= 0x0U,
+	SelfTest				= 0x6U,
+	ErrorForcing			= 0x9U,
+	SelfTestErrorForcing	= 0xFU
+}pmm_Mode_t;
+
+/*Pmm Configuration Registers*/
+typedef struct pmm_config_reg
+{
+	uint32 CONFIG_LOGICPDPWRCTRL0;
+	uint32 CONFIG_MEMPDPWRCTRL0;
+	uint32 CONFIG_PDCLKDISREG;
+	uint32 CONFIG_GLOBALCTRL1;
+}pmm_config_reg_t;
+
+/**
+ * @defgroup PMM PMM
+ * @brief Power Management Module
+ *
+ * The PMM provides memory-mapped registers that control the states of the supported power domains. 
+ * The PMM includes interfaces to the Power Mode Controller (PMC) and the Power State Controller (PSCON). 
+ * The PMC and PSCON control the power up/down sequence of each power domain.
+ *
+ * Related files:
+ * - reg_pmm.h
+ * - sys_pmm.h
+ * - sys_pmm.c
+ *
+ * @addtogroup PMM
+ * @{
+ */
+ 
+/* Pmm Interface Functions */
+void pmmInit(void);
+void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD);
+void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD);
+void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD);
+void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD);
+boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD);
+boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD);
+void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type);
+void pmmSetMode(pmm_Mode_t mode);
+boolean pmmPerformSelfTest(void);
+
+/**@}*/
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#endif
+
diff --git a/bsp/rm48x50/HALCoGen/include/sys_pmu.h b/bsp/rm48x50/HALCoGen/include/sys_pmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..19e65c078c29459ffef36a88d8f6b93d5a17110b
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_pmu.h
@@ -0,0 +1,191 @@
+/** @file sys_pmu.h
+*   @brief System Pmu Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Pmu Interface Functions
+*   .
+*   which are relevant for the performance monitor unit driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __SYS_PMU_H__
+#define __SYS_PMU_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def pmuCOUNTER0
+*   @brief pmu event counter 0
+*
+*   Alias for pmu event counter 0
+*/
+#define pmuCOUNTER0 0x00000001U
+
+/** @def pmuCOUNTER1
+*   @brief pmu event counter 1
+*
+*   Alias for pmu event counter 1
+*/
+#define pmuCOUNTER1 0x00000002U
+
+/** @def pmuCOUNTER2
+*   @brief pmu event counter 2
+*
+*   Alias for pmu event counter 2
+*/
+#define pmuCOUNTER2 0x00000004U
+
+/** @def pmuCYCLE_COUNTER
+*   @brief pmu cycle counter
+*
+*   Alias for pmu event counter
+*/
+#define pmuCYCLE_COUNTER 0x80000000U
+
+/** @enum pmuEvent
+*   @brief pmu event
+*
+*   Alias for pmu event counter increment source
+*/
+enum pmuEvent
+{
+    PMU_INST_CACHE_MISS                     = 0x01U,
+    PMU_DATA_CACHE_MISS                     = 0x03U,
+    PMU_DATA_CACHE_ACCESS                   = 0x04U,
+    PMU_DATA_READ_ARCH_EXECUTED             = 0x06U,
+    PMU_DATA_WRITE_ARCH_EXECUTED            = 0x07U,
+    PMU_INST_ARCH_EXECUTED                  = 0x08U,
+    PMU_EXCEPTION_TAKEN                     = 0x09U,
+    PMU_EXCEPTION_RETURN_ARCH_EXECUTED      = 0x0AU,
+    PMU_CHANGE_TO_CONTEXT_ID_EXECUTED       = 0x0BU,
+    PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED       = 0x0CU,
+    PMU_BRANCH_IMM_INST_ARCH_EXECUTED       = 0x0DU,
+    PMU_PROC_RETURN_ARCH_EXECUTED           = 0x0EU,
+    PMU_UNALIGNED_ACCESS_ARCH_EXECUTED      = 0x0FU,
+    PMU_BRANCH_MISSPREDICTED                = 0x10U,
+    PMU_CYCLE_COUNT                         = 0x11U,
+    PMU_PREDICTABLE_BRANCHES                = 0x12U,
+    PMU_INST_BUFFER_STALL                   = 0x40U,
+    PMU_DATA_DEPENDENCY_INST_STALL          = 0x41U,
+    PMU_DATA_CACHE_WRITE_BACK               = 0x42U,
+    PMU_EXT_MEMORY_REQUEST                  = 0x43U,
+    PMU_LSU_BUSY_STALL                      = 0x44U,
+    PMU_FORCED_DRAIN_OFSTORE_BUFFER         = 0x45U,
+    PMU_FIQ_DISABLED_CYCLE_COUNT            = 0x46U,
+    PMU_IRQ_DISABLED_CYCLE_COUNT            = 0x47U,
+    PMU_ETMEXTOUT_0                         = 0x48U,
+    PMU_ETMEXTOUT_1                         = 0x49U,
+    PMU_INST_CACHE_TAG_ECC_ERROR            = 0x4AU,
+    PMU_INST_CACHE_DATA_ECC_ERROR           = 0x4BU,
+    PMU_DATA_CACHE_TAG_ECC_ERROR            = 0x4CU,
+    PMU_DATA_CACHE_DATA_ECC_ERROR           = 0x4DU,
+    PMU_TCM_FATAL_ECC_ERROR_PREFETCH        = 0x4EU,
+    PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE      = 0x4FU,
+    PMU_STORE_BUFFER_MERGE                  = 0x50U,
+    PMU_LSU_STALL_STORE_BUFFER_FULL         = 0x51U,
+    PMU_LSU_STALL_STORE_QUEUE_FULL          = 0x52U,
+    PMU_INTEGER_DIV_EXECUTED                = 0x53U,
+    PMU_STALL_INTEGER_DIV                   = 0x54U,
+    PMU_PLD_INST_LINE_FILL                  = 0x55U,
+    PMU_PLD_INST_NO_LINE_FILL               = 0x56U,
+    PMU_NON_CACHEABLE_ACCESS_AXI_MASTER     = 0x57U,
+    PMU_INST_CACHE_ACCESS                   = 0x58U,
+    PMU_DOUBLE_DATA_CACHE_ISSUE             = 0x59U,
+    PMU_DUAL_ISSUE_CASE_A                   = 0x5AU,
+    PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D        = 0x5BU,
+    PMU_DUAL_ISSUE_OTHER                    = 0x5CU,
+    PMU_DP_FLOAT_INST_EXCECUTED             = 0x5DU,
+    PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU,
+    PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR     = 0x60U,
+    PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR      = 0x61U,
+    PMU_PROCESSOR_LIVE_LOCK                 = 0x62U,
+    PMU_ATCM_MULTI_BIT_ECC_ERROR            = 0x64U,
+    PMU_B0TCM_MULTI_BIT_ECC_ERROR           = 0x65U,
+    PMU_B1TCM_MULTI_BIT_ECC_ERROR           = 0x66U,
+    PMU_ATCM_SINGLE_BIT_ECC_ERROR           = 0x67U,
+    PMU_B0TCM_SINGLE_BIT_ECC_ERROR          = 0x68U,
+    PMU_B1TCM_SINGLE_BIT_ECC_ERROR          = 0x69U,
+    PMU_TCM_COR_ECC_ERROR_LOAD_STORE        = 0x6AU,
+    PMU_TCM_COR_ECC_ERROR_PREFETCH          = 0x6BU,
+    PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE       = 0x6CU,
+    PMU_TCM_COR_ECC_ERROR_AXI_SLAVE         = 0x6DU
+};
+
+/** @fn void _pmuInit_(void)
+*   @brief Initialize Performance Monitor Unit
+*/
+void _pmuInit_(void);
+
+/** @fn void _pmuEnableCountersGlobal_(void)
+*   @brief Enable and reset cycle counter and all 3 event counters
+*/
+void _pmuEnableCountersGlobal_(void);
+
+/** @fn void _pmuDisableCountersGlobal_(void)
+*   @brief Disable cycle counter and all 3 event counters
+*/
+void _pmuDisableCountersGlobal_(void);
+
+/** @fn void _pmuResetCycleCounter_(void)
+*   @brief Reset cycle counter
+*/
+void _pmuResetCycleCounter_(void);
+
+/** @fn void _pmuResetEventCounters_(void)
+*   @brief Reset event counters 0-2
+*/
+void _pmuResetEventCounters_(void);
+
+/** @fn void _pmuResetCounters_(void)
+*   @brief Reset cycle counter and event counters 0-2
+*/
+void _pmuResetCounters_(void);
+
+/** @fn void _pmuStartCounters_(uint32 counters)
+*   @brief Starts selected counters
+*   @param[in] counters - Counter mask
+*/
+void _pmuStartCounters_(uint32 counters);
+
+/** @fn void _pmuStopCounters_(uint32 counters)
+*   @brief Stops selected counters
+*   @param[in] counters - Counter mask
+*/
+void _pmuStopCounters_(uint32 counters);
+
+/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event)
+*   @brief Set event counter count event
+*   @param[in] counter - Counter select 0..2
+*   @param[in] event   - Count event
+*/
+void _pmuSetCountEvent_(uint32 counter, uint32 event);
+
+/** @fn uint32 _pmuGetCycleCount_(void)
+*   @brief Returns current cycle counter value
+*
+*   @return cycle count.
+*/
+uint32 _pmuGetCycleCount_(void);
+
+/** @fn uint32 _pmuGetEventCount_(uint32 counter)
+*   @brief Returns current event counter value
+*   @param[in] counter - Counter select 0..2
+*
+*   @return event counter count.
+*/
+uint32 _pmuGetEventCount_(uint32 counter);
+
+/** @fn uint32 _pmuGetOverflow_(void)
+*   @brief Returns current overflow register and clear flags
+*
+*   @return overflow flags.
+*/
+uint32 _pmuGetOverflow_(void);
+
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/sys_selftest.h b/bsp/rm48x50/HALCoGen/include/sys_selftest.h
new file mode 100644
index 0000000000000000000000000000000000000000..86d9b3f76d6ecfef690856a7e8df1998f14fad51
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_selftest.h
@@ -0,0 +1,387 @@
+/** @file sys_selftest.h
+*   @brief System Memory Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Efuse Self Test Functions
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __sys_selftest_H__
+#define __sys_selftest_H__
+
+#include "reg_pbist.h"
+#include "reg_stc.h"
+#include "reg_efc.h"
+#include "sys_core.h"
+#include "system.h"
+#include "sys_vim.h"
+#include "adc.h"
+#include "can.h"
+#include "mibspi.h"
+#include "het.h"
+#include "htu.h"
+#include "esm.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#define flash1bitError	(*(volatile uint32 *)(0xF00803F0U))
+#define flash2bitError	(*(volatile uint32 *)(0xF00803F8U))
+
+#define tcramA1bitError	(*(volatile uint32 *)(0x08400000U))
+#define tcramA2bitError (*(volatile uint32 *)(0x08400010U))
+
+#define tcramB1bitError	(*(volatile uint32 *)(0x08400008U))
+#define tcramB2bitError (*(volatile uint32 *)(0x08400018U))
+
+#define tcramA1bit		(*(volatile uint32 *)(0x08000000U))
+#define tcramA2bit		(*(volatile uint32 *)(0x08000010U))
+
+#define tcramB1bit		(*(volatile uint32 *)(0x08000008U))
+#define tcramB2bit		(*(volatile uint32 *)(0x08000018U))
+
+#define flashBadECC		(*(volatile uint32 *)(0x20040000U))
+
+#define CCMSR 			(*(volatile uint32 *)(0xFFFFF600U))
+#define CCMKEYR			(*(volatile uint32 *)(0xFFFFF604U))
+
+
+#define DMA_PARCR		(*(volatile uint32 *)(0xFFFFF1A8U))
+#define DMA_PARADDR		(*(volatile uint32 *)(0xFFFFF1ACU))
+
+#define DMARAMLOC		(*(volatile uint32 *)(0xFFF80000U))
+#define DMARAMPARLOC	(*(volatile uint32 *)(0xFFF80A00U))
+
+
+#ifndef __PBIST_H__
+#define __PBIST_H__
+
+/** @enum pbistPort
+*   @brief Alias names for pbist Port number
+*
+*   This enumeration is used to provide alias names for the pbist Port number
+*     - PBIST_PORT0
+*     - PBIST_PORT1
+*/
+enum pbistPort
+{
+    PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */
+    PBIST_PORT1 = 1U  /**< Alias for PBIST Port 1 */
+};
+/** @enum pbistAlgo
+*   @brief Alias names for pbist Algorithm
+*
+*   This enumeration is used to provide alias names for the pbist Algorithm
+*     - PBIST_TripleReadSlow 
+*     - PBIST_TripleReadFast 
+*     - PBIST_March13N_DP    
+*     - PBIST_March13N_SP    
+*     - PBIST_DOWN1a_DP      
+*     - PBIST_DOWN1a_SP      
+*     - PBIST_MapColumn_DP   
+*     - PBIST_MapColumn_SP   
+*     - PBIST_Precharge_DP   
+*     - PBIST_Precharge_SP   
+*     - PBIST_DTXN2a_DP      
+*     - PBIST_DTXN2a_SP      
+*     - PBIST_PMOSOpen_DP    
+*     - PBIST_PMOSOpen_SP    
+*     - PBIST_PPMOSOpenSlice1_DP
+*     - PBIST_PPMOSOpenSlice1_SP
+*     - PBIST_PPMOSOpenSlice2_DP
+*     - PBIST_PPMOSOpenSlice2_SP
+
+*/
+enum pbistAlgo
+{
+    PBIST_TripleReadSlow     = 0x00000001U,
+    PBIST_TripleReadFast     = 0x00000002U,
+    PBIST_March13N_DP        = 0x00000004U,
+	PBIST_March13N_SP        = 0x00000008U,
+    PBIST_DOWN1a_DP          = 0x00000010U,
+	PBIST_DOWN1a_SP          = 0x00000020U,
+    PBIST_MapColumn_DP       = 0x00000040U,
+	PBIST_MapColumn_SP       = 0x00000080U,
+    PBIST_Precharge_DP       = 0x00000100U,
+	PBIST_Precharge_SP       = 0x00000200U,
+    PBIST_DTXN2a_DP          = 0x00000400U,
+	PBIST_DTXN2a_SP          = 0x00000800U,
+	PBIST_PMOSOpen_DP        = 0x00001000U,
+    PBIST_PMOSOpen_SP        = 0x00002000U,
+	PBIST_PPMOSOpenSlice1_DP = 0x00004000U,
+    PBIST_PPMOSOpenSlice1_SP = 0x00008000U,
+	PBIST_PPMOSOpenSlice2_DP = 0x00010000U,
+    PBIST_PPMOSOpenSlice2_SP = 0x00020000U
+};
+/* PBIST configuration registers */
+typedef struct pbist_config_reg
+{
+    uint32 CONFIG_RAMT;
+    uint32 CONFIG_DLR;
+    uint32 CONFIG_PACT;
+    uint32 CONFIG_PBISTID;
+    uint32 CONFIG_OVER;
+    uint32 CONFIG_FSRDL1;
+    uint32 CONFIG_ROM;
+    uint32 CONFIG_ALGO;
+    uint32 CONFIG_RINFOL;
+    uint32 CONFIG_RINFOU;
+} pbist_config_reg_t;
+
+/* PBIST congiruration registers initial value */
+#define PBIST_RAMT_CONFIGVALUE 0U
+#define PBIST_DLR_CONFIGVALUE 0U
+#define PBIST_PACT_CONFIGVALUE 0U
+#define PBIST_PBISTID_CONFIGVALUE 0U
+#define PBIST_OVER_CONFIGVALUE 0U
+#define PBIST_FSRDL1_CONFIGVALUE 0U
+#define PBIST_ROM_CONFIGVALUE 0U
+#define PBIST_ALGO_CONFIGVALUE 0U
+#define PBIST_RINFOL_CONFIGVALUE 0U
+#define PBIST_RINFOU_CONFIGVALUE 0U
+
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
+*   @brief Memory Port 0 test fail notification
+*   @param[in] groupSelect Failing Ram group select:
+*   @param[in] dataSelect Failing Ram data select:
+*   @param[in] address Failing Ram offset:
+*   @param[in] data Failing data at address:
+*
+*   @note This function has to be provide by the user.
+*/
+void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data);
+
+/** @fn void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
+*   @brief Memory Port 1 test fail notification
+*   @param[in] groupSelect Failing Ram group select:
+*   @param[in] dataSelect Failing Ram data select:
+*   @param[in] address Failing Ram offset:
+*   @param[in] data Failing data at address:
+*
+*   @note This function has to be provide by the user.
+*/
+void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data);
+
+void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type);
+#endif
+
+#ifndef __STC_H__
+#define __STC_H__
+
+/* STC General Definitions */
+
+/* STC Test Intervals supported in the Device */
+#define STC_INTERVAL 24U
+#define STC_MAX_TIMEOUT 0xFFFFFFFFU
+
+
+
+/* Configuration registers */
+typedef struct stc_config_reg
+{
+	uint32 CONFIG_STCGCR0;
+    uint32 CONFIG_STCGCR1;
+    uint32 CONFIG_STCTPR;
+    uint32 CONFIG_STCSCSCR;
+} stc_config_reg_t;
+
+/* Configuration registers initial value */
+#define STC_STCGCR0_CONFIGVALUE	0xFFFF0000U
+#define STC_STCGCR1_CONFIGVALUE	0x5U
+#define STC_STCTPR_CONFIGVALUE	0xFFFFFFFFU
+#define STC_STCSCSCR_CONFIGVALUE 0x5U
+
+void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type);
+
+#endif
+
+#ifndef __EFC_H__
+#define __EFC_H__
+
+#define INPUT_ENABLE         0x0000000FU
+#define INPUT_DISABLE        0x00000000U
+
+#define SYS_WS_READ_STATES   0x00000000U
+
+
+#define SYS_REPAIR_EN_0      0x00000000U
+#define SYS_REPAIR_EN_3      0x00000100U
+#define SYS_REPAIR_EN_5      0x00000200U
+
+#define SYS_DEID_AUTOLOAD_EN 0x00000400U
+
+#define EFC_FDI_EN            0x00000800U
+#define EFC_FDI_DIS           0x00000000U
+
+#define SYS_ECC_OVERRIDE_EN   0x00001000U
+#define SYS_ECC_OVERRIDE_DIS  0x00000000U
+
+#define SYS_ECC_SELF_TEST_EN  0x00002000U
+#define SYS_ECC_SELF_TEST_DIS 0x00000000U
+
+#define OUTPUT_ENABLE         0x0003C000U
+#define OUTPUT_DISABLE        0x00000000U
+
+/*********** OUTPUT **************/
+
+#define EFC_AUTOLOAD_ERROR_EN    0x00040000U
+#define EFC_INSTRUCTION_ERROR_EN 0x00080000U
+#define EFC_INSTRUCTION_INFO_EN  0x00100000U
+#define EFC_SELF_TEST_ERROR_EN   0x00200000U
+
+
+#define EFC_AUTOLOAD_ERROR_DIS    0x00000000U
+#define EFC_INSTRUCTION_ERROR_DIS 0x00000000U
+#define EFC_INSTRUCTION_INFO_DIS  0x00000000U
+#define EFC_SELF_TEST_ERROR_DIS   0x00000000U
+
+#define DISABLE_READ_ROW0         0x00800000U
+
+/********************************************************************/
+
+#define SYS_REPAIR_0         0x00000010U
+#define SYS_REPAIR_3         0x00000010U
+#define SYS_REPAIR_5         0x00000020U
+
+#define SYS_DEID_AUTOLOAD    0x00000040U
+#define SYS_FCLRZ            0x00000080U
+#define EFC_READY            0x00000100U
+#define SYS_ECC_OVERRIDE     0x00000200U
+#define EFC_AUTOLOAD_ERROR   0x00000400U
+#define EFC_INSTRUCTION_ERROR 0x00000800U
+#define EFC_INSTRUCTION_INFO  0x00001000U
+#define SYS_ECC_SELF_TEST    0x00002000U
+#define EFC_SELF_TEST_ERROR  0x00004000U
+#define EFC_SELF_TEST_DONE   0x00008000U
+
+/**************   0x3C error status register ******************************************************/
+
+#define TIME_OUT 0x01
+#define AUTOLOAD_NO_FUSEROM_DATA      0x02U 
+#define AUTOLOAD_SIGN_FAIL            0x03U
+#define AUTOLOAD_PROG_INTERRUPT       0x04U
+#define AUTOLOAD_TWO_BIT_ERR          0x05U
+#define PROGRAME_WR_P_SET             0x06U
+#define PROGRAME_MNY_DATA_ITERTN      0x07U
+#define PROGRAME_MNY_CNTR_ITERTN      0x08U
+#define UN_PROGRAME_BIT_SET           0x09U
+#define REDUNDANT_REPAIR_ROW          0x0AU
+#define PROGRAME_MNY_CRA_ITERTN       0x0BU
+#define PROGRAME_SAME_DATA            0x0CU
+#define PROGRAME_CMP_SKIP			  0x0DU
+#define PROGRAME_ABORT                0x0EU
+#define PROGRAME_INCORRECT_KEY		  0x0FU
+#define FUSEROM_LASTROW_STUCK		  0x10U
+#define AUTOLOAD_SINGLE_BIT_ERR		  0x15U
+#define DUMPWORD_TWO_BIT_ERR	      0x16U
+#define DUMPWORD_ONE_BIT_ERR          0x17U
+#define SELF_TEST_ERROR               0x18U
+
+#define INSTRUCTION_DONE              0x20U
+
+/**************   Efuse Instruction set ******************************************************/
+
+#define TEST_UNPROGRAME_ROM  0x01000000U
+#define PROGRAME_CRA         0x02000000U 
+#define DUMP_WORD            0x04000000U
+#define LOAD_FUSE_SCAN_CHAIN 0x05000000U
+#define PROGRAME_DATA        0x07000000U
+#define RUN_AUTOLOAD_8       0x08000000U
+#define RUN_AUTOLOAD_A       0x0A000000U
+
+/* Configuration registers */
+typedef struct efc_config_reg
+{
+	uint32 CONFIG_BOUNDARY;
+	uint32 CONFIG_PINS;
+	uint32 CONFIG_SELFTESTCYCLES;
+	uint32 CONFIG_SELFTESTSIGN;
+}efc_config_reg_t;
+
+/* Configuration registers initial value */
+#define EFC_BOUNDARY_CONFIGVALUE	0x0000200FU
+#define EFC_PINS_CONFIGVALUE		0x000082E0U
+#define EFC_SELFTESTCYCLES_CONFIGVALUE	0x00000258U
+#define EFC_SELFTESTSIGN_CONFIGVALUE	0x5362F97FU
+
+void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type);
+#endif
+
+/* safety Init Interface Functions */
+void ccmSelfCheck(void);
+void ccmFail(uint32 x);
+
+void stcSelfCheck(void);
+void stcSelfCheckFail(void);
+void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test);
+void cpuSelfTestFail(void);
+
+void memoryInit(uint32 ram);
+
+void pbistSelfCheck(void);
+void pbistRun(uint32 raminfoL, uint32 algomask);
+void pbistStop(void);
+void pbistSelfCheckFail(void);
+boolean pbistIsTestCompleted(void);
+boolean pbistIsTestPassed(void);
+boolean pbistPortTestStatus(uint32 port);
+
+void efcCheck(void);
+void efcSelfTest(void);
+boolean efcStuckZeroTest(void);
+boolean checkefcSelfTest(void);
+void efcClass1Error(void);
+void efcClass2Error(void);
+
+void fmcBus2Check(void);
+void fmcECCcheck(void);
+void fmcClass1Error(void);
+void fmcClass2Error(void);
+
+void checkB0RAMECC(void);
+void checkB1RAMECC(void);
+void tcramClass1Error(void);
+void tcramClass2Error(void);
+
+void checkFlashECC(void);
+void flashClass1Error(void);
+void flashClass2Error(void);
+
+void vimParityCheck(void);
+void dmaParityCheck(void);
+void adc1ParityCheck(void);
+void adc2ParityCheck(void);
+void het1ParityCheck(void);
+void htu1ParityCheck(void);
+void het2ParityCheck(void);
+void htu2ParityCheck(void);
+void can1ParityCheck(void);
+void can2ParityCheck(void);
+void can3ParityCheck(void);
+void mibspi1ParityCheck(void);
+void mibspi3ParityCheck(void);
+void mibspi5ParityCheck(void);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/* Configuration registers */
+typedef struct ccmr4_config_reg
+{
+	uint32 CONFIG_CCMKEYR;
+}ccmr4_config_reg_t;
+
+/* Configuration registers initial value */
+#define CCMR4_CCMKEYR_CONFIGVALUE	0U
+
+void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type);
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/sys_vim.h b/bsp/rm48x50/HALCoGen/include/sys_vim.h
new file mode 100644
index 0000000000000000000000000000000000000000..ada653e630ad3db0ba96e84d5691d19c8dd49210
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/sys_vim.h
@@ -0,0 +1,400 @@
+/** @file sys_vim.h
+*   @brief Vectored Interrupt Module Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - VIM Type Definitions
+*   - VIM General Definitions
+*   .
+*   which are relevant for Vectored Interrupt Controller.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __SYS_VIM_H__
+#define __SYS_VIM_H__
+
+#include "reg_vim.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* VIM Type Definitions */
+
+/** @typedef t_isrFuncPTR
+*   @brief ISR Function Pointer Type Definition
+*
+*   This type is used to access the ISR handler.
+*/
+typedef void (*t_isrFuncPTR)(void);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* VIM General Configuration */
+
+#define VIM_CHANNELS 96U
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/* Interrupt Handlers */
+
+extern void esmHighInterrupt(void);
+extern void phantomInterrupt(void);
+extern void rtiCompare3Interrupt(void);
+extern void linHighLevelInterrupt(void);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+#define VIM_PARFLG		(*(volatile uint32 *)0xFFFFFDECU)
+#define VIM_PARCTL		(*(volatile uint32 *)0xFFFFFDF0U)
+#define VIM_ADDERR		(*(volatile uint32 *)0xFFFFFDF4U)
+#define VIM_FBPARERR	(*(volatile uint32 *)0xFFFFFDF8U)
+
+#define VIMRAMPARLOC	(*(volatile uint32 *)0xFFF82400U)
+#define VIMRAMLOC		(*(volatile uint32 *)0xFFF82000U)
+
+/* Configuration registers */
+typedef struct vim_config_reg
+{
+    uint32 CONFIG_FIRQPR0;
+    uint32 CONFIG_FIRQPR1;
+    uint32 CONFIG_FIRQPR2;
+    uint32 CONFIG_FIRQPR3;
+    uint32 CONFIG_REQMASKSET0;
+    uint32 CONFIG_REQMASKSET1;
+    uint32 CONFIG_REQMASKSET2;
+    uint32 CONFIG_REQMASKSET3;
+    uint32 CONFIG_WAKEMASKSET0;
+    uint32 CONFIG_WAKEMASKSET1;
+    uint32 CONFIG_WAKEMASKSET2;
+    uint32 CONFIG_WAKEMASKSET3;
+    uint32 CONFIG_CAPEVT;
+    uint32 CONFIG_CHANCTRL[24U];
+} vim_config_reg_t;
+
+/* Configuration registers initial value */
+#define VIM_FIRQPR0_CONFIGVALUE	SYS_FIQ\
+                    | (SYS_FIQ <<  1U)\
+                    | (SYS_IRQ <<  2U)\
+                    | (SYS_IRQ <<  3U)\
+                    | (SYS_IRQ <<  4U)\
+                    | (SYS_IRQ <<  5U)\
+                    | (SYS_IRQ <<  6U)\
+                    | (SYS_IRQ <<  7U)\
+                    | (SYS_IRQ <<  8U)\
+                    | (SYS_IRQ <<  9U)\
+                    | (SYS_IRQ << 10U)\
+                    | (SYS_IRQ << 11U)\
+                    | (SYS_IRQ << 12U)\
+                    | (SYS_IRQ << 13U)\
+                    | (SYS_IRQ << 14U)\
+                    | (SYS_IRQ << 15U)\
+                    | (SYS_IRQ << 16U)\
+                    | (SYS_IRQ << 17U)\
+                    | (SYS_IRQ << 18U)\
+                    | (SYS_IRQ << 19U)\
+                    | (SYS_IRQ << 20U)\
+                    | (SYS_IRQ << 21U)\
+                    | (SYS_IRQ << 22U)\
+                    | (SYS_IRQ << 23U)\
+                    | (SYS_IRQ << 24U)\
+                    | (SYS_IRQ << 25U)\
+                    | (SYS_IRQ << 26U)\
+                    | (SYS_IRQ << 27U)\
+                    | (SYS_IRQ << 28U)\
+                    | (SYS_IRQ << 29U)\
+                    | (SYS_IRQ << 30U)\
+                    | (SYS_IRQ << 31U)
+					
+#define VIM_FIRQPR1_CONFIGVALUE	SYS_IRQ\
+                    | (SYS_IRQ <<  1U)\
+                    | (SYS_IRQ <<  2U)\
+                    | (SYS_IRQ <<  3U)\
+                    | (SYS_IRQ <<  4U)\
+                    | (SYS_IRQ <<  5U)\
+                    | (SYS_IRQ <<  6U)\
+                    | (SYS_IRQ <<  7U)\
+                    | (SYS_IRQ <<  8U)\
+                    | (SYS_IRQ <<  9U)\
+                    | (SYS_IRQ << 10U)\
+                    | (SYS_IRQ << 11U)\
+                    | (SYS_IRQ << 12U)\
+                    | (SYS_IRQ << 13U)\
+                    | (SYS_IRQ << 14U)\
+                    | (SYS_IRQ << 15U)\
+                    | (SYS_IRQ << 16U)\
+                    | (SYS_IRQ << 17U)\
+                    | (SYS_IRQ << 18U)\
+                    | (SYS_IRQ << 19U)\
+                    | (SYS_IRQ << 20U)\
+                    | (SYS_IRQ << 21U)\
+                    | (SYS_IRQ << 22U)\
+                    | (SYS_IRQ << 23U)\
+                    | (SYS_IRQ << 24U)\
+                    | (SYS_IRQ << 25U)\
+                    | (SYS_IRQ << 26U)\
+                    | (SYS_IRQ << 27U)\
+                    | (SYS_IRQ << 28U)\
+                    | (SYS_IRQ << 29U)\
+                    | (SYS_IRQ << 30U)\
+                    | (SYS_IRQ << 31U)
+					
+#define VIM_FIRQPR2_CONFIGVALUE	SYS_IRQ\
+                    | (SYS_IRQ << 1U)\
+                    | (SYS_IRQ << 2U)\
+                    | (SYS_IRQ << 3U)\
+                    | (SYS_IRQ << 4U)\
+                    | (SYS_IRQ << 5U)\
+                    | (SYS_IRQ << 6U)\
+                    | (SYS_IRQ << 7U)\
+                    | (SYS_IRQ << 8U)\
+                    | (SYS_IRQ << 9U)\
+                    | (SYS_IRQ << 10U)\
+                    | (SYS_IRQ << 11U)\
+                    | (SYS_IRQ << 12U)\
+                    | (SYS_IRQ << 13U)\
+                    | (SYS_IRQ << 14U)\
+                    | (SYS_IRQ << 15U)\
+                    | (SYS_IRQ << 16U)\
+                    | (SYS_IRQ << 17U)\
+                    | (SYS_IRQ << 18U)\
+                    | (SYS_IRQ << 19U)\
+                    | (SYS_IRQ << 20U)\
+                    | (SYS_IRQ << 21U)\
+                    | (SYS_IRQ << 22U)\
+                    | (SYS_IRQ << 23U)\
+                    | (SYS_IRQ << 24U)\
+                    | (SYS_IRQ << 25U)\
+					| (SYS_IRQ << 26U)\
+                    | (SYS_IRQ << 27U)\
+                    | (SYS_IRQ << 28U)\
+                    | (SYS_IRQ << 29U)\
+                    | (SYS_IRQ << 30U)\
+                    | (SYS_IRQ << 31U)
+					
+#define VIM_FIRQPR3_CONFIGVALUE	SYS_IRQ\
+                    | (SYS_IRQ << 1U)\
+                    | (SYS_IRQ << 2U)\
+                    | (SYS_IRQ << 3U)\
+                    | (SYS_IRQ << 4U)\
+                    | (SYS_IRQ << 5U)\
+                    | (SYS_IRQ << 6U)\
+                    | (SYS_IRQ << 7U)\
+                    | (SYS_IRQ << 8U)\
+                    | (SYS_IRQ << 9U)\
+                    | (SYS_IRQ << 10U)\
+                    | (SYS_IRQ << 11U)\
+                    | (SYS_IRQ << 12U)\
+                    | (SYS_IRQ << 13U)\
+                    | (SYS_IRQ << 14U)\
+                    | (SYS_IRQ << 15U)\
+                    | (SYS_IRQ << 16U)\
+                    | (SYS_IRQ << 17U)\
+                    | (SYS_IRQ << 18U)\
+                    | (SYS_IRQ << 19U)\
+                    | (SYS_IRQ << 20U)\
+                    | (SYS_IRQ << 21U)\
+                    | (SYS_IRQ << 22U)\
+                    | (SYS_IRQ << 23U)\
+                    | (SYS_IRQ << 24U)\
+                    | (SYS_IRQ << 25U)\
+					| (SYS_IRQ << 26U)\
+                    | (SYS_IRQ << 27U)\
+                    | (SYS_IRQ << 28U)\
+                    | (SYS_IRQ << 29U)\
+                    | (SYS_IRQ << 30U)\
+                    | (SYS_IRQ << 31U)
+					
+#define VIM_REQMASKSET0_CONFIGVALUE	1U\
+                        | (1U << 1U)\
+                        | (0U << 2U)\
+                        | (0U << 3U)\
+                        | (0U << 4U)\
+                        | (1U << 5U)\
+                        | (0U << 6U)\
+                        | (0U << 7U)\
+                        | (0U << 8U)\
+                        | (0U << 9U)\
+                        | (0U << 10U)\
+                        | (0U << 11U)\
+                        | (0U << 12U)\
+                        | (1U << 13U)\
+                        | (0U << 14U)\
+                        | (0U << 15U)\
+                        | (0U << 16U)\
+                        | (0U << 17U)\
+                        | (0U << 18U)\
+                        | (0U << 19U)\
+                        | (0U << 20U)\
+                        | (0U << 21U)\
+                        | (0U << 22U)\
+                        | (0U << 23U)\
+                        | (0U << 24U)\
+                        | (0U << 25U)\
+                        | (0U << 26U)\
+                        | (0U << 27U)\
+                        | (0U << 28U)\
+                        | (0U << 29U)\
+                        | (0U << 30U)\
+                        | (0U << 31U)
+						
+#define VIM_REQMASKSET1_CONFIGVALUE	0U\
+                        | (0U << 1U)\
+                        | (0U << 2U)\
+                        | (0U << 3U)\
+                        | (0U << 4U)\
+                        | (0U << 5U)\
+                        | (0U << 6U)\
+                        | (0U << 7U)\
+                        | (0U << 8U)\
+                        | (0U << 9U)\
+                        | (0U << 10U)\
+                        | (0U << 11U)\
+                        | (0U << 12U)\
+                        | (0U << 13U)\
+                        | (0U << 14U)\
+                        | (0U << 15U)\
+                        | (0U << 16U)\
+                        | (0U << 17U)\
+                        | (0U << 18U)\
+                        | (0U << 19U)\
+                        | (0U << 20U)\
+                        | (0U << 21U)\
+                        | (0U << 22U)\
+                        | (0U << 23U)\
+                        | (0U << 24U)\
+                        | (0U << 25U)\
+                        | (0U << 26U)\
+                        | (0U << 27U)\
+                        | (0U << 28U)\
+                        | (0U << 29U)\
+                        | (0U << 30U)\
+                        | (0U << 31U)
+						
+#define VIM_REQMASKSET2_CONFIGVALUE	0U\
+                        | (0U << 1U)\
+                        | (0U << 2U)\
+                        | (0U << 3U)\
+                        | (0U << 4U)\
+                        | (0U << 5U)\
+                        | (0U << 6U)\
+                        | (0U << 7U)\
+                        | (0U << 8U)\
+                        | (0U << 9U)\
+                        | (0U << 10U)\
+                        | (0U << 11U)\
+                        | (0U << 12U)\
+                        | (0U << 13U)\
+                        | (0U << 14U)\
+                        | (0U << 15U)\
+                        | (0U << 16U)\
+                        | (0U << 17U)\
+                        | (0U << 18U)\
+                        | (0U << 19U)\
+                        | (0U << 20U)\
+                        | (0U << 21U)\
+                        | (0U << 22U)\
+                        | (0U << 23U)\
+                        | (0U << 24U)\
+                        | (0U << 25U)\
+					    | (0U << 26U)\
+                        | (0U << 27U)\
+                        | (0U << 28U)\
+                        | (0U << 29U)\
+                        | (0U << 30U)\
+                        | (0U << 31U)
+						
+#define VIM_REQMASKSET3_CONFIGVALUE	0U\
+                        | (0U << 1U)\
+                        | (0U << 2U)\
+                        | (0U << 3U)\
+                        | (0U << 4U)\
+                        | (0U << 5U)\
+                        | (0U << 6U)\
+                        | (0U << 7U)\
+                        | (0U << 8U)\
+                        | (0U << 9U)\
+                        | (0U << 10U)\
+                        | (0U << 11U)\
+                        | (0U << 12U)\
+                        | (0U << 13U)\
+                        | (0U << 14U)\
+                        | (0U << 15U)\
+                        | (0U << 16U)\
+                        | (0U << 17U)\
+                        | (0U << 18U)\
+                        | (0U << 19U)\
+                        | (0U << 20U)\
+                        | (0U << 21U)\
+                        | (0U << 22U)\
+                        | (0U << 23U)\
+                        | (0U << 24U)\
+                        | (0U << 25U)\
+						| (0U << 26U)\
+                        | (0U << 27U)\
+                        | (0U << 28U)\
+                        | (0U << 29U)\
+                        | (0U << 30U)\
+                        | (0U << 31U)
+						
+#define VIM_WAKEMASKSET0_CONFIGVALUE	0xFFFFFFFFU
+#define VIM_WAKEMASKSET1_CONFIGVALUE	0xFFFFFFFFU
+#define VIM_WAKEMASKSET2_CONFIGVALUE	0xFFFFFFFFU
+#define VIM_WAKEMASKSET3_CONFIGVALUE	0U
+#define VIM_CAPEVT_CONFIGVALUE	    	0U
+
+#define VIM_CHANCTRL_CONFIGVALUE	{0x00010203U,\
+	0x04050607U,\
+	0x08090A0BU,\
+	0x0C0D0E0FU,\
+	0x10111213U,\
+	0x14151617U,\
+	0x18191A1BU,\
+	0x1C1D1E1FU,\
+	0x20212223U,\
+	0x24252627U,\
+	0x28292A2BU,\
+	0x2C2D2E2FU,\
+	0x30313233U,\
+	0x34353637U,\
+	0x38393A3BU,\
+	0x3C3D3E3FU,\
+	0x40414243U,\
+	0x44454647U,\
+	0x48494A4BU,\
+	0x4C4D4E4FU,\
+	0x50515253U,\
+	0x54555657U,\
+	0x58595A5BU,\
+	0x5C5D5E5FU}
+
+/**
+ * @defgroup VIM VIM
+ * @brief Vectored Interrupt Manager
+ *
+ * The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
+ * many interrupt sources present on a device. Interrupts are caused by events outside of the normal flow of
+ * program execution.
+ *
+ * Related files:
+ * - reg_vim.h
+ * - sys_vim.h
+ * - sys_vim.c
+ *
+ * @addtogroup VIM
+ * @{
+ */
+/*VIM Interface functions*/
+void vimInit(void);
+void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler);
+void vimEnableInterrupt(uint32 channel, boolean inttype);
+void vimDisableInterrupt(uint32 channel);
+void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type);
+/*@}*/
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/system.h b/bsp/rm48x50/HALCoGen/include/system.h
new file mode 100644
index 0000000000000000000000000000000000000000..eca940457e755d900b58a8716c9fd2797d90281c
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/system.h
@@ -0,0 +1,465 @@
+/** @file system.h
+*   @brief System Driver Header File
+*   @date 29.May.2013
+*   @version 03.05.02
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#ifndef __SYS_SYSTEM_H__
+#define __SYS_SYSTEM_H__
+
+#include "reg_system.h"
+#include "reg_flash.h"
+#include "reg_tcram.h"
+#include "gio.h"
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* System General Definitions */
+
+/** @enum systemInterrupt
+*   @brief Alias names for clock sources
+*
+*   This enumeration is used to provide alias names for the clock sources:
+*     - IRQ
+*     - FIQ
+*/
+enum systemInterrupt
+{
+    SYS_IRQ, /**< Alias for IRQ interrupt */
+    SYS_FIQ  /**< Alias for FIQ interrupt */
+};
+
+/** @enum systemClockSource
+*   @brief Alias names for clock sources
+*
+*   This enumeration is used to provide alias names for the clock sources:
+*     - Oscillator
+*     - Pll1
+*     - External1
+*     - Low Power Oscillator Low
+*     - Low Power Oscillator High
+*     - PLL2
+*     - External2
+*     - Synchronous VCLK1
+*/
+enum systemClockSource
+{
+    SYS_OSC       		= 0U,  /**< Alias for oscillator clock Source                */
+    SYS_PLL1      		= 1U,  /**< Alias for Pll1 clock Source                      */
+    SYS_EXTERNAL1  		= 3U,  /**< Alias for external clock Source                  */
+    SYS_LPO_LOW   		= 4U,  /**< Alias for low power oscillator low clock Source  */
+    SYS_LPO_HIGH  		= 5U,  /**< Alias for low power oscillator high clock Source */
+    SYS_PLL2    		= 6U,  /**< Alias for Pll2 clock Source                      */
+    SYS_EXTERNAL2 		= 7U,  /**< Alias for external 2 clock Source                */
+    SYS_VCLK      		= 9U   /**< Alias for synchronous VCLK1 clock Source         */
+};
+
+#define SYS_DOZE_MODE        0x000F3F02U
+#define SYS_SNOOZE_MODE      0x000F3F03U
+#define SYS_SLEEP_MODE       0x000FFFFFU
+#define LPO_TRIM_VALUE       (((*(volatile uint32   *)0xF00801B4U) & 0xFFFF0000U)>>16U)
+#define SYS_EXCEPTION        (*(volatile uint32   *)0xFFFFFFE4U)
+
+#define POWERON_RESET        0x8000U
+#define OSC_FAILURE_RESET    0x4000U
+#define WATCHDOG_RESET       0x2000U
+#define ICEPICK_RESET        0x2000U
+#define CPU_RESET            0x0020U
+#define SW_RESET             0x0010U
+
+#define WATCHDOG_STATUS     (*(volatile uint32   *)0xFFFFFC98U)
+#define DEVICE_ID_REV       (*(volatile uint32   *)0xFFFFFFF0U)
+
+/** @def OSC_FREQ
+*   @brief Oscillator clock source exported from HALCoGen GUI
+*
+*   Oscillator clock source exported from HALCoGen GUI
+*/
+#define OSC_FREQ     16.0F
+
+/** @def PLL1_FREQ
+*   @brief PLL 1 clock source exported from HALCoGen GUI
+*
+*   PLL 1 clock source exported from HALCoGen GUI
+*/
+#define PLL1_FREQ    200.00F
+
+/** @def LPO_LF_FREQ
+*   @brief LPO Low Freq Oscillator source exported from HALCoGen GUI
+*
+*   LPO Low Freq Oscillator source exported from HALCoGen GUI
+*/
+#define LPO_LF_FREQ  0.080F
+
+/** @def LPO_HF_FREQ
+*   @brief LPO High Freq Oscillator source exported from HALCoGen GUI
+*
+*   LPO High Freq Oscillator source exported from HALCoGen GUI
+*/
+#define LPO_HF_FREQ  10.000F
+
+/** @def PLL1_FREQ
+*   @brief PLL 2 clock source exported from HALCoGen GUI
+*
+*   PLL 2 clock source exported from HALCoGen GUI
+*/
+#define PLL2_FREQ    200.00F
+
+/** @def GCLK_FREQ
+*   @brief GCLK domain frequency exported from HALCoGen GUI
+*
+*   GCLK domain frequency exported from HALCoGen GUI
+*/
+#define GCLK_FREQ    200.000F
+
+/** @def HCLK_FREQ
+*   @brief HCLK domain frequency exported from HALCoGen GUI
+*
+*   HCLK domain frequency exported from HALCoGen GUI
+*/
+#define HCLK_FREQ    200.000F
+
+/** @def RTI_FREQ
+*   @brief RTI Clock frequency exported from HALCoGen GUI
+*
+*   RTI Clock frequency exported from HALCoGen GUI
+*/
+#define RTI_FREQ     100.000F
+
+/** @def AVCLK1_FREQ
+*   @brief AVCLK1 Domain frequency exported from HALCoGen GUI
+*
+*   AVCLK Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK1_FREQ  100.000F
+
+/** @def AVCLK2_FREQ
+*   @brief AVCLK2 Domain frequency exported from HALCoGen GUI
+*
+*   AVCLK2 Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK2_FREQ  100.0F
+
+/** @def AVCLK3_FREQ
+*   @brief AVCLK3 Domain frequency exported from HALCoGen GUI
+*
+*   AVCLK3 Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK3_FREQ  100.000F
+
+/** @def VCLK1_FREQ
+*   @brief VCLK1 Domain frequency exported from HALCoGen GUI
+*
+*   VCLK1 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK1_FREQ   100.000F
+
+/** @def VCLK2_FREQ
+*   @brief VCLK2 Domain frequency exported from HALCoGen GUI
+*
+*   VCLK2 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK2_FREQ   100.000F
+
+
+/** @def SYS_PRE1
+*   @brief Alias name for RTI1CLK PRE clock source
+*
+*   This is an alias name for the RTI1CLK pre clock source.
+*   This can be either:
+*     - Oscillator
+*     - Pll
+*     - 32 kHz Oscillator
+*     - External
+*     - Low Power Oscillator Low
+*     - Low Power Oscillator High
+*     - Flexray Pll
+*/
+/*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
+#define SYS_PRE1 SYS_PLL1
+
+/** @def SYS_PRE2
+*   @brief Alias name for RTI2CLK pre clock source
+*
+*   This is an alias name for the RTI2CLK pre clock source.
+*   This can be either:
+*     - Oscillator
+*     - Pll
+*     - 32 kHz Oscillator
+*     - External
+*     - Low Power Oscillator Low
+*     - Low Power Oscillator High
+*     - Flexray Pll
+*/
+/*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
+#define SYS_PRE2 SYS_PLL1
+
+/* Configuration registers */
+typedef struct system_config_reg
+{
+	uint32 CONFIG_SYSPC1;
+    uint32 CONFIG_SYSPC2;
+    uint32 CONFIG_SYSPC7;
+    uint32 CONFIG_SYSPC8;
+    uint32 CONFIG_SYSPC9;
+    uint32 CONFIG_CSDIS;
+    uint32 CONFIG_CDDIS;
+    uint32 CONFIG_GHVSRC;
+    uint32 CONFIG_VCLKASRC;
+    uint32 CONFIG_RCLKSRC;
+    uint32 CONFIG_MSTGCR;
+    uint32 CONFIG_MINITGCR;
+    uint32 CONFIG_MSINENA;
+    uint32 CONFIG_PLLCTL1;
+    uint32 CONFIG_PLLCTL2;
+    uint32 CONFIG_UERFLAG;
+    uint32 CONFIG_LPOMONCTL;
+    uint32 CONFIG_CLKTEST;
+    uint32 CONFIG_DFTCTRLREG1;
+    uint32 CONFIG_DFTCTRLREG2;
+    uint32 CONFIG_GPREG1;
+    uint32 CONFIG_RAMGCR;
+    uint32 CONFIG_BMMCR1;
+    uint32 CONFIG_MMUGCR;
+    uint32 CONFIG_CLKCNTL;
+    uint32 CONFIG_ECPCNTL;
+    uint32 CONFIG_DEVCR1;
+    uint32 CONFIG_SYSECR;
+    uint32 CONFIG_PLLCTL3;
+    uint32 CONFIG_STCCLKDIV;
+    uint32 CONFIG_CLK2CNTL;
+    uint32 CONFIG_VCLKACON1;
+    uint32 CONFIG_CLKSLIP;
+    uint32 CONFIG_EFC_CTLEN;
+} system_config_reg_t;
+
+/* Configuration registers initial value */
+#define SYS_SYSPC1_CONFIGVALUE	0U
+
+#define SYS_SYSPC2_CONFIGVALUE	1U
+
+#define SYS_SYSPC7_CONFIGVALUE	0U
+
+#define SYS_SYSPC8_CONFIGVALUE	0U
+
+#define SYS_SYSPC9_CONFIGVALUE	1U
+
+#define SYS_CSDIS_CONFIGVALUE	0x00000000U\
+								| 0x00000000U \
+								| 0x00000008U \
+								| 0x00000080U \
+								| 0x00000000U \
+								| 0x00000000U \
+								| 0x00000000U\
+								| (1U << 2U)
+					  
+#define SYS_CDDIS_CONFIGVALUE	(FALSE << 4U )\
+								|(TRUE << 5U )\
+								|(FALSE << 8U )\
+								|(FALSE << 10U)\
+								|(FALSE << 11U)
+					  
+#define SYS_GHVSRC_CONFIGVALUE	(SYS_PLL1 << 24U) \
+								| (SYS_PLL1 << 16U) \
+								|  SYS_PLL1
+								
+#define SYS_VCLKASRC_CONFIGVALUE	(SYS_VCLK << 8U)\
+									|  SYS_VCLK
+									
+#define SYS_RCLKSRC_CONFIGVALUE		(1U << 24U)\
+									| (SYS_VCLK << 16U)\
+									| (1U << 8U)\
+									|  SYS_VCLK
+									
+#define SYS_MSTGCR_CONFIGVALUE		0x00000105U
+
+#define SYS_MINITGCR_CONFIGVALUE 	0x5U
+
+#define SYS_MSINENA_CONFIGVALUE		0U
+
+#define SYS_PLLCTL1_CONFIGVALUE_1		0x00000000U \
+									|  0x20000000U \
+									| ((0x1FU)<< 24U) \
+									|  0x00000000U \
+									| ((6U - 1U)<< 16U)\
+									| ((150U - 1U)<< 8U)
+									
+#define SYS_PLLCTL1_CONFIGVALUE_2	( (SYS_PLLCTL1_CONFIGVALUE_1) & 0xE0FFFFFFU)|((1U - 1U)<< 24U)
+									
+#define SYS_PLLCTL2_CONFIGVALUE		0x00000000U\
+									| (255U << 22U)\
+									| (7U << 12U)\
+									| ((2U - 1U)<< 9U)\
+									|  61U
+									
+#define SYS_UERFLAG_CONFIGVALUE		0U
+
+#define SYS_LPOMONCTL_CONFIGVALUE_1	(1U << 24U) | LPO_TRIM_VALUE
+#define SYS_LPOMONCTL_CONFIGVALUE_2	(1U << 24U) | (16U << 8U) | 8U
+
+#define SYS_CLKTEST_CONFIGVALUE		0x000A0000U
+
+#define SYS_DFTCTRLREG1_CONFIGVALUE	0x00002205U
+
+#define SYS_DFTCTRLREG2_CONFIGVALUE	0x5U
+
+#define SYS_GPREG1_CONFIGVALUE	0x0005FFFFU
+
+#define SYS_RAMGCR_CONFIGVALUE	0x00050000U
+
+#define SYS_BMMCR1_CONFIGVALUE	0xAU
+
+#define SYS_MMUGCR_CONFIGVALUE	0U
+
+#define SYS_CLKCNTL_CONFIGVALUE	(1U << 8U) \
+                                | (1U << 16U) \
+								| (1U << 24U) 
+								
+#define SYS_ECPCNTL_CONFIGVALUE	(0U << 24U)\
+								| (0U << 23U)\
+								| ((8U - 1U) & 0xFFFFU)
+								
+#define SYS_DEVCR1_CONFIGVALUE	0xAU
+
+#define SYS_SYSECR_CONFIGVALUE	0x00004000U
+#define SYS2_PLLCTL3_CONFIGVALUE_1	((2U - 1U) << 29U)\
+									| ((0x1FU)<< 24U) \
+									| ((6U - 1U)<< 16U) \
+									| ((150U - 1U) << 8U)
+									
+#define SYS2_PLLCTL3_CONFIGVALUE_2	((SYS2_PLLCTL3_CONFIGVALUE_1) & 0xE0FFFFFFU)|((1U - 1U)<< 24U)
+#define SYS2_STCCLKDIV_CONFIGVALUE	0U
+#define SYS2_CLK2CNTL_CONFIGVALUE	(1U) \
+                                    | (1U << 8U)
+#define SYS2_VCLKACON1_CONFIGVALUE	(1U << 24U) \
+									| (1U << 20U) \
+									| (SYS_VCLK << 16U)\
+									| (1U << 8U)\
+									| (1U << 4U) \
+									| SYS_VCLK
+#define SYS2_CLKSLIP_CONFIGVALUE	0x5U
+#define SYS2_EFC_CTLEN_CONFIGVALUE	0x5U
+	
+void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* FlashW General Definitions */
+
+
+/** @enum flashWPowerModes
+*   @brief Alias names for flash bank power modes
+*
+*   This enumeration is used to provide alias names for the flash bank power modes:
+*     - sleep
+*     - standby
+*     - active
+*/
+enum flashWPowerModes
+{
+    SYS_SLEEP   = 0U, /**< Alias for flash bank power mode sleep   */
+    SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
+    SYS_ACTIVE  = 3U  /**< Alias for flash bank power mode active  */
+};
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+#define FSM_WR_ENA_HL		(*(volatile uint32 *)0xFFF87288U)
+#define EEPROM_CONFIG_HL	(*(volatile uint32 *)0xFFF872B8U)
+
+/* Configuration registers */
+typedef struct tcmflash_config_reg
+{
+    uint32 CONFIG_FRDCNTL;
+    uint32 CONFIG_FEDACCTRL1;
+    uint32 CONFIG_FEDACCTRL2;
+    uint32 CONFIG_FEDACSDIS;
+    uint32 CONFIG_FBPROT;
+    uint32 CONFIG_FBSE;
+    uint32 CONFIG_FBAC;
+    uint32 CONFIG_FBFALLBACK;
+    uint32 CONFIG_FPAC1;
+    uint32 CONFIG_FPAC2;
+    uint32 CONFIG_FMAC;
+    uint32 CONFIG_FLOCK;
+    uint32 CONFIG_FDIAGCTRL;
+    uint32 CONFIG_FEDACSDIS2;
+} tcmflash_config_reg_t;
+
+/* Configuration registers initial value */
+#define TCMFLASH_FRDCNTL_CONFIGVALUE		0x00000000U | (3U << 8U) | (1U << 4U) |  1U
+#define TCMFLASH_FEDACCTRL1_CONFIGVALUE		0x000A0005U
+#define TCMFLASH_FEDACCTRL2_CONFIGVALUE		0U
+#define TCMFLASH_FEDACSDIS_CONFIGVALUE		0U
+#define TCMFLASH_FBPROT_CONFIGVALUE			0U
+#define TCMFLASH_FBSE_CONFIGVALUE			0U
+#define TCMFLASH_FBAC_CONFIGVALUE			0xFU
+#define TCMFLASH_FBFALLBACK_CONFIGVALUE		0x00000000U\
+											| (SYS_ACTIVE << 14U) \
+											| (SYS_SLEEP << 12U) \
+											| (SYS_SLEEP << 10U) \
+											| (SYS_SLEEP << 8U) \
+											| (SYS_SLEEP << 6U) \
+											| (SYS_SLEEP << 4U) \
+											| (SYS_ACTIVE << 2U) \
+											|  SYS_ACTIVE \
+						  
+#define TCMFLASH_FPAC1_CONFIGVALUE			0x00C80001U
+#define TCMFLASH_FPAC2_CONFIGVALUE			0U
+#define TCMFLASH_FMAC_CONFIGVALUE			0U
+#define TCMFLASH_FLOCK_CONFIGVALUE			0x55AAU
+#define TCMFLASH_FDIAGCTRL_CONFIGVALUE		0x000A0000U
+#define TCMFLASH_FEDACSDIS2_CONFIGVALUE		0U
+
+void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+
+/* System Interface Functions */
+void setupPLL(void);
+void trimLPO(void);
+void setupFlash(void);
+void periphInit(void);
+void mapClocks(void);
+void systemInit(void);
+void systemPowerDown(uint32 mode);
+
+
+/*Configuration registers
+* index 0: Even RAM
+* index 1: Odd RAM
+*/
+typedef struct sram_config_reg
+{
+    uint32 CONFIG_RAMCTRL[2U];
+    uint32 CONFIG_RAMTHRESHOLD[2U];
+    uint32 CONFIG_RAMINTCTRL[2U];
+    uint32 CONFIG_RAMTEST[2U];
+    uint32 CONFIG_RAMADDRDECVECT[2U];
+} sram_config_reg_t;
+
+/* Configuration registers initial value */
+#define SRAM_RAMCTRL_CONFIGVALUE		0x0005000AU
+#define SRAM_RAMTHRESHOLD_CONFIGVALUE	1U
+#define SRAM_RAMINTCTRL_CONFIGVALUE	1U
+#define SRAM_RAMTEST_CONFIGVALUE		0x5U
+#define SRAM_RAMADDRDECVECT_CONFIGVALUE	0U
+
+void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type);
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/usb-ids.h b/bsp/rm48x50/HALCoGen/include/usb-ids.h
new file mode 100644
index 0000000000000000000000000000000000000000..052f766df75af1330a161f69e785c7e5c990e68c
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/usb-ids.h
@@ -0,0 +1,53 @@
+//*****************************************************************************
+//
+// usb-ids.h - Definitions of VIDs and PIDs used by Stellaris USB examples.
+//
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 6288 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBIDS_H__
+#define __USBIDS_H__
+
+//*****************************************************************************
+//
+// TI Vendor ID.
+//
+//*****************************************************************************
+#define USB_VID_TI       0x0000
+
+//*****************************************************************************
+//
+// Product IDs.
+//
+//*****************************************************************************
+#define USB_PID_MOUSE           0x0000
+#define USB_PID_KEYBOARD        0x0001
+#define USB_PID_SERIAL          0x0000
+#define USB_PID_BULK            0x0003
+#define USB_PID_SCOPE           0x0004
+#define USB_PID_MSC             0x0005
+#define USB_PID_AUDIO           0x0006
+#define USB_PID_COMP_SERIAL     0x0007
+#define USB_PID_COMP_AUDIO_HID  0x0008
+#define USB_PID_COMP_HID_SER    0x0009
+#define USB_PID_DFU             0x00FF
+
+
+#endif /* __USBIDS_H__ */
diff --git a/bsp/rm48x50/HALCoGen/include/usb.h b/bsp/rm48x50/HALCoGen/include/usb.h
new file mode 100644
index 0000000000000000000000000000000000000000..87cd8a5e4ccf7565f6f5ab4bc51468c57bbc6263
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/usb.h
@@ -0,0 +1,644 @@
+#ifndef USB_H_
+#define USB_H_
+
+//*****************************************************************************
+//
+// These macros allow conversion between 0-based endpoint indices and the
+// USB_EP_x values required when calling various USB APIs.
+//
+//*****************************************************************************
+#define INDEX_TO_USB_EP(x)      ((x) << 4)
+#define USB_EP_TO_INDEX(x)      ((x) >> 4)
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBFIFOConfigSet() as the
+// uFIFOSize parameter.
+//
+//*****************************************************************************
+#define USB_FIFO_SZ_8           0x00000000  // 8 byte FIFO
+#define USB_FIFO_SZ_16          0x00000001  // 16 byte FIFO
+#define USB_FIFO_SZ_32          0x00000002  // 32 byte FIFO
+#define USB_FIFO_SZ_64          0x00000003  // 64 byte FIFO
+#define USB_FIFO_SZ_128         0x00000004  // 128 byte FIFO
+#define USB_FIFO_SZ_256         0x00000005  // 256 byte FIFO
+#define USB_FIFO_SZ_512         0x00000006  // 512 byte FIFO
+#define USB_FIFO_SZ_1024        0x00000007  // 1024 byte FIFO
+
+
+//*****************************************************************************
+//
+// This macro allow conversion from a FIFO size label as defined above to
+// a number of bytes
+//
+//*****************************************************************************
+#define USB_FIFO_SIZE_DB_FLAG  0x00000010
+#define USB_FIFO_SZ_TO_BYTES(x) ((8 << ((x) & ~ USB_FIFO_SIZE_DB_FLAG)) * \
+                                 (((x) & USB_FIFO_SIZE_DB_FLAG) ? 2 : 1))
+
+								 
+//*****************************************************************************
+//
+//! The maximum number of independent interfaces that any single device
+//! implementation can support.  Independent interfaces means interface
+//! descriptors with different bInterfaceNumber values - several interface
+//! descriptors offering different alternative settings but the same interface
+//! number count as a single interface.
+//
+//*****************************************************************************
+#define USB_MAX_INTERFACES_PER_DEVICE 8
+
+
+//*****************************************************************************
+//
+//! Following macro directives can be used for the configuring the USB device.
+//! Note that these directives map directly to the hardware bit definitions and
+//! cannot be modified to any other value.
+//
+//*****************************************************************************
+#define USBD_PWR_BUS_PWR				(0x0000u) 	//Device is bus powered
+#define USBD_PWR_SELF_PWR   			(0x0004u)	//Device is self powered
+#define USBD_DATA_ENDIAN_LITTLE			(0x0000u)	//Little Endian Data (RM48x)
+#define USBD_DATA_ENDIAN_BIG			(0x0080u)	//Bit Endian Data
+#define USBD_DMA_ENDIAN_LITTLE			(0x0000u)	//DMA is Little Endian
+#define USBD_DMA_ENDIAN_BIG				(0x0040u)	//DMA is Big Endian
+
+//*****************************************************************************
+//
+//! Following macro directives can be used for the configuring the Endpoints
+//! Note that these directives map directly to the hardware bit definitions and
+//! cannot be modified to any other value.
+//
+//*****************************************************************************
+#define USBD_EP_DIR_IN       			(0x0010u)		//IN Endpoint
+#define USBD_EP_DIR_OUT       			(0x0000u)		//OUT Endpoint
+#define USB_EP_DEV_IN					USBD_EP_DIR_IN	//IN Endpoint
+#define USB_EP_DEV_OUT					USBD_EP_DIR_OUT	//OUT Endpoint
+#define USB_TRANS_IN					USBD_EP_DIR_IN	//IN Endpoint
+#define USB_TRANS_OUT					USBD_EP_DIR_OUT	//OUT Endpoint
+#define USB_EP_DIR_IN					USBD_EP_DIR_IN
+#define USB_EP_DIR_OUT					USBD_EP_DIR_OUT
+#define USB_TRANS_IN_LAST				0				//Used to indicate the last transaction
+														//(NOT USED in this port of USB)
+
+#define USBD_TXRX_EP_VALID_VALID		(0x8000u)		//EP is valid & configured
+#define USBD_TXRX_EP_VALID_NOTVALID		(0x0000u)		//EP is not valid & not configured
+#define USBD_TXRX_EP_ISO_ISO			(0x0800u)		//EP is of ISO type
+#define USBD_TXRX_EP_ISO_NONISO			(0x0000u)		//EP is either Bulk/Interrup/Control
+#define USBD_TXRX_EP_DB_ENABLED			(0x4000u) 		//EP has double buffering enabled
+														// For IN EPs DB should be enabled only in DMA mode */
+#define USBD_TXRX_EP_DB_DISABLED		(0x0000u)		//EP has double buffering disabled
+
+//*****************************************************************************
+//
+//! Following macro directives are to be used for enabling/disabling interrupts
+//! Note that these directives map directly to the hardware bit definitions and
+//! cannot be modified to any other value.
+//
+//*****************************************************************************
+#define USBD_INT_EN_SOF_IE      				(0x0080u)	//Start-of-Frame Interrupt
+#define USBD_INT_EN_EPN_RX_IE   				(0x0020u)	//Non-EP0 RX Interrupt
+#define USBD_INT_EN_EPN_TX_IE   				(0x0010u)	//Non-EP0 TX Interrupt
+#define USBD_INT_EN_DS_CHG_IE   				(0x0008u)	//Device State change interrupt
+#define USBD_INT_EN_EP0_IE      				(0x0001u)	//EP0 Interrupt
+#define USBD_INT_EN_ALL							(USBD_IRQ_EN_SOF_IE | \
+												 USBD_IRQ_EN_EPN_RX_IE | \
+												 USBD_IRQ_EN_EPN_TX_IE | \
+												 USBD_IRQ_EN_DS_CHG_IE | \
+												 USBD_IRQ_EN_EP0_IE)
+
+
+//*****************************************************************************
+//
+//! Following macro directives are to be used for decoding the interrupt source
+//! Note that these directives map directly to the hardware bit definitions and
+//! cannot be modified to any other value.
+//
+//*****************************************************************************
+#define USBD_INT_SRC_TXN_DONE   				(0x0400u)	//non-EP0 TX done interrupt
+#define USBD_INT_SRC_RXN_CNT    				(0x0200u)	//non-EP0 RX Count
+#define USBD_INT_SRC_RXN_EOT    				(0x0100u)	//non-EP0 RX end of transfer
+#define USBD_INT_SRC_SOF        				(0x0080u)	//Start-of-frame interrupt
+#define USBD_INT_SRC_EPN_RX     				(0x0020u)	//non-EP0 RX interrupt
+#define USBD_INT_SRC_EPN_TX    					(0x0010u)	//non-EP0 TX interrupt
+#define USBD_INT_SRC_DS_CHG     				(0x0008u)	//Device State change interrupt
+#define USBD_INT_SRC_SETUP      				(0x0004u)	//Setup interrupt
+#define USBD_INT_SRC_EP0_RX     				(0x0002u)	//EP0 RX Interrupt
+#define USBD_INT_SRC_EP0_TX     				(0x0001u)	//EP0 TX Interrupt
+
+
+//*****************************************************************************
+//
+// These values are used to indicate which endpoint to access.
+//
+//*****************************************************************************
+#define USB_EP_0                0x00000000  // Endpoint 0
+#define USB_EP_1                0x00000010  // Endpoint 1
+#define USB_EP_2                0x00000020  // Endpoint 2
+#define USB_EP_3                0x00000030  // Endpoint 3
+#define USB_EP_4                0x00000040  // Endpoint 4
+#define USB_EP_5                0x00000050  // Endpoint 5
+#define USB_EP_6                0x00000060  // Endpoint 6
+#define USB_EP_7                0x00000070  // Endpoint 7
+#define USB_EP_8                0x00000080  // Endpoint 8
+#define USB_EP_9                0x00000090  // Endpoint 9
+#define USB_EP_10               0x000000A0  // Endpoint 10
+#define USB_EP_11               0x000000B0  // Endpoint 11
+#define USB_EP_12               0x000000C0  // Endpoint 12
+#define USB_EP_13               0x000000D0  // Endpoint 13
+#define USB_EP_14               0x000000E0  // Endpoint 14
+#define USB_EP_15               0x000000F0  // Endpoint 15
+#define NUM_USB_EP              16          // Number of supported endpoints
+
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostEndpointConfig() and
+// USBDevEndpointConfigSet() as the ulFlags parameter.
+//
+//*****************************************************************************
+#define USB_EP_AUTO_SET         0x00000001u  // Auto set feature enabled
+#define USB_EP_AUTO_REQUEST     0x00000002u  // Auto request feature enabled
+#define USB_EP_AUTO_CLEAR       0x00000004u  // Auto clear feature enabled
+#define USB_EP_DMA_MODE_0       0x00000008u  // Enable DMA access using mode 0
+#define USB_EP_DMA_MODE_1       0x00000010u  // Enable DMA access using mode 1
+#define USB_EP_MODE_ISOC        0x00000000u  // Isochronous endpoint
+#define USB_EP_MODE_BULK        0x00000100u  // Bulk endpoint
+#define USB_EP_MODE_INT         0x00000200u  // Interrupt endpoint
+#define USB_EP_MODE_CTRL        0x00000300u  // Control endpoint
+#define USB_EP_MODE_MASK        0x00000300u  // Mode Mask
+#define USB_EP_SPEED_LOW        0x00000000u  // Low Speed
+#define USB_EP_SPEED_FULL       0x00001000u  // Full Speed
+
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBEndpointStatus().  The
+// USB_HOST_* values are used when the USB controller is in host mode and the
+// USB_DEV_* values are used when the USB controller is in device mode.
+//
+//*****************************************************************************
+#define USB_DEV_EP0_OUT_PKTRDY 0x00000001u  // Receive data packet ready
+#define USB_DEV_RX_PKT_RDY    	0x00010000u  // Data packet ready
+#define USB_DEV_TX_TXPKTRDY		0x00000001u
+#define USB_DEV_TX_FIFO_NE		0x00000002u
+
+
+//*****************************************************************************
+//
+// This value specifies the maximum size of transfers on endpoint 0 as 64
+// bytes.  This value is fixed in hardware as the FIFO size for endpoint 0.
+//
+//*****************************************************************************
+#define MAX_PACKET_SIZE_EP0     64
+
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x) 				(*((volatile unsigned int *)(x)))
+
+
+
+
+//*****************************************************************************
+//
+//! Initialize the USB Device
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usFlags specifies the bus/self powered and endianness for data & dma.
+//!			Should be a combination of the following flags
+//! 			USBD_PWR_BUS_PWR or USBD_PWR_SELF_PWR
+//!				USBD_DATA_ENDIAN_LITTLE or USBD_DATA_ENDIAN_BIG
+//!				USBD_DMA_ENDIAN_LITTLE or USBD_DMA_ENDIAN_BIG
+//! \param usFifoPtr specifies the start of the EP0 FIFO.
+//!
+//! This function will initialize the USB Device controller specified by the
+//! \e ulBase parameter.
+//!
+//! \return None
+//!
+//! Note This function does not intiate a device connect (pull ups are
+//! not enabled). Also the EP0 is intialized with FIFO size of 64Bytes.
+//!
+//
+//*****************************************************************************
+void USBDevInit(uint32 ulBase, uint16 usFlags, uint16 usFifoPtr);
+
+
+//*****************************************************************************
+//
+//! Initialize the USB Device's EP0
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usSize FIFO size. Supported values are USB_FIFO_SZ_8/USB_FIFO_SZ_16/
+//!			USB_FIFO_SZ_32/USB_FIFO_SZ_64.
+//! \param usFifoPtr specifies the start of the EP0 FIFO.
+//!
+//! This function will initialize the USB Device controller specified by the
+//! \e ulBase parameter.  The \e uFlags parameter is not used by this
+//! implementation.
+//!
+//! \return None
+//!
+//
+//*****************************************************************************
+void USBDevEp0Config(uint32 ulBase, uint16 usSize, uint16 usFifoPtr);
+
+
+//*****************************************************************************
+//
+//! Disable control interrupts on a given USB device controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usFlags specifies which control interrupts to disable.
+//!
+//! This function will disable the interrupts for the USB device controller
+//! specified by the \e ulBase parameter.  The \e usFlags parameter specifies
+//! which control interrupts to disable.  The flags passed in the \e usFlags
+//! parameters should be the definitions that start with \b USBD_INT_EN_*
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBIntDisable(uint32 ulBase, uint16 usFlags);
+
+
+//*****************************************************************************
+//
+//! Enable control interrupts on a given USB device controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usFlags specifies which control interrupts to enable.
+//!
+//! This function will enable the control interrupts for the USB device controller
+//! specified by the \e ulBase parameter.  The \e usFlags parameter specifies
+//! which control interrupts to enable.  The flags passed in the \e usFlags
+//! parameters should be the definitions that start with \b USBD_INT_EN_* and
+//! not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBIntEnable(uint32 ulBase, uint16 usFlags);
+
+
+//*****************************************************************************
+//
+//! Returns the control interrupt status on a given USB device controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read interrupt status for a USB device controller.
+//! The bit values returned should be compared against the \b USBD_INT_SRC_*
+//! values.
+//!
+//! \return Returns the status of the control interrupts for a USB device controller.
+//
+//*****************************************************************************
+uint16 USBIntStatus(uint32 ulBase);
+
+
+//*****************************************************************************
+//
+//! Stalls the specified endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint specifies the endpoint to stall.
+//! \param usFlags specifies whether to stall the IN or OUT endpoint.
+//!
+//! This function will cause to endpoint number passed in to go into a stall
+//! condition.  If the \e usFlags parameter is \b USB_EP_DEV_IN then the stall
+//! will be issued on the IN portion of this endpoint.  If the \e usFlags
+//! parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevEndpointStall(uint32 ulBase, uint16 usEndpoint, uint16 usFlags);
+
+
+//*****************************************************************************
+//
+//! Clears the stall condition on the specified endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint specifies which endpoint to remove the stall condition.
+//! \param usFlags specifies whether to remove the stall condition from the IN
+//! or the OUT portion of this endpoint.
+//!
+//! This function will cause the endpoint number passed in to exit the stall
+//! condition.  If the \e usFlags parameter is \b USB_EP_DEV_IN then the stall
+//! will be cleared on the IN portion of this endpoint.  If the \e usFlags
+//! parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevEndpointStallClear(uint32 ulBase, uint16 usEndpoint, uint16 usFlags);
+
+
+//*****************************************************************************
+//
+//! Connects the USB device controller to the bus in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will cause the soft connect feature of the USB device controller to
+//! be enabled.  Call USBDisconnect() to remove the USB device from the bus.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevConnect(uint32 ulBase);
+
+
+//*****************************************************************************
+//
+//! Removes the USB device controller from the bus in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will cause the soft disconnect feature of the USB device controller to
+//! remove the device from the USB bus.  A call to USBDevConnect() is needed to
+//! reconnect to the bus.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevDisconnect(uint32 ulBase);
+
+
+//*****************************************************************************
+//
+//! Sets the address in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulAddress is the address to use for a device.
+//!
+//! This function will set the device address on the USB bus.  This address was
+//! likely received via a SET ADDRESS command from the host controller.
+//!
+//! \note This function is not available on this controller. This is maintained
+//! 		for compatibility.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevAddrSet(uint32 ulBase, uint32 ulAddress);
+
+
+//*****************************************************************************
+//
+//! Determine the number of bytes of data available in a given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint is the endpoint to access.
+//!
+//! This function will return the number of bytes of data currently available
+//! in the FIFO for the given receive (OUT) endpoint.  It may be used prior to
+//! calling USBEndpointDataGet() to determine the size of buffer required to
+//! hold the newly-received packet.
+//!
+//! \return This call will return the number of bytes available in a given
+//! endpoint FIFO.
+//
+//*****************************************************************************
+uint16 USBEndpointDataAvail(uint32 ulBase, uint16 usEndpoint);
+
+
+//*****************************************************************************
+//
+//! Retrieves data from the given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint is the endpoint to access.
+//! \param pucData is a pointer to the data area used to return the data from
+//! the FIFO.
+//! \param pulSize is initially the size of the buffer passed into this call
+//! via the \e pucData parameter.  It will be set to the amount of data
+//! returned in the buffer.
+//!
+//! This function will return the data from the FIFO for the given endpoint.
+//! The \e pulSize parameter should indicate the size of the buffer passed in
+//! the \e pulData parameter.  The data in the \e pulSize parameter will be
+//! changed to match the amount of data returned in the \e pucData parameter.
+//! If a zero byte packet was received this call will not return a error but
+//! will instead just return a zero in the \e pulSize parameter.  The only
+//! error case occurs when there is no data packet available.
+//!
+//! \return This call will return 0, or -1 if no packet was received.
+//
+//*****************************************************************************
+uint32 USBEndpointDataGet(uint32 ulBase, uint16 usEndpoint, uint8 *pucData, uint32 *pulSize);
+
+
+//*****************************************************************************
+//
+//! Retrieves the setup packet from EP0 Setup FIFO
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param sPkt Pointer to the data area for storing the setup packet.
+//!			Atleast 8 bytes should be available.
+//! \param pusPktSize On return this contains the size of the setup packet (8Bytes)
+//!
+//! This function will retrieves the 8Byte long setup packet from the EP0 setup
+//! FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevGetSetupPacket (uint32 ulBase, uint8 * sPkt, uint16 * pusPktSize);
+
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in device
+//! mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint is the endpoint to access.
+//! \param bIsLastPacket This parameter is not used.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! The \e bIsLastPacket parameter is set to a \b true value if this is the
+//! last in a series of data packets on endpoint zero.  The \e bIsLastPacket
+//! parameter is not used for endpoints other than endpoint zero.  This call
+//! can be used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevEndpointDataAck(uint32 ulBase, uint16 usEndpoint, uint8 bIsLastPacket);
+
+
+//*****************************************************************************
+//
+//! Puts data into the given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint is the endpoint to access.
+//! \param pucData is a pointer to the data area used as the source for the
+//! data to put into the FIFO.
+//! \param ulSize is the amount of data to put into the FIFO.
+//!
+//! This function will put the data from the \e pucData parameter into the FIFO
+//! for this endpoint.  If a packet is already pending for transmission then
+//! this call will not put any of the data into the FIFO and will return -1.
+//! Care should be taken to not write more data than can fit into the FIFO
+//! allocated by the call to USBFIFOConfig().
+//!
+//! \return This call will return 0 on success, or -1 to indicate that the FIFO
+//! is in use and cannot be written.
+//
+//*****************************************************************************
+uint32 USBEndpointDataPut(uint32 ulBase, uint16 usEndpoint,uint8 *pucData, uint32 ulSize);
+
+
+//*****************************************************************************
+//
+//! Starts the transfer of data from an endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint is the endpoint to access.
+//! \param ulTransType Not used.
+//!
+//! This function will start the transfer of data from the FIFO for a given
+//! endpoint.
+//!
+//! \return This call will return 0 on success, or -1 if a transmission is
+//! already in progress.
+//
+//*****************************************************************************
+uint32 USBEndpointDataSend(uint32 ulBase, uint16 usEndpoint, uint32 ulTransType);
+
+
+//*****************************************************************************
+//
+//! Resets the USB Device Controller
+//!
+//! \param void
+//!
+//! \return None.
+//
+//! \note Since the USB Device reset is handled by the host, this is a dummy
+//! function & maintained for compatibility purpose.
+//
+//*****************************************************************************
+void USBReset(void);
+
+
+//*****************************************************************************
+//
+//! Sets the FIFO configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint is the endpoint to access.
+//! \param uFIFOAddress is the starting address for the FIFO.
+//! \param uFIFOSize is the size of the FIFO in bytes.
+//! \param uFlags specifies what information to set in the FIFO configuration.
+//!
+//! This function will set the starting FIFO RAM address and size of the FIFO
+//! for a given endpoint.  Endpoint zero does not have a dynamically
+//! configurable FIFO so this function should not be called for endpoint zero.
+//! The \e uFIFOSize parameter should be one of the values in the
+//! \b USB_FIFO_SZ_ values.  If the endpoint is going to use double buffering
+//! it should use the values with the \b _DB at the end of the value.  For
+//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16
+//! byte double buffered FIFO.  If a double buffered FIFO is used, then the
+//! actual size of the FIFO will be twice the size indicated by the
+//! \e uFIFOSize parameter.  This means that the \b USB_FIFO_SZ_16_DB value
+//! will use 32 bytes of the USB controller's FIFO memory.
+//!
+//! The \e uFIFOAddress value should be a multiple of 8 bytes and directly
+//! indicates the starting address in the USB controller's FIFO RAM.  For
+//! example, a value of 64 indicates that the FIFO should start 64 bytes into
+//! the USB controller's FIFO memory.  The \e uFlags value specifies whether
+//! the endpoint's OUT or IN FIFO should be configured.  If in host mode, use
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use
+//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBFIFOConfigSet(uint32 ulBase, uint32 usEndpoint, uint32 uFIFOAddress, uint32 uFIFOSize, uint16 uFlags);
+
+
+//*****************************************************************************
+//
+//! Gets the current configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint is the endpoint to access.
+//! \param pulMaxPacketSize is a pointer which will be written with the
+//! maximum packet size for this endpoint.
+//! \param puFlags is a pointer which will be written with the current
+//! endpoint settings. On entry to the function, this pointer must contain
+//! either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or
+//! OUT endpoint is to be queried.
+//!
+//! This function will return the basic configuration for an endpoint in device
+//! mode. The values returned in \e *pulMaxPacketSize and \e *puFlags are
+//! equivalent to the \e ulMaxPacketSize and \e uFlags previously passed to
+//! USBDevEndpointConfigSet() for this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevEndpointConfigGet(uint32 ulBase, uint16 usEndpoint, uint32*pulMaxPacketSize, uint32*puFlags);
+
+
+//*****************************************************************************
+//
+//! Sets the configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param usEndpoint is the endpoint to access.
+//! \param ulMaxPacketSize is the maximum packet size for this endpoint.
+//! \param uFlags are used to configure other endpoint settings.
+//!
+//! This function will set the basic configuration for an endpoint in device
+//! mode.  Endpoint zero does not have a dynamic configuration, so this
+//! function should not be called for endpoint zero.  The \e uFlags parameter
+//! determines some of the configuration while the other parameters provide the
+//! rest.
+//!
+//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint.
+//!
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void USBDevEndpointConfigSet(uint32 ulBase, uint16 usEndpoint, uint32 ulMaxPacketSize, uint16 uFlags);
+
+void USBDevSetDevCfg(uint32 ulBase);
+void USBDevClearDevCfg(uint32 ulBase);
+uint16 USBDevGetEPnStat(uint32 ulBase);
+void USBDevPullEnableDisable(uint32 ulBase, uint32 ulSet);
+void USBIntStatusClear (uint16 uFlag);
+uint16 USBDevGetDevStat(uint32 ulBase);
+void USBDevCfgUnlock(uint32 ulBase);
+void USBDevCfgLock(uint32 ulBase);
+
+#endif /*USB_H_*/
diff --git a/bsp/rm48x50/HALCoGen/include/usb_serial_structs.h b/bsp/rm48x50/HALCoGen/include/usb_serial_structs.h
new file mode 100644
index 0000000000000000000000000000000000000000..3ebbce22198c41cc1f01ea951f9eaeecd51e64e1
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/usb_serial_structs.h
@@ -0,0 +1,48 @@
+//*****************************************************************************
+//
+// usb_serial_structs.h - Data structures defining this USB CDC device.
+//
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+//
+//*****************************************************************************
+
+#ifndef _USB_SERIAL_STRUCTS_H_
+#define _USB_SERIAL_STRUCTS_H_
+
+//*****************************************************************************
+//
+// The size of the transmit and receive buffers used for the redirected UART.
+// This number should be a power of 2 for best performance.  256 is chosen
+// pretty much at random though the buffer should be at least twice the size of
+// a maxmum-sized USB packet.
+//
+//*****************************************************************************
+#define UART_BUFFER_SIZE 0x0001
+
+extern uint32 RxHandler(void *pvCBData, uint32 ulEvent,
+                               uint32 ulMsgValue, void *pvMsgData);
+extern uint32 TxHandler(void *pvlCBData, uint32 ulEvent,
+                               uint32 ulMsgValue, void *pvMsgData);
+
+extern const tUSBBuffer g_sTxBuffer;
+extern const tUSBBuffer g_sRxBuffer;
+extern const tUSBDCDCDevice g_sCDCDevice;
+extern uint8 g_pucUSBTxBuffer[];
+extern uint8 g_pucUSBRxBuffer[];
+
+#endif
diff --git a/bsp/rm48x50/HALCoGen/include/usbcdc.h b/bsp/rm48x50/HALCoGen/include/usbcdc.h
new file mode 100644
index 0000000000000000000000000000000000000000..c4a91601dffe160f315aadae51cdbe588a3a1bf2
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/usbcdc.h
@@ -0,0 +1,788 @@
+//*****************************************************************************
+//
+// usbhid.h - Definitions used by Communication Device Class devices.
+//
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Note: This header contains definitions related to the USB Communication
+//       Device Class specification.  The header is complete for ACM model
+//       devices but request and notification definitions specific to other
+//       modem types, ISDN, ATM and Ethernet are currently incomplete or
+//       omitted.
+//
+//*****************************************************************************
+
+#ifndef __USBCDC_H__
+#define __USBCDC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup cdc_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Generic macros to read a byte, word or long from a character pointer.
+//
+//*****************************************************************************
+#define BYTE(pucData)           (*(uint8 *)(pucData))
+#define SHORT(pucData)          (*(uint16 *)(pucData))
+#define LONG(pucData)           (*(uint32 *)(pucData))
+
+//*****************************************************************************
+//
+// USB CDC subclass codes.  Used in interface descriptor, bInterfaceClass
+//
+//*****************************************************************************
+#define USB_CDC_SUBCLASS_DIRECT_LINE_MODEL          0x01
+#define USB_CDC_SUBCLASS_ABSTRACT_MODEL             0x02
+#define USB_CDC_SUBCLASS_TELEPHONE_MODEL            0x03
+#define USB_CDC_SUBCLASS_MULTI_CHANNEL_MODEL        0x04
+#define USB_CDC_SUBCLASS_CAPI_MODEL                 0x05
+#define USB_CDC_SUBCLASS_ETHERNET_MODEL             0x06
+#define USB_CDC_SUBCLASS_ATM_MODEL                  0x07
+
+//*****************************************************************************
+//
+// USB CDC control interface protocols.  Used in control interface descriptor,
+// bInterfaceProtocol
+//
+//*****************************************************************************
+#define USB_CDC_PROTOCOL_NONE                       0x00
+#define USB_CDC_PROTOCOL_V25TER                     0x01
+#define USB_CDC_PROTOCOL_VENDOR                     0xFF
+
+//*****************************************************************************
+//
+// USB CDC data interface protocols.  Used in data interface descriptor,
+// bInterfaceProtocol
+//
+//*****************************************************************************
+//      USB_CDC_PROTOCOL_NONE                       0x00
+#define USB_CDC_PROTOCOL_I420                       0x30
+#define USB_CDC_PROTOCOL_TRANSPARENT                0x32
+#define USB_CDC_PROTOCOL_Q921M                      0x50
+#define USB_CDC_PROTOCOL_Q921                       0x51
+#define USB_CDC_PROTOCOL_Q921TM                     0x52
+#define USB_CDC_PROTOCOL_V42BIS                     0x90
+#define USB_CDC_PROTOCOL_Q921EURO                   0x91
+#define USB_CDC_PROTOCOL_V120                       0x92
+#define USB_CDC_PROTOCOL_CAPI20                     0x93
+#define USB_CDC_PROTOCOL_HOST_DRIVER                0xFD
+#define USB_CDC_PROTOCOL_CDC_SPEC                   0xFE
+//      USB_CDC_PROTOCOL_VENDOR                     0xFF
+
+//*****************************************************************************
+//
+// Functional descriptor definitions
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Functional descriptor types
+//
+//*****************************************************************************
+#define USB_CDC_CS_INTERFACE                    0x24
+#define USB_CDC_CS_ENDPOINT                     0x25
+
+//*****************************************************************************
+//
+// Functional descriptor subtypes
+//
+//*****************************************************************************
+#define USB_CDC_FD_SUBTYPE_HEADER               0x00
+#define USB_CDC_FD_SUBTYPE_CALL_MGMT            0x01
+#define USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT    0x02
+#define USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT     0x03
+#define USB_CDC_FD_SUBTYPE_TELEPHONE_RINGER     0x04
+#define USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS      0x05
+#define USB_CDC_FD_SUBTYPE_UNION                0x06
+#define USB_CDC_FD_SUBTYPE_COUNTRY              0x07
+#define USB_CDC_FD_SUBTYPE_TELEPHONE_MODES      0x08
+#define USB_CDC_FD_SUBTYPE_USB_TERMINAL         0x09
+#define USB_CDC_FD_SUBTYPE_NETWORK_TERMINAL     0x0A
+#define USB_CDC_FD_SUBTYPE_PROTOCOL_UNIT        0x0B
+#define USB_CDC_FD_SUBTYPE_EXTENSION_UNIT       0x0C
+#define USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT   0x0D
+#define USB_CDC_FD_SUBTYPE_CAPI_MGMT            0x0E
+#define USB_CDC_FD_SUBTYPE_ETHERNET             0x0F
+#define USB_CDC_FD_SUBTYPE_ATM                  0x10
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_CALL_MGMT, Header functional descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_CALL_MGMT_VIA_DATA              0x02
+#define USB_CDC_CALL_MGMT_HANDLED               0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT, Abstract Control Management functional
+// descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_ACM_SUPPORTS_NETWORK_CONNECTION 0x08
+#define USB_CDC_ACM_SUPPORTS_SEND_BREAK         0x04
+#define USB_CDC_ACM_SUPPORTS_LINE_PARAMS        0x02
+#define USB_CDC_ACM_SUPPORTS_COMM_FEATURE       0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT, Direct Line Management functional
+// descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_DLM_NEEDS_EXTRA_PULSE_SETUP     0x04
+#define USB_CDC_DLM_SUPPORTS_AUX                0x02
+#define USB_CDC_DLM_SUPPORTS_PULSE              0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_TELEPHONE_MODES, Telephone Operational Modes functional
+// descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_TELEPHONE_SUPPORTS_COMPUTER     0x04
+#define USB_CDC_TELEPHONE_SUPPORTS_STANDALONE   0x02
+#define USB_CDC_TELEPHONE_SUPPORTS_SIMPLE       0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS, Telephone Call and Line State Reporting
+// Capabilities descriptor
+//
+//*****************************************************************************
+#define USB_CDC_LINE_STATE_CHANGES_NOTIFIED     0x20
+#define USB_CDC_LINE_STATE_REPORTS_DTMF         0x10
+#define USB_CDC_LINE_STATE_REPORTS_DIST_RING    0x08
+#define USB_CDC_LINE_STATE_REPORTS_CALLERID     0x04
+#define USB_CDC_LINE_STATE_REPORTS_BUSY         0x02
+#define USB_CDC_LINE_STATE_REPORTS_INT_DIALTONE 0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_USB_TERMINAL, USB Terminal functional descriptor,
+// bmOptions
+//
+//*****************************************************************************
+#define USB_CDC_TERMINAL_NO_WRAPPER_USED        0x00
+#define USB_CDC_TERMINAL_WRAPPER_USED           0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT, Multi-Channel Management functional
+// descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_MCM_SUPPORTS_SET_UNIT_PARAM     0x04
+#define USB_CDC_MCM_SUPPORTS_CLEAR_UNIT_PARAM   0x02
+#define USB_CDC_MCM_UNIT_PARAMS_NON_VOLATILE    0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_CAPI_MGMT, CAPI Control Management functional descriptor,
+// bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_CAPI_INTELLIGENT                0x01
+#define USB_CDC_CAPI_SIMPLE                     0x00
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_ETHERNET, Ethernet Networking functional descriptor,
+// bmEthernetStatistics
+//
+//*****************************************************************************
+#define USB_CDC_ETHERNET_XMIT_OK                0x01000000
+#define USB_CDC_ETHERNET_RCV_OK                 0x02000000
+#define USB_CDC_ETHERNET_XMIT_ERROR             0x04000000
+#define USB_CDC_ETHERNET_RCV_ERROR              0x08000000
+#define USB_CDC_ETHERNET_RCV_NO_BUFFER          0x10000000
+#define USB_CDC_ETHERNET_DIRECTED_BYTES_XMIT    0x20000000
+#define USB_CDC_ETHERNET_DIRECTED_FRAMES_XMIT   0x40000000
+#define USB_CDC_ETHERNET_MULTICAST_BYTES_XMIT   0x80000000
+#define USB_CDC_ETHERNET_MULTICAST_FRAMES_XMIT  0x00010000
+#define USB_CDC_ETHERNET_BROADCAST_BYTES_XMIT   0x00020000
+#define USB_CDC_ETHERNET_BROADCAST_FRAMES_XMIT  0x00040000
+#define USB_CDC_ETHERNET_DIRECTED_BYTES_RCV     0x00080000
+#define USB_CDC_ETHERNET_DIRECTED_FRAMES_RCV    0x00100000
+#define USB_CDC_ETHERNET_MULTICAST_BYTES_RCV    0x00200000
+#define USB_CDC_ETHERNET_MULTICAST_FRAMES_RCV   0x00400000
+#define USB_CDC_ETHERNET_BROADCAST_BYTES_RCV    0x00800000
+#define USB_CDC_ETHERNET_BROADCAST_FRAMES_RCV   0x00000100
+#define USB_CDC_ETHERNET_RCV_CRC_ERROR          0x00000200
+#define USB_CDC_ETHERNET_TRANSMIT_QUEUE_LENGTH  0x00000400
+#define USB_CDC_ETHERNET_RCV_ERROR_ALIGNMENT    0x00000800
+#define USB_CDC_ETHERNET_XMIT_ONE_COLLISION     0x00001000
+#define USB_CDC_ETHERNET_XMIT_MORE_COLLISIONS   0x00002000
+#define USB_CDC_ETHERNET_XMIT_DEFERRED          0x00004000
+#define USB_CDC_ETHERNET_XMIT_MAX_COLLISIONS    0x00008000
+#define USB_CDC_ETHERNET_RCV_OVERRUN            0x00000001
+#define USB_CDC_ETHERNET_XMIT_UNDERRUN          0x00000002
+#define USB_CDC_ETHERNET_XMIT_HEARTBEAT_FAILURE 0x00000004
+#define USB_CDC_ETHERNET_XMIT_TIMES_CRS_LOST    0x00000008
+#define USB_CDC_ETHERNET_XMIT_LATE_COLLISIONS   0x00000010
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_ATM, ATM Networking functional descriptor,
+// bmDataCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_ATM_TYPE_3                      0x08
+#define USB_CDC_ATM_TYPE_2                      0x04
+#define USB_CDC_ATM_TYPE_1                      0x02
+
+//*****************************************************************************
+//
+// bmATMDeviceStatistics
+//
+//*****************************************************************************
+#define USB_CDC_ATM_VC_US_CELLS_SENT            0x10
+#define USB_CDC_ATM_VC_US_CELLS_RECEIVED        0x08
+#define USB_CDC_ATM_DS_CELLS_HEC_ERR_CORRECTED  0x04
+#define USB_CDC_ATM_US_CELLS_SENT               0x02
+#define USB_CDC_ATM_US_CELLS_RECEIVED           0x01
+
+//*****************************************************************************
+//
+// Management Element Requests (provided in tUSBRequest.ucRequest)
+//
+//*****************************************************************************
+#define USB_CDC_SEND_ENCAPSULATED_COMMAND                       0x00
+#define USB_CDC_GET_ENCAPSULATED_RESPONSE                       0x01
+#define USB_CDC_SET_COMM_FEATURE                                0x02
+#define USB_CDC_GET_COMM_FEATURE                                0x03
+#define USB_CDC_CLEAR_COMM_FEATURE                              0x04
+#define USB_CDC_SET_AUX_LINE_STATE                              0x10
+#define USB_CDC_SET_HOOK_STATE                                  0x11
+#define USB_CDC_PULSE_SETUP                                     0x12
+#define USB_CDC_SEND_PULSE                                      0x13
+#define USB_CDC_SET_PULSE_TIME                                  0x14
+#define USB_CDC_RING_AUX_JACK                                   0x15
+#define USB_CDC_SET_LINE_CODING                                 0x20
+#define USB_CDC_GET_LINE_CODING                                 0x21
+#define USB_CDC_SET_CONTROL_LINE_STATE                          0x22
+#define USB_CDC_SEND_BREAK                                      0x23
+#define USB_CDC_SET_RINGER_PARMS                                0x30
+#define USB_CDC_GET_RINGER_PARMS                                0x31
+#define USB_CDC_SET_OPERATION_PARMS                             0x32
+#define USB_CDC_GET_OPERATION_PARMS                             0x33
+#define USB_CDC_SET_LINE_PARMS                                  0x34
+#define USB_CDC_GET_LINE_PARMS                                  0x35
+#define USB_CDC_DIAL_DIGITS                                     0x36
+#define USB_CDC_SET_UNIT_PARAMETER                              0x37
+#define USB_CDC_GET_UNIT_PARAMETER                              0x38
+#define USB_CDC_CLEAR_UNIT_PARAMETER                            0x39
+#define USB_CDC_GET_PROFILE                                     0x3A
+#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS                  0x40
+#define USB_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    0x41
+#define USB_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    0x42
+#define USB_CDC_SET_ETHERNET_PACKET_FILTER                      0x43
+#define USB_CDC_GET_ETHERNET_STATISTIC                          0x44
+#define USB_CDC_SET_ATM_DATA_FORMAT                             0x50
+#define USB_CDC_GET_ATM_DEVICE_STATISTICS                       0x51
+#define USB_CDC_SET_ATM_DEFAULT_VC                              0x52
+#define USB_CDC_GET_ATM_VC_STATISTICS                           0x53
+
+//*****************************************************************************
+//
+// In cases where a request defined above results in the return of a fixed size
+// data block, the following group of labels define the size of that block.  In
+// each of these cases, an access macro is also provided to write the response
+// data into an appropriately-sized array of uint8acters.
+//
+//*****************************************************************************
+#define USB_CDC_SIZE_COMM_FEATURE                                2
+#define USB_CDC_SIZE_LINE_CODING                                 7
+#define USB_CDC_SIZE_RINGER_PARMS                                4
+#define USB_CDC_SIZE_OPERATION_PARMS                             2
+#define USB_CDC_SIZE_UNIT_PARAMETER                              2
+#define USB_CDC_SIZE_PROFILE                                     64
+#define USB_CDC_SIZE_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    2
+#define USB_CDC_SIZE_ETHERNET_STATISTIC                          4
+#define USB_CDC_SIZE_ATM_DEVICE_STATISTICS                       4
+#define USB_CDC_SIZE_ATM_VC_STATISTICS                           4
+#define USB_CDC_SIZE_LINE_PARMS                                  10
+
+//*****************************************************************************
+//
+// NB: USB_CDC_SIZE_LINE_PARAMS assumes only a single call.  For multiple
+// calls, add 4 bytes per additional call.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// USB_CDC_GET_COMM_FEATURE & USB_CDC_SET_COMM_FEATURE
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// wValue (Feature Selector)
+//
+//*****************************************************************************
+#define USB_CDC_ABSTRACT_STATE                  0x0001
+#define USB_CDC_COUNTRY_SETTING                 0x0002
+
+//*****************************************************************************
+//
+// Data when feature selector is USB_DCD_ABSTRACT_STATE
+//
+//*****************************************************************************
+#define USB_CDC_ABSTRACT_CALL_DATA_MULTIPLEXED  0x0002
+#define USB_CDC_ABSTRACT_ENDPOINTS_IDLE         0x0001
+
+//*****************************************************************************
+//
+// Macros to populate the response data buffer (whose size in bytes is defined
+// by USB_CDC_SIZE_COMM_FEATURE).
+//
+//*****************************************************************************
+#define SetResponseCommFeature(pcBuf, usData)        \
+        do                                           \
+        {                                            \
+            (*(uint16 *)(pcBuf)) = (usData); \
+        }                                            \
+        while(0)
+
+//*****************************************************************************
+//
+// USB_CDC_SET_AUX_LINE_STATE, wValue
+//
+//*****************************************************************************
+#define USB_CDC_AUX_DISCONNECT                  0x0000
+#define USB_CDC_AUX_CONNECT                     0x0001
+
+//*****************************************************************************
+//
+// USB_CDC_SET_HOOK_STATE, wValue
+//
+//*****************************************************************************
+#define USB_CDC_ON_HOOK                         0x0000
+#define USB_CDC_OFF_HOOK                        0x0001
+#define USB_CDC_SNOOPING                        0x0002
+
+//*****************************************************************************
+//
+// USB_CDC_GET_LINE_CODING
+//
+//*****************************************************************************
+#define USB_CDC_STOP_BITS_1                     0x00
+#define USB_CDC_STOP_BITS_1_5                   0x01
+#define USB_CDC_STOP_BITS_2                     0x02
+
+#define USB_CDC_PARITY_NONE                     0x00
+#define USB_CDC_PARITY_ODD                      0x01
+#define USB_CDC_PARITY_EVEN                     0x02
+#define USB_CDC_PARITY_MARK                     0x03
+#define USB_CDC_PARITY_SPACE                    0x04
+
+//*****************************************************************************
+//
+// Macro to populate the response data buffer (whose size in bytes is defined
+// by USB_CDC_SIZE_LINE_CODING).
+//
+//*****************************************************************************
+#define SetResponseLineCoding(pcBuf, ucRate, ucStop, ucParity, ucDatabits) \
+        do                                                                 \
+        {                                                                  \
+            (*(uint32 *)(pcBuf)) = (ucRate);                        \
+            (*((uint8 *)(pcBuf) + 4)) = (ucStop);                  \
+            (*((uint8 *)(pcBuf) + 5)) = (ucParity);                \
+            (*((uint8 *)(pcBuf) + 6)) = (ucDatabits);              \
+        }                                                                  \
+        while(0)
+
+//*****************************************************************************
+//
+// USB_CDC_SET_CONTROL_LINE_STATE, wValue
+//
+//*****************************************************************************
+#define USB_CDC_DEACTIVATE_CARRIER              0x00
+#define USB_CDC_ACTIVATE_CARRIER                0x02
+#define USB_CDC_DTE_NOT_PRESENT                 0x00
+#define USB_CDC_DTE_PRESENT                     0x01
+
+//*****************************************************************************
+//
+// USB_CDC_SET_RINGER_PARMS, USB_CDC_GET_RINGER_PARMS and
+// USB_CDC_GET_LINE_PARMS (ulRingerBmp)
+//
+//*****************************************************************************
+#define USB_CDC_RINGER_EXISTS                   0x80000000
+#define USB_CDC_RINGER_DOES_NOT_EXIST           0x00000000
+
+//*****************************************************************************
+//
+// Macro to populate the response data buffer to USB_CDC_GET_RINGER_PARMS.
+// Parameter buf points to a buffer of size USB_CDC_SIZE_RINGER_PARMS bytes.
+//
+//*****************************************************************************
+#define SetResponseRingerParms(pcBuf, ucPattern, ucVolume, ulExists)          \
+        do                                                                    \
+        {                                                                     \
+            *(uint32 *)(pcBuf) = ((ucPattern) +                        \
+                                         ((ucVolume & 0xFF) << 8) +           \
+                                         (ulExists & USB_CDC_RINGER_EXISTS)); \
+        }                                                                     \
+        while(0)
+
+//*****************************************************************************
+//
+// Macros to extract fields from the USB_CDC_SET_RINGER_PARMS data
+//
+//*****************************************************************************
+#define GetRingerVolume(pcData)  (BYTE((pcData)+1))
+#define GetRingerPattern(pcData) (BYTE(pcData))
+#define GetRingerExists(pcData)  ((LONG(pcData)) & USB_CDC_RINGER_EXISTS)
+
+//*****************************************************************************
+//
+// USB_CDC_SET_OPERATION_PARMS, wValue
+//
+//*****************************************************************************
+#define USB_CDC_SIMPLE_MODE                     0x0000
+#define USB_CDC_STANDALONE_MODE                 0x0001
+#define USB_CDC_HOST_CENTRIC_MODE               0x0002
+
+//*****************************************************************************
+//
+// Macro to populate the response data buffer to USB_CDC_GET_OPERATION_PARMS.
+// Parameter buf points to a buffer of size USB_CDC_SIZE_OPERATION_PARMS
+// bytes.
+//
+//*****************************************************************************
+#define SetResponseOperationParms(pBbuf, usData) \
+        do                                       \
+        {                                        \
+            WORD(pcBuf) = (usData);              \
+        }                                        \
+        while(0)
+
+//*****************************************************************************
+//
+// USB_CDC_SET_LINE_PARMS, wParam - Line State Change
+//
+//*****************************************************************************
+#define USB_CDC_DROP_ACTIVE_CALL                0x0000
+#define USB_CDC_START_NEW_CALL                  0x0001
+#define USB_CDC_APPLY_RINGING                   0x0002
+#define USB_CDC_REMOVE_RINGING                  0x0003
+#define USB_CDC_SWITCH_CALL                     0x0004
+
+//*****************************************************************************
+//
+// Line state bitmap in USB_CDC_GET_LINE_PARMS response
+//
+//*****************************************************************************
+#define USB_CDC_LINE_IS_ACTIVE                  0x80000000
+#define USB_CDC_LINE_IS_IDLE                    0x00000000
+#define USB_CDC_LINE_NO_ACTIVE_CALL             0x000000FF
+
+#define USB_CDC_CALL_ACTIVE                     0x80000000
+
+//*****************************************************************************
+//
+// Call state value definitions
+//
+//*****************************************************************************
+#define USB_CDC_CALL_IDLE                       0x00000000
+#define USB_CDC_CALL_TYPICAL_DIALTONE           0x00000001
+#define USB_CDC_CALL_INTERRUPTED_DIALTONE       0x00000002
+#define USB_CDC_CALL_DIALING                    0x00000003
+#define USB_CDC_CALL_RINGBACK                   0x00000004
+#define USB_CDC_CALL_CONNECTED                  0x00000005
+#define USB_CDC_CALL_INCOMING                   0x00000006
+
+//*****************************************************************************
+//
+// Call state change value definitions
+//
+//*****************************************************************************
+#define USB_CDC_CALL_STATE_IDLE                 0x01
+#define USB_CDC_CALL_STATE_DIALING              0x02
+#define USB_CDC_CALL_STATE_RINGBACK             0x03
+#define USB_CDC_CALL_STATE_CONNECTED            0x04
+#define USB_CDC_CALL_STATE_INCOMING             0x05
+
+//*****************************************************************************
+//
+// Extra byte of data describing the connection type for
+// USB_CDC_CALL_STATE_CONNECTED.
+//
+//*****************************************************************************
+#define USB_CDC_VOICE                           0x00
+#define USB_CDC_ANSWERING_MACHINE               0x01
+#define USB_CDC_FAX                             0x02
+#define USB_CDC_MODEM                           0x03
+#define USB_CDC_UNKNOWN                         0xFF
+
+//*****************************************************************************
+//
+// Macro to extract call index from request in cases where wParam is
+// USB_CDC_SWITCH_CALL.
+//
+//*****************************************************************************
+#define GetCallIndex(pcData) (BYTE(pcData))
+
+//*****************************************************************************
+//
+// Macro to populate the CallState entries in response to request
+// USB_CDC_GET_LINE_PARMS.  The ucIndex parameter is a zero based index
+// indicating which call entry in the pcBuf response buffer to fill in.  Note
+// that pcBuf points to the first byte of the buffer (the wLength field).
+//
+//*****************************************************************************
+#define SetResponseCallState(pcBuf, ucIndex, ulActive, ucStateChange,   \
+                             ucState)                                   \
+        do                                                              \
+        {                                                               \
+            (LONG((uint8 *)(pcBuf) + (10 + (4 * (ucIndex))))) = \
+                (((ulActive) & USB_CDC_CALL_IS_ACTIVE) +                \
+                 (((ucStateChange) & 0xFF) << 8) +                      \
+                 ((ucState) & 0xFF));                                   \
+        }                                                               \
+        while(0)
+
+//*****************************************************************************
+//
+// Macro to populate the response data buffer (whose size in bytes is defined
+// by USB_CDC_SIZE_LINE_PARMS).  Note that this macro only populates fields for
+// a single call.  If multiple calls are being managed, additional 4 byte
+// fields must be appended to provide call state for each call after the first.
+// This may be done using the SetResponseCallState macro with the appropriate
+// call index supplied.
+//
+//*****************************************************************************
+#define SetResponseLineParms(pcBuf, usLength,                              \
+                             ucRingPattern, ucRingVolume, ulRingExists,    \
+                             ulLineActive, ucLineCallIndex,                \
+                             ulCallActive, ucCallStateChange, ucCallState) \
+        do                                                                 \
+        {                                                                  \
+            (WORD(pcBuf)) = (usLength);                                    \
+            SetResponseRingerParams(((uint8 *)(pcBuf) + 2),        \
+                                    (ucRingPattern), (ucRingVolume),       \
+                                    (ulRingExists));                       \
+            (LONG((uint8 *)(pcBuf) + 6)) =                         \
+                (((ulLineActive) & USB_CDC_LINE_IS_ACTIVE) +               \
+                 ((ucLineCallIndex) & 0xFF)) ;                             \
+            SetResponseCallState((pcBuf), 0, (ulCallActive),               \
+                                 (ucCallStateChange), (ucCallState));      \
+        }                                                                  \
+        while(0)
+
+//*****************************************************************************
+//
+// Notification Element definitions
+//
+//*****************************************************************************
+#define USB_CDC_NOTIFY_NETWORK_CONNECTION               0x00
+#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE               0x01
+#define USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE              0x08
+#define USB_CDC_NOTIFY_RING_DETECT                      0x09
+#define USB_CDC_NOTIFY_SERIAL_STATE                     0x20
+#define USB_CDC_NOTIFY_CALL_STATE_CHANGE                0x28
+#define USB_CDC_NOTIFY_LINE_STATE_CHANGE                0x29
+#define USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE          0x2A
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_NETWORK_CONNECTION, wValue
+//
+//*****************************************************************************
+#define USB_CDC_NETWORK_DISCONNECTED                    0x0000
+#define USB_CDC_NETWORK_CONNECTED                       0x0001
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE, wValue
+//
+//*****************************************************************************
+#define USB_CDC_AUX_JACK_ON_HOOK                        0x0000
+#define USB_CDC_AUX_JACK_OFF_HOOK                       0x0001
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_SERIAL_STATE, Data
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Number of bytes of data returned alongside this notification.
+//
+//*****************************************************************************
+#define USB_CDC_NOTIFY_SERIAL_STATE_SIZE                2
+
+#define USB_CDC_SERIAL_STATE_OVERRUN                    0x0040
+#define USB_CDC_SERIAL_STATE_PARITY                     0x0020
+#define USB_CDC_SERIAL_STATE_FRAMING                    0x0010
+#define USB_CDC_SERIAL_STATE_RING_SIGNAL                0x0008
+#define USB_CDC_SERIAL_STATE_BREAK                      0x0004
+#define USB_CDC_SERIAL_STATE_TXCARRIER                  0x0002
+#define USB_CDC_SERIAL_STATE_RXCARRIER                  0x0001
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_CALL_STATE_CHANGE, wValue
+//
+// Call state values are defined above in the group beginning
+// USB_CDC_CALL_STATE_IDLE.  Note that the data returned alongside this
+// notification are heavily dependent upon the call state being reported so no
+// specific lengths or access macros are provided here.
+//
+// Macro to construct the correct wValue for this notification given a state
+// and call index.
+//
+//*****************************************************************************
+#define SetNotifyCallStatewValue(psResult, ucCallState, ucIndex) \
+        do                                                       \
+        {                                                        \
+            (WORD(psResult)) = (((ucCallState) & 0xFF) +         \
+                                (((ucIndex) & 0xFF) << 8));      \
+        }                                                        \
+        while(0)
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_LINE_STATE_CHANGE, wValue
+//
+// Note that the data returned alongside this notification are heavily
+// dependent upon the call state being reported so no specific lengths or
+// access macros are provided here.
+//
+//*****************************************************************************
+#define USB_CDC_LINE_STATE_IDLE                         0x0000
+#define USB_CDC_LINE_STATE_HOLD                         0x0001
+#define USB_CDC_LINE_STATE_OFF_HOOK                     0x0002
+#define USB_CDC_LINE_STATE_ON_HOOK                      0x0003
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE, Data
+//
+// Macro to populate the 8 byte data structure returned alongside this
+// notification.
+//
+//*****************************************************************************
+#define SetNotifyConnectionSpeedChange(pcBuf, ulUSBitRate, ulDSBitRate) \
+        do                                                              \
+        {                                                               \
+            LONG(pcBuf) = ulUSBitRate;                                  \
+            LONG((uint8 *)(pcBuf) + 4) = ulDSBitRate;           \
+        }                                                               \
+        while(0)
+
+//*****************************************************************************
+//
+// Packed structure definitions for request/response data blocks
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// All structures defined in this section of the header require byte packing of
+// fields.  This is usually accomplished using the PACKED macro but, for IAR
+// Embedded Workbench, this requires a pragma.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+//! USB_CDC_GET/SET_LINE_CODING request-specific data.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The data terminal rate in bits per second.
+    //
+    uint32 ulRate;
+
+    //
+    //! The number of stop bits.  Valid values are USB_CDC_STOP_BITS_1,
+    //! USB_CDC_STOP_BITS_1_5 or USB_CDC_STOP_BITS_2
+    //
+    uint8 ucStop;
+
+    //
+    //! The parity setting.  Valid values are USB_CDC_PARITY_NONE,
+    //! USB_CDC_PARITY_ODD, USB_CDC_PARITY_EVEN, USB_CDC_PARITY_MARK and
+    //! USB_CDC_PARITY_SPACE.
+    //
+    uint8 ucParity;
+
+    //
+    //! The number of data bits per character.  Valid values are 5, 6, 7 and 8
+    //! in this implementation.
+    //
+    uint8 ucDatabits;
+}
+PACKED tLineCoding;
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBCDC_H__
diff --git a/bsp/rm48x50/HALCoGen/include/usbdcdc.h b/bsp/rm48x50/HALCoGen/include/usbdcdc.h
new file mode 100644
index 0000000000000000000000000000000000000000..b4bb5b1bb5c41d18d274c567fa931b261683cd4d
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/usbdcdc.h
@@ -0,0 +1,352 @@
+//*****************************************************************************
+//
+// usbdcdc.h - USBLib support for generic CDC ACM (serial) device.
+//
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+//
+//*****************************************************************************
+
+#ifndef __USBDCDC_H__
+#define __USBDCDC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup cdc_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// The first few sections of this header are private defines that are used by
+// the USB CDC Serial code and are here only to help with the application
+// allocating the correct amount of memory for the CDC Serial device code.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This enumeration holds the various states that the device can be in during
+// normal operation.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // Unconfigured.
+    //
+    CDC_STATE_UNCONFIGURED,
+
+    //
+    // No outstanding transaction remains to be completed.
+    //
+    CDC_STATE_IDLE,
+
+    //
+    // Waiting on completion of a send or receive transaction.
+    //
+    CDC_STATE_WAIT_DATA,
+
+    //
+    // Waiting for client to process data.
+    //
+    CDC_STATE_WAIT_CLIENT
+}
+tCDCState;
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data and state variables for the
+// CDC Serial device.  The memory for this structure is pointed to by the
+// psPrivateCDCSerData field in the tUSBDCDCDevice structure passed on
+// USBDCDCInit().
+//
+//*****************************************************************************
+typedef struct
+{
+    uint32 ulUSBBase;
+    tDeviceInfo *psDevInfo;
+    tConfigDescriptor *psConfDescriptor;
+    volatile tCDCState eCDCRxState;
+    volatile tCDCState eCDCTxState;
+    volatile tCDCState eCDCRequestState;
+    volatile tCDCState eCDCInterruptState;
+    volatile uint8 ucPendingRequest;
+    uint16 usBreakDuration;
+    uint16 usControlLineState;
+    uint16 usSerialState;
+    volatile uint16 usDeferredOpFlags;
+    uint16 usLastTxSize;
+    tLineCoding sLineCoding;
+    volatile tBoolean bRxBlocked;
+    volatile tBoolean bControlBlocked;
+    volatile tBoolean bConnected;
+    uint8 ucControlEndpoint;
+    uint8 ucBulkINEndpoint;
+    uint8 ucBulkOUTEndpoint;
+    uint8 ucInterfaceControl;
+    uint8 ucInterfaceData;
+}
+tCDCSerInstance;
+
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The number of bytes of workspace required by the CDC device class driver.
+// The client must provide a block of RAM of at least this size in the
+// psPrivateCDCSerData field of the tUSBCDCDevice structure passed on
+// USBDCDCInit().
+//
+// This value is deprecated and should not be used, any new code should just
+// pass in a tUSBCDCDevice structure in the psPrivateCDCSerData field.
+//
+//*****************************************************************************
+#define USB_CDCSER_WORKSPACE_SIZE (sizeof(tCDCSerInstance))
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used when working with composite devices.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The size of the memory that should be allocated to create a configuration
+//! descriptor for a single instance of the USB Serial CDC Device.
+//! This does not include the configuration descriptor which is automatically
+//! ignored by the composite device class.
+//
+// For reference this is sizeof(g_pIADSerDescriptor) +
+// sizeof(g_pCDCSerCommInterface) + sizeof(g_pCDCSerDataInterface)
+//
+//*****************************************************************************
+#define COMPOSITE_DCDC_SIZE     (8 + 35 + 23)
+
+//*****************************************************************************
+//
+// CDC-specific events These events are provided to the application in the
+// \e ulMsg parameter of the tUSBCallback function.
+//
+//*****************************************************************************
+
+//
+//! The host requests that the device send a BREAK condition on its
+//! serial communication channel.  The BREAK should remain active until
+//! a USBD_CDC_EVENT_CLEAR_BREAK event is received.
+//
+#define USBD_CDC_EVENT_SEND_BREAK (USBD_CDC_EVENT_BASE + 0)
+
+//
+//! The host requests that the device stop sending a BREAK condition on its
+//! serial communication channel.
+//
+#define USBD_CDC_EVENT_CLEAR_BREAK (USBD_CDC_EVENT_BASE + 1)
+
+//
+//! The host requests that the device set the RS232 signaling lines to
+//! a particular state.  The ulMsgValue parameter contains the RTS and
+//! DTR control line states as defined in table 51 of the USB CDC class
+//! definition and is a combination of the following values:
+//!
+//! (RTS) USB_CDC_DEACTIVATE_CARRIER or USB_CDC_ACTIVATE_CARRIER
+//! (DTR) USB_CDC_DTE_NOT_PRESENT or USB_CDC_DTE_PRESENT
+//
+#define USBD_CDC_EVENT_SET_CONTROL_LINE_STATE (USBD_CDC_EVENT_BASE + 2)
+
+//
+//! The host requests that the device set the RS232 communication
+//! parameters.  The pvMsgData parameter points to a tLineCoding structure
+//! defining the required number of bits per character, parity mode,
+//! number of stop bits and the baud rate.
+//
+#define USBD_CDC_EVENT_SET_LINE_CODING (USBD_CDC_EVENT_BASE + 3)
+
+//
+//! The host is querying the current RS232 communication parameters.  The
+//! pvMsgData parameter points to a tLineCoding structure that the
+//! application must fill with the current settings prior to returning
+//! from the callback.
+//
+#define USBD_CDC_EVENT_GET_LINE_CODING (USBD_CDC_EVENT_BASE + 4)
+
+//*****************************************************************************
+//
+//! The structure used by the application to define operating parameters for
+//! the CDC device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    uint16 usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    uint16 usPID;
+
+    //
+    //! The maximum power consumption of the device, expressed in milliamps.
+    //
+    uint16 usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self- or bus-powered and whether or not
+    //! it supports remote wakeup.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    uint8 ucPwrAttributes;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of all asynchronous control events related to the
+    //! operation of the device.
+    //
+    tUSBCallback pfnControlCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the control channel callback,
+    //! pfnControlCallback.
+    //
+    void *pvControlCBData;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events related to the device's data receive channel.
+    //
+    tUSBCallback pfnRxCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the receive channel callback,
+    //! pfnRxCallback.
+    //
+    void *pvRxCBData;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events related to the device's data transmit
+    //! channel.
+    //
+    tUSBCallback pfnTxCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the transmit channel callback,
+    //! pfnTxCallback.
+    //
+    void *pvTxCBData;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain the following string descriptor pointers in this order.
+    //! Language descriptor, Manufacturer name string (language 1), Product
+    //! name string (language 1), Serial number string (language 1),
+    //! Control interface description string (language 1), Configuration
+    //! description string (language 1).
+    //!
+    //! If supporting more than 1 language, the strings for indices 1 through 5
+    //! must be repeated for each of the other languages defined in the
+    //! language descriptor.
+    //
+    const uint8 * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors
+    //! array.  This must be 1 + (5 * number of supported languages).
+    //
+    uint32 ulNumStringDescriptors;
+
+    //
+    //! A pointer to the private instance data for this device.  This memory
+    //! must remain accessible for as long as the CDC device is in use and must
+    //! not be modified by any code outside the CDC class driver.
+    //
+    tCDCSerInstance *psPrivateCDCSerData;
+}
+tUSBDCDCDevice;
+
+extern tDeviceInfo g_sCDCSerDeviceInfo;
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void * USBDCDCCompositeInit(uint32 ulIndex,
+                                   const tUSBDCDCDevice *psCDCDevice);
+extern void *USBDCDCInit(uint32 ulIndex,
+                         const tUSBDCDCDevice *psCDCDevice);
+extern void USBDCDCTerm(void *pvInstance);
+extern void *USBDCDCSetControlCBData(void *pvInstance, void *pvCBData);
+extern void *USBDCDCSetRxCBData(void *pvInstance, void *pvCBData);
+extern void *USBDCDCSetTxCBData(void *pvInstance, void *pvCBData);
+extern uint32 USBDCDCPacketWrite(void *pvInstance,
+                                        uint8 *pcData,
+                                        uint32 ulLength,
+                                        tBoolean bLast);
+extern uint32 USBDCDCPacketRead(void *pvInstance,
+                                       uint8 *pcData,
+                                       uint32 ulLength,
+                                       tBoolean bLast);
+extern uint32 USBDCDCTxPacketAvailable(void *pvInstance);
+extern uint32 USBDCDCRxPacketAvailable(void *pvInstance);
+extern void USBDCDCSerialStateChange(void *pvInstance,
+                                     uint16 usState);
+extern void USBDCDCPowerStatusSet(void *pvInstance, uint8 ucPower);
+extern tBoolean USBDCDCRemoteWakeupRequest(void *pvInstance);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDCDC_H__
diff --git a/bsp/rm48x50/HALCoGen/include/usbdevice.h b/bsp/rm48x50/HALCoGen/include/usbdevice.h
new file mode 100644
index 0000000000000000000000000000000000000000..9d18615c244365c9e2d500a3be6ec992d4d96546
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/usbdevice.h
@@ -0,0 +1,140 @@
+//*****************************************************************************
+//
+// usbdevice.h - types and definitions used during USB enumeration.
+//
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+//
+//*****************************************************************************
+
+#ifndef __USBDEVICE_H__
+#define __USBDEVICE_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup device_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The maximum number of independent interfaces that any single device
+//! implementation can support.  Independent interfaces means interface
+//! descriptors with different bInterfaceNumber values - several interface
+//! descriptors offering different alternative settings but the same interface
+//! number count as a single interface.
+//
+//*****************************************************************************
+#define USB_MAX_INTERFACES_PER_DEVICE 8
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The default USB endpoint FIFO configuration structure.  This structure
+// contains definitions to set all USB FIFOs into single buffered mode with
+// no DMA use.  Each endpoint's FIFO is sized to hold the largest maximum
+// packet size for any interface alternate setting in the current config
+// descriptor.  A pointer to this structure may be passed in the psFIFOConfig
+// field of the tDeviceInfo structure passed to USBCDCInit if the application
+// does not require any special handling of the USB controller FIFO.
+//
+//*****************************************************************************
+extern const tFIFOConfig g_sUSBDefaultFIFOConfig;
+
+//*****************************************************************************
+//
+// Public APIs offered by the USB library device control driver.
+//
+//*****************************************************************************
+extern void USBDCDInit(uint32 ulIndex, tDeviceInfo *psDevice);
+extern void USBDCDTerm(uint32 ulIndex);
+extern void USBDCDStallEP0(uint32 ulIndex);
+extern void USBDCDRequestDataEP0(uint32 ulIndex, uint8 *pucData,
+                                 uint32 ulSize);
+extern void USBDCDSendDataEP0(uint32 ulIndex, uint8 *pucData,
+                              uint32 ulSize);
+extern void USBDCDSetDefaultConfiguration(uint32 ulIndex,
+                                          uint32 ulDefaultConfig);
+extern uint32 USBDCDConfigDescGetSize(const tConfigHeader *psConfig);
+extern uint32 USBDCDConfigDescGetNum(const tConfigHeader *psConfig,
+                                            uint32 ulType);
+extern tDescriptorHeader *USBDCDConfigDescGet(const tConfigHeader *psConfig,
+                                              uint32 ulType,
+                                              uint32 ulIndex,
+                                              uint32 *pulSection);
+extern uint32
+       USBDCDConfigGetNumAlternateInterfaces(const tConfigHeader *psConfig,
+                                             uint8 ucInterfaceNumber);
+extern tInterfaceDescriptor *
+       USBDCDConfigGetInterface(const tConfigHeader *psConfig,
+                                uint32 ulIndex, uint32 ulAltCfg,
+                                uint32 *pulSection);
+extern tEndpointDescriptor *
+       USBDCDConfigGetInterfaceEndpoint(const tConfigHeader *psConfig,
+                                        uint32 ulInterfaceNumber,
+                                        uint32 ulAltCfg,
+                                        uint32 ulIndex);
+extern void USBDCDPowerStatusSet(uint32 ulIndex, uint8 ucPower);
+extern tBoolean USBDCDRemoteWakeupRequest(uint32 ulIndex);
+
+//*****************************************************************************
+//
+// Early releases of the USB library had the following function named
+// incorrectly.  This macro ensures that any code which used the previous name
+// will still operate as expected.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define USBCDCConfigGetInterfaceEndpoint(a, b, c, d)                          \
+            USBDCDConfigGetInterfaceEndpoint((a), (b), (c), (d))
+#endif
+
+//*****************************************************************************
+//
+// Device mode interrupt handler for controller index 0.
+//
+//*****************************************************************************
+extern void USB0DeviceIntHandler(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBENUM_H__
diff --git a/bsp/rm48x50/HALCoGen/include/usbdevicepriv.h b/bsp/rm48x50/HALCoGen/include/usbdevicepriv.h
new file mode 100644
index 0000000000000000000000000000000000000000..1e794f4a0b9b072a090970da0883cb093bdc417f
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/usbdevicepriv.h
@@ -0,0 +1,65 @@
+//*****************************************************************************
+//
+// usbdevicepriv.h - Private header file used to share internal variables and
+//                   function prototypes between the various device-related
+//                   modules in the USB library.  This header MUST NOT be
+//                   used by application code.
+//
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+//
+//*****************************************************************************
+
+#ifndef __USBDEVICEPRIV_H__
+#define __USBDEVICEPRIV_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Device enumeration functions provided by device/usbenum.c and called from
+// the interrupt handler in device/usbhandler.c
+//
+//*****************************************************************************
+extern tBoolean USBDeviceConfig(uint32 ulIndex,
+                                const tConfigHeader *psConfig,
+                                const tFIFOConfig *psFIFOConfig);
+extern tBoolean USBDeviceConfigAlternate(uint32 ulIndex,
+                                         const tConfigHeader *psConfig,
+                                         uint8 ucInterfaceNum,
+                                         uint8 ucAlternateSetting);
+extern void USBDeviceResumeTickHandler(uint32 ulIndex);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDEVICEPRIV_H__
diff --git a/bsp/rm48x50/HALCoGen/include/usblib.h b/bsp/rm48x50/HALCoGen/include/usblib.h
new file mode 100644
index 0000000000000000000000000000000000000000..585ad79a89295c002ae928a655a52fbe26d40c87
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/include/usblib.h
@@ -0,0 +1,1853 @@
+//
+// usblib.h - Main header file for the USB Library.
+//
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+//
+//*****************************************************************************
+
+#ifndef __USBLIB_H__
+#define __USBLIB_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+/* standard device requests -- USB_SetupDataPacket::bRequest */
+#define USB_REQUEST_GETSTATUS           (0u)
+#define USB_REQUEST_CLEARFEATURE        (1u)
+#define USB_REQUEST_SETFEATURE          (3u)
+#define USB_REQUEST_SETADDRESS          (5u)
+#define USB_REQUEST_GETDESCRIPTOR       (6u)
+#define USB_REQUEST_SETDESCRIPTOR       (7u)
+#define USB_REQUEST_GETCONFIGURATION    (8u)
+#define USB_REQUEST_SETCONFIGURATION    (9u)
+#define USB_REQUEST_GETINTERFACE        (10u)
+#define USB_REQUEST_SETINTERFACE        (11u)
+#define USB_REQUEST_SYNCHFRAME          (12u)
+
+
+//*****************************************************************************
+//
+// This is the maximum number of endpoints supported by the usblib.
+//
+//*****************************************************************************
+#define USBLIB_NUM_EP           16   // Number of supported endpoints.
+
+//*****************************************************************************
+//
+// The following macro allows compiler-independent syntax to be used to
+// define packed structures.  A typical structure definition using these
+// macros will look similar to the following example:
+//
+//   #ifdef ewarm
+//   #pragma pack(1)
+//   #endif
+//
+//   typedef struct _PackedStructName
+//   {
+//      uint32 ulFirstField;
+//      char cCharMember;
+//      uint16 usShort;
+//   }
+//   PACKED tPackedStructName;
+//
+//   #ifdef ewarm
+//   #pragma pack()
+//   #endif
+//
+// The conditional blocks related to ewarm include the #pragma pack() lines
+// only if the IAR Embedded Workbench compiler is being used.  Unfortunately,
+// it is not possible to emit a #pragma from within a macro definition so this
+// must be done explicitly.
+//
+//*****************************************************************************
+#if defined(ccs) ||             \
+    defined(codered) ||         \
+    defined(gcc) ||             \
+    defined(rvmdk) ||           \
+    defined(__ARMCC_VERSION) || \
+    defined(sourcerygxx)
+#define PACKED __attribute__ ((packed))
+#elif defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#define PACKED
+#elif (__TMS470__)
+#define PACKED __attribute__ ((packed))
+#else
+#error Unrecognized COMPILER!
+#endif
+
+//*****************************************************************************
+//
+// Assorted language IDs from the document "USB_LANGIDs.pdf" provided by the
+// USB Implementers' Forum (Version 1.0).
+//
+//*****************************************************************************
+#define USB_LANG_CHINESE_PRC    0x0804      // Chinese (PRC)
+#define USB_LANG_CHINESE_TAIWAN 0x0404      // Chinese (Taiwan)
+#define USB_LANG_EN_US          0x0409      // English (United States)
+#define USB_LANG_EN_UK          0x0809      // English (United Kingdom)
+#define USB_LANG_EN_AUS         0x0C09      // English (Australia)
+#define USB_LANG_EN_CA          0x1009      // English (Canada)
+#define USB_LANG_EN_NZ          0x1409      // English (New Zealand)
+#define USB_LANG_FRENCH         0x040C      // French (Standard)
+#define USB_LANG_GERMAN         0x0407      // German (Standard)
+#define USB_LANG_HINDI          0x0439      // Hindi
+#define USB_LANG_ITALIAN        0x0410      // Italian (Standard)
+#define USB_LANG_JAPANESE       0x0411      // Japanese
+#define USB_LANG_KOREAN         0x0412      // Korean
+#define USB_LANG_ES_TRAD        0x040A      // Spanish (Traditional)
+#define USB_LANG_ES_MODERN      0x0C0A      // Spanish (Modern)
+#define USB_LANG_SWAHILI        0x0441      // Swahili (Kenya)
+#define USB_LANG_URDU_IN        0x0820      // Urdu (India)
+#define USB_LANG_URDU_PK        0x0420      // Urdu (Pakistan)
+//*****************************************************************************
+//
+//! \addtogroup usbchap9_src
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Note:
+//
+// Structure definitions which are derived directly from the USB specification
+// use field names from the specification.  Since a somewhat different version
+// of Hungarian prefix notation is used from the Stellaris standard, beware of
+// making assumptions about field sizes based on the field prefix when using
+// these structures.  Of particular note is the difference in the meaning of
+// the 'i' prefix.  In USB structures, this indicates a single byte index
+// whereas in Stellaris code, this is a 32 bit integer.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// All structures defined in this section of the header require byte packing of
+// fields.  This is usually accomplished using the PACKED macro but, for IAR
+// Embedded Workbench, this requires a pragma.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+// Definitions related to standard USB device requests (sections 9.3 & 9.4)
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The standard USB request header as defined in section 9.3 of the USB 2.0
+//! specification.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Determines the type and direction of the request.
+    //
+    uint8 bmRequestType;
+
+    //
+    //! Identifies the specific request being made.
+    //
+    uint8 bRequest;
+
+    //
+    //! Word-sized field that varies according to the request.
+    //
+    uint16 wValue;
+
+    //
+    //! Word-sized field that varies according to the request; typically used
+    //! to pass an index or offset.
+    //
+    uint16 wIndex;
+
+    //
+    //! The number of bytes to transfer if there is a data stage to the
+    //! request.
+    //
+    uint16 wLength;
+
+}
+PACKED tUSBRequest;
+
+//*****************************************************************************
+//
+// The following defines are used with the bmRequestType member of tUSBRequest.
+//
+// Request types have 3 bit fields:
+// 4:0 - Is the recipient type.
+// 6:5 - Is the request type.
+// 7 - Is the direction of the request.
+//
+//*****************************************************************************
+#define USB_RTYPE_DIR_IN        0x80
+#define USB_RTYPE_DIR_OUT       0x00
+
+#define USB_RTYPE_TYPE_M        0x60
+#define USB_RTYPE_VENDOR        0x40
+#define USB_RTYPE_CLASS         0x20
+#define USB_RTYPE_STANDARD      0x00
+
+#define USB_RTYPE_RECIPIENT_M   0x1f
+#define USB_RTYPE_OTHER         0x03
+#define USB_RTYPE_ENDPOINT      0x02
+#define USB_RTYPE_INTERFACE     0x01
+#define USB_RTYPE_DEVICE        0x00
+
+//*****************************************************************************
+//
+// Standard USB requests IDs used in the bRequest field of tUSBRequest.
+//
+//*****************************************************************************
+#define USBREQ_GET_STATUS       0x00
+#define USBREQ_CLEAR_FEATURE    0x01
+#define USBREQ_SET_FEATURE      0x03
+#define USBREQ_SET_ADDRESS      0x05
+#define USBREQ_GET_DESCRIPTOR   0x06
+#define USBREQ_SET_DESCRIPTOR   0x07
+#define USBREQ_GET_CONFIG       0x08
+#define USBREQ_SET_CONFIG       0x09
+#define USBREQ_GET_INTERFACE    0x0a
+#define USBREQ_SET_INTERFACE    0x0b
+#define USBREQ_SYNC_FRAME       0x0c
+
+//*****************************************************************************
+//
+// Data returned from a USBREQ_GET_STATUS request to a device.
+//
+//*****************************************************************************
+#define USB_STATUS_SELF_PWR     0x0001  // Currently self powered.
+#define USB_STATUS_BUS_PWR      0x0000  // Currently bus-powered.
+#define USB_STATUS_PWR_M        0x0001  // Mask for power mode.
+#define USB_STATUS_REMOTE_WAKE  0x0002  // Remote wake-up is currently enabled.
+
+//*****************************************************************************
+//
+// Feature Selectors (tUSBRequest.wValue) passed on USBREQ_CLEAR_FEATURE and
+// USBREQ_SET_FEATURE.
+//
+//*****************************************************************************
+#define USB_FEATURE_EP_HALT     0x0000  // Endpoint halt feature.
+#define USB_FEATURE_REMOTE_WAKE 0x0001  // Remote wake feature, device only.
+#define USB_FEATURE_TEST_MODE   0x0002  // Test mode
+
+//*****************************************************************************
+//
+// Endpoint Selectors (tUSBRequest.wIndex) passed on USBREQ_CLEAR_FEATURE,
+// USBREQ_SET_FEATURE and USBREQ_GET_STATUS.
+//
+//*****************************************************************************
+#define USB_REQ_EP_NUM_M   0x007F
+#define USB_REQ_EP_DIR_M   0x0080
+#define USB_REQ_EP_DIR_IN  0x0080
+#define USB_REQ_EP_DIR_OUT 0x0000
+
+//*****************************************************************************
+//
+// Standard USB descriptor types.  These values are passed in the upper bytes
+// of tUSBRequest.wValue on USBREQ_GET_DESCRIPTOR and also appear in the
+// bDescriptorType field of standard USB descriptors.
+//
+//*****************************************************************************
+#define USB_DTYPE_DEVICE        1
+#define USB_DTYPE_CONFIGURATION 2
+#define USB_DTYPE_STRING        3
+#define USB_DTYPE_INTERFACE     4
+#define USB_DTYPE_ENDPOINT      5
+#define USB_DTYPE_DEVICE_QUAL   6
+#define USB_DTYPE_OSPEED_CONF   7
+#define USB_DTYPE_INTERFACE_PWR 8
+#define USB_DTYPE_OTG           9
+#define USB_DTYPE_INTERFACE_ASC 11
+#define USB_DTYPE_CS_INTERFACE  36
+
+//*****************************************************************************
+//
+// Definitions related to USB descriptors (sections 9.5 & 9.6)
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This structure describes a generic descriptor header.  These fields are to
+//! be found at the beginning of all valid USB descriptors.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor (including this length byte) expressed
+    //! in bytes.
+    //
+    uint8 bLength;
+
+    //
+    //! The type identifier of the descriptor whose information follows.  For
+    //! standard descriptors, this field could contain, for example,
+    //! USB_DTYPE_DEVICE to identify a device descriptor or USB_DTYPE_ENDPOINT
+    //! to identify an endpoint descriptor.
+    //
+    uint8 bDescriptorType;
+}
+PACKED tDescriptorHeader;
+
+//*****************************************************************************
+//
+//! This structure describes the USB device descriptor as defined in USB
+//! 2.0 specification section 9.6.1.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All device descriptors are
+    //! 18 bytes long.
+    //
+    uint8 bLength;
+
+    //
+    //! The type of the descriptor.  For a device descriptor, this will be
+    //! USB_DTYPE_DEVICE (1).
+    //
+    uint8 bDescriptorType;
+
+    //
+    //! The USB Specification Release Number in BCD format.  For USB 2.0, this
+    //! will be 0x0200.
+    //
+    uint16 bcdUSB;
+
+    //
+    //! The device class code.
+    //
+    uint8 bDeviceClass;
+
+    //
+    //! The device subclass code.  This value qualifies the value found in the
+    //! bDeviceClass field.
+    //
+    uint8 bDeviceSubClass;
+
+    //
+    //! The device protocol code.  This value is qualified by the values of
+    //! bDeviceClass and bDeviceSubClass.
+    //
+    uint8 bDeviceProtocol;
+
+    //
+    //! The maximum packet size for endpoint zero.  Valid values are 8, 16, 32
+    //! and 64.
+    //
+    uint8 bMaxPacketSize0;
+
+    //
+    //! The device Vendor ID (VID) as assigned by the USB-IF.
+    //
+    uint16 idVendor;
+
+    //
+    //! The device Product ID (PID) as assigned by the manufacturer.
+    //
+    uint16 idProduct;
+
+    //
+    //! The device release number in BCD format.
+    //
+    uint16 bcdDevice;
+
+    //
+    //! The index of a string descriptor describing the manufacturer.
+    //
+    uint8 iManufacturer;
+
+    //
+    //! The index of a string descriptor describing the product.
+    //
+    uint8 iProduct;
+
+    //
+    //! The index of a string descriptor describing the device's serial
+    //! number.
+    //
+    uint8 iSerialNumber;
+
+    //
+    //! The number of possible configurations offered by the device.  This
+    //! field indicates the number of distinct configuration descriptors that
+    //! the device offers.
+    //
+    uint8 bNumConfigurations;
+}
+PACKED tDeviceDescriptor;
+
+//*****************************************************************************
+//
+// USB Device Class codes used in the tDeviceDescriptor.bDeviceClass field.
+// Definitions for the bDeviceSubClass and bDeviceProtocol fields are device
+// specific and can be found in the appropriate device class header files.
+//
+//*****************************************************************************
+#define USB_CLASS_DEVICE        0x00
+#define USB_CLASS_AUDIO         0x01
+#define USB_CLASS_CDC           0x02
+#define USB_CLASS_HID           0x03
+#define USB_CLASS_PHYSICAL      0x05
+#define USB_CLASS_IMAGE         0x06
+#define USB_CLASS_PRINTER       0x07
+#define USB_CLASS_MASS_STORAGE  0x08
+#define USB_CLASS_HUB           0x09
+#define USB_CLASS_CDC_DATA      0x0a
+#define USB_CLASS_SMART_CARD    0x0b
+#define USB_CLASS_SECURITY      0x0d
+#define USB_CLASS_VIDEO         0x0e
+#define USB_CLASS_HEALTHCARE    0x0f
+#define USB_CLASS_DIAG_DEVICE   0xdc
+#define USB_CLASS_WIRELESS      0xe0
+#define USB_CLASS_MISC          0xef
+#define USB_CLASS_APP_SPECIFIC  0xfe
+#define USB_CLASS_VEND_SPECIFIC 0xff
+#define USB_CLASS_EVENTS        0xffffffff
+
+//*****************************************************************************
+//
+// Generic values for undefined subclass and protocol.
+//
+//*****************************************************************************
+#define USB_SUBCLASS_UNDEFINED  0x00
+#define USB_PROTOCOL_UNDEFINED  0x00
+
+//*****************************************************************************
+//
+// The following are the miscellaneous subclass values.
+//
+//*****************************************************************************
+#define USB_MISC_SUBCLASS_SYNC      0x01
+#define USB_MISC_SUBCLASS_COMMON    0x02
+
+//*****************************************************************************
+//
+// These following are miscellaneous protocol values.
+//
+//*****************************************************************************
+#define USB_MISC_PROTOCOL_IAD   0x01
+
+//*****************************************************************************
+//
+//! This structure describes the USB device qualifier descriptor as defined in
+//! the USB 2.0 specification, section 9.6.2.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All device qualifier
+    //! descriptors are 10 bytes long.
+    //
+    uint8 bLength;
+
+    //
+    //! The type of the descriptor.  For a device descriptor, this will be
+    //! USB_DTYPE_DEVICE_QUAL (6).
+    //
+    uint8 bDescriptorType;
+
+    //
+    //! The USB Specification Release Number in BCD format.  For USB 2.0, this
+    //! will be 0x0200.
+    //
+    uint16 bcdUSB;
+
+    //
+    //! The device class code.
+    //
+    uint8 bDeviceClass;
+
+    //
+    //! The device subclass code.  This value qualifies the value found in the
+    //! bDeviceClass field.
+    //
+    uint8 bDeviceSubClass;
+
+    //
+    //! The device protocol code.  This value is qualified by the values of
+    //! bDeviceClass and bDeviceSubClass.
+    //
+    uint8 bDeviceProtocol;
+
+    //
+    //! The maximum packet size for endpoint zero when operating at a speed
+    //! other than high speed.
+    //
+    uint8 bMaxPacketSize0;
+
+    //
+    //! The number of other-speed configurations supported.
+    //
+    uint8 bNumConfigurations;
+
+    //
+    //! Reserved for future use.  Must be set to zero.
+    //
+    uint8 bReserved;
+}
+PACKED tDeviceQualifierDescriptor;
+
+//*****************************************************************************
+//
+//! This structure describes the USB configuration descriptor as defined in
+//! USB 2.0 specification section 9.6.3.  This structure also applies to the
+//! USB other speed configuration descriptor defined in section 9.6.4.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All configuration descriptors
+    //! are 9 bytes long.
+    //
+    uint8 bLength;
+
+    //
+    //! The type of the descriptor.  For a configuration descriptor, this will
+    //! be USB_DTYPE_CONFIGURATION (2).
+    //
+    uint8 bDescriptorType;
+
+    //
+    //! The total length of data returned for this configuration.  This
+    //! includes the combined length of all descriptors (configuration,
+    //! interface, endpoint and class- or vendor-specific) returned for this
+    //! configuration.
+    //
+    uint16 wTotalLength;
+
+    //
+    //! The number of interface supported by this configuration.
+    //
+    uint8 bNumInterfaces;
+
+    //
+    //! The value used as an argument to the SetConfiguration standard request
+    //! to select this configuration.
+    //
+    uint8 bConfigurationValue;
+
+    //
+    //! The index of a string descriptor describing this configuration.
+    //
+    uint8 iConfiguration;
+
+    //
+    //! Attributes of this configuration.
+    //
+    uint8 bmAttributes;
+
+    //
+    //! The maximum power consumption of the USB device from the bus in this
+    //! configuration when the device is fully operational.  This is expressed
+    //! in units of 2mA so, for example, 100 represents 200mA.
+    //
+    uint8 bMaxPower;
+}
+PACKED tConfigDescriptor;
+
+//*****************************************************************************
+//
+// Flags used in constructing the value assigned to the field
+// tConfigDescriptor.bmAttributes.  Note that bit 7 is reserved and must be set
+// to 1.
+//
+//*****************************************************************************
+#define USB_CONF_ATTR_PWR_M     0xC0
+
+#define USB_CONF_ATTR_SELF_PWR  0xC0
+#define USB_CONF_ATTR_BUS_PWR   0x80
+#define USB_CONF_ATTR_RWAKE     0xA0
+
+//*****************************************************************************
+//
+//! This structure describes the USB interface descriptor as defined in USB
+//! 2.0 specification section 9.6.5.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All interface descriptors
+    //! are 9 bytes long.
+    //
+    uint8 bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_INTERFACE (4).
+    //
+    uint8 bDescriptorType;
+
+    //
+    //! The number of this interface.  This is a zero based index into the
+    //! array of concurrent interfaces supported by this configuration.
+    //
+    uint8 bInterfaceNumber;
+
+    //
+    //! The value used to select this alternate setting for the interface
+    //! defined in bInterfaceNumber.
+    //
+    uint8 bAlternateSetting;
+
+    //
+    //! The number of endpoints used by this interface (excluding endpoint
+    //! zero).
+    //
+    uint8 bNumEndpoints;
+
+    //
+    //! The interface class code as assigned by the USB-IF.
+    //
+    uint8 bInterfaceClass;
+
+    //
+    //! The interface subclass code as assigned by the USB-IF.
+    //
+    uint8 bInterfaceSubClass;
+
+    //
+    //! The interface protocol code as assigned by the USB-IF.
+    //
+    uint8 bInterfaceProtocol;
+
+    //
+    //! The index of a string descriptor describing this interface.
+    //
+    uint8 iInterface;
+}
+PACKED tInterfaceDescriptor;
+
+//*****************************************************************************
+//
+//! This structure describes the USB endpoint descriptor as defined in USB
+//! 2.0 specification section 9.6.6.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All endpoint descriptors
+    //! are 7 bytes long.
+    //
+    uint8 bLength;
+
+    //
+    //! The type of the descriptor.  For an endpoint descriptor, this will
+    //! be USB_DTYPE_ENDPOINT (5).
+    //
+    uint8 bDescriptorType;
+
+    //
+    //! The address of the endpoint.  This field contains the endpoint number
+    //! ORed with flag USB_EP_DESC_OUT or USB_EP_DESC_IN to indicate the
+    //! endpoint direction.
+    //
+    uint8 bEndpointAddress;
+
+    //
+    //! The endpoint transfer type, USB_EP_ATTR_CONTROL, USB_EP_ATTR_ISOC,
+    //! USB_EP_ATTR_BULK or USB_EP_ATTR_INT and, if isochronous, additional
+    //! flags indicating usage type and synchronization method.
+    //
+    uint8 bmAttributes;
+
+    //
+    //! The maximum packet size this endpoint is capable of sending or
+    //! receiving when this configuration is selected.  For high speed
+    //! isochronous or interrupt endpoints, bits 11 and 12 are used to
+    //! pass additional information.
+    //
+    uint16 wMaxPacketSize;
+
+    //
+    //! The polling interval for data transfers expressed in frames or
+    //! micro frames depending upon the operating speed.
+    //
+    uint8 bInterval;
+}
+PACKED tEndpointDescriptor;
+
+//*****************************************************************************
+//
+// Flags used in constructing the value assigned to the field
+// tEndpointDescriptor.bEndpointAddress.
+//
+//*****************************************************************************
+#define USB_EP_DESC_OUT                 0x00
+#define USB_EP_DESC_IN                  0x80
+#define USB_EP_DESC_NUM_M               0x0f
+
+//*****************************************************************************
+//
+// Mask used to extract the maximum packet size (in bytes) from the
+// wMaxPacketSize field of the endpoint descriptor.
+//
+//*****************************************************************************
+#define USB_EP_MAX_PACKET_COUNT_M       0x07FF
+
+//*****************************************************************************
+//
+// Endpoint attributes used in tEndpointDescriptor.bmAttributes.
+//
+//*****************************************************************************
+#define USB_EP_ATTR_CONTROL             0x00
+#define USB_EP_ATTR_ISOC                0x01
+#define USB_EP_ATTR_BULK                0x02
+#define USB_EP_ATTR_INT                 0x03
+#define USB_EP_ATTR_TYPE_M              0x03
+
+#define USB_EP_ATTR_ISOC_M              0x0c
+#define USB_EP_ATTR_ISOC_NOSYNC         0x00
+#define USB_EP_ATTR_ISOC_ASYNC          0x04
+#define USB_EP_ATTR_ISOC_ADAPT          0x08
+#define USB_EP_ATTR_ISOC_SYNC           0x0c
+#define USB_EP_ATTR_USAGE_M             0x30
+#define USB_EP_ATTR_USAGE_DATA          0x00
+#define USB_EP_ATTR_USAGE_FEEDBACK      0x10
+#define USB_EP_ATTR_USAGE_IMPFEEDBACK   0x20
+
+//*****************************************************************************
+//
+//! This structure describes the USB string descriptor for index 0 as defined
+//! in USB 2.0 specification section 9.6.7.  Note that the number of language
+//! IDs is variable and can be determined by examining bLength.  The number of
+//! language IDs present in the descriptor is given by ((bLength - 2) / 2).
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  This value will vary
+    //! depending upon the number of language codes provided in the descriptor.
+    //
+    uint8 bLength;
+
+    //
+    //! The type of the descriptor.  For a string descriptor, this will be
+    //! USB_DTYPE_STRING (3).
+    //
+    uint8 bDescriptorType;
+
+    //
+    //! The language code (LANGID) for the first supported language.  Note that
+    //! this descriptor may support multiple languages, in which case, the
+    //! number of elements in the wLANGID array will increase and bLength will
+    //! be updated accordingly.
+    //
+    uint16 wLANGID[1];
+}
+PACKED tString0Descriptor;
+
+//*****************************************************************************
+//
+//! This structure describes the USB string descriptor for all string indexes
+//! other than 0 as defined in USB 2.0 specification section 9.6.7.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  This value will be 2 greater
+    //! than the number of bytes comprising the UNICODE string that the
+    //! descriptor contains.
+    //
+    uint8 bLength;
+
+    //
+    //! The type of the descriptor.  For a string descriptor, this will be
+    //! USB_DTYPE_STRING (3).
+    //
+    uint8 bDescriptorType;
+
+    //
+    //! The first byte of the UNICODE string.  This string is not NULL
+    //! terminated.  Its length (in bytes) can be computed by subtracting 2
+    //! from the value in the bLength field.
+    //
+    uint8 bString;
+}
+PACKED tStringDescriptor;
+
+//*****************************************************************************
+//
+//! Write a 2 byte uint16 value to a USB descriptor block.
+//!
+//! \param usValue is the two byte uint16 that is to be written to
+//! the descriptor.
+//!
+//! This helper macro is used in descriptor definitions to write two-byte
+//! values.  Since the configuration descriptor contains all interface and
+//! endpoint descriptors in a contiguous block of memory, these descriptors are
+//! typically defined using an array of bytes rather than as packed structures.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define USBShort(usValue)       (usValue & 0xff), (usValue >> 8)
+
+//*****************************************************************************
+//
+//! Write a 3 byte uint32 value to a USB descriptor block.
+//!
+//! \param ulValue is the three byte unsigned value that is to be written to the
+//! descriptor.
+//!
+//! This helper macro is used in descriptor definitions to write three-byte
+//! values.  Since the configuration descriptor contains all interface and
+//! endpoint descriptors in a contiguous block of memory, these descriptors are
+//! typically defined using an array of bytes rather than as packed structures.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define USB3Byte(ulValue)       (ulValue & 0xff),              \
+                                ((ulValue >> 8) & 0xff),       \
+                                ((ulValue >> 16) & 0xff)
+
+//*****************************************************************************
+//
+//! Write a 4 byte uint32 value to a USB descriptor block.
+//!
+//! \param ulValue is the four byte uint32 that is to be written to the
+//! descriptor.
+//!
+//! This helper macro is used in descriptor definitions to write four-byte
+//! values.  Since the configuration descriptor contains all interface and
+//! endpoint descriptors in a contiguous block of memory, these descriptors are
+//! typically defined using an array of bytes rather than as packed structures.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define USBLong(ulValue)        (ulValue & 0xff),              \
+                                ((ulValue >> 8) & 0xff),       \
+                                ((ulValue >> 16) & 0xff),      \
+                                ((ulValue >> 24) & 0xff)
+
+//*****************************************************************************
+//
+//! Traverse to the next USB descriptor in a block.
+//!
+//! \param ptr points to the first byte of a descriptor in a block of
+//! USB descriptors.
+//!
+//! This macro aids in traversing lists of descriptors by returning a pointer
+//! to the next descriptor in the list given a pointer to the current one.
+//!
+//! \return Returns a pointer to the next descriptor in the block following
+//! \e ptr.
+//!
+//*****************************************************************************
+#define NEXT_USB_DESCRIPTOR(ptr)                         \
+        (tDescriptorHeader *)(((uint8 *)(ptr)) + \
+                              *((uint8 *)(ptr)))
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+// Close the usbchap9_src Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup device_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Function prototype for any standard USB request.
+//
+//*****************************************************************************
+typedef void (* tStdRequest)(void *pvInstance, tUSBRequest *pUSBRequest);
+
+//*****************************************************************************
+//
+// Data callback for receiving data from an endpoint.
+//
+//*****************************************************************************
+typedef void (* tInfoCallback)(void *pvInstance, uint32 ulInfo);
+
+//*****************************************************************************
+//
+// Callback made to indicate that an interface alternate setting change has
+// occurred.
+//
+//*****************************************************************************
+typedef void (* tInterfaceCallback)(void *pvInstance,
+                                    uint8 ucInterfaceNum,
+                                    uint8 ucAlternateSetting);
+
+//*****************************************************************************
+//
+// Generic interrupt handler callbacks.
+//
+//*****************************************************************************
+typedef void (* tUSBIntHandler)(void *pvInstance);
+
+//*****************************************************************************
+//
+// Interrupt handler callbacks that have status information.
+//
+//*****************************************************************************
+typedef void (* tUSBEPIntHandler)(void *pvInstance,
+                                  uint32 ulStatus);
+
+//*****************************************************************************
+//
+// Generic handler callbacks that are used when the callers needs to call into
+// an instance of class.
+//
+//*****************************************************************************
+typedef void (* tUSBDeviceHandler)(void *pvInstance,
+                                   uint32 ulRequest,
+                                   void *pvRequestData);
+
+//*****************************************************************************
+//
+//! USB event handler functions used during enumeration and operation of the
+//! device stack.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! This callback is made whenever the USB host requests a non-standard
+    //! descriptor from the device.
+    //
+    tStdRequest pfnGetDescriptor;
+
+    //
+    //! This callback is made whenever the USB host makes a non-standard
+    //! request.
+    //
+    tStdRequest pfnRequestHandler;
+
+    //
+    //! This callback is made in response to a SetInterface request from the
+    //! host.
+    //
+    tInterfaceCallback pfnInterfaceChange;
+
+    //
+    //! This callback is made in response to a SetConfiguration request from
+    //! the host.
+    //
+    tInfoCallback pfnConfigChange;
+
+    //
+    //! This callback is made when data has been received following to a call
+    //! to USBDCDRequestDataEP0.
+    //
+    tInfoCallback pfnDataReceived;
+
+    //
+    //! This callback is made when data has been transmitted following a call
+    //! to USBDCDSendDataEP0.
+    //
+    tInfoCallback pfnDataSent;
+
+    //
+    //! This callback is made when a USB reset is detected.
+    //
+    tUSBIntHandler pfnResetHandler;
+
+    //
+    //! This callback is made when the bus has been inactive long enough to
+    //! trigger a suspend condition.
+    //
+    tUSBIntHandler pfnSuspendHandler;
+
+    //
+    //! This is called when resume signaling is detected.
+    //
+    tUSBIntHandler pfnResumeHandler;
+
+    //
+    //! This callback is made when the device is disconnected from the USB bus.
+    //
+    tUSBIntHandler pfnDisconnectHandler;
+
+    //
+    //! This callback is made to inform the device of activity on all endpoints
+    //! other than endpoint zero.
+    //
+    tUSBEPIntHandler pfnEndpointHandler;
+
+    //
+    //! This generic handler is provided to allow requests based on
+    //! a given instance to be passed into a device.  This is commonly used
+    //! by a top level composite device that is using multiple instances of
+    //! a class.
+    //
+    tUSBDeviceHandler pfnDeviceHandler;
+}
+tCustomHandlers;
+
+//*****************************************************************************
+//
+//! This structure defines how a given endpoint's FIFO is configured in
+//! relation to the maximum packet size for the endpoint as specified in the
+//! endpoint descriptor.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The multiplier to apply to an endpoint's maximum packet size when
+    //! configuring the FIFO for that endpoint.  For example, setting this
+    //! value to 2 will result in a 128 byte FIFO being configured if
+    //! bDoubleBuffer is FALSE and the associated endpoint is set to use a 64
+    //! byte maximum packet size.
+    //
+    uint8 cMultiplier;
+
+    //
+    //! This field indicates whether to configure an endpoint's FIFO to be
+    //! double- or single-buffered.  If TRUE, a double-buffered FIFO is
+    //! created and the amount of required FIFO storage is multiplied by two.
+    //
+    tBoolean bDoubleBuffer;
+
+    //
+    //! This field defines endpoint mode flags which cannot be deduced from
+    //! the configuration descriptor, namely any in the set USB_EP_AUTO_xxx or
+    //! USB_EP_DMA_MODE_x.  USBDCDConfig adds these flags to the endpoint
+    //! mode and direction determined from the config descriptor before it
+    //! configures the endpoint using a call to USBDevEndpointConfigSet().
+    //
+    uint16 usEPFlags;
+}
+tFIFOEntry;
+
+//*****************************************************************************
+//
+//! This structure defines endpoint and FIFO configuration information for
+//! all endpoints that the device wishes to use.  This information cannot be
+//! determined by examining the USB configuration descriptor and is
+//! provided to USBDCDConfig by the application to allow the USB controller
+//! endpoints to be correctly configured.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! An array containing one FIFO entry for each of the IN endpoints.
+    //! Note that endpoint 0 is configured and managed by the USB device stack
+    //! so is excluded from this array.  The index 0 entry of the array
+    //! corresponds to endpoint 1, index 1 to endpoint 2, etc.
+    //
+    tFIFOEntry sIn[USBLIB_NUM_EP - 1];
+
+    //
+    //! An array containing one FIFO entry for each of the OUT endpoints.
+    //! Note that endpoint 0 is configured and managed by the USB device stack
+    //! so is excluded from this array.  The index 0 entry of the array
+    //! corresponds to endpoint 1, index 1 to endpoint 2, etc.
+    //
+    tFIFOEntry sOut[USBLIB_NUM_EP - 1];
+}
+tFIFOConfig;
+
+//*****************************************************************************
+//
+//! This structure defines a contiguous block of data which contains a group
+//! of descriptors that form part of a configuration descriptor for a device.
+//! It is assumed that a config section contains only whole descriptors.  It is
+//! not valid to split a single descriptor across multiple sections.
+//!
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The number of bytes of descriptor data pointed to by pucData.
+    //
+    uint8 ucSize;
+
+    //
+    //! A pointer to a block of data containing an integral number of
+    //! USB descriptors which form part of a larger configuration descriptor.
+    //
+    const uint8 *pucData;
+}
+tConfigSection;
+
+//*****************************************************************************
+//
+//! This is the top level structure defining a USB device configuration
+//! descriptor.  A configuration descriptor contains a collection of device-
+//! specific descriptors in addition to the basic config, interface and
+//! endpoint descriptors.  To allow flexibility in constructing the
+//! configuration, the descriptor is described in terms of a list of data
+//! blocks.  The first block must contain the configuration descriptor itself
+//! and the following blocks are appended to this in order to produce the
+//! full descriptor sent to the host in response to a GetDescriptor request
+//! for the configuration descriptor.
+//!
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The number of sections comprising the full descriptor for this
+    //! configuration.
+    //
+    uint8 ucNumSections;
+
+    //
+    //! A pointer to an array of ucNumSections section pointers which must
+    //! be concatenated to form the configuration descriptor.
+    //
+    const tConfigSection * const *psSections;
+}
+tConfigHeader;
+
+//*****************************************************************************
+//
+//! This structure is passed to the USB library on a call to USBDCDInit and
+//! provides the library with information about the device that the
+//! application is implementing.  It contains functions pointers for the
+//! various USB event handlers and pointers to each of the standard device
+//! descriptors.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! A pointer to a structure containing pointers to event handler functions
+    //! provided by the client to support the operation of this device.
+    //
+    tCustomHandlers sCallbacks;
+
+    //
+    //! A pointer to the device descriptor for this device.
+    //
+    const uint8 *pDeviceDescriptor;
+
+    //
+    //! A pointer to an array of configuration descriptor pointers.  Each entry
+    //! in the array corresponds to one configuration that the device may be set
+    //! to use by the USB host.  The number of entries in the array must
+    //! match the bNumConfigurations value in the device descriptor
+    //! array, pDeviceDescriptor.
+    //
+    const tConfigHeader * const *ppConfigDescriptors;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must be arranged as follows:
+    //!
+    //!   - [0]   - Standard descriptor containing supported language codes.
+    //!   - [1]   - String 1 for the first language listed in descriptor 0.
+    //!   - [2]   - String 2 for the first language listed in descriptor 0.
+    //!   - ...
+    //!   - [n]   - String n for the first language listed in descriptor 0.
+    //!   - [n+1] - String 1 for the second language listed in descriptor 0.
+    //!   - ...
+    //!   - [2n]  - String n for the second language listed in descriptor 0.
+    //!   - [2n+1]- String 1 for the third language listed in descriptor 0.
+    //!   - ...
+    //!   - [3n]  - String n for the third language listed in descriptor 0.
+    //!
+    //! and so on.
+    //
+    const uint8 * const *ppStringDescriptors;
+
+    //
+    //! The total number of descriptors provided in the ppStringDescriptors
+    //! array.
+    //
+    uint32 ulNumStringDescriptors;
+
+    //
+    //! A structure defining how the USB controller FIFO is to be partitioned
+    //! between the various endpoints.  This member can be set to point to
+    //! g_sUSBDefaultFIFOConfig if the default FIFO configuration is acceptable
+    //! This configuration sets each endpoint FIFO to be single buffered and
+    //! sized to hold the maximum packet size for the endpoint.
+    //
+    const tFIFOConfig *psFIFOConfig;
+
+    //
+    //! This value will be passed back to all call back functions so that
+    //! they have access to individual instance data based on the this pointer.
+    //
+    void *pvInstance;
+}
+tDeviceInfo;
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup general_usblib_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// USB descriptor parsing functions found in usbdesc.c
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The USB_DESC_ANY label is used as a wild card in several of the descriptor
+//! parsing APIs to determine whether or not particular search criteria should
+//! be ignored.
+//
+//*****************************************************************************
+#define USB_DESC_ANY 0xFFFFFFFF
+
+extern uint32 USBDescGetNum(tDescriptorHeader *psDesc,
+                                   uint32 ulSize, uint32 ulType);
+extern tDescriptorHeader *USBDescGet(tDescriptorHeader *psDesc,
+                                     uint32 ulSize,
+                                     uint32 ulType,
+                                     uint32 ulIndex);
+extern uint32
+       USBDescGetNumAlternateInterfaces(tConfigDescriptor *psConfig,
+                                        uint8 ucInterfaceNumber);
+extern tInterfaceDescriptor *USBDescGetInterface(tConfigDescriptor *psConfig,
+                                                 uint32 ulIndex,
+                                                 uint32 ulAltCfg);
+extern tEndpointDescriptor *
+       USBDescGetInterfaceEndpoint(tInterfaceDescriptor *psInterface,
+                                   uint32 ulIndex,
+                                   uint32 ulSize);
+
+//*****************************************************************************
+//
+//! The operating mode required by the USB library client.  This type is used
+//! by applications which wish to be able to switch between host and device
+//! modes by calling the USBStackModeSet() API.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! The application wishes to operate as a USB device.
+    //
+    USB_MODE_DEVICE = 0,
+
+    //
+    //! The application wishes to operate as a USB host.
+    //
+    USB_MODE_HOST,
+
+    //
+    //! The application wishes to operate as both a host and device using
+    //! On-The-Go protocols to negotiate.
+    //
+    USB_MODE_OTG,
+
+    //
+    //! A marker indicating that no USB mode has yet been set by the
+    //! application.
+    //
+    USB_MODE_NONE
+} tUSBMode;
+
+//*****************************************************************************
+//
+// A pointer to a USB mode callback function.  This function is called by the
+// USB library to indicate to the application which operating mode it should
+// use, host or device.
+//
+//*****************************************************************************
+typedef void (*tUSBModeCallback)(uint32 ulIndex, tUSBMode eMode);
+
+//*****************************************************************************
+//
+// Mode selection and dual mode interrupt steering functions.
+//
+//*****************************************************************************
+extern void USBStackModeSet(uint32 ulIndex, tUSBMode eUSBMode,
+                            tUSBModeCallback pfnCallback);
+extern void USBDualModeInit(uint32 ulIndex);
+extern void USBDualModeTerm(uint32 ulIndex);
+extern void USBOTGMain(uint32 ulMsTicks);
+extern void USBOTGPollRate(uint32 ulIndex, uint32 ulPollRate);
+extern void USBOTGModeInit(uint32 ulIndex, uint32 ulPollRate,
+                           void *pHostData, uint32 ulHostDataSize);
+extern void USBOTGModeTerm(uint32 ulIndex);
+extern void USB0OTGModeIntHandler(void);
+extern void USB0DualModeIntHandler(void);
+
+//*****************************************************************************
+//
+//! USB callback function.
+//!
+//! \param pvCBData is the callback pointer associated with the instance
+//!  generating the callback.  This is a value provided by the client during
+//! initialization of the instance making the callback.
+//! \param ulEvent is the identifier of the asynchronous event which is being
+//! notified to the client.
+//! \param ulMsgParam is an event-specific parameter.
+//! \param pvMsgData is an event-specific data pointer.
+//!
+//! A function pointer provided to the USB layer by the application
+//! which will be called to notify it of all asynchronous events relating to
+//! data transmission or reception.  This callback is used by device class
+//! drivers and host pipe functions.
+//!
+//! \return Returns an event-dependent value.
+//
+//*****************************************************************************
+typedef uint32 (* tUSBCallback)(void *pvCBData, uint32 ulEvent,
+                                       uint32 ulMsgParam,
+                                       void *pvMsgData);
+
+//*****************************************************************************
+//
+// Base identifiers for groups of USB events.  These are used by both the
+// device class drivers and host layer.
+//
+// USB_CLASS_EVENT_BASE is the lowest identifier that should be used for
+// a class-specific event.  Individual event bases are defined for each
+// of the supported device class drivers.  Events with IDs between
+// USB_EVENT_BASE and USB_CLASS_EVENT_BASE are reserved for stack use.
+//
+//*****************************************************************************
+#define USB_EVENT_BASE          0x0000
+#define USB_CLASS_EVENT_BASE    0x8000
+
+//*****************************************************************************
+//
+// Event base identifiers for the various device classes supported in host
+// and device modes.
+// The first 0x800 values of a range are reserved for the device specific
+// messages and the second 0x800 values of a range are used for the host
+// specific messages for a given class.
+//
+//*****************************************************************************
+#define USBD_CDC_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0)
+#define USBD_HID_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0x1000)
+#define USBD_HID_KEYB_EVENT_BASE (USBD_HID_EVENT_BASE + 0x100)
+#define USBD_BULK_EVENT_BASE     (USB_CLASS_EVENT_BASE + 0x2000)
+#define USBD_MSC_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0x3000)
+#define USBD_AUDIO_EVENT_BASE    (USB_CLASS_EVENT_BASE + 0x4000)
+
+#define USBH_CDC_EVENT_BASE   (USBD_CDC_EVENT_BASE  + 0x800)
+#define USBH_HID_EVENT_BASE   (USBD_HID_EVENT_BASE  + 0x800)
+#define USBH_BULK_EVENT_BASE  (USBD_BULK_EVENT_BASE + 0x800)
+#define USBH_MSC_EVENT_BASE   (USBD_MSC_EVENT_BASE  + 0x800)
+#define USBH_AUDIO_EVENT_BASE (USBD_AUDIO_EVENT_BASE  + 0x800)
+
+//*****************************************************************************
+//
+// General events supported by device classes and host pipes.
+//
+//*****************************************************************************
+
+//
+//! The device is now attached to a USB host and ready to begin sending
+//! and receiving data (used by device classes only).
+//
+#define USB_EVENT_CONNECTED (USB_EVENT_BASE + 0)
+
+//
+//! The device has been disconnected from the USB host (used by device classes
+//! only).
+//!
+//! Note: Due to a hardware erratum in revision A of LM3S3748, this
+//! event is not posted to self-powered USB devices when they are disconnected
+//! from the USB host.
+//
+#define USB_EVENT_DISCONNECTED (USB_EVENT_BASE + 1)
+
+//
+//! Data has been received and is in the buffer provided.
+//
+#define USB_EVENT_RX_AVAILABLE (USB_EVENT_BASE + 2)
+
+//
+//! This event is sent by a lower layer to inquire about the amount of
+//! unprocessed data buffered in the layers above.  It is used in cases
+//! where a low level driver needs to ensure that all preceding data has
+//! been processed prior to performing some action or making some notification.
+//! Clients receiving this event should return the number of bytes of data
+//! that are unprocessed or 0 if no outstanding data remains.
+//
+#define USB_EVENT_DATA_REMAINING (USB_EVENT_BASE + 3)
+
+//
+//! This event is sent by a lower layer supporting DMA to request a buffer in
+//! which the next received packet may be stored.  The \e ulMsgValue parameter
+//! indicates the maximum size of packet that can be received in this channel
+//! and \e pvMsgData points to storage which should be written with the
+//! returned buffer pointer.  The return value from the callback should be the
+//! size of the buffer allocated (which may be less than the maximum size
+//! passed in \e ulMsgValue if the client knows that fewer bytes are expected
+//! to be received) or 0 if no buffer is being returned.
+//
+#define USB_EVENT_REQUEST_BUFFER (USB_EVENT_BASE + 4)
+
+//
+//! Data has been sent and acknowledged.  If this event is received via the
+//! USB buffer callback, the \e ulMsgValue parameter indicates the number of
+//! bytes from the transmit buffer that have been successfully transmitted
+//! and acknowledged.
+//
+#define USB_EVENT_TX_COMPLETE (USB_EVENT_BASE + 5)
+
+//
+//! An error has been reported on the channel or pipe.  The \e ulMsgValue
+//! parameter indicates the source(s) of the error and is the logical OR
+//! combination of "USBERR_" flags defined below.
+//
+#define USB_EVENT_ERROR (USB_EVENT_BASE + 6)
+
+//
+//! The bus has entered suspend state.
+//
+#define USB_EVENT_SUSPEND (USB_EVENT_BASE + 7)
+
+//
+//! The bus has left suspend state.
+//
+#define USB_EVENT_RESUME (USB_EVENT_BASE + 8)
+
+//
+//! A scheduler event has occurred.
+//
+#define USB_EVENT_SCHEDULER     (USB_EVENT_BASE + 9)
+//
+//! A device or host has detected a stall condition.
+//
+#define USB_EVENT_STALL         (USB_EVENT_BASE + 10)
+
+//
+//! The host detected a power fault condition.
+//
+#define USB_EVENT_POWER_FAULT   (USB_EVENT_BASE + 11)
+
+//
+//! The controller has detected a A-Side cable and needs power applied  This is
+//! only generated on OTG parts if automatic power control is disabled.
+//
+#define USB_EVENT_POWER_ENABLE  (USB_EVENT_BASE + 12)
+
+//
+//! The controller needs power removed,  This is only generated on OTG parts
+//! if automatic power control is disabled.
+//
+#define USB_EVENT_POWER_DISABLE (USB_EVENT_BASE + 13)
+
+//
+//! Used with pfnDeviceHandler handler function is classes to indicate changes
+//! in the interface number by a class outside the class being accessed.
+//! Typically this is when composite device class is in use.
+//!
+//! The \e pvInstance value should point to an instance of the device being
+//! accessed.
+//!
+//! The \e ulRequest should be USB_EVENT_COMP_IFACE_CHANGE.
+//!
+//! The \e pvRequestData should point to a two byte array where the first value
+//! is the old interface number and the second is the new interface number.
+//
+#define USB_EVENT_COMP_IFACE_CHANGE (USB_EVENT_BASE + 14)
+
+//
+//! Used with pfnDeviceHandler handler function is classes to indicate changes
+//! in endpoint number by a class outside the class being accessed.
+//! Typically this is when composite device class is in use.
+//!
+//! The \e pvInstance value should point to an instance of the device being
+//! accessed.
+//!
+//! The \e ulRequest should be USB_EVENT_COMP_EP_CHANGE.
+//!
+//! The \e pvRequestData should point to a two byte array where the first value
+//! is the old endpoint number and the second is the new endpoint number.  The
+//! endpoint numbers should be exactly as USB specification defines them and
+//! bit 7 set indicates an IN endpoint and bit 7 clear indicates an OUT
+//! endpoint.
+//
+#define USB_EVENT_COMP_EP_CHANGE    (USB_EVENT_BASE + 15)
+
+//
+//! Used with pfnDeviceHandler handler function is classes to indicate changes
+//! in string index number by a class outside the class being accessed.
+//! Typically this is when composite device class is in use.
+//!
+//! The \e pvInstance value should point to an instance of the device being
+//! accessed.
+//!
+//! The \e ulRequest should be USB_EVENT_COMP_STR_CHANGE.
+//!
+//! The \e pvRequestData should point to a two byte array where the first value
+//! is the old string index and the second is the new string index.
+//
+#define USB_EVENT_COMP_STR_CHANGE    (USB_EVENT_BASE + 16)
+
+//
+//! Used with pfnDeviceHandler handler function is classes to allow the device
+//! class to make final adjustments to the configuration descriptor.
+//! This is only used when a device class is used in a composite device class
+//! is in use.
+//!
+//! The \e pvInstance value should point to an instance of the device being
+//! accessed.
+//!
+//! The \e ulRequest should be USB_EVENT_COMP_CONFIG.
+//!
+//! The \e pvRequestData should point to the beginning of the configuration
+//! descriptor for the device instance.
+//
+#define USB_EVENT_COMP_CONFIG        (USB_EVENT_BASE + 17)
+
+//*****************************************************************************
+//
+// Error sources reported via USB_EVENT_ERROR.
+//
+//*****************************************************************************
+
+//
+//! The host received an invalid PID in a transaction.
+//
+#define USBERR_HOST_IN_PID_ERROR   0x01000000
+
+//
+//! The host did not receive a response from a device.
+//
+#define USBERR_HOST_IN_NOT_COMP    0x00100000
+
+//
+//! The host received a stall on an IN endpoint.
+//
+#define USBERR_HOST_IN_STALL       0x00400000
+
+//
+//! The host detected a CRC or bit-stuffing error (isochronous mode).
+//
+#define USBERR_HOST_IN_DATA_ERROR  0x00080000
+
+//
+//! The host received NAK on an IN endpoint for longer than the specified
+//! timeout period (interrupt, bulk and control modes).
+//
+#define USBERR_HOST_IN_NAK_TO      0x00080000
+
+//
+//! The host failed to communicate with a device via an IN endpoint.
+//
+#define USBERR_HOST_IN_ERROR       0x00040000
+
+//
+//! The host receive FIFO is full.
+//
+#define USBERR_HOST_IN_FIFO_FULL   0x00020000  // RX FIFO full
+//
+//! The host received NAK on an OUT endpoint for longer than the specified
+//! timeout period (bulk, interrupt and control modes).
+//
+#define USBERR_HOST_OUT_NAK_TO     0x00000080
+
+//
+//! The host did not receive a response from a device (isochronous mode).
+//
+#define USBERR_HOST_OUT_NOT_COMP   0x00000080
+
+//
+//! The host received a stall on an OUT endpoint.
+//
+#define USBERR_HOST_OUT_STALL      0x00000020
+
+//
+//! The host failed to communicate with a device via an OUT endpoint.
+//
+#define USBERR_HOST_OUT_ERROR      0x00000004
+
+//
+//! The host received NAK on endpoint 0 for longer than the configured
+//! timeout.
+//
+#define USBERR_HOST_EP0_NAK_TO     0x00000080
+
+//
+//! The host failed to communicate with a device via an endpoint zero.
+//
+#define USBERR_HOST_EP0_ERROR      0x00000010
+
+//
+//! The device detected a CRC error in received data.
+//
+#define USBERR_DEV_RX_DATA_ERROR   0x00080000
+
+//
+//! The device was unable to receive a packet from the host since the receive
+//! FIFO is full.
+//
+#define USBERR_DEV_RX_OVERRUN      0x00040000
+
+//
+//! The device receive FIFO is full.
+//
+#define USBERR_DEV_RX_FIFO_FULL    0x00020000  // RX FIFO full
+
+//*****************************************************************************
+//
+// Close the general_usblib_api Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_buffer_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! A function pointer type which describes either a class driver packet read
+//! or packet write function (both have the same prototype) to the USB
+//! buffer object.
+//
+//*****************************************************************************
+typedef uint32 (* tUSBPacketTransfer)(void *pvHandle,
+                                             uint8 *pcData,
+                                             uint32 ulLength,
+                                             tBoolean bLast);
+
+//*****************************************************************************
+//
+//! A function pointer type which describes either a class driver transmit
+//! or receive packet available function (both have the same prototype) to the
+//! USB buffer object.
+//
+//*****************************************************************************
+typedef uint32 (* tUSBPacketAvailable)(void *pvHandle);
+
+//*****************************************************************************
+//
+//! The number of bytes of workspace that each USB buffer object requires.
+//! This workspace memory is provided to the buffer on USBBufferInit() in
+//! the \e pvWorkspace field of the \e tUSBBuffer structure.
+//
+//*****************************************************************************
+#define USB_BUFFER_WORKSPACE_SIZE 16
+
+//*****************************************************************************
+//
+//! The structure used by the application to initialize a buffer object that
+//! will provide buffered access to either a transmit or receive channel.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! This field sets the mode of the buffer.  If TRUE, the buffer
+    //! operates as a transmit buffer and supports calls to USBBufferWrite
+    //! by the client.  If FALSE, the buffer operates as a receive buffer
+    //! and supports calls to USBBufferRead.
+    //
+    tBoolean bTransmitBuffer;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of all asynchronous events related to the operation
+    //! of the buffer.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    //! A pointer that the buffer will pass back to the client in the
+    //! first parameter of all callbacks related to this instance.
+    //
+    void *pvCBData;
+
+    //
+    //! The function which should be called to transmit a packet of data
+    //! in transmit mode or receive a packet in receive mode.
+    //
+    tUSBPacketTransfer pfnTransfer;
+
+    //
+    //! The function which should be called to determine if the endpoint is
+    //! ready to accept a new packet for transmission in transmit mode or
+    //! to determine the size of the buffer required to read a packet in
+    //! receive mode.
+    //
+    tUSBPacketAvailable pfnAvailable;
+
+    //
+    //! The handle to pass to the low level function pointers
+    //! provided in the pfnTransfer and pfnAvailable members.  For USB device
+    //! use, this is the psDevice parameter required by the relevant device
+    //! class driver APIs.  For USB host use, this is the pipe identifier
+    //! returned by USBHCDPipeAlloc.
+    //
+    void *pvHandle;
+
+    //
+    //! A pointer to memory to be used as the ring buffer for this
+    //! instance.
+    //
+    uint8 *pcBuffer;
+
+    //
+    //! The size, in bytes, of the buffer pointed to by pcBuffer.
+    //
+    uint32 ulBufferSize;
+
+    //
+    //! A pointer to USB_BUFFER_WORKSPACE_SIZE bytes of RAM that the buffer
+    //! object can use for workspace.
+    //
+    void *pvWorkspace;
+}
+tUSBBuffer;
+
+//*****************************************************************************
+//
+//! The structure used for encapsulating all the items associated with a
+//! ring buffer.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The ring buffer size.
+    //
+    uint32 ulSize;
+
+    //
+    //! The ring buffer write index.
+    //
+    volatile uint32 ulWriteIndex;
+
+    //
+    //! The ring buffer read index.
+    //
+    volatile uint32 ulReadIndex;
+
+    //
+    //! The ring buffer.
+    //
+    uint8 *pucBuf;
+}
+tUSBRingBufObject;
+
+//*****************************************************************************
+//
+// USB buffer API function prototypes.
+//
+//*****************************************************************************
+extern const tUSBBuffer *USBBufferInit(const tUSBBuffer *psBuffer);
+extern void USBBufferInfoGet(const tUSBBuffer *psBuffer,
+                             tUSBRingBufObject *psRingBuf);
+extern void *USBBufferCallbackDataSet(tUSBBuffer *psBuffer, void *pvCBData);
+extern uint32 USBBufferWrite(const tUSBBuffer *psBuffer,
+                                    const uint8 *pucData,
+                                    uint32 ulLength);
+extern void USBBufferDataWritten(const tUSBBuffer *psBuffer,
+                                 uint32 ulLength);
+extern void USBBufferDataRemoved(const tUSBBuffer *psBuffer,
+                                 uint32 ulLength);
+extern void USBBufferFlush(const tUSBBuffer *psBuffer);
+extern uint32 USBBufferRead(const tUSBBuffer *psBuffer,
+                                   uint8 *pucData,
+                                   uint32 ulLength);
+extern uint32 USBBufferDataAvailable(const tUSBBuffer *psBuffer);
+extern uint32 USBBufferSpaceAvailable(const tUSBBuffer *psBuffer);
+extern uint32 USBBufferEventCallback(void *pvCBData,
+                                            uint32 ulEvent,
+                                            uint32 ulMsgValue,
+                                            void *pvMsgData);
+extern tBoolean USBRingBufFull(tUSBRingBufObject *ptUSBRingBuf);
+extern tBoolean USBRingBufEmpty(tUSBRingBufObject *ptUSBRingBuf);
+extern void USBRingBufFlush(tUSBRingBufObject *ptUSBRingBuf);
+extern uint32 USBRingBufUsed(tUSBRingBufObject *ptUSBRingBuf);
+extern uint32 USBRingBufFree(tUSBRingBufObject *ptUSBRingBuf);
+extern uint32 USBRingBufContigUsed(tUSBRingBufObject *ptUSBRingBuf);
+extern uint32 USBRingBufContigFree(tUSBRingBufObject *ptUSBRingBuf);
+extern uint32 USBRingBufSize(tUSBRingBufObject *ptUSBRingBuf);
+extern uint8 USBRingBufReadOne(tUSBRingBufObject *ptUSBRingBuf);
+extern void USBRingBufRead(tUSBRingBufObject *ptUSBRingBuf,
+                           uint8 *pucData, uint32 ulLength);
+extern void USBRingBufWriteOne(tUSBRingBufObject *ptUSBRingBuf,
+                               uint8 ucData);
+extern void USBRingBufWrite(tUSBRingBufObject *ptUSBRingBuf,
+                            const uint8 *pucData,
+                            uint32 ulLength);
+extern void USBRingBufAdvanceWrite(tUSBRingBufObject *ptUSBRingBuf,
+                                   uint32 ulNumBytes);
+extern void USBRingBufAdvanceRead(tUSBRingBufObject *ptUSBRingBuf,
+                                  uint32 ulNumBytes);
+extern void USBRingBufInit(tUSBRingBufObject *ptUSBRingBuf,
+                           uint8 *pucBuf, uint32 ulSize);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBLIB_H__
diff --git a/bsp/rm48x50/HALCoGen/misra-c.txt b/bsp/rm48x50/HALCoGen/misra-c.txt
new file mode 100644
index 0000000000000000000000000000000000000000..50fb604ab2bc8872c97914bb62327ccef297cea3
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/misra-c.txt
@@ -0,0 +1,56 @@
+Generic
+-------
+/*SAFETYMCUSW 26 S MR:12.3 <REVIEWED> "Infinite loops needed" */
+/*SAFETYMCUSW 69 S MR:12.2 <REVIEWED> "pragma for interrupts a must" */
+/*SAFETYMCUSW 134 S MR:12.3 <REVIEWED> "Volatile variables in expressions cannot be avoided" */
+/*SAFETYMCUSW 139 S MR:13.7 <REVIEWED> "GUI parameter substitution is a feature" */
+/*SAFETYMCUSW 139 S MR:13.7 <REVIEWED> "LDRA-Space around -> or [] can be ignored" */
+/*SAFETYMCUSW 440 S MR:11.3 <REVIEWED> "Casting for #defines" */
+/*SAFETYMCUSW 5 C MR: <REVIEWED> "Infinite loops needed" */
+/*SAFETYMCUSW 28 D MR: <REVIEWED> "Infinite loops needed" */
+/*SAFETYMCUSW 24 D MR:8.1 <REVIEWED> "ISR’s declaration is there in the vector table" */
+/*SAFETYMCUSW 30 S MR:12.2 <REVIEWED> "++ and -- usage cannot be avoided" */
+(Advisory)
+/*SAFETYMCUSW 189 S MR: <REVIEWED> "Input lines may exceed" */
+/*SAFETYMCUSW 62 D MR:16.7 <REVIEWED> "Pointer parameters to be const" */
+
+Module Specific
+---------------
+/*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */
+/*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
+/*SAFETYMCUSW 96 S MR:6.1 <REVIEWED> "Calculations including int and float cannot be avoided" */
+/*SAFETYMCUSW 488 S MR:10.1 <REVIEWED> "Cannot avoid multiple OR’ing" */
+/*SAFETYMCUSW 493 S MR:21.1 <REVIEWED> "Cannot avoid multiple OR’ing" */
+/*SAFETYMCUSW 45 D MR:21.1 <REVIEWED> "Pointer NULL check needs structural change in the Halcogen" */
+/*SAFETYMCUSW 63 S MR:11.1 <REVIEWED> "LDRA-Definitions for gio.h and system.h already present" */
+/*SAFETYMCUSW 77 D MR:17.6 <REVIEWED> "LDRA-Structure Pass By Value is appropriate" */
+(Advisory)
+/*SAFETYMCUSW 88 S MR:2.1 <REVIEWED> "Assembly in C" */
+/*SAFETYMCUSW 93 S MR:6.1 <REVIEWED> "Calculations including int and float cannot be avoided" */
+
+Startup code
+------------
+/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
+/*SAFETYMCUSW 122 S MR:20.11 <REVIEWED> "Startup code(exit and abort need to be present)" */
+/*SAFETYMCUSW 296 S MR:8.6 <REVIEWED> "Startup code(library functions at block scope)" */
+/*SAFETYMCUSW 298 S MR:  <REVIEWED> "Startup code(handler pointers)" */
+/*SAFETYMCUSW 299 S MR:  <REVIEWED> "Startup code(typedef for handler pointers in library )" */
+/*SAFETYMCUSW 326 S MR:8.2 <REVIEWED> "Startup code(Declaration for main in library)" */
+/*SAFETYMCUSW 60 D MR:8.8 <REVIEWED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
+/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
+/*SAFETYMCUSW 354 S MR:1.4 <REVIEWED> " Startup code(Extern declaration present in the library)" */
+(Advisory)
+/*SAFETYMCUSW 218 S MR:20.2 <REVIEWED> "Functions from library" */
+
+EMAC and MDIO
+-------------
+/*SAFETYMCUSW 95 S MR:11.1 <REVIEWED> "EMAC & MDIO-Casting operation to a pointer" */
+/*SAFETYMCUSW 340 S MR:19.7 <REVIEWED> "EMAC & MDIO-Function like Macro" */
+/*SAFETYMCUSW 384 S MR:5.1 <REVIEWED> "EMAC & MDIO-Size of Macro" */
+/*SAFETYMCUSW 446 S MR:10.1 <REVIEWED> "EMAC & MDIO-Narrower int conversion without cast" */
+/*SAFETYMCUSW 436 S MR:17.1 <REVIEWED> "EMAC & MDIO-Array declaration issue" */
+/*SAFETYMCUSW 7 C MR:14.7 <REVIEWED> "EMAC & MDIO-More than one exit" */
+(Advisory)
+/*SAFETYMCUSW 185 S MR: <REVIEWED> "EMAC & MDIO-space >< unary operators" */
+/*SAFETYMCUSW 25 D MR:8.7 <REVIEWED> "EMAC & MDIO-scope of the variable to be reduced" */
+
diff --git a/bsp/rm48x50/HALCoGen/source/dabort.asm b/bsp/rm48x50/HALCoGen/source/dabort.asm
new file mode 100644
index 0000000000000000000000000000000000000000..dcc88229e41b2f2a3bb48ea23a524c39fb3688b4
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/dabort.asm
@@ -0,0 +1,98 @@
+;-------------------------------------------------------------------------------
+; dabort.asm
+;
+; (c) Texas Instruments 2009-2013, All rights reserved.
+;
+
+    .text
+    .arm
+
+
+;-------------------------------------------------------------------------------
+; Run Memory Test
+
+    .ref	custom_dabort
+    .def	_dabort
+    .asmfunc
+
+_dabort
+		stmfd	r13!, {r0 - r12, lr}; push registers and link register on to stack
+
+        ldr		r12, esmsr3			; ESM Group3 status register
+        ldr		r0,  [r12]
+        tst		r0,  #0x8			; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
+        bne		ramErrorFound
+        tst		r0, #0x20			; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
+        bne		ramErrorFound
+
+noRAMerror
+		tst		r0, #0x80			; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
+		bne		flashErrorFound
+
+		bl		custom_dabort		; custom data abort handler required
+									; If this custom handler is written in assembly, all registers used in the routine
+									; and the link register must be saved on to the stack upon entry, and restored before
+									; return from the routine.
+
+		ldmfd	r13!, {r0 - r12, lr}; pop registers and link register from stack
+		subs	pc, lr, #8			; restore state of CPU when abort occurred, and branch back to instruction that was aborted
+
+ramErrorFound
+		ldr		r1, ramctrl			; RAM control register for B0TCM TCRAMW
+		ldr		r2, [r1]
+		tst		r2, #0x100			; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
+		beq		ramErrorReal
+		mov		r2, #0x20
+		str		r2, [r1, #0x10]		; clear RAM error status register
+		ldr		r1, ram2ctrl
+		str		r2, [r1, #0x10]		; clear RAM error status register
+
+		mov		r2, #0x28
+		str		r2, [r12]			; clear ESM group3 flags for uncorrectable RAM ECC errors
+		mov		r2, #5
+		str		r2, [r12, #0x18]	; The nERROR pin will become inactive once the LTC counter expires
+
+		ldmfd	r13!, {r0 - r12, lr}
+		subs	pc, lr, #4			; branch to instruction after the one that caused the abort
+									; this is the case because the data abort was caused intentionally
+									; and we do not want to cause the same data abort again.
+
+ramErrorReal
+		b		ramErrorReal		; branch here forever as continuing operation is not recommended
+
+flashErrorFound
+		ldr		r1, flashbase
+		ldr		r2, [r1, #0x6C]		; read FDIAGCTRL register
+
+		mov     r2, r2, lsr #16
+		tst		r2, #5				; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
+		beq		flashErrorReal
+		mov		r2, #1
+		mov     r2, r2, lsl #8		
+		
+		str		r2, [r1, #0x1C]		; clear FEDACSTATUS error flag
+
+		mov		r2, #0x80
+		str		r2, [r12]			; clear ESM group3 flag for uncorrectable flash ECC error
+		mov		r2, #5
+		str		r2, [r12, #0x18]	; The nERROR pin will become inactive once the LTC counter expires
+
+		ldmfd	r13!, {r0 - r12, lr}
+		subs	pc, lr, #4			; branch to instruction after the one that caused the abort
+									; this is the case because the data abort was caused intentionally
+									; and we do not want to cause the same data abort again.
+
+
+flashErrorReal
+		b		flashErrorReal		; branch here forever as continuing operation is not recommended
+		
+esmsr3		.word	0xFFFFF520
+ramctrl		.word	0xFFFFF800
+ram2ctrl	.word	0xFFFFF900
+ram1errstat	.word	0xFFFFF810
+ram2errstat	.word	0xFFFFF910
+flashbase	.word	0xFFF87000
+
+    .endasmfunc
+	
+	
diff --git a/bsp/rm48x50/HALCoGen/source/esm.c b/bsp/rm48x50/HALCoGen/source/esm.c
new file mode 100644
index 0000000000000000000000000000000000000000..a56e32950d0502bdfaa49cbe8d2bffbcd5072cec
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/esm.c
@@ -0,0 +1,713 @@
+/** @file esm.c 
+*   @brief Esm Driver Source File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*   This file contains:
+*   - API Functions
+*   .
+*   which are relevant for the Esm driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "esm.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void esmInit(void)
+*   @brief Initializes Esm Driver
+*
+*   This function initializes the Esm driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+void esmInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /** - Disable error pin channels */
+    esmREG->EPENACLR1 = 0xFFFFFFFFU;
+    esmREG->EPENACLR4 = 0xFFFFFFFFU;
+
+    /** - Disable interrupts */
+    esmREG->INTENACLR1 = 0xFFFFFFFFU;
+    esmREG->INTENACLR4 = 0xFFFFFFFFU;
+
+    /** - Clear error status flags */
+    esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
+    esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
+    esmREG->ESTATUS2EMU  = 0xFFFFFFFFU;
+    esmREG->ESTATUS1[2U] = 0xFFFFFFFFU;
+    esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
+    esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
+    esmREG->ESTATUS5EMU  = 0xFFFFFFFFU;
+    esmREG->ESTATUS4[2U] = 0xFFFFFFFFU;
+
+    /** - Setup LPC preload */
+    esmREG->LTCPRELOAD = 16384U - 1U;
+
+    /** - Reset error pin */
+    if (esmREG->EPSTATUS == 0U)
+    {
+        esmREG->KEY = 0x00000005U;
+    }
+    else
+    {
+        esmREG->KEY = 0x00000000U;
+    }
+
+    /** - Clear interrupt level */
+    esmREG->INTLVLCLR1 = 0xFFFFFFFFU;
+    esmREG->INTLVLCLR4 = 0xFFFFFFFFU;
+
+    /** - Set interrupt level */
+    esmREG->INTLVLSET1 = (0U << 31U)
+                       | (0U << 30U)
+                       | (0U << 29U)
+                       | (0U << 28U)
+                       | (0U << 27U)
+                       | (0U << 26U)
+                       | (0U << 25U)
+                       | (0U << 24U)
+                       | (0U << 23U)
+                       | (0U << 22U)
+                       | (0U << 21U)
+                       | (0U << 20U)
+                       | (0U << 19U)
+                       | (0U << 18U)
+                       | (0U << 17U)
+                       | (0U << 16U)
+                       | (0U << 15U)
+                       | (0U << 14U)
+                       | (0U << 13U)
+                       | (0U << 12U)
+                       | (0U << 11U)
+                       | (0U << 10U)
+                       | (0U <<  9U)
+                       | (0U <<  8U)
+                       | (0U <<  7U)
+                       | (0U <<  6U)
+                       | (0U <<  5U)
+                       | (0U <<  4U)
+                       | (0U <<  3U)
+                       | (0U <<  2U)
+                       | (0U <<  1U)
+                       | (0U);
+
+    esmREG->INTLVLSET4 = (0U << 31U)
+                       | (0U << 30U)
+                       | (0U << 29U)
+                       | (0U << 28U)
+                       | (0U << 27U)
+                       | (0U << 26U)
+                       | (0U << 25U)
+                       | (0U << 24U)
+                       | (0U << 23U)
+                       | (0U << 22U)
+                       | (0U << 21U)
+                       | (0U << 20U)
+                       | (0U << 19U)
+                       | (0U << 18U)
+                       | (0U << 17U)
+                       | (0U << 16U)
+                       | (0U << 15U)
+                       | (0U << 14U)
+                       | (0U << 13U)
+                       | (0U << 12U)
+                       | (0U << 11U)
+                       | (0U << 10U)
+                       | (0U <<  9U)
+                       | (0U <<  8U)
+                       | (0U <<  7U)
+                       | (0U <<  6U)
+                       | (0U <<  5U)
+                       | (0U <<  4U)
+                       | (0U <<  3U)
+                       | (0U <<  2U)
+                       | (0U <<  1U)
+                       | (0U);
+
+    /** - Enable error pin channels */
+    esmREG->EPENASET1 = (0U << 31U)
+                      | (0U << 30U)
+                      | (0U << 29U)
+                      | (0U << 28U)
+                      | (0U << 27U)
+                      | (0U << 26U)
+                      | (0U << 25U)
+                      | (0U << 24U)
+                      | (0U << 23U)
+                      | (0U << 22U)
+                      | (0U << 21U)
+                      | (0U << 20U)
+                      | (0U << 19U)
+                      | (0U << 18U)
+                      | (0U << 17U)
+                      | (0U << 16U)
+                      | (0U << 15U)
+                      | (0U << 14U)
+                      | (0U << 13U)
+                      | (0U << 12U)
+                      | (0U << 11U)
+                      | (0U << 10U)
+                      | (0U <<  9U)
+                      | (0U <<  8U)
+                      | (0U <<  7U)
+                      | (0U <<  6U)
+                      | (0U <<  5U)
+                      | (0U <<  4U)
+                      | (0U <<  3U)
+                      | (0U <<  2U)
+                      | (0U <<  1U)
+                      | (0U);
+
+    esmREG->EPENASET4 = (0U << 31U)
+                      | (0U << 30U)
+                      | (0U << 29U)
+                      | (0U << 28U)
+                      | (0U << 27U)
+                      | (0U << 26U)
+                      | (0U << 25U)
+                      | (0U << 24U)
+                      | (0U << 23U)
+                      | (0U << 22U)
+                      | (0U << 21U)
+                      | (0U << 20U)
+                      | (0U << 19U)
+                      | (0U << 18U)
+                      | (0U << 17U)
+                      | (0U << 16U)
+                      | (0U << 15U)
+                      | (0U << 14U)
+                      | (0U << 13U)
+                      | (0U << 12U)
+                      | (0U << 11U)
+                      | (0U << 10U)
+                      | (0U <<  9U)
+                      | (0U <<  8U)
+                      | (0U <<  7U)
+                      | (0U <<  6U)
+                      | (0U <<  5U)
+                      | (0U <<  4U)
+                      | (0U <<  3U)
+                      | (0U <<  2U)
+                      | (0U <<  1U)
+                      | (0U);
+
+    /** - Enable interrupts */
+    esmREG->INTENASET1 = (0U << 31U)
+                       | (0U << 30U)
+                       | (0U << 29U)
+                       | (0U << 28U)
+                       | (0U << 27U)
+                       | (0U << 26U)
+                       | (0U << 25U)
+                       | (0U << 24U)
+                       | (0U << 23U)
+                       | (0U << 22U)
+                       | (0U << 21U)
+                       | (0U << 20U)
+                       | (0U << 19U)
+                       | (0U << 18U)
+                       | (0U << 17U)
+                       | (0U << 16U)
+                       | (0U << 15U)
+                       | (0U << 14U)
+                       | (0U << 13U)
+                       | (0U << 12U)
+                       | (0U << 11U)
+                       | (0U << 10U)
+                       | (0U <<  9U)
+                       | (0U <<  8U)
+                       | (0U <<  7U)
+                       | (0U <<  6U)
+                       | (0U <<  5U)
+                       | (0U <<  4U)
+                       | (0U <<  3U)
+                       | (0U <<  2U)
+                       | (0U <<  1U)
+                       | (0U);
+
+    esmREG->INTENASET4 = (0U << 31U)
+                       | (0U << 30U)
+                       | (0U << 29U)
+                       | (0U << 28U)
+                       | (0U << 27U)
+                       | (0U << 26U)
+                       | (0U << 25U)
+                       | (0U << 24U)
+                       | (0U << 23U)
+                       | (0U << 22U)
+                       | (0U << 21U)
+                       | (0U << 20U)
+                       | (0U << 19U)
+                       | (0U << 18U)
+                       | (0U << 17U)
+                       | (0U << 16U)
+                       | (0U << 15U)
+                       | (0U << 14U)
+                       | (0U << 13U)
+                       | (0U << 12U)
+                       | (0U << 11U)
+                       | (0U << 10U)
+                       | (0U <<  9U)
+                       | (0U <<  8U)
+                       | (0U <<  7U)
+                       | (0U <<  6U)
+                       | (0U <<  5U)
+                       | (0U <<  4U)
+                       | (0U <<  3U)
+                       | (0U <<  2U)
+                       | (0U <<  1U)
+                       | (0U);
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32 esmError(void)
+*   @brief Return Error status
+*
+*   @return The error status
+*
+*   Returns the error status.
+*/
+uint32 esmError(void)
+{
+    uint32 status;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+    status = esmREG->EPSTATUS;
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    return status;
+}
+
+
+/** @fn void esmEnableError(uint64 channels)
+*   @brief Enable Group 1 Channels Error Signals propagation
+*
+*   @param[in] channels - Channel mask
+*
+*   Enable Group 1 Channels Error Signals propagation to the error pin.
+*/
+void esmEnableError(uint64 channels)
+{
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    esmREG->EPENASET4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->EPENASET1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmDisableError(uint64 channels)
+*   @brief Disable Group 1 Channels Error Signals propagation
+*
+*   @param[in] channels - Channel mask
+*
+*   Disable Group 1 Channels Error Signals propagation to the error pin.
+*/
+void esmDisableError(uint64 channels)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    esmREG->EPENACLR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->EPENACLR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmTriggerErrorPinReset(void)
+*   @brief Trigger error pin reset and switch back to normal operation
+*
+*   Trigger error pin reset and switch back to normal operation.
+*/
+void esmTriggerErrorPinReset(void)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    esmREG->KEY = 5U;
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmActivateNormalOperation(void)
+*   @brief Activate normal operation
+*
+*   Activates normal operation mode.
+*/
+void esmActivateNormalOperation(void)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    esmREG->KEY = 0U;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmEnableInterrupt(uint64 channels)
+*   @brief Enable Group 1 Channels Interrupts
+*
+*   @param[in] channels - Channel mask
+*
+*   Enable Group 1 Channels Interrupts.
+*/
+void esmEnableInterrupt(uint64 channels)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+    esmREG->INTENASET4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->INTENASET1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmDisableInterrupt(uint64 channels)
+*   @brief Disable Group 1 Channels Interrupts
+*
+*   @param[in] channels - Channel mask
+*
+*   Disable Group 1 Channels Interrupts.
+*/
+void esmDisableInterrupt(uint64 channels)
+{
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+    esmREG->INTENACLR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->INTENACLR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags)
+*   @brief Set Group 1 Channels Interrupt Levels
+*
+*   @param[in] channels - Channel mask
+*   @param[in] flags - Level mask: - 0: Low priority interrupt
+*                                  - 1: High priority interrupt
+*
+*   Set Group 1 Channels Interrupts levels.
+*/
+void esmSetInterruptLevel(uint64 channels, uint64 flags)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+    esmREG->INTLVLCLR4 = (uint32)(((channels & (~flags)) >> 32U) & 0xFFFFFFFU);
+    esmREG->INTLVLSET4 = (uint32)(((channels & flags) >> 32U) & 0xFFFFFFFFU);
+    esmREG->INTLVLCLR1 = (uint32)((channels & (~flags)) & 0xFFFFFFFU);
+    esmREG->INTLVLSET1 = (uint32)((channels & flags) & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmClearStatus(uint32 group, uint64 channels)
+*   @brief Clear Group error status
+*
+*   @param[in] group    - Error group
+*   @param[in] channels - Channel mask
+*
+*   Clear Group error status.
+*/
+void esmClearStatus(uint32 group, uint64 channels)
+{
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+    esmREG->ESTATUS4[group] = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->ESTATUS1[group] = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmClearStatusBuffer(uint64 channels)
+*   @brief Clear Group 2 error status buffer
+*
+*   @param[in] channels - Channel mask
+*
+*   Clear Group 2 error status buffer.
+*/
+void esmClearStatusBuffer(uint64 channels)
+{
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    esmREG->ESTATUS5EMU = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->ESTATUS2EMU = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmSetCounterPreloadValue(uint32 value)
+*   @brief Set counter preload value
+*
+*   @param[in] value - Counter preload value
+*
+*   Set counter preload value.
+*/
+void esmSetCounterPreloadValue(uint32 value)
+{
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+    esmREG->LTCPRELOAD = value & 0xC000U;
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+
+/** @fn uint64 esmGetStatus(uint32 group, uint64 channels)
+*   @brief Return Error status
+*
+*   @param[in] group   - Error group
+*   @param[in] channels - Error Channels
+*
+*   @return The channels status of selected group
+*
+*   Returns the channels status of selected group.
+*/
+uint64 esmGetStatus(uint32 group, uint64 channels)
+{
+    uint64 status;
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+    /*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */
+    status = (((uint64)esmREG->ESTATUS4[group] << 32U) | (uint64)esmREG->ESTATUS1[group]) & channels;
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+    return status;
+}
+
+
+/** @fn uint64 esmGetStatusBuffer(uint64 channels)
+*   @brief Return Group 2 channel x Error status buffer
+*
+*   @param[in] channels - Error Channels
+*
+*   @return The channels status
+*
+*   Returns the group 2 buffered status of selected channels.
+*/
+uint64 esmGetStatusBuffer(uint64 channels)
+{
+    uint64 status;
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+    /*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */
+    status = (((uint64)esmREG->ESTATUS5EMU << 32U) | (uint64)esmREG->ESTATUS2EMU) & channels;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+    return status;
+}
+
+/** @fn esmSelfTestFlag_t esmEnterSelfTest(void)
+*   @brief Return ESM Self test status
+*
+*   @return ESM Self test status
+*
+*   Returns the ESM Self test status.
+*/
+esmSelfTestFlag_t esmEnterSelfTest(void)
+{
+    esmSelfTestFlag_t status;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+	if(((esmREG->EPSTATUS & 0x1U) == 0x0U) && (esmREG->KEY == 0x0U))
+	{
+	  status = esmSelfTest_NotStarted;
+	}
+	else
+	{
+	  esmREG->KEY = 0xAU;
+	  status = esmSelfTest_Active;
+	  if((esmREG->EPSTATUS & 0x1U) != 0x0U)
+	  {
+	    status = esmSelfTest_Failed;
+	  }
+	  esmREG->KEY = 0x5U;
+	}
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+	return status;
+}
+
+/** @fn esmSelfTestFlag_t esmSelfTestStatus(void)
+*   @brief Return ESM Self test status
+*
+*   Returns the ESM Self test status.
+*/
+esmSelfTestFlag_t esmSelfTestStatus(void)
+{
+    esmSelfTestFlag_t status;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+	if((esmREG->EPSTATUS & 0x1U) == 0x0U) 
+	{
+	  if(esmREG->KEY == 0x5U)
+	  { 
+	    status = esmSelfTest_Active;
+	  }
+	  else
+	  {
+	    status = esmSelfTest_Failed;
+	  }
+	}
+	else
+	{
+	    status = esmSelfTest_Passed;
+	}
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+	return status;
+}
+
+/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current 
+*                           value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') 
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_EPENASET1 = ESM_EPENASET1_CONFIGVALUE;
+		config_reg->CONFIG_INTENASET1 = ESM_INTENASET1_CONFIGVALUE;
+		config_reg->CONFIG_INTLVLSET1 = ESM_INTLVLSET1_CONFIGVALUE;
+		config_reg->CONFIG_LTCPRELOAD = ESM_LTCPRELOAD_CONFIGVALUE;
+		config_reg->CONFIG_KEY = ESM_KEY_CONFIGVALUE;  
+		config_reg->CONFIG_EPENASET4 = ESM_EPENASET4_CONFIGVALUE;
+		config_reg->CONFIG_INTENASET4 = ESM_INTENASET4_CONFIGVALUE;
+		config_reg->CONFIG_INTLVLSET4 = ESM_INTLVLSET4_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg->CONFIG_EPENASET1 = esmREG->EPENASET1;
+		config_reg->CONFIG_INTENASET1 = esmREG->INTENASET1;
+		config_reg->CONFIG_INTLVLSET1 = esmREG->INTLVLSET1;
+		config_reg->CONFIG_LTCPRELOAD = esmREG->LTCPRELOAD;
+		config_reg->CONFIG_KEY = esmREG->KEY;  
+		config_reg->CONFIG_EPENASET4 = esmREG->EPENASET4;
+		config_reg->CONFIG_INTENASET4 = esmREG->INTENASET4;
+		config_reg->CONFIG_INTLVLSET4 = esmREG->INTLVLSET4;
+	}
+}
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+/** @fn void esmHighInterrupt(void)
+*   @brief High Level Interrupt for ESM
+*/
+#pragma CODE_STATE(esmHighInterrupt, 32)
+#pragma INTERRUPT(esmHighInterrupt, FIQ)
+
+void esmHighInterrupt(void)
+{
+    sint32 vec = esmREG->INTOFFH - 1U;
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+    if (vec >= 96U)
+    {
+        esmREG->ESTATUS4[1U] = 1U << (vec-96U);
+        esmGroup2Notification(vec-64U);
+    }
+    else if (vec >= 64U)
+    {
+        esmREG->ESTATUS4[0U] = 1U << (vec-64U);
+        esmGroup1Notification(vec-32U);
+    }
+    else if (vec >= 32U)
+    {
+        esmREG->ESTATUS1[1U] = 1U << (vec-32U);
+        esmGroup2Notification(vec-32U);
+    }
+    else if (vec >= 0U)
+    {
+        esmREG->ESTATUS1[0U] = 1U << vec;
+        esmGroup1Notification(vec);
+    }
+    else
+    {
+        esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
+		esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
+        esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
+        esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
+    }
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+}
+
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
diff --git a/bsp/rm48x50/HALCoGen/source/gio.c b/bsp/rm48x50/HALCoGen/source/gio.c
new file mode 100644
index 0000000000000000000000000000000000000000..5465b48397881c1ae45308e8d027b073c2c6e56d
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/gio.c
@@ -0,0 +1,421 @@
+/** @file gio.c 
+*   @brief GIO Driver Implementation File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "gio.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void gioInit(void)
+*   @brief Initializes the GIO Driver
+*
+*   This function initializes the GIO module and set the GIO ports 
+*   to the initial values.
+*/
+/* SourceId : GIO_SourceId_001 */
+/* Requirements : HL_SR115, HL_SR116, HL_SR117, HL_SR118, HL_SR119, HL_SR120, HL_SR121, HL_SR122 */
+void gioInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+    /** bring GIO module out of reset */
+    gioREG->GCR0      = 1U;
+    gioREG->INTENACLR = 0xFFU;
+    gioREG->LVLCLR    = 0xFFU;              
+
+    /** @b initialize @b Port @b A */
+
+    /** - Port A output values */
+    gioPORTA->DOUT =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U); /* Bit 7 */
+
+    /** - Port A direction */
+    gioPORTA->DIR  =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U); /* Bit 7 */
+
+    /** - Port A open drain enable */
+    gioPORTA->PDR  =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U); /* Bit 7 */
+
+    /** - Port A pullup / pulldown selection */
+    gioPORTA->PSL  =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U); /* Bit 7 */
+
+    /** - Port A pullup / pulldown enable*/
+    gioPORTA->PULDIS  =  0U         /* Bit 0 */
+                      | (0U << 1U)  /* Bit 1 */
+                      | (0U << 2U)  /* Bit 2 */
+                      | (0U << 3U)  /* Bit 3 */
+                      | (0U << 4U)  /* Bit 4 */
+                      | (0U << 5U)  /* Bit 5 */
+                      | (0U << 6U)  /* Bit 6 */
+                      | (0U << 7U); /* Bit 7 */
+
+    /** @b initialize @b Port @b B */
+
+    /** - Port B output values */
+    gioPORTB->DOUT =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U); /* Bit 7 */
+
+    /** - Port B direction */
+    gioPORTB->DIR  =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U); /* Bit 7 */
+
+    /** - Port B open drain enable */
+    gioPORTB->PDR  =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U); /* Bit 7 */
+
+    /** - Port B pullup / pulldown selection */
+    gioPORTB->PSL  =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U); /* Bit 7 */
+
+    /** - Port B pullup / pulldown enable*/
+    gioPORTB->PULDIS  =  0U         /* Bit 0 */
+                      | (0U << 1U)  /* Bit 1 */
+                      | (0U << 2U)  /* Bit 2 */
+                      | (0U << 3U)  /* Bit 3 */
+                      | (0U << 4U)  /* Bit 4 */
+                      | (0U << 5U)  /* Bit 5 */
+                      | (0U << 6U)  /* Bit 6 */
+                      | (0U << 7U); /* Bit 7 */
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /** @b initialize @b interrupts */
+
+    /** - interrupt polarity */
+    gioREG->POL =  0U         /* Bit 0 */
+                | (0U << 1U)  /* Bit 1 */
+                | (0U << 2U)  /* Bit 2 */
+                | (0U << 3U)  /* Bit 3 */
+                | (0U << 4U)  /* Bit 4 */
+                | (0U << 5U)  /* Bit 5 */
+                | (0U << 6U)  /* Bit 6 */
+                | (0U << 7U)  /* Bit 7 */
+
+                | (0U << 8U)  /* Bit 8  */
+                | (0U << 9U)  /* Bit 9  */
+                | (0U << 10U) /* Bit 10 */
+                | (0U << 11U) /* Bit 11 */
+                | (0U << 12U) /* Bit 12 */
+                | (0U << 13U) /* Bit 13 */
+                | (0U << 14U) /* Bit 14 */
+                | (0U << 15U);/* Bit 15 */
+
+
+    /** - interrupt level */
+    gioREG->LVLSET =  0U         /* Bit 0 */
+                   | (0U << 1U)  /* Bit 1 */
+                   | (0U << 2U)  /* Bit 2 */
+                   | (0U << 3U)  /* Bit 3 */
+                   | (0U << 4U)  /* Bit 4 */
+                   | (0U << 5U)  /* Bit 5 */
+                   | (0U << 6U)  /* Bit 6 */
+                   | (0U << 7U)  /* Bit 7 */
+
+                   | (0U << 8U)  /* Bit 8  */
+                   | (0U << 9U)  /* Bit 9  */
+                   | (0U << 10U) /* Bit 10 */
+                   | (0U << 11U) /* Bit 11 */
+                   | (0U << 12U) /* Bit 12 */
+                   | (0U << 13U) /* Bit 13 */
+                   | (0U << 14U) /* Bit 14 */
+                   | (0U << 15U);/* Bit 15 */
+
+    
+
+
+    /** - clear all pending interrupts */
+    gioREG->FLG = 0xFFU;
+
+    /** - enable interrupts */
+    gioREG->INTENASET =  0U         /* Bit 0 */
+                      | (0U << 1U)  /* Bit 1 */
+                      | (0U << 2U)  /* Bit 2 */
+                      | (0U << 3U)  /* Bit 3 */
+                      | (0U << 4U)  /* Bit 4 */
+                      | (0U << 5U)  /* Bit 5 */
+                      | (0U << 6U)  /* Bit 6 */
+                      | (0U << 7U)  /* Bit 7 */
+
+                      | (0U << 8U)  /* Bit 8  */
+                      | (0U << 9U)  /* Bit 9  */
+                      | (0U << 10U) /* Bit 10 */
+                      | (0U << 11U) /* Bit 11 */
+                      | (0U << 12U) /* Bit 12 */
+                      | (0U << 13U) /* Bit 13 */
+                      | (0U << 14U) /* Bit 14 */
+                      | (0U << 15U);/* Bit 15 */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+
+/** @fn void gioSetDirection(gioPORT_t *port, uint32 dir)
+*   @brief Set Port Direction
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] dir value to write to DIR register
+*
+*   Set the direction of GIO pins at runtime.
+*/
+/* SourceId : GIO_SourceId_002 */
+/* Requirements : HL_SR123 */
+void gioSetDirection(gioPORT_t *port, uint32 dir)
+{
+    port->DIR = dir;
+}
+
+
+/** @fn void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value)
+*   @brief Write Bit
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit number 0-7 that specifies the bit to be written to.
+*              - 0: LSB
+*              - 7: MSB
+*   @param[in] value binary value to write to bit
+*
+*   Writes a value to the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_003 */
+/* Requirements : HL_SR126 */
+void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value)
+{
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+    if (value != 0U)
+    {
+        port->DSET = 1U << bit;
+    }
+    else
+    {
+        port->DCLR = 1U << bit;
+    }
+}
+
+
+/** @fn void gioSetPort(gioPORT_t *port, uint32 value)
+*   @brief Write Port Value
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] value value to write to port
+*
+*   Writes a value to all pin of a given GIO port
+*/
+/* SourceId : GIO_SourceId_004 */
+/* Requirements : HL_SR127 */
+void gioSetPort(gioPORT_t *port, uint32 value)
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    port->DOUT = value;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+}
+
+
+/** @fn uint32 gioGetBit(gioPORT_t *port, uint32 bit)
+*   @brief Read Bit
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit number 0-7 that specifies the bit to be written to.
+*              - 0: LSB
+*              - 7: MSB
+*
+*   Reads a the current value from the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_005 */
+/* Requirements : HL_SR124 */
+uint32 gioGetBit(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+    return (port->DIN >> bit) & 1U;
+}
+
+
+/** @fn uint32 gioGetPort(gioPORT_t *port)
+*   @brief Read Port Value
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*
+*   Reads a the current value of a given GIO port
+*/
+/* SourceId : GIO_SourceId_006 */
+/* Requirements : HL_SR125 */
+uint32 gioGetPort(gioPORT_t *port)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    return port->DIN;
+}
+
+/** @fn void gioToggleBit(gioPORT_t *port, uint32 bit)
+*   @brief Write Bit
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit number 0-7 that specifies the bit to be written to.
+*              - 0: LSB
+*              - 7: MSB
+*
+*   Toggle a value to the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_007 */
+/* Requirements :  */
+void gioToggleBit(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+    if ((port->DIN & (1U << bit)) != 0U)
+    {
+        port->DCLR = 1U << bit;
+    }
+    else
+    {
+        port->DSET = 1U << bit;
+    }
+}
+
+/** @fn void gioEnableNotification(uint32 bit)
+*   @brief Enable Interrupt
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit interrupt pin to enable
+*              - 0: LSB
+*              - 7: MSB
+*
+*   Enables an interrupt pin of selected port
+*/
+/* SourceId : GIO_SourceId_008 */
+/* Requirements : HL_SR128 */
+void gioEnableNotification(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+	if (port == gioPORTA)
+	{
+		gioREG->INTENASET = 1U << bit;
+	}
+	else if (port == gioPORTB)
+	{
+		gioREG->INTENASET = 1U << (bit + 8);
+	}
+	else
+	{
+		/* Empty */
+	}
+}
+
+
+/** @fn void gioDisableNotification(uint32 bit)
+*   @brief Disable Interrupt
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit interrupt pin to enable
+*              - 0: LSB
+*              - 7: MSB
+*
+*   Disables an interrupt pin of selected port
+*/
+/* SourceId : GIO_SourceId_009 */
+/* Requirements : HL_SR129 */
+void gioDisableNotification(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+	if (port == gioPORTA)
+	{
+		gioREG->INTENACLR = 1U << bit;
+	}
+	else if (port == gioPORTB)
+	{
+		gioREG->INTENACLR = 1U << (bit + 8);
+	}
+	else
+	{
+		/* Empty */
+	}
+}
+
+
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
diff --git a/bsp/rm48x50/HALCoGen/source/notification.c b/bsp/rm48x50/HALCoGen/source/notification.c
new file mode 100644
index 0000000000000000000000000000000000000000..4d1e06c89c8747a07d3fb0d56fe63ff2da5a2c77
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/notification.c
@@ -0,0 +1,125 @@
+/** @file notification.c 
+*   @brief User Notification Definition File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*   This file  defines  empty  notification  routines to avoid
+*   linker errors, Driver expects user to define the notification. 
+*   The user needs to either remove this file and use their custom 
+*   notification function or place their code sequence in this file 
+*   between the provided USER CODE BEGIN and USER CODE END.
+*
+*/
+
+/* Include Files */
+
+#include "esm.h"
+#include "sys_selftest.h"
+#include "gio.h"
+#include "sci.h"
+#include "rti.h"
+#include "sys_dma.h"
+/* USER CODE BEGIN (0) */
+#include <stdint.h>
+/* USER CODE END */
+
+void esmGroup1Notification(uint32 channel)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+void esmGroup2Notification(uint32 channel)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+void rtiNotification(uint32 notification)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (9) */
+sciSendByte(scilinREG, 'I');
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+void gioNotification(gioPORT_t *port, sint32 bit)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+void sciNotification(sciBASE_t *sci, uint32 flags)     
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (29) */
+	if (sci == scilinREG && flags == SCI_RX_INT)
+	{
+	}
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+}
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
diff --git a/bsp/rm48x50/HALCoGen/source/pinmux.c b/bsp/rm48x50/HALCoGen/source/pinmux.c
new file mode 100644
index 0000000000000000000000000000000000000000..d6aa3d876997567447fdee55f6c09ab80568ebe7
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/pinmux.c
@@ -0,0 +1,121 @@
+/** @file pinmux.c 
+*   @brief PINMUX Driver Inmplmentation File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+/* Include Files */
+
+#include "pinmux.h"
+
+#define PINMUX_SET(REG, BALLID, MUX)								\
+				pinMuxReg->PINMMR##REG## = (pinMuxReg->PINMMR##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
+
+#define PINMUX_GATE_EMIF_CLK_ENABLE(state)		\
+			pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)
+
+#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state)	\
+			pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)
+			
+#define PINMUX_ALT_ADC_TRIGGER_SELECT(num)	\
+			pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
+			
+#define PINMUX_ETHERNET_SELECT(interface)	\
+			pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+void muxInit(void){
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+	/* Enable Pin Muxing */
+	kickerReg->KICKER0 = 0x83E70B13U;
+	kickerReg->KICKER1 = 0x95A4F1E0U;
+	
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+	pinMuxReg->PINMMR0 = 	PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2;
+	
+	pinMuxReg->PINMMR1 = 	PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;
+	
+	pinMuxReg->PINMMR2 = 	PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
+	
+	pinMuxReg->PINMMR3 = 	PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;
+	
+	pinMuxReg->PINMMR4 = 	PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
+	
+	pinMuxReg->PINMMR5 = 	PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;
+	
+	pinMuxReg->PINMMR6 = 	PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;
+	
+	pinMuxReg->PINMMR7 =	PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30;
+	
+	pinMuxReg->PINMMR8 = 	PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;
+	
+	pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
+	
+	pinMuxReg->PINMMR10 = 	PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;
+	
+	pinMuxReg->PINMMR11 = 	PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;
+	
+	pinMuxReg->PINMMR12 = 	PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;
+	
+	pinMuxReg->PINMMR13 = 	PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
+	
+	pinMuxReg->PINMMR14 = 	PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
+	
+	pinMuxReg->PINMMR15 = 	PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
+	
+	pinMuxReg->PINMMR16 = 	PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;
+	
+	pinMuxReg->PINMMR17 = 	PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;
+	
+	pinMuxReg->PINMMR18 = 	PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
+	
+	pinMuxReg->PINMMR19 = 	PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;
+	
+	pinMuxReg->PINMMR20 = 	PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11;
+	
+	pinMuxReg->PINMMR21 = 	PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
+	
+	pinMuxReg->PINMMR22 = 	PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;
+	
+	pinMuxReg->PINMMR23 = (~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U |(~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U| PINMUX_BALL_C6_EMIF_ADDR_8;
+	
+	pinMuxReg->PINMMR24 = (~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U | (~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U;
+	
+	pinMuxReg->PINMMR25 = (~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U;
+	
+	pinMuxReg->PINMMR26 = (~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U|PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
+	
+	pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
+	
+	pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
+	
+	pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA;
+	
+	PINMUX_GATE_EMIF_CLK_ENABLE(OFF);
+	PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
+	PINMUX_ALT_ADC_TRIGGER_SELECT(1);
+	PINMUX_ETHERNET_SELECT(RMII);
+	
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+	
+	/* Disable Pin Muxing */
+	kickerReg->KICKER0 = 0x00000000U;
+	kickerReg->KICKER1 = 0x00000000U;
+	
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
diff --git a/bsp/rm48x50/HALCoGen/source/rti.c b/bsp/rm48x50/HALCoGen/source/rti.c
new file mode 100644
index 0000000000000000000000000000000000000000..254a55499cffd85739ee26bbb5779d0d44b1bcc4
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/rti.c
@@ -0,0 +1,794 @@
+/** @file rti.c 
+*   @brief RTI Driver Source File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*   This file contains:
+*   - API Functions
+*   - Interrupt Handlers
+*   .
+*   which are relevant for the RTI driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "rti.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void rtiInit(void)
+*   @brief Initializes RTI Driver
+*
+*   This function initializes the RTI driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+void rtiInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+    /** @b Initialize @b RTI1: */
+
+    /** - Setup NTU source, debug options and disable both counter blocks */
+    rtiREG1->GCTRL = (1U << 16U) | 0x00000000U;
+
+    /** - Setup timebase for free running counter 0 */
+    rtiREG1->TBCTRL = 0x00000000U;
+
+    /** - Enable/Disable capture event sources for both counter blocks */
+    rtiREG1->CAPCTRL = 0U | 0U;
+
+    /** - Setup input source compare 0-3 */
+    rtiREG1->COMPCTRL = 0x00001000U | 0x00000100U | 0x00000000U | 0x00000000U;
+
+    /** - Reset up counter 0 */
+    rtiREG1->CNT[0U].UCx = 0x00000000U;
+
+    /** - Reset free running counter 0 */
+    rtiREG1->CNT[0U].FRCx = 0x00000000U;
+
+    /** - Setup up counter 0 compare value 
+    *     - 0x00000000: Divide by 2^32
+    *     - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1)
+    */
+    rtiREG1->CNT[0U].CPUCx = 9U;
+
+    /** - Reset up counter 1 */
+    rtiREG1->CNT[1U].UCx = 0x00000000U;
+
+    /** - Reset free running counter 1 */
+    rtiREG1->CNT[1U].FRCx  = 0x00000000U;
+
+    /** - Setup up counter 1 compare value 
+    *     - 0x00000000: Divide by 2^32
+    *     - 0x00000001-0xFFFFFFFF: Divide by (CPUC1 + 1)
+    */
+    rtiREG1->CNT[1U].CPUCx = 9U;
+
+    /** - Setup compare 0 value. This value is compared with selected free running counter. */
+    rtiREG1->CMP[0U].COMPx = 10000U;
+
+    /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */
+    rtiREG1->CMP[0U].UDCPx = 10000U;
+
+    /** - Setup compare 1 value. This value is compared with selected free running counter. */
+    rtiREG1->CMP[1U].COMPx = 50000U;
+
+    /** - Setup update compare 1 value. This value is added to the compare 1 value on each compare match. */
+    rtiREG1->CMP[1U].UDCPx = 50000U;
+
+    /** - Setup compare 2 value. This value is compared with selected free running counter. */
+    rtiREG1->CMP[2U].COMPx = 80000U;
+
+    /** - Setup update compare 2 value. This value is added to the compare 2 value on each compare match. */
+    rtiREG1->CMP[2U].UDCPx = 80000U;
+
+    /** - Setup compare 3 value. This value is compared with selected free running counter. */
+    rtiREG1->CMP[3U].COMPx = 100000U;
+
+    /** - Setup update compare 3 value. This value is added to the compare 3 value on each compare match. */
+    rtiREG1->CMP[3U].UDCPx = 100000U;
+
+    /** - Clear all pending interrupts */
+    rtiREG1->INTFLAG = 0x0007000FU;
+
+    /** - Disable all interrupts */
+    rtiREG1->CLEARINT = 0x00070F0FU;
+
+    /**   @note This function has to be called before the driver can be used.\n
+    *           This function has to be executed in privileged mode.\n
+    *           This function does not start the counters.
+    */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+
+/** @fn void rtiStartCounter(uint32 counter)
+*   @brief Starts RTI Counter block
+*   @param[in] counter Select counter block to be started:
+*              - rtiCOUNTER_BLOCK0: RTI counter block 0 will be started
+*              - rtiCOUNTER_BLOCK1: RTI counter block 1 will be started
+*
+*   This function starts selected counter block of the selected RTI module.
+*/
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+void rtiStartCounter(uint32 counter)
+{
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    rtiREG1->GCTRL |= (1U << (counter & 3U));
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.
+    */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+
+/** @fn void rtiStopCounter(uint32 counter)
+*   @brief Stops RTI Counter block
+*   @param[in] counter Select counter to be stopped:
+*              - rtiCOUNTER_BLOCK0: RTI counter block 0 will be stopped
+*              - rtiCOUNTER_BLOCK1: RTI counter block 1 will be stopped
+*
+*   This function stops selected counter block of the selected RTI module.
+*/
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+void rtiStopCounter(uint32 counter)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    rtiREG1->GCTRL &= ~(1U << (counter & 3U));
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.
+    */
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+
+/** @fn uint32 rtiResetCounter(uint32 counter)
+*   @brief Reset RTI Counter block
+*   @param[in] counter Select counter block to be reset:
+*              - rtiCOUNTER_BLOCK0: RTI counter block 0 will be reset
+*              - rtiCOUNTER_BLOCK1: RTI counter block 1 will be reset
+*   @return The function will return:
+*           - 0: When the counter reset wasn't successful   
+*           - 1: When the counter reset was successful   
+*
+*   This function resets selected counter block of the selected RTI module.
+*/
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+uint32 rtiResetCounter(uint32 counter)
+{
+    uint32 success = 0U;
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+    if ((!(rtiREG1->GCTRL & (1U << (counter & 3U)))) != 0U)
+    {
+        rtiREG1->CNT[counter].UCx = 0x00000000U;
+        rtiREG1->CNT[counter].FRCx = 0x00000000U;
+
+        success = 1U;
+    }
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.\n
+    *           The selected counter block has to be stopped before it can reset.
+    */
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+    return success;
+}
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+
+/** @fn void rtiSetPeriod(uint32 compare, uint32 period)
+*   @brief Set new period of RTI compare
+*   @param[in] compare Select compare to change period:
+*              - rtiCOMPARE0: RTI compare 0 will change the period
+*              - rtiCOMPARE1: RTI compare 1 will change the period
+*              - rtiCOMPARE2: RTI compare 2 will change the period
+*              - rtiCOMPARE3: RTI compare 3 will change the period
+*   @param[in] period new period in [ticks - 1]:
+*              - 0x00000000: Divide by 1
+*              - n: Divide by n + 1
+*
+*   This function will change the period of the selected compare.
+*/
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+void rtiSetPeriod(uint32 compare, uint32 period)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+    rtiREG1->CMP[compare].UDCPx = period;
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.\n
+    *           When the corresponding counter block is not stopped,\n
+    *           the period will change on the next compare match of the old period.
+    */
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+
+/** @fn uint32 rtiGetPeriod(uint32 compare)
+*   @brief Get current period of RTI compare
+*   @param[in] compare Select compare to return the current period:
+*              - rtiCOMPARE0: RTI compare 0 will return the current period
+*              - rtiCOMPARE1: RTI compare 1 will return the current period
+*              - rtiCOMPARE2: RTI compare 2 will return the current period
+*              - rtiCOMPARE3: RTI compare 3 will return the current period
+*   @return Current period of selected compare in [ticks - 1]:
+*           - 0x00000000: Divide by 1
+*           - n: Divide by n + 1
+*
+*   This function will return the period of the selected compare.
+*/
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+uint32 rtiGetPeriod(uint32 compare)
+{
+    uint32 period;
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    period = rtiREG1->CMP[compare].UDCPx;
+
+    /**   @note The function rtiInit has to be called before this function can be used.
+    */
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+    return period;
+}
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+
+/** @fn uint32 rtiGetCurrentTick(uint32 compare)
+*   @brief Get current tick of RTI compare
+*   @param[in] compare Select compare to return the current tick:
+*              - rtiCOMPARE0: RTI compare 0 will return the current tick
+*              - rtiCOMPARE1: RTI compare 1 will return the current tick
+*              - rtiCOMPARE2: RTI compare 2 will return the current tick
+*              - rtiCOMPARE3: RTI compare 3 will return the current tick
+*   @return Current tick of selected compare
+*
+*   This function will return the current tick of the selected compare.
+*/
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+uint32 rtiGetCurrentTick(uint32 compare)
+{
+    uint32 tick;
+    uint32 counter = ((rtiREG1->COMPCTRL & (1U << (compare << 2U))) !=0U ) ? 1U : 0U;
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+    tick = rtiREG1->CNT[counter].FRCx - (rtiREG1->CMP[compare].COMPx - rtiREG1->CMP[compare].UDCPx);
+
+    /**   @note The function rtiInit has to be called before this function can be used.
+    */
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+    return tick;
+}
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+/** @fn void dwdInit(uint16 dwdPreload)
+*   @brief Initialize DWD Expiration Period 
+*   @param[in] dwdPreload DWD Preload value for expiration time.
+*              - Texp = (dwdPreload +1) / RTICLK
+*              - n: Divide by n + 1
+*
+*   This function can be called to set the DWD expiration
+*   
+*/
+void dwdInit(uint16 dwdPreload)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+    /* Clear the violations if already present */
+	rtiREG1->WDSTATUS = 0xFFU;
+	
+	rtiREG1->DWDPRLD = dwdPreload;
+	
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+/** @fn void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size)
+*   @brief Initialize DWD Expiration Period 
+*   @param[in] Reaction DWWD reaction if the watchdog is serviced outside the time window.
+*              - Generate_Reset  
+*              - Generate_NMI
+*   @param[in] dwdPreload DWWD Preload value for the watchdog expiration time.
+*              - Texp = (dwdPreload +1) / RTICLK
+*              - n: Divide by n + 1
+*   @param[in] Window_Size DWWD time window size
+*              - Size_100_Percent
+*              - Size_50_Percent
+*              - Size_25_Percent
+*              - Size_12_5_Percent
+*              - Size_6_25_Percent
+*              - Size_3_125_Percent
+*
+*   This function can be called to set the DWD expiration
+*   
+*/
+void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size)
+{
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+    /* Clear the violations if already present */
+	rtiREG1->WDSTATUS = 0xFFU;
+
+    rtiREG1->WWDSIZECTRL = (uint32) Window_Size;
+	rtiREG1->DWDPRLD     = (uint32) dwdPreload;
+	rtiREG1->WWDRXNCTRL  = (uint32) Reaction;
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+/** @fn uint32 dwwdGetCurrentDownCounter(void)
+*   @brief Get the current DWWD Down Counter 
+*   @return Current tick of selected compare
+*
+*   This function will get the current DWWD down counter value.
+*   
+*/
+uint32 dwwdGetCurrentDownCounter(void)
+{
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+    return (rtiREG1->DWDCNTR);
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+/** @fn void dwdCounterEnable(void)
+*   @brief Enable DWD
+*
+*   This function will Enable the DWD counter.
+*   
+*/
+void dwdCounterEnable(void)
+{
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+	rtiREG1->DWDCTRL = 0xA98559DAU;
+	
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+/** @fn void dwdSetPreload(uint16 dwdPreload)
+*   @brief Initialize DWD Expiration Period 
+*   @param[in] dwdPreload DWD Preload value for the watchdog expiration time.
+*              - Texp = (dwdPreload +1) / RTICLK
+*              - n: Divide by n + 1
+*
+*   This function can be called to set the Preload value for the watchdog expiration time.
+*   
+*/
+void dwdSetPreload(uint16 dwdPreload)
+{
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+	rtiREG1->DWDPRLD = dwdPreload;
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+/** @fn void dwdReset(void)
+*   @brief Reset Digital Watchdog 
+*
+*   This function can be called to reset Digital Watchdog.
+*   
+*/
+void dwdReset(void)
+{
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+	rtiREG1->WDKEY = 0x0000E51AU;
+	rtiREG1->WDKEY = 0x0000A35CU;
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+}
+
+/** @fn void dwdGenerateSysReset(void)
+*   @brief Generate System Reset through DWD
+*
+*   This function can be called to generate system reset using DWD.
+*   
+*/
+void dwdGenerateSysReset(void)
+{
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+	rtiREG1->WDKEY = 0x0000E51AU;
+	rtiREG1->WDKEY = 0x00002345U;
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+
+/** @fn boolean IsdwdKeySequenceCorrect(void)
+*   @brief Check if DWD Key sequence correct.
+*   @return The function will return:
+*           - TRUE: When the DWD key sequence is written correctly.
+*           - FALSE: When the DWD key sequence is written incorrectly / not written.
+*
+*   This function will get status of the DWD Key sequence.
+*   
+*/
+boolean IsdwdKeySequenceCorrect(void)
+{
+	boolean Status;
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+	if((rtiREG1->WDSTATUS & 0x4U) == 0x4U)
+	{
+		Status = FALSE;
+	}
+	else
+	{
+		Status = TRUE;
+	}
+
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+
+	return Status;
+}
+
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+/** @fn dwdResetStatus_t dwdGetStatus(void)
+*   @brief Check if Reset is generated due to DWD.
+*   @return The function will return:
+*           - Reset_Generated: When the Reset is generated due to DWD.
+*           - No_Reset_Generated: No Reset is generated due to DWD.
+*
+*   This function will get dwd Reset status.
+*   
+*/
+dwdResetStatus_t dwdGetStatus(void)
+{
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+	dwdResetStatus_t Reset_Status;
+	if((rtiREG1->WDSTATUS & 0x2U) == 0x2U)
+	{
+		Reset_Status = Reset_Generated;
+	}
+	else
+	{
+		Reset_Status = No_Reset_Generated;
+	}
+
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+	return Reset_Status;
+}
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+
+/** @fn void dwdClearFlag(void)
+*   @brief Clear the DWD violation flag.
+*
+*   This function will clear dwd status register.
+*   
+*/
+void dwdClearFlag(void)
+{
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+	rtiREG1->WDSTATUS = 0xFFU;
+
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
+
+/** @fn dwdViolation_t dwdGetViolationStatus(void)
+*   @brief Check the status of the DWD or DWWD violation happened.
+*   @return The function will return one of following violations occured:
+*           - NoTime_Violation
+*           - Key_Seq_Violation
+*           - Time_Window_Violation
+*           - EndTime_Window_Violation
+*           - StartTime_Window_Violation
+*
+*   This function will get status of the DWD or DWWD violation status.
+*   
+*/
+dwdViolation_t dwdGetViolationStatus(void)
+{
+/* USER CODE BEGIN (62) */
+/* USER CODE END */
+	dwdViolation_t Violation_Status;
+
+	if ((rtiREG1->WDSTATUS & 0x20U) == 0x20U)
+	{
+		Violation_Status = Time_Window_Violation;
+	}
+	else if ((rtiREG1->WDSTATUS & 0x04U) == 0x04U)
+	{
+		Violation_Status = Key_Seq_Violation;
+	}	
+	else if((rtiREG1->WDSTATUS & 0x8U) == 0x8U)
+	{
+		Violation_Status = StartTime_Window_Violation;
+	}
+	else if ((rtiREG1->WDSTATUS & 0x10U) == 0x10U)
+	{
+		Violation_Status = EndTime_Window_Violation;
+	}
+	else
+	{
+		Violation_Status = NoTime_Violation;
+	}
+	
+/* USER CODE BEGIN (63) */
+/* USER CODE END */
+
+	return Violation_Status;
+}
+
+/* USER CODE BEGIN (64) */
+/* USER CODE END */
+
+/** @fn void rtiEnableNotification(uint32 notification)
+*   @brief Enable notification of RTI module
+*   @param[in] notification Select notification of RTI module:
+*              - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification
+*              - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification
+*              - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification
+*              - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification
+*              - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification
+*              - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification
+*              - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification
+*
+*   This function will enable the selected notification of a RTI module.
+*   It is possible to enable multiple notifications masked.
+*/
+
+/* USER CODE BEGIN (65) */
+/* USER CODE END */
+
+void rtiEnableNotification(uint32 notification)
+{
+/* USER CODE BEGIN (66) */
+/* USER CODE END */
+
+    rtiREG1->INTFLAG = notification;
+    rtiREG1->SETINT   = notification;
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.
+    */
+
+/* USER CODE BEGIN (67) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (68) */
+/* USER CODE END */
+
+/** @fn void rtiDisableNotification(uint32 notification)
+*   @brief Disable notification of RTI module
+*   @param[in] notification Select notification of RTI module:
+*              - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification
+*              - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification
+*              - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification
+*              - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification
+*              - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification
+*              - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification
+*              - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification
+*
+*   This function will disable the selected notification of a RTI module.
+*   It is possible to disable multiple notifications masked.
+*/
+
+/* USER CODE BEGIN (69) */
+/* USER CODE END */
+
+void rtiDisableNotification(uint32 notification)
+{
+/* USER CODE BEGIN (70) */
+/* USER CODE END */
+
+    rtiREG1->CLEARINT = notification;
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.
+    */
+
+/* USER CODE BEGIN (71) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (72) */
+/* USER CODE END */
+
+/** @fn void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_GCTRL = RTI_GCTRL_CONFIGVALUE;
+		config_reg->CONFIG_TBCTRL = RTI_TBCTRL_CONFIGVALUE;
+		config_reg->CONFIG_CAPCTRL = RTI_CAPCTRL_CONFIGVALUE;
+		config_reg->CONFIG_COMPCTRL = RTI_COMPCTRL_CONFIGVALUE;
+		config_reg->CONFIG_UDCP0 = RTI_UDCP0_CONFIGVALUE;
+		config_reg->CONFIG_UDCP1 = RTI_UDCP1_CONFIGVALUE;
+		config_reg->CONFIG_UDCP2 = RTI_UDCP2_CONFIGVALUE;
+		config_reg->CONFIG_UDCP3 = RTI_UDCP3_CONFIGVALUE;
+		config_reg->CONFIG_TBLCOMP = RTI_TBLCOMP_CONFIGVALUE;
+		config_reg->CONFIG_TBHCOMP = RTI_TBHCOMP_CONFIGVALUE;
+		config_reg->CONFIG_SETINT = RTI_SETINT_CONFIGVALUE;
+		config_reg->CONFIG_DWDCTRL = RTI_DWDCTRL_CONFIGVALUE;
+		config_reg->CONFIG_DWDPRLD = RTI_DWDPRLD_CONFIGVALUE;
+		config_reg->CONFIG_WWDRXNCTRL = RTI_WWDRXNCTRL_CONFIGVALUE;
+		config_reg->CONFIG_WWDSIZECTRL = RTI_WWDSIZECTRL_CONFIGVALUE;
+	}
+	else
+	{	 
+		config_reg->CONFIG_GCTRL = rtiREG1->GCTRL;
+		config_reg->CONFIG_TBCTRL = rtiREG1->TBCTRL;
+		config_reg->CONFIG_CAPCTRL = rtiREG1->CAPCTRL;
+		config_reg->CONFIG_COMPCTRL = rtiREG1->COMPCTRL;
+		config_reg->CONFIG_UDCP0 = rtiREG1->CMP[0U].UDCPx;
+		config_reg->CONFIG_UDCP1 = rtiREG1->CMP[1U].UDCPx;
+		config_reg->CONFIG_UDCP2 = rtiREG1->CMP[2U].UDCPx;
+		config_reg->CONFIG_UDCP3 = rtiREG1->CMP[3U].UDCPx;
+		config_reg->CONFIG_TBLCOMP = rtiREG1->TBLCOMP;
+		config_reg->CONFIG_TBHCOMP = rtiREG1->TBHCOMP;
+		config_reg->CONFIG_SETINT = rtiREG1->SETINT;
+		config_reg->CONFIG_DWDCTRL = rtiREG1->DWDCTRL;
+		config_reg->CONFIG_DWDPRLD = rtiREG1->DWDPRLD;
+		config_reg->CONFIG_WWDRXNCTRL = rtiREG1->WWDRXNCTRL;
+		config_reg->CONFIG_WWDSIZECTRL = rtiREG1->WWDSIZECTRL;
+	}
+}
+
+
+
+
+/* USER CODE BEGIN (82) */
+/* USER CODE END */
+
+/** @fn void rtiCompare3Interrupt(void)
+*   @brief RTI1 Compare 3 Interrupt Handler
+*
+*   RTI1 Compare 3 interrupt handler 
+*
+*/
+
+void rtiCompare3Interrupt(void)
+{
+/* USER CODE BEGIN (83) */
+/* USER CODE END */
+
+    rtiREG1->INTFLAG = 8U;
+    rtiNotification(rtiNOTIFICATION_COMPARE3);
+
+/* USER CODE BEGIN (84) */
+/* USER CODE END */
+}
+
+
+
+
diff --git a/bsp/rm48x50/HALCoGen/source/sci.c b/bsp/rm48x50/HALCoGen/source/sci.c
new file mode 100644
index 0000000000000000000000000000000000000000..67a1bbc1d738f430ba0c992200a8e4f78e55767e
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sci.c
@@ -0,0 +1,549 @@
+/** @file sci.c 
+*   @brief SCI Driver Implementation File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sci.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+/** @struct g_sciTransfer
+*   @brief Interrupt mode globals
+*
+*/
+static struct g_sciTransfer
+{
+    uint32   mode;
+    uint32   length;
+    uint8    * data;
+} g_sciTransfer_t[2U];
+
+
+/** @fn void sciInit(void)
+*   @brief Initializes the SCI Driver
+*
+*   This function initializes the SCI module.
+*/
+void sciInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+    /** @b initialize @b SCILIN */
+
+    /** - bring SCI out of reset */
+    scilinREG->GCR0 = 1U;
+
+    /** - Disable all interrupts */
+    scilinREG->CLRINT    = 0xFFFFFFFFU;
+    scilinREG->CLRINTLVL = 0xFFFFFFFFU;
+
+    /** - global control 1 */
+    scilinREG->GCR1 = (1U << 25U)  /* enable transmit */
+                  | (1U << 24U)  /* enable receive */
+                  | (1U << 5U)   /* internal clock (device has no clock pin) */
+                  | ((1U-1U) << 4U)  /* number of stop bits */
+                  | (0U << 3U)  /* even parity, otherwise odd */
+                  | (0U << 2U)  /* enable parity */
+                  | (1U << 1U);  /* asynchronous timing mode */
+
+    /** - set baudrate */
+    scilinREG->BRS = 53U;  /* baudrate */
+
+    /** - transmission length */
+    scilinREG->FORMAT = 8U - 1U;  /* length */
+
+    /** - set SCI pins functional mode */
+    scilinREG->FUN = (1U << 2U)  /* tx pin */
+                 | (1U << 1U)  /* rx pin */
+                 | (0U);  /* clk pin */
+
+    /** - set SCI pins default output value */
+    scilinREG->DOUT = (0U << 2U)  /* tx pin */
+                  | (0U << 1U)  /* rx pin */
+                  | (0U);  /* clk pin */
+
+    /** - set SCI pins output direction */
+    scilinREG->DIR = (0U << 2U)  /* tx pin */
+                 | (0U << 1U)  /* rx pin */
+                 | (0U);  /* clk pin */
+
+    /** - set SCI pins open drain enable */
+    scilinREG->ODR = (0U << 2U)  /* tx pin */
+                 | (0U << 1U)  /* rx pin */
+                 | (0U);  /* clk pin */
+
+    /** - set SCI pins pullup/pulldown enable */
+    scilinREG->PD = (0U << 2U)  /* tx pin */
+                | (0U << 1U)  /* rx pin */
+                | (0U);  /* clk pin */
+
+    /** - set SCI pins pullup/pulldown select */
+    scilinREG->PSL = (1U << 2U)  /* tx pin */
+                 | (1U << 1U)  /* rx pin */
+                 | (1U);  /* clk pin */
+
+    /** - set interrupt level */
+    scilinREG->SETINTLVL = (0U << 26U)  /* Framing error */
+                       | (0U << 25U)  /* Overrun error */
+                       | (0U << 24U)  /* Parity error */
+                       | (0U << 9U)  /* Receive */
+                       | (0U << 8U)  /* Transmit */
+                       | (0U << 1U)  /* Wakeup */
+                       | (0U);  /* Break detect */
+
+    /** - set interrupt enable */
+    scilinREG->SETINT = (0U << 26U)  /* Framing error */
+                    | (0U << 25U)  /* Overrun error */
+                    | (0U << 24U)  /* Parity error */
+                    | (1U << 9U)  /* Receive */
+                    | (0U << 1U)  /* Wakeup */
+                    | (0U);  /* Break detect */
+
+    /** - initialize global transfer variables */
+    g_sciTransfer_t[1U].mode   = 0U << 8U;
+    g_sciTransfer_t[1U].length = 0U;
+
+    /** - Finaly start SCILIN */
+    scilinREG->GCR1 |= (1U << 7U);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port)
+*   @brief Change functional behavior of pins at runtime.
+*   @param[in] sci   - sci module base address
+*   @param[in] port  - Value to write to FUN register
+*
+*   Change the value of the PCFUN register at runtime, this allows to
+*   dynamically change the functionality of the SCI pins between functional
+*   and GIO mode.
+*/
+void sciSetFunctional(sciBASE_t *sci, uint32 port)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+    sci->FUN = port;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud)
+*   @brief Change baudrate at runtime.
+*   @param[in] sci  - sci module base address
+*   @param[in] baud - baudrate in Hz
+*
+*   Change the SCI baudrate at runtime.
+*/
+void sciSetBaudrate(sciBASE_t *sci, uint32 baud)
+{
+    float64   vclk = 100.000 * 1000000.0;
+    uint32 f    = ((sci->GCR1 & 2U) == 2U) ? 16U : 1U;
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+	/*SAFETYMCUSW 96 S MR:6.1 <REVIEWED> "Calculations including int and float cannot be avoided" */
+    sci->BRS = ((uint32)((vclk /(f*baud) + 0.5)) - 1U) & 0x00FFFFFFU;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32 sciIsTxReady(sciBASE_t *sci)
+*   @brief Check if Tx buffer empty
+*   @param[in] sci - sci module base address
+*
+*   @return The TX ready flag
+*
+*   Checks to see if the Tx buffer ready flag is set, returns
+*   0 is flags not set otherwise will return the Tx flag itself.
+*/
+uint32 sciIsTxReady(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+    return sci->FLR & SCI_TX_INT;
+}
+
+
+/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte)
+*   @brief Send Byte
+*   @param[in] sci  - sci module base address
+*   @param[in] byte - byte to transfer
+*
+*   Sends a single byte in polling mode, will wait in the
+*   routine until the transmit buffer is empty before sending
+*   the byte.  Use sciIsTxReady to check for Tx buffer empty
+*   before calling sciSendByte to avoid waiting.
+*/
+void sciSendByte(sciBASE_t *sci, uint8 byte)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    while ((sci->FLR & SCI_TX_INT) == 0U) 
+    { 
+	} /* Wait */
+    sci->TD = byte;
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data)
+*   @brief Send Data
+*   @param[in] sci    - sci module base address
+*   @param[in] length - number of data words to transfer
+*   @param[in] data   - pointer to data to send
+*
+*   Send a block of data pointed to by 'data' and 'length' bytes
+*   long.  If interrupts have been enabled the data is sent using
+*   interrupt mode, otherwise polling mode is used.  In interrupt
+*   mode transmission of the first byte is started and the routine
+*   returns immediately, sciSend must not be called again until the
+*   transfer is complete, when the sciNotification callback will
+*   be called.  In polling mode, sciSend will not return  until 
+*   the transfer is complete.
+*
+*   @note if data word is less than 8 bits, then the data must be left
+*         aligned in the data byte.
+*/
+void sciSend(sciBASE_t *sci, uint32 length, uint8 * data)
+{
+    uint32 index = sci == sciREG ? 0U : 1U;
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    if ((g_sciTransfer_t[index].mode & SCI_TX_INT) != 0U)
+    {
+        /* we are in interrupt mode */
+        
+        g_sciTransfer_t[index].length = length;
+        g_sciTransfer_t[index].data   = data;
+
+        /* start transmit by sending first byte */        
+        sci->TD     = *g_sciTransfer_t[index].data++ ;
+        sci->SETINT = SCI_TX_INT;
+    }
+    else
+    {
+        /* send the data */
+        while (length-- > 0U)
+        {
+            while ((sci->FLR & SCI_TX_INT) == 0U)
+            { 
+	        } /* Wait */
+            sci->TD = *data++;
+        }
+    }
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32 sciIsRxReady(sciBASE_t *sci)
+*   @brief Check if Rx buffer full
+*   @param[in] sci - sci module base address
+*
+*   @return The Rx ready flag
+*
+*   Checks to see if the Rx buffer full flag is set, returns
+*   0 is flags not set otherwise will return the Rx flag itself.
+*/
+uint32 sciIsRxReady(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    return sci->FLR & SCI_RX_INT;
+}
+
+/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci)
+*   @brief Check if Idle Period is Detected
+*   @param[in] sci - sci module base address
+*
+*   @return The Idle flag
+*
+*   Checks to see if the SCI Idle flag is set, returns 0 is flags 
+*   not set otherwise will return the Ilde flag itself.
+*/
+uint32 sciIsIdleDetected(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+    return sci->FLR & SCI_IDLE;
+}
+
+
+/** @fn uint32 sciRxError(sciBASE_t *sci)
+*   @brief Return Rx Error flags
+*   @param[in] sci - sci module base address
+*
+*   @return The Rx error flags
+*
+*   Returns the Rx framing, overrun and parity errors flags,
+*   also clears the error flags before returning.
+*/
+uint32 sciRxError(sciBASE_t *sci)
+{
+    uint32 status = sci->FLR & (SCI_FE_INT | SCI_OE_INT |SCI_PE_INT);
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+    sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;
+    return status;
+}
+
+
+/** @fn uint32 sciReceiveByte(sciBASE_t *sci)
+*   @brief Receive Byte
+*   @param[in] sci - sci module base address
+*
+*   @return Received byte
+*
+*    Receives a single byte in polling mode.  If there is
+*    not a byte in the receive buffer the routine will wait
+*    until one is received.   Use sciIsRxReady to check to
+*    see if the buffer is full to avoid waiting.
+*/
+uint32 sciReceiveByte(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+    while ((sci->FLR & SCI_RX_INT) == 0U) 
+    { 
+	} /* Wait */
+
+    return (sci->RD & 0x000000FFU);
+}
+
+
+/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data)
+*   @brief Receive Data
+*   @param[in] sci    - sci module base address
+*   @param[in] length - number of data words to transfer
+*   @param[in] data   - pointer to data buffer
+*
+*   Receive a block of 'length' bytes long and place it into the 
+*   data buffer pointed to by 'data'.  If interrupts have been 
+*   enabled the data is received using interrupt mode, otherwise
+*   polling mode is used.  In interrupt mode receive is setup and
+*   the routine returns immediately, sciReceive must not be called 
+*   again until the transfer is complete, when the sciNotification 
+*   callback will be called.  In polling mode, sciReceive will not
+*   return  until the transfer is complete.
+*/
+void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data)
+{
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+    if ((sci->SETINT & SCI_RX_INT) == SCI_RX_INT)
+    {
+        /* we are in interrupt mode */
+        uint32 index = sci == sciREG ? 0U : 1U;
+        
+        /* clear error flags */
+        sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;
+
+        g_sciTransfer_t[index].length = length;
+        g_sciTransfer_t[index].data   = data;
+    }
+    else
+    {   
+        while (length-- > 0U)
+        {
+            while ((sci->FLR & SCI_RX_INT) == 0U) 
+		    { 
+	        } /* Wait */
+            *data++ = (uint8)(sci->RD & 0x000000FFU);
+        }
+    }
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype)
+*   @brief Enable Loopback mode for self test
+*   @param[in] sci        - sci module base address
+*   @param[in] Loopbacktype  - Digital or Analog
+*
+*   This function enables the Loopback mode for self test.
+*/
+void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+    
+	/* Clear Loopback incase enabled already */
+	sci->IODFTCTRL = 0U;
+	
+	/* Enable Loopback either in Analog or Digital Mode */
+    sci->IODFTCTRL = 0x00000A00U
+                   | (Loopbacktype << 1U);
+	
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+/** @fn void sciDisableLoopback(sciBASE_t *sci)
+*   @brief Enable Loopback mode for self test
+*   @param[in] sci        - sci module base address
+*
+*   This function disable the Loopback mode.
+*/
+void sciDisableLoopback(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+    
+	/* Disable Loopback Mode */
+    sci->IODFTCTRL = 0x00000500U;
+	
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+}
+
+/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags)
+*   @brief Enable interrupts
+*   @param[in] sci   - sci module base address
+*   @param[in] flags - Interrupts to be enabled, can be ored value of:
+*                      SCI_FE_INT    - framing error,
+*                      SCI_OE_INT    - overrun error,
+*                      SCI_PE_INT    - parity error,
+*                      SCI_RX_INT    - receive buffer ready,
+*                      SCI_TX_INT    - transmit buffer ready,
+*                      SCI_WAKE_INT  - wakeup,
+*                      SCI_BREAK_INT - break detect
+*/
+void sciEnableNotification(sciBASE_t *sci, uint32 flags)
+{
+    uint32 index = sci == sciREG ? 0U : 1U;
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    g_sciTransfer_t[index].mode |= (flags & SCI_TX_INT);
+    sci->SETINT                = (flags & (~(SCI_TX_INT)));
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+
+/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags)
+*   @brief Disable interrupts
+*   @param[in] sci   - sci module base address
+*   @param[in] flags - Interrupts to be disabled, can be ored value of:
+*                      SCI_FE_INT    - framing error,
+*                      SCI_OE_INT    - overrun error,
+*                      SCI_PE_INT    - parity error,
+*                      SCI_RX_INT    - receive buffer ready,
+*                      SCI_TX_INT    - transmit buffer ready,
+*                      SCI_WAKE_INT  - wakeup,
+*                      SCI_BREAK_INT - break detect
+*/
+void sciDisableNotification(sciBASE_t *sci, uint32 flags)
+{
+    uint32 index = sci == sciREG ? 0U : 1U;
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+    g_sciTransfer_t[index].mode &= ~(flags & SCI_TX_INT);
+    sci->CLRINT                = (flags & (~SCI_TX_INT));
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+/** @fn void linHighLevelInterrupt(void)
+*   @brief Level 0 Interrupt for SCILIN
+*/
+void linHighLevelInterrupt(void)
+{
+    uint32 vec = scilinREG->INTVECT0;
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+    switch (vec)
+    {
+    case 1U:
+        sciNotification(scilinREG, SCI_WAKE_INT);
+        break;
+    case 3U:
+        sciNotification(scilinREG, SCI_PE_INT);
+        break;
+    case 6U:
+        sciNotification(scilinREG, SCI_FE_INT);
+        break;
+    case 7U:
+        sciNotification(scilinREG, SCI_BREAK_INT);
+        break;
+    case 9U:
+        sciNotification(scilinREG, SCI_OE_INT);
+        break;
+
+    case 11U:
+        /* receive */
+        {   uint32 byte = (scilinREG->RD & 0x000000FFU);
+
+            if (g_sciTransfer_t[1U].length > 0U)
+            {
+                *g_sciTransfer_t[1U].data++ = byte;
+                g_sciTransfer_t[1U].length--;
+                if (g_sciTransfer_t[1U].length == 0U)
+                {
+                    sciNotification(scilinREG, SCI_RX_INT);
+                }
+            }
+        }
+        break;
+
+    case 12U:
+        /* transmit */
+        if (--g_sciTransfer_t[1U].length > 0U)
+        {
+            scilinREG->TD = *g_sciTransfer_t[1U].data++;
+        }
+        else
+        {
+            scilinREG->CLRINT = SCI_TX_INT;
+            sciNotification(scilinREG, SCI_TX_INT);
+        }
+        break;
+
+    default:
+        /* phantom interrupt, clear flags and return */
+        scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U;
+        break;
+    }
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+}
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
diff --git a/bsp/rm48x50/HALCoGen/source/sys_core.asm b/bsp/rm48x50/HALCoGen/source/sys_core.asm
new file mode 100644
index 0000000000000000000000000000000000000000..ae2a9ebd930415cefbc86eb2686edac2b0143fb6
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_core.asm
@@ -0,0 +1,660 @@
+;-------------------------------------------------------------------------------
+; sys_core.asm
+;
+; (c) Texas Instruments 2009-2013, All rights reserved.
+;
+
+    .text
+    .arm
+
+;-------------------------------------------------------------------------------
+; Initialize CPU Registers
+
+    .def     _coreInitRegisters_
+    .asmfunc
+    
+
+_coreInitRegisters_
+
+
+    ; After reset, the CPU is in the Supervisor mode (M = 10011)
+        mov r0, lr
+        mov r1, #0x0000
+        mov r2, #0x0000
+        mov r3, #0x0000
+        mov r4, #0x0000
+        mov r5, #0x0000
+        mov r6, #0x0000
+        mov r7, #0x0000
+        mov r8, #0x0000
+        mov r9, #0x0000
+        mov r10, #0x0000
+        mov r11, #0x0000
+        mov r12, #0x0000
+        mov r13, #0x0000
+        mrs r1, cpsr
+        msr spsr_cxsf, r1 
+        ; Switch to FIQ mode (M = 10001)
+        cps #17
+        mov lr, r0
+        mov r8, #0x0000
+        mov r9, #0x0000
+        mov r10, #0x0000
+        mov r11, #0x0000
+        mov r12, #0x0000
+        mrs r1, cpsr
+        msr spsr_cxsf, r1 
+        ; Switch to IRQ mode (M = 10010)
+        cps #18
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1         
+        ; Switch to Abort mode (M = 10111)
+        cps #23
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1         
+        ; Switch to Undefined Instruction Mode (M = 11011)
+        cps #27
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1         
+        ; Switch to System Mode ( Shares User Mode registers ) (M = 11111)
+        cps #31
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1         
+        ; Switch back to Supervisor Mode (M = 10011)
+        cps #19
+
+        ; Turn on FPV coprocessor
+        mrc   p15,     #0x00,      r2,       c1, c0, #0x02
+        orr   r2,      r2,         #0xF00000
+        mcr   p15,     #0x00,      r2,       c1, c0, #0x02
+
+        .if (RT_VFP_LAZY_STACKING) = 0
+        fmrx  r2,      fpexc
+        orr   r2,      r2,   #0x40000000
+        fmxr  fpexc,   r2
+
+        fmdrr d0,         r1,     r1
+        fmdrr d1,         r1,     r1
+        fmdrr d2,         r1,     r1
+        fmdrr d3,         r1,     r1
+        fmdrr d4,         r1,     r1
+        fmdrr d5,         r1,     r1
+        fmdrr d6,         r1,     r1
+        fmdrr d7,         r1,     r1
+        fmdrr d8,         r1,     r1
+        fmdrr d9,         r1,     r1
+        fmdrr d10,        r1,     r1
+        fmdrr d11,        r1,     r1
+        fmdrr d12,        r1,     r1
+        fmdrr d13,        r1,     r1
+        fmdrr d14,        r1,     r1
+        fmdrr d15,        r1,     r1
+        .endif
+        bl    next1
+next1
+        bl    next2
+next2
+        bl    next3
+next3
+        bl    next4
+next4
+        bx    r0
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Initialize Stack Pointers
+
+    .def     _coreInitStackPointer_
+    .asmfunc
+
+_coreInitStackPointer_
+
+        cps   #17
+        ldr   sp,       fiqSp
+        cps   #18
+        ldr   sp,       irqSp
+        cps   #23
+        ldr   sp,       abortSp
+        cps   #27
+        ldr   sp,       undefSp
+        cps   #31
+        ldr   sp,       userSp
+        cps   #19
+        ldr   sp,       svcSp
+        bx    lr
+
+userSp  .word 0x08000000+0x00001000
+svcSp   .word 0x08000000+0x00001000+0x00000100
+fiqSp   .word 0x08000000+0x00001000+0x00000100+0x00000100
+irqSp   .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100
+abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100
+undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Get CPSR Value
+
+    .def     _getCPSRValue_
+    .asmfunc
+
+_getCPSRValue_
+
+        mrs   r0, CPSR
+        bx    lr
+
+    .endasmfunc
+    
+;-------------------------------------------------------------------------------
+; Take CPU to IDLE state
+
+    .def     _gotoCPUIdle_
+    .asmfunc
+
+_gotoCPUIdle_
+
+        WFI
+        nop
+        nop
+        nop
+        nop
+        bx    lr
+        
+    .endasmfunc
+    
+
+;-------------------------------------------------------------------------------
+; Enable VFP Unit
+
+    .def     _coreEnableVfp_
+    .asmfunc
+
+_coreEnableVfp_
+
+        mrc   p15,     #0x00,      r0,       c1, c0, #0x02
+        orr   r0,      r0,         #0xF00000
+        mcr   p15,     #0x00,      r0,       c1, c0, #0x02
+        mov   r0,      #0x40000000
+        fmxr  fpexc,   r0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Enable Event Bus Export
+
+    .def     _coreEnableEventBusExport_
+    .asmfunc
+
+_coreEnableEventBusExport_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c9, c12, #0x00
+        orr   r0,  r0,    #0x10
+        mcr   p15, #0x00, r0,         c9, c12, #0x00
+        ldmfd sp!, {r0}
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable Event Bus Export
+
+    .def     _coreDisableEventBusExport_
+    .asmfunc
+
+_coreDisableEventBusExport_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c9, c12, #0x00
+        bic   r0,  r0,    #0x10
+        mcr   p15, #0x00, r0,         c9, c12, #0x00
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable RAM ECC Support
+
+    .def     _coreEnableRamEcc_
+    .asmfunc
+
+_coreEnableRamEcc_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        orr   r0,  r0,    #0x0C000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable RAM ECC Support
+
+    .def     _coreDisableRamEcc_
+    .asmfunc
+
+_coreDisableRamEcc_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        bic   r0,  r0,    #0x0C000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Flash ECC Support
+
+    .def     _coreEnableFlashEcc_
+    .asmfunc
+
+_coreEnableFlashEcc_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        orr   r0,  r0,    #0x02000000
+        dmb
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable Flash ECC Support
+
+    .def     _coreDisableFlashEcc_
+    .asmfunc
+
+_coreDisableFlashEcc_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        bic   r0,  r0,    #0x02000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Offset via Vic controller
+
+    .def     _coreEnableIrqVicOffset_
+    .asmfunc
+
+_coreEnableIrqVicOffset_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0,         c1, c0,  #0
+        orr   r0,  r0,    #0x01000000
+        mcr   p15, #0, r0,         c1, c0,  #0
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get data fault status register
+
+    .def     _coreGetDataFault_
+    .asmfunc
+
+_coreGetDataFault_
+
+        mrc   p15, #0, r0, c5, c0,  #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear data fault status register
+
+    .def     _coreClearDataFault_
+    .asmfunc
+
+_coreClearDataFault_
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c0,  #0
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get instruction fault status register
+
+    .def     _coreGetInstructionFault_
+    .asmfunc
+
+_coreGetInstructionFault_
+
+        mrc   p15, #0, r0, c5, c0, #1
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear instruction fault status register
+
+    .def     _coreClearInstructionFault_
+    .asmfunc
+
+_coreClearInstructionFault_
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c0, #1
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get data fault address register
+
+    .def     _coreGetDataFaultAddress_
+    .asmfunc
+
+_coreGetDataFaultAddress_
+
+        mrc   p15, #0, r0, c6, c0,  #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear data fault address register
+
+    .def     _coreClearDataFaultAddress_
+    .asmfunc
+
+_coreClearDataFaultAddress_
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c6, c0,  #0
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get instruction fault address register
+
+    .def     _coreGetInstructionFaultAddress_
+    .asmfunc
+
+_coreGetInstructionFaultAddress_
+
+        mrc   p15, #0, r0, c6, c0, #2
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear instruction fault address register
+
+    .def     _coreClearInstructionFaultAddress_
+    .asmfunc
+
+_coreClearInstructionFaultAddress_
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c6, c0, #2
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get auxiliary data fault status register
+
+    .def     _coreGetAuxiliaryDataFault_
+    .asmfunc
+
+_coreGetAuxiliaryDataFault_
+
+        mrc   p15, #0, r0, c5, c1, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear auxiliary data fault status register
+
+    .def     _coreClearAuxiliaryDataFault_
+    .asmfunc
+
+_coreClearAuxiliaryDataFault_
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c1, #0
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get auxiliary instruction fault status register
+
+    .def     _coreGetAuxiliaryInstructionFault_
+    .asmfunc
+
+_coreGetAuxiliaryInstructionFault_
+
+        mrc   p15, #0, r0, c5, c1, #1
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Clear auxiliary instruction fault status register
+
+    .def     _coreClearAuxiliaryInstructionFault_
+    .asmfunc
+
+_coreClearAuxiliaryInstructionFault_
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mrc   p15, #0, r0, c5, c1, #1
+        ldmfd sp!, {r0}        
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Disable interrupts - R4 IRQ & FIQ
+
+        .def _disable_interrupt_
+        .asmfunc
+        
+_disable_interrupt_
+
+        cpsid if
+        bx    lr
+        
+        .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Disable FIQ interrupt
+
+        .def _disable_FIQ_interrupt_
+        .asmfunc
+        
+_disable_FIQ_interrupt_
+
+        cpsid f
+        bx    lr
+        
+        .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Disable FIQ interrupt
+
+        .def _disable_IRQ_interrupt_    
+        .asmfunc
+        
+_disable_IRQ_interrupt_
+
+        cpsid i
+        bx    lr
+        
+        .endasmfunc
+        
+;-------------------------------------------------------------------------------
+; Enable interrupts - R4 IRQ & FIQ
+
+       .def _enable_interrupt_
+       .asmfunc
+
+_enable_interrupt_
+
+        cpsie if
+        bx    lr
+        
+        .endasmfunc
+
+        
+;-------------------------------------------------------------------------------
+; Clear ESM CCM errorss
+
+       .def _esmCcmErrorsClear_
+       .asmfunc
+
+_esmCcmErrorsClear_
+
+        stmfd sp!, {r0-r2}        
+        ldr   r0, ESMSR1_REG    ; load the ESMSR1 status register address
+        ldr   r2, ESMSR1_ERR_CLR
+        str   r2, [r0]         ; clear the ESMSR1 register
+
+        ldr   r0, ESMSR2_REG    ; load the ESMSR2 status register address
+        ldr   r2, ESMSR2_ERR_CLR
+        str   r2, [r0]         ; clear the ESMSR2 register
+
+        ldr   r0, ESMSSR2_REG    ; load the ESMSSR2 status register address
+        ldr   r2, ESMSSR2_ERR_CLR
+        str   r2, [r0]             ; clear the ESMSSR2 register
+
+        ldr   r0, ESMKEY_REG    ; load the ESMKEY register address
+        mov   r2, #0x5             ; load R2 with 0x5
+        str   r2, [r0]             ; clear the ESMKEY register
+
+        ldr   r0, VIM_INTREQ    ; load the INTREQ register address
+        ldr   r2, VIM_INT_CLR
+        str   r2, [r0]         ; clear the INTREQ register
+        ldr   r0, CCMR4_STAT_REG    ; load the CCMR4 status register address
+        ldr   r2, CCMR4_ERR_CLR
+        str   r2, [r0]         ; clear the CCMR4 status register
+        ldmfd sp!, {r0-r2}        
+        bx    lr
+
+ESMSR1_REG        .word 0xFFFFF518
+ESMSR2_REG        .word 0xFFFFF51C
+ESMSR3_REG        .word 0xFFFFF520
+ESMKEY_REG        .word 0xFFFFF538
+ESMSSR2_REG       .word 0xFFFFF53C
+CCMR4_STAT_REG    .word 0xFFFFF600
+ERR_CLR_WRD       .word 0xFFFFFFFF
+CCMR4_ERR_CLR     .word 0x00010000
+ESMSR1_ERR_CLR    .word 0x80000000
+ESMSR2_ERR_CLR    .word 0x00000004
+ESMSSR2_ERR_CLR   .word 0x00000004
+VIM_INT_CLR       .word 0x00000001
+VIM_INTREQ        .word 0xFFFFFE20
+
+        .endasmfunc    
+
+;-------------------------------------------------------------------------------
+; Work Around for Errata CORTEX-R4#57:
+; 
+; Errata Description: 
+;            Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
+; Workaround:
+;            Disable out-of-order single-precision floating point 
+;            multiply-accumulate instruction completion 
+
+        .def     _errata_CORTEXR4_57_
+        .asmfunc
+
+_errata_CORTEXR4_57_
+
+        push {r0}
+        mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register 
+        orr r0, r0, #0x10000         ; Set BIT 16 (Set DOOFMACS) 
+        mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register 
+        pop {r0}
+        bx lr
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Work Around for Errata CORTEX-R4#66:
+; 
+; Errata Description:            
+;            Register Corruption During A Load-Multiple Instruction At 
+;            an Exception Vector
+; Workaround:
+;            Disable out-of-order completion for divide instructions in 
+;            Auxiliary Control register 
+
+        .def     _errata_CORTEXR4_66_
+        .asmfunc
+
+_errata_CORTEXR4_66_
+
+        push {r0}
+        mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register
+          orr r0, r0, #0x80           ; Set BIT 7 (Disable out-of-order completion 
+                                    ; for divide instructions.)
+           mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register
+        pop {r0}    
+        bx lr
+    .endasmfunc
+;-------------------------------------------------------------------------------
+; C++ construct table pointers
+
+    .def    __TI_PINIT_Base, __TI_PINIT_Limit
+    .weak   SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit
+
+__TI_PINIT_Base  .long SHT$$INIT_ARRAY$$Base
+__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
+
+
+    
+;-------------------------------------------------------------------------------
+
diff --git a/bsp/rm48x50/HALCoGen/source/sys_dma.c b/bsp/rm48x50/HALCoGen/source/sys_dma.c
new file mode 100644
index 0000000000000000000000000000000000000000..0756d25050702364e9a452f07b150498d9f0dbd7
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_dma.c
@@ -0,0 +1,322 @@
+/** @file dma.c 
+*   @brief DMA Driver Inmplmentation File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#include "sys_dma.h"
+
+
+/** @fn void dmaEnable(void)
+*   @brief enables DMA module
+*
+*   This function brings DMA out of reset
+*/
+void dmaEnable(void)
+{
+  dmaREG->GCTRL  = 0x00000001U; /* reset dma       */
+  dmaREG->GCTRL |= 0x00010000U; /* enable dma      */
+  dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */   
+}
+
+/** @fn void dmaDisable(void)
+*   @brief disables DMA module
+*
+*   This function disables DMA module
+*/
+void dmaDisable(void)
+{
+    /* Wait until DMA's external bus has completed data transfer */
+	while((dmaREG->GCTRL & DMA_GCTRL_BUSBUSY) != 0U)
+    { 
+	} /* Wait */
+    /* Disable DMA module */
+	dmaREG->GCTRL = 0U;
+}
+
+
+/** @fn void dmaReqAssign(uint32 channel,uint32 reqline)
+*   @brief Initializes the DMA Driver
+*   @param[in] channel DMA channel
+*   @param[in] reqline DMA request line
+*
+*   This function assigns dma request lines to channels
+*/
+void dmaReqAssign(uint32 channel,uint32 reqline)
+{
+    register uint32 i=0U,j=0U;
+
+    i = channel >> 2U;              /* Find the register to configure */
+    j = channel -(i<<2U);           /* Find the offset of the type    */
+    j = 3U-j;                       /* reverse the byte order         */
+    j = j<<3U;                      /* find the bit location          */
+
+    /* mapping channel 'i' to request line 'j' */
+    dmaREG->DREQASI[i] &= ~(0xffU<<j);   
+    dmaREG->DREQASI[i] |= (reqline<<j);
+}
+
+
+/** @fn uint32 dmaGetReq(uint32 channel)
+*   @brief Gets the request line number mapped to the selected channel
+*   @param[in] channel DMA channel
+*
+*   This function returns the request line number mapped to the selected channel
+*/
+uint32 dmaGetReq(uint32 channel)
+{
+	register uint32 i=0U,j=0U;
+
+    i = channel >> 2U;              /* Find the register to configure */
+    j = channel -(i<<2U);           /* Find the offset of the type    */
+    j = 3U-j;                       /* reverse the byte order         */
+    j = j<<3U;                      /* find the bit location          */
+    return ((dmaREG->DREQASI[i] >> j) &0xffU);
+}
+
+
+/** @fn void dmaSetCtrlPacket(uint32 channel)
+*   @brief Initializes the DMA Driver
+*
+*   This function sets control packet
+*/
+void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT)
+{
+    register uint32 i=0U,j=0U;
+    
+    dmaRAMREG->PCP[channel].ISADDR  =  g_dmaCTRLPKT.SADD;
+    
+    dmaRAMREG->PCP[channel].IDADDR  =  g_dmaCTRLPKT.DADD;
+    
+    dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16U) | g_dmaCTRLPKT.ELCNT;
+  
+    dmaRAMREG->PCP[channel].CHCTRL  = (g_dmaCTRLPKT.RDSIZE    << 14U) | (g_dmaCTRLPKT.WRSIZE    << 12U) | (g_dmaCTRLPKT.TTYPE << 8U)| \
+                                      (g_dmaCTRLPKT.ADDMODERD << 3U ) | (g_dmaCTRLPKT.ADDMODEWR << 1U ) | (g_dmaCTRLPKT.AUTOINIT);
+
+    dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U);
+
+    dmaRAMREG->PCP[channel].EIOFF   = (g_dmaCTRLPKT.ELDOFFSET << 16U) | (g_dmaCTRLPKT.ELSOFFSET);
+  
+    dmaRAMREG->PCP[channel].FIOFF   = (g_dmaCTRLPKT.FRDOFFSET << 16U) | (g_dmaCTRLPKT.FRSOFFSET);
+
+    i = channel >> 3U;                /* Find the register to write                    */
+    j = channel -(i << 3U);           /* Find the offset of the 4th bit                */
+    j = 7U -j;                        /* Reverse the order of the 4th bit offset       */
+    j = j<<2U;                        /* Find the bit location of the 4th bit to write */
+
+    dmaREG->PAR[i] &= ~(0xfU<<j);
+    dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j);
+}
+
+
+
+/** @fn void dmaSetChEnable(uint32 channel,uint32 type)
+*   @brief Enable channel
+*   @param[in] channel DMA channel
+*   @param[in] type Type of triggering
+*                    - DMA_HW: Enables the selected DMA channel for hardware triggering
+*                    - DMA_SW: Enables the selected DMA channel for software triggering
+*
+*   This function enables the DMA channel for hardware or software triggering
+*/
+void dmaSetChEnable(uint32 channel,uint32 type)
+{
+    if(type == DMA_HW)
+    {
+     dmaREG->HWCHENAS = (1U << channel);
+    }
+    else if(type == DMA_SW)
+    {
+     dmaREG->SWCHENAS = (1U << channel);
+    }
+	else
+	{
+    /** Empty  */
+	}	
+}
+
+
+
+/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
+*   @brief Assign Priority to the channel
+*   @param[in] channel DMA channel
+*   @param[in] priority Priority queue to which channel needs to be assigned
+*                        - LOWPRIORITY : The selected channel will be assigned to low priority queue
+*                        - HIGHPRIORITY: The selected channel will be assigned to high priority queue
+*
+*   This function assigns the selected priority to the selected channel
+*/
+void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
+{
+	if (priority == LOWPRIORITY)
+	{
+		dmaREG->CHPRIOR |= 1U << channel;
+	}
+	else
+	{
+		dmaREG->CHPRIOS |= 1U << channel;
+	}
+}
+
+
+/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
+*   @brief Enable selected interrupt
+*   @param[in] channel DMA channel
+*   @param[in] inttype Interrupt to be enabled
+*                       - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
+*                       - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
+*                       - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
+*                       - BTC: Block transfer complete Interrupt will be disabled for the selected channel
+*                       - BER: Bus Error Interrupt will be disabled for the selected channel
+*
+*   This function enables the selected interrupt for the selected channel
+*/
+void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
+{
+	dmaREG->GCHIENAS = 1 << channel;
+	
+	switch (inttype)
+	{
+	case FTC: 	dmaREG->FTCINTENAS |= 1U << channel;
+				break;
+	case LFS:	dmaREG->LFSINTENAS |= 1U << channel;
+				break;
+	case HBC:	dmaREG->HBCINTENAS |= 1U << channel;
+				break;
+	case BTC:	dmaREG->BTCINTENAS |= 1U << channel;
+				break;
+	default :
+	            break;
+	}
+}
+
+
+
+/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
+*   @brief Disable selected interrupt
+*   @param[in] channel DMA channel
+*   @param[in] inttype Interrupt to be disabled
+*                       - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
+*                       - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
+*                       - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
+*                       - BTC: Block transfer complete Interrupt will be disabled for the selected channel
+*                       - BER: Bus Error Interrupt will be disabled for the selected channel
+*
+*   This function disables the selected interrupt for the selected channel
+*/
+void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
+{
+	switch (inttype)
+	{
+	case FTC: 	dmaREG->FTCINTENAR |= 1U << channel;
+				break;
+	case LFS:	dmaREG->LFSINTENAR |= 1U << channel;
+				break;
+	case HBC:	dmaREG->HBCINTENAR |= 1U << channel;
+				break;
+	case BTC:	dmaREG->BTCINTENAR |= 1U << channel;
+				break;
+	default :
+	            break;				
+	}
+}
+
+
+
+/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
+*   @brief Configure start and end address of the region
+*   @param[in] region Memory Region
+*                     - DMA_REGION0
+*                     - DMA_REGION1
+*                     - DMA_REGION2
+*                     - DMA_REGION3
+*   @param[in] start_add Start address of the the region
+*   @param[in] end_add End address of the region
+*
+*   This function configure start and end address of the selected region
+*/
+void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
+{
+	dmaREG->DMAMPR[region].STARTADD = start_add;
+	dmaREG->DMAMPR[region].ENDADD = end_add;
+}
+
+
+
+/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
+*   @brief Enable the selected region
+*   @param[in] region Memory Region
+*                     - DMA_REGION0
+*                     - DMA_REGION1
+*                     - DMA_REGION2
+*                     - DMA_REGION3
+*   @param[in] access Access permission of the selected region
+*                      - FULLACCESS
+*                      - READONLY
+*                      - WRITEONLY
+*                      - NOACCESS
+*   @param[in] intenable Interrupt to be enabled or not
+*                         - INTERRUPT_ENABLE : Enable interrupt for the selected region
+*                         - INTERRUPT_DISABLE: Disable interrupt for the selected region
+*
+*   This function enables the selected region with selected access permission with or without interrupt enable
+*/
+void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
+{
+    /* Enable the region */
+	dmaREG->DMAMPCTRL |= 1U << (region*8U);
+    /* Set access permission for the region */
+	dmaREG->DMAMPCTRL |= access << ((region*8U) + 1U);
+    /* Enable or Disable interrupt */
+	dmaREG->DMAMPCTRL |= intenable << ((region*8U) + 3U);
+}
+
+
+
+/** @fn void dmaDisableRegion(dmaREGION_t region)
+*   @brief Disable the selected region
+*   @param[in] region Memory Region
+*                     - DMA_REGION0
+*                     - DMA_REGION1
+*                     - DMA_REGION2
+*                     - DMA_REGION3
+*
+*   This function disables the selected region(no address checking done).
+*/
+void dmaDisableRegion(dmaREGION_t region)
+{
+	dmaREG->DMAMPCTRL &= ~(1U << (region*8U));
+}
+
+
+
+/** @fn void dmaEnableParityCheck(void)
+*   @brief Enable Parity Check
+*
+*   This function enables parit check
+*/
+void dmaEnableParityCheck(void)
+{
+	dmaREG->DMAPCR = 0x5U;
+}
+
+
+
+/** @fn void dmaDisableParityCheck(void)
+*   @brief Disable Parity Check
+*
+*   This function disables parity check
+*/
+void dmaDisableParityCheck(void)
+{
+	dmaREG->DMAPCR = 0xAU;
+}
+
+
+
+
+
diff --git a/bsp/rm48x50/HALCoGen/source/sys_intvecs.asm b/bsp/rm48x50/HALCoGen/source/sys_intvecs.asm
new file mode 100644
index 0000000000000000000000000000000000000000..e97ba448ac3a5e538d584792ba28faa50bda0c17
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_intvecs.asm
@@ -0,0 +1,44 @@
+;-------------------------------------------------------------------------------
+; sys_intvecs.asm
+;
+; (c) Texas Instruments 2009-2013, All rights reserved.
+;
+
+    .sect ".intvecs"
+    .arm
+
+;-------------------------------------------------------------------------------
+; import reference for interrupt routines
+
+    .ref _c_int00
+    .ref _dabort
+    .ref IRQ_Handler
+    
+    .def resetEntry
+
+;-------------------------------------------------------------------------------
+; interrupt vectors
+
+resetEntry
+        b   _c_int00
+        b   turnon_VFP
+svcEntry
+        b   svcEntry
+prefetchEntry
+        b   prefetchEntry
+        b   _dabort
+reservedEntry
+        b   reservedEntry
+        b   IRQ_Handler
+        ldr pc,[pc,#-0x1b0]
+
+    .sect ".text"
+turnon_VFP
+        ; Enable FPV
+        STMDB sp!,     {r0}
+        fmrx  r0,      fpexc
+        orr   r0,      r0,   #0x40000000
+        fmxr  fpexc,   r0
+        LDMIA sp!,     {r0}
+        subs  pc,      lr,   #4
+;-------------------------------------------------------------------------------
diff --git a/bsp/rm48x50/HALCoGen/source/sys_link.cmd b/bsp/rm48x50/HALCoGen/source/sys_link.cmd
new file mode 100644
index 0000000000000000000000000000000000000000..1cf658fac5bf452a142ff11f9b82231ddc524238
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_link.cmd
@@ -0,0 +1,85 @@
+/*----------------------------------------------------------------------------*/
+/* sys_link.cmd                                                               */
+/*                                                                            */
+/* (c) Texas Instruments 2009-2013, All rights reserved.                      */
+/*                                                                            */
+/*----------------------------------------------------------------------------*/
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+
+--retain="*(.intvecs)"
+--retain="*(FSymTab)"
+--retain="*(VSymTab)"
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map                                                                 */
+
+MEMORY
+{
+    VECTORS (X)  : origin=0x00000000 length=0x00000020
+    FLASH0  (RX) : origin=0x00000020 length=0x0017FFE0
+    FLASH1  (RX) : origin=0x00180000 length=0x00180000
+    STACKS  (RW) : origin=0x08000000 length=0x00001500
+    RAM     (RW) : origin=0x08001500 length=0x0003eaff
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+
+SECTIONS
+{
+    .intvecs : {} > VECTORS
+    .text    : {} > FLASH0 | FLASH1
+    .const   : {} > FLASH0 | FLASH1
+    .cinit   : {} > FLASH0 | FLASH1
+    .pinit   : {} > FLASH0 | FLASH1
+    GROUP
+    {
+        .bss     : {}
+        .data    : {}
+        .sysmem  : {}
+        ._dummy  : {system_data_end = .;}
+    } > RAM
+
+
+/* USER CODE BEGIN (11) */
+    /* place this section in the last section in RAM. The brain damaged linker
+     * could only create symbols in sections. */
+    ._FSymTab  : {
+        __fsymtab_start = .;
+        *(FSymTab)
+        __fsymtab_end = .;
+    } > FLASH0 | FLASH1
+    ._VSymTab  : {
+        __vsymtab_start = .;
+        *(VSymTab)
+        __vsymtab_end = .;
+    } > FLASH0 | FLASH1
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+
+/*----------------------------------------------------------------------------*/
+/* Misc                                                                       */
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+/*----------------------------------------------------------------------------*/
+
diff --git a/bsp/rm48x50/HALCoGen/source/sys_main.c b/bsp/rm48x50/HALCoGen/source/sys_main.c
new file mode 100644
index 0000000000000000000000000000000000000000..b59cfe37f4401612c57cee0165e16df0f65bd8fd
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_main.c
@@ -0,0 +1,82 @@
+/** @file sys_main.c 
+*   @brief Application main file
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*   This file contains an empty main function,
+*   which can be used for the application.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* we will use our own main and get rid off everything from HALCoGen here */
+#if 0
+#include <stdint.h>
+/* USER CODE END */
+
+/* Include Files */
+
+#include "sys_common.h"
+#include "system.h"
+
+/* USER CODE BEGIN (1) */
+
+/* Include HET header file - types, definitions and function declarations for system driver */
+#include "het.h"
+#include "esm.h"
+#include "sci.h"
+#include "rti.h"
+
+/* Task1 */
+void vTaskDelay(int t)
+{
+    for (; t; t--)
+    {
+        int i;
+        for(i = 100000;i ; i--)
+        {
+        }
+    }
+}
+/* USER CODE END */
+
+/** @fn void main(void)
+*   @brief Application main function
+*   @note This function is empty by default.
+*
+*   This function is called after startup.
+*   The user can use this function to implement the application.
+*/
+
+/* USER CODE BEGIN (2) */
+uint8_t sci_buf;
+/* USER CODE END */
+
+void main(void)
+{
+/* USER CODE BEGIN (3) */
+
+    /* Set high end timer GIO port hetPort pin direction to all output */
+    gioSetDirection(hetPORT1, 0xFFFFFFFF);
+    sciInit();
+    rtiInit();
+    rtiStartCounter(rtiCOUNTER_BLOCK1);
+    rtiEnableNotification(rtiNOTIFICATION_COMPARE3);
+    _enable_IRQ();
+    sciReceive(scilinREG, 1, &sci_buf);
+
+    for(;;)
+    {
+        gioSetBit(hetPORT1, 17, gioGetBit(hetPORT1, 17) ^ 1);
+        /* Taggle HET[1] with timer tick */
+        /*sciSendByte(scilinREG, 'b');*/
+        vTaskDelay(100);
+        /*sciSendByte(scilinREG, 'a');*/
+    }
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (4) */
+#endif
+/* USER CODE END */
diff --git a/bsp/rm48x50/HALCoGen/source/sys_mpu.asm b/bsp/rm48x50/HALCoGen/source/sys_mpu.asm
new file mode 100644
index 0000000000000000000000000000000000000000..9d5ca152dd86512a5e8e1ac3a1db87f8936473d2
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_mpu.asm
@@ -0,0 +1,403 @@
+;-------------------------------------------------------------------------------
+; sys_mpu.asm
+;
+; (c) Texas Instruments 2009-2013, All rights reserved.
+;
+
+    .text
+    .arm
+
+
+;-------------------------------------------------------------------------------
+; Initalize Mpu
+
+    .def     _mpuInit_
+    .asmfunc
+
+_mpuInit_
+        stmfd sp!, {r0}
+        ; Disable mpu
+        mrc   p15, #0, r0, c1, c0, #0
+        bic   r0,  r0, #1
+        dsb
+        mcr   p15, #0, r0, c1, c0, #0
+        isb
+        ; Disable background region
+        mrc   p15, #0, r0,      c1, c0, #0
+        bic   r0,  r0, #0x20000
+        mcr   p15, #0, r0,      c1, c0, #0
+        ; Setup region 1
+        mov   r0,  #0
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r1Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x1000
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 <<  9) + (1 <<  8) + (0x1F << 1) + (1)) 
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 2
+        mov   r0,  #1
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r2Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x0600
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x15 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region  
+        mov   r0,  #2
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r3Base
+        mcr   p15, #0,    r0, c6, c1, #0    
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x11 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 4
+        mov   r0,  #3
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r4Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x11 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 5
+        mov   r0,  #4
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r5Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0000
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x19 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 6
+        mov   r0,  #5
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r6Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0000
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x1A << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 7
+        mov   r0,  #6
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r7Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x1200
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x16 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 8
+        mov   r0,  #7
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r8Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0010
+        orr   r0,  r0,    #0x1300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x17 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 9
+        mov   r0,  #8
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r9Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0010
+        orr   r0,  r0,    #0x1300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x08 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 10
+        mov   r0,  #9
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r10Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0010
+        orr   r0,  r0,    #0x1300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x17 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 11
+        mov   r0,  #10
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r11Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x1100
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x0A << 1) + (0))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 12
+        mov   r0,  #11
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r12Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x1300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x15 << 1) + (0))
+        mcr   p15, #0,    r0, c6, c1, #2
+
+
+        ; Enable mpu background region
+        mrc   p15, #0, r0,      c1, c0, #0
+        orr   r0,  r0, #0x20000
+        mcr   p15, #0, r0,      c1, c0, #0
+        ; Enable mpu
+        mrc   p15, #0, r0, c1, c0, #0
+        orr   r0,  r0, #1
+        dsb
+        mcr   p15, #0, r0, c1, c0, #0
+        isb
+        ldmfd sp!, {r0}
+        bx    lr
+
+r1Base  .word 0x00000000  
+r2Base  .word 0x00000000  
+r3Base  .word 0x08000000  
+r4Base  .word 0x08400000  
+r5Base  .word 0x60000000  
+r6Base  .word 0x80000000  
+r7Base  .word 0xF0000000  
+r8Base  .word 0xFC000000  
+r9Base  .word 0xFE000000  
+r10Base  .word 0xFF000000  
+r11Base  .word 0x08001000  
+r12Base  .word 0x20000000  
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Mpu
+
+    .def     _mpuEnable_
+    .asmfunc
+
+_mpuEnable_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0, c1, c0, #0
+        orr   r0,  r0, #1
+        dsb
+        mcr   p15, #0, r0, c1, c0, #0
+        isb
+        ldmfd sp!, {r0}		
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable Mpu
+
+    .def     _mpuDisable_
+    .asmfunc
+
+_mpuDisable_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0, c1, c0, #0
+        bic   r0,  r0, #1
+        dsb
+        mcr   p15, #0, r0, c1, c0, #0
+        isb
+        ldmfd sp!, {r0}		
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Mpu background region
+
+    .def     _mpuEnableBackgroundRegion_
+    .asmfunc
+
+_mpuEnableBackgroundRegion_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0,      c1, c0, #0
+        orr   r0,  r0, #0x20000
+        mcr   p15, #0, r0,      c1, c0, #0
+        ldmfd sp!, {r0}		
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable Mpu background region
+
+    .def     _mpuDisableBackgroundRegion_
+    .asmfunc
+
+_mpuDisableBackgroundRegion_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0,      c1, c0, #0
+        bic   r0,  r0, #0x20000
+        mcr   p15, #0, r0,      c1, c0, #0
+        ldmfd sp!, {r0}
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Returns number of implemented Mpu regions
+
+    .def     _mpuGetNumberOfRegions_
+    .asmfunc
+
+_mpuGetNumberOfRegions_
+
+        mrc   p15, #0, r0,      c0, c0, #4
+        uxtb  r0,  r0, ROR #8
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Returns the type of the implemented mpu regions
+
+    .def     _mpuAreRegionsSeparate_
+    .asmfunc
+
+_mpuAreRegionsSeparate_
+
+        mrc   p15, #0, r0,      c0, c0, #4
+        uxtb  r0,  r0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Set mpu region number
+
+    .def     _mpuSetRegion_
+    .asmfunc
+
+_mpuSetRegion_
+
+        mcr   p15, #0, r0, c6, c2, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get mpu region number
+
+    .def     _mpuGetRegion_
+    .asmfunc
+
+_mpuGetRegion_
+
+        mrc   p15, #0, r0, c6, c2, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Set base address
+
+    .def     _mpuSetRegionBaseAddress_
+    .asmfunc
+
+_mpuSetRegionBaseAddress_
+
+        mcr   p15, #0, r0, c6, c1, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get base address
+
+    .def     _mpuGetRegionBaseAddress_
+    .asmfunc
+
+_mpuGetRegionBaseAddress_
+
+        mrc   p15, #0, r0, c6, c1, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Set type and permission
+
+    .def     _mpuSetRegionTypeAndPermission_
+    .asmfunc
+
+_mpuSetRegionTypeAndPermission_
+
+        orr   r0,  r0, r1
+        mcr   p15, #0, r0, c6, c1, #4
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get type
+
+    .def     _mpuGetRegionType_
+    .asmfunc
+
+_mpuGetRegionType_
+
+        mrc   p15, #0, r0,     c6, c1, #4
+        bic   r0,  r0, #0xFF00
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get permission
+
+    .def     _mpuGetRegionPermission_
+    .asmfunc
+
+_mpuGetRegionPermission_
+
+        mrc   p15, #0, r0,   c6, c1, #4
+        bic   r0,  r0, #0xFF
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Set region size register value
+
+    .def     _mpuSetRegionSizeRegister_
+    .asmfunc
+
+_mpuSetRegionSizeRegister_
+
+        mcr   p15, #0, r0, c6, c1, #2
+        bx    lr
+
+    .endasmfunc
+
+    
+
+;-------------------------------------------------------------------------------
+
diff --git a/bsp/rm48x50/HALCoGen/source/sys_pcr.c b/bsp/rm48x50/HALCoGen/source/sys_pcr.c
new file mode 100644
index 0000000000000000000000000000000000000000..870fc6e3b348a55f5df7fa047199ff7d069d9f85
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_pcr.c
@@ -0,0 +1,602 @@
+/** @file sys_pcr.c
+*   @brief PCR Driver Implementation File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*/
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#include "sys_pcr.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame)
+*   @brief Set the peripheral protection of the selected frame 
+*   @param[in] peripheral_Frame - Peripheral frame to be protected
+*
+*   This function sets the protection for the selected frame.
+*/
+void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame)
+{
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+	uint32 Quarant_selct;
+
+	chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
+	Quarant_selct  = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
+
+    if (chip_select_grp >= 3U)
+    {
+        pcrREG->PPROTSET3 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 2U)
+    {
+        pcrREG->PPROTSET2 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 1U)
+    {
+        pcrREG->PPROTSET1 = Quarant_selct;
+    }
+	else
+    {
+        pcrREG->PPROTSET0 = Quarant_selct;
+    }
+	
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @fn void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame)
+*   @brief Clear the peripheral protection of the selected frame 
+*   @param[in] peripheral_Frame - Peripheral frame to be out of protection
+*
+*   This function clears the protection set for the selected frame.
+*/
+void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame)
+{
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+	uint32 Quarant_selct;
+
+	chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
+	Quarant_selct  = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
+
+    if (chip_select_grp >= 3U)
+    {
+        pcrREG->PPROTCLR3 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 2U)
+    {
+        pcrREG->PPROTCLR2 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 1U)
+    {
+        pcrREG->PPROTCLR1 = Quarant_selct;
+    }
+	else
+    {
+        pcrREG->PPROTCLR0 = Quarant_selct;
+    }
+	
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+/** @fn void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame)
+*   @brief Take the selected peripheral to powerdown
+*   @param[in] peripheral_Frame - Peripheral frame to be taken to powerdown
+*
+*   This function will set the selected peripheral frame to powerdown.
+*/
+void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame)
+{
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+	uint32 Quarant_selct;
+
+	chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
+	Quarant_selct  = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
+	
+    if (chip_select_grp >= 3U)
+    {
+        pcrREG->PSPWRDWNSET3 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 2U)
+    {
+        pcrREG->PSPWRDWNSET2 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 1U)
+    {
+        pcrREG->PSPWRDWNSET1 = Quarant_selct;
+    }
+	else
+    {
+        pcrREG->PSPWRDWNSET0 = Quarant_selct;
+    }
+	
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+/** @fn void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame)
+*   @brief Bring the selected peripheral frame out of powerdown
+*   @param[in] peripheral_Frame - Peripheral frame to be taken out of powerdown
+*
+*   This function will bring the selected peripheral frame out of powerdown.
+*/
+void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame)
+{
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+	uint32 Quarant_selct;
+
+	chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
+	Quarant_selct  = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
+	
+    if (chip_select_grp >= 3U)
+    {
+        pcrREG->PSPWRDWNCLR3 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 2U)
+    {
+        pcrREG->PSPWRDWNCLR2 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 1U)
+    {
+        pcrREG->PSPWRDWNCLR1 = Quarant_selct;
+    }
+	else
+    {
+        pcrREG->PSPWRDWNCLR0 = Quarant_selct;
+    }
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+/** @fn void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+*   @brief Set the peripheral memory protection of the selected frame 
+*   @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be protected
+*
+*   This function sets the protection for the selected peripheral memory frame.
+*/
+void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+{
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+
+	chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
+
+	if (chip_select_grp >= 1U)
+    {
+        pcrREG->PMPROTSET1 = (1U << (peripheral_Memory_Frame_CS & 0xFU));
+    }
+	else
+    {
+        pcrREG->PMPROTSET0 = (1U << peripheral_Memory_Frame_CS);
+    }
+	
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+/** @fn void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+*   @brief Clear the peripheral memory protection of the selected frame 
+*   @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be cleared from protection
+*
+*   This function clears the protection set for the selected peripheral memory frame.
+*/
+void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+{
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+
+	chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
+
+	if (chip_select_grp >= 1U)
+    {
+        pcrREG->PMPROTCLR1 = (1U << (peripheral_Memory_Frame_CS & 0xFU));
+    }
+	else
+    {
+        pcrREG->PMPROTCLR0 = (1U << peripheral_Memory_Frame_CS);
+    }
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+/** @fn void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+*   @brief Take the selected peripheral memory frame to powerdown
+*   @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken to powerdown
+*
+*   This function will set the selected peripheral memory frame to powerdown.
+*/
+void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+{
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+
+	chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
+
+	if (chip_select_grp >= 1U)
+    {
+        pcrREG->PSPWRDWNSET1 = (1U << (peripheral_Memory_Frame_CS & 0xFU));
+    }
+	else
+    {
+        pcrREG->PSPWRDWNSET0 = (1U << peripheral_Memory_Frame_CS);
+    }
+	
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+/** @fn void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+*   @brief Bring the selected peripheral Memory frame out of powerdown
+*   @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken out of powerdown
+*
+*   This function will bring the selected peripheral memory frame out of powerdown.
+*/
+void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+{
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+
+	chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
+
+	if (chip_select_grp >= 1U)
+    {
+        pcrREG->PSPWRDWNCLR1 = (1U << (peripheral_Memory_Frame_CS & 0xFU));
+    }
+	else
+    {
+        pcrREG->PSPWRDWNCLR0 = (1U << peripheral_Memory_Frame_CS);
+    }
+	
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+/** @fn void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+*   @brief Set the peripheral protection of all the selected frames 
+*   @param[in] peripheral_Quad_CS - All Peripheral frames to be protected
+*
+*   This function sets the protection for all the selected frames.
+*/
+void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+    pcrREG->PPROTSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
+    pcrREG->PPROTSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
+    pcrREG->PPROTSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
+    pcrREG->PPROTSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
+	
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+/** @fn void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+*   @brief Clear the peripheral protection of all the selected frames 
+*   @param[in] peripheral_Quad_CS - All Peripheral frames to be out of protection.
+*
+*   This function clears the protection set for all the selected frame.
+*/
+void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+    pcrREG->PPROTCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
+    pcrREG->PPROTCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
+    pcrREG->PPROTCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
+    pcrREG->PPROTCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+/** @fn void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+*   @brief Take all the selected peripheral frame to powerdown
+*   @param[in] peripheral_Quad_CS - Peripheral frames to be taken to powerdown
+*
+*   This function will set all the selected peripheral frame to powerdown.
+*/
+void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+    pcrREG->PSPWRDWNSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
+    pcrREG->PSPWRDWNSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
+    pcrREG->PSPWRDWNSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
+    pcrREG->PSPWRDWNSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+/** @fn void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+*   @brief Bring all the selected peripheral frame out of powerdown
+*   @param[in] peripheral_Quad_CS - Peripheral frames to be taken out of powerdown
+*
+*   This function will bring all the selected peripheral frame out of powerdown.
+*/
+void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+    pcrREG->PSPWRDWNCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
+    pcrREG->PSPWRDWNCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
+    pcrREG->PSPWRDWNCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
+    pcrREG->PSPWRDWNCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+*   @brief Set the peripheral memory protection of all the selected frame 
+*   @param[in] peripheral_Memory_CS - Peripheral memory frames to be protected
+*
+*   This function sets the protection for all the selected peripheral memory frame.
+*/
+void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+    pcrREG->PMPROTSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
+    pcrREG->PMPROTSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+*   @brief Clear the peripheral memory protection of all the selected frame 
+*   @param[in] peripheral_Memory_CS - Peripheral memory frames to be cleared from protection
+*
+*   This function clears the protection set for all the selected peripheral memory frame.
+*/
+void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+    pcrREG->PMPROTCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
+    pcrREG->PMPROTCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
+
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+*   @brief Take all the selected peripheral memory frame to powerdown
+*   @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken to powerdown
+*
+*   This function will set all the selected peripheral memory frame to powerdown.
+*/
+void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+
+    pcrREG->PSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
+    pcrREG->PSPWRDWNSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
+	
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+*   @brief Bring all the selected peripheral Memory frame out of powerdown
+*   @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken out of powerdown
+*
+*   This function will bring all the selected peripheral memory frame out of powerdown.
+*/
+void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+    pcrREG->PSPWRDWNCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
+    pcrREG->PSPWRDWNCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
+
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+
+/** @fn peripheral_Quad_ChipSelect_t peripheral_Powerdown_Status(void)
+*   @brief Get the powerdown status of the peripheral frames.
+*   @return Peripheral frames power down status
+*
+*   This function gets the powerdown status of the peripheral frames.
+*/
+peripheral_Quad_ChipSelect_t peripheral_Powerdown_Status(void)
+{
+
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+
+    peripheral_Quad_ChipSelect_t peripheral_Quad_CS;
+
+    peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7      = pcrREG->PSPWRDWNSET0;
+    peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15     = pcrREG->PSPWRDWNSET1; 
+    peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23   = pcrREG->PSPWRDWNSET2; 
+    peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31  = pcrREG->PSPWRDWNSET3; 
+
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+   
+    return peripheral_Quad_CS;
+}
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+
+/** @fn peripheral_Quad_ChipSelect_t peripheral_Protection_Status(void)
+*   @brief Get the protection status of the peripheral frames
+*   @return Peripheral frames protection status
+*
+*   This function gets the protection status of the peripheral frames.
+*/
+peripheral_Quad_ChipSelect_t peripheral_Protection_Status(void)
+{
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+    peripheral_Quad_ChipSelect_t peripheral_Quad_CS;
+
+    peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7     = pcrREG->PPROTSET0; 
+    peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15    = pcrREG->PPROTSET1; 
+    peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23  = pcrREG->PPROTSET2; 
+    peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31 = pcrREG->PPROTSET3;
+
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+   
+    return peripheral_Quad_CS;
+}
+
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+/** @fn peripheral_Memory_ChipSelect_t peripheral_Memory_Protection_Status(void)
+*   @brief Get the protection set of all the peripheral Memory frame
+*   @return Peripheral memory frames protection status
+*
+*   This function gets the protection status of all the peripheral Memory frame.
+*/
+peripheral_Memory_ChipSelect_t peripheral_Memory_Protection_Status(void)
+{
+
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+    peripheral_Memory_ChipSelect_t peripheral_Memory_CS;
+
+    peripheral_Memory_CS.Peripheral_Mem_CS0_31 = pcrREG->PMPROTSET0;
+    peripheral_Memory_CS.Peripheral_Mem_CS32_63 = pcrREG->PMPROTSET1;
+
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+
+    return peripheral_Memory_CS;
+}
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+
+/** @fn peripheral_Memory_ChipSelect_t Periipheral_Memory_Powerdown_Status(void)
+*   @brief Get the powerdown status of all the peripheral Memory frame
+*   @return Peripheral memory frames powerdown status
+*
+*   This function gets the powerdown status of all the peripheral Memory frame.
+*/
+peripheral_Memory_ChipSelect_t Periipheral_Memory_Powerdown_Status(void)
+{
+
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+    peripheral_Memory_ChipSelect_t peripheral_Memory_CS;
+
+    peripheral_Memory_CS.Peripheral_Mem_CS0_31 = pcrREG->PSPWRDWNSET0;
+    peripheral_Memory_CS.Peripheral_Mem_CS32_63 = pcrREG->PSPWRDWNSET1;
+
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+
+    return peripheral_Memory_CS;
+}
+
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
diff --git a/bsp/rm48x50/HALCoGen/source/sys_phantom.c b/bsp/rm48x50/HALCoGen/source/sys_phantom.c
new file mode 100644
index 0000000000000000000000000000000000000000..3e84d2c237fc3f10655ff433fd49e4e692c95622
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_phantom.c
@@ -0,0 +1,32 @@
+/** @file sys_phantom.c 
+*   @brief Phantom Interrupt Source File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*   This file contains:
+*   - Phantom Interrupt Handler
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Phantom Interrupt Handler */
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#pragma CODE_STATE(phantomInterrupt, 32)
+#pragma INTERRUPT(phantomInterrupt, IRQ)
+
+void phantomInterrupt(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
diff --git a/bsp/rm48x50/HALCoGen/source/sys_pmm.c b/bsp/rm48x50/HALCoGen/source/sys_pmm.c
new file mode 100644
index 0000000000000000000000000000000000000000..8dc5615d47227ec30448ea68e400277a1db4c7d7
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_pmm.c
@@ -0,0 +1,348 @@
+/** @file sys_pmm.c
+*   @brief PCR Driver Implementation File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*/
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+#include "sys_pmm.h"
+
+/** @fn void pmmInit(void)
+*   @brief Initializes the PMM Driver
+*
+*   This function initializes the PMM module.
+*/
+void pmmInit(void)
+{
+	/*Disable clocks to all logic domains*/
+	pmmREG->PDCLKDISREG = 0xFU;
+	/*Enable or disable clock to pmctrl_wakeup block and automatic clock wake up*/
+	pmmREG->GLOBALCTRL1 = (0U << 8U) | (0U << 0U); /*from GUI*/
+	/*Power on the logic power domains*/
+	pmmREG->LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
+	/*Power on the memory-only power domains*/
+	pmmREG->MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
+
+	/*wait till Logic Power Domain PD2 turns ON*/
+		while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD2] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+		{ 
+		}/* Wait */  
+		/*wait till Logic Power Domain PD3 turns ON*/
+		while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD3] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+		{ 
+		}/* Wait */  
+		/*wait till Logic Power Domain PD4 turns OFF*/
+		while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD4] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
+		{ 
+		}/* Wait */  
+		/*wait till Logic Power Domain PD5 turns ON*/
+		while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD5] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+		{ 
+		}/* Wait */  
+
+		/*wait till Memory Only Power Domain RAM_PD1 turns ON*/
+		while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD1] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+		{ 
+		}/* Wait */  
+		/*wait till Memory Only Power Domain RAM_PD2 turns ON*/
+		while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD2] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+		{ 
+		}/* Wait */  
+		/*wait till Memory Only Power Domain RAM_PD3 turns ON*/
+		while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD3] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+		{ 
+		}/* Wait */  
+	if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
+	{
+		/* Enable clocks for the selected logic domain */
+		pmmREG->PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
+	}
+
+}
+
+
+/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
+*   @brief Turns on Logic Power Domain
+*   @param[in] logicPD - Power Domain to be turned on
+*              - PMM_LOGICPD2: Power domain PD2 will be turned on
+*              - PMM_LOGICPD3: Power domain PD3 will be turned on
+*              - PMM_LOGICPD4: Power domain PD4 will be turned on
+*              - PMM_LOGICPD5: Power domain PD5 will be turned on
+*
+*   This function turns on the selected Logic Power Domain
+*
+*/
+void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
+{
+	if (logicPD != PMM_LOGICPD1)
+	{
+		/* Power on the domain */
+		if (logicPD == PMM_LOGICPD2)
+		{
+			pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U);
+		}
+		else if (logicPD == PMM_LOGICPD3)
+		{
+			pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U);
+		}
+		else if (logicPD == PMM_LOGICPD4)
+		{
+			pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U);
+		}
+		else
+		{
+			pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0x5U << 0U);
+		}
+		/* Wait until the power domain turns on */
+		while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+		{ 
+		}/* Wait */  
+		if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
+		{
+			/* Enable clocks to the power domain */
+			pmmREG->PDCLKDISCLRREG = 1U << (uint32)logicPD;
+		}
+	}
+}
+
+/** @fn void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
+*   @brief Turns on Memory Power Domain
+*   @param[in] memPD - Power Domain to be tured on
+*              - PMM_MEMPD1: Power domain RAM_PD1 will be turned on
+*              - PMM_MEMPD2: Power domain RAM_PD2 will be turned on
+*              - PMM_MEMPD3: Power domain RAM_PD3 will be turned on
+*
+*   This function turns on the selected Memory Power Domain
+*
+*/
+void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
+{
+	/* Power on the domain */
+	if (memPD == PMM_MEMPD1)
+	{
+		pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U);
+	}
+	else if (memPD == PMM_MEMPD2)
+	{
+		pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U);
+	}
+	else
+	{
+		pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U);
+	}
+	/*Wait until the power domain turns on*/
+	while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+		{ 
+		}/* Wait */  
+}
+
+/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
+*   @brief Turns off Logic Power Domain
+*	@param[in] logicPD - Power Domain to be tured off
+*              - PMM_LOGICPD2: Power domain PD2 will be turned off
+*              - PMM_LOGICPD3: Power domain PD3 will be turned off
+*              - PMM_LOGICPD4: Power domain PD4 will be turned off
+*              - PMM_LOGICPD5: Power doamin PD5 will be turned off
+*
+*   This function turns off the selected Logic Power Domain
+*
+*/
+void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
+{
+	if (logicPD != PMM_LOGICPD1)
+	{
+		/* Disable all clocks to the power domain */
+		pmmREG->PDCLKDISSETREG = 1U << (uint32)logicPD;
+		
+		/* Power down the domain */
+		if (logicPD == PMM_LOGICPD2)
+		{
+			pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U);
+		}
+		else if (logicPD == PMM_LOGICPD3)
+		{
+			pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U);
+		}
+		else if (logicPD == PMM_LOGICPD4)
+		{
+			pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U);
+		}
+		else
+		{
+			pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0xAU << 0U);
+		}
+		/* Wait until the power domain turns off */
+		while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
+		{ 
+		}/* Wait */  
+	}
+}
+
+/** @fn void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
+*   @brief Turns off Memory Power Domain
+*   @param[in] memPD - Power Domain to be tured off
+*              - PMM_MEMPD1: Power domain RAM_PD1 will be turned off
+*              - PMM_MEMPD2: Power domain RAM_PD2 will be turned off
+*              - PMM_MEMPD3: Power domain RAM_PD3 will be turned off
+*
+*   This function turns off the selected Memory Power Domain
+*
+*/
+void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
+{
+	/* Power down the domain */
+	if (memPD == PMM_MEMPD1)
+	{
+		pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U);
+	}
+	else if (memPD == PMM_MEMPD2)
+	{
+		pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U);
+	}
+	else
+	{
+		pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U);
+	}
+	/*Wait until the power domain turns off*/
+	while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_MEMPDPWRSTAT) != 0U)
+		{ 
+		}/* Wait */  
+}
+
+/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
+*   @brief Check if the power domain is active or not
+*	@param[in] logicPD - Power Domain to be be checked
+*              - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not
+*              - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not
+*              - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not
+*              - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not
+*	@return The function will return:
+*              - TRUE : When the selected power domain is in Active state.
+*              - FALSE: When the selected power domain is in OFF state.
+*
+*   This function checks whether the selected power domain is active or not.
+*
+*/
+boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
+{
+	boolean status;
+	if ((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+	{
+		status = FALSE;
+	}
+	else
+	{
+		status = TRUE;
+	}
+	return status;
+}
+
+/** @fn boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
+*   @brief Check if the power domain is active or not
+*	@param[in] memPD - Power Domain to be tured off
+*              - PMM_MEMPD1: Checks whether Power domain RAM_PD1 is active or not
+*              - PMM_MEMPD2: Checks whether Power domain RAM_PD2 is active or not
+*              - PMM_MEMPD3: Checks whether Power domain RAM_PD3 is active or not
+*	@return The function will return:
+*              - TRUE : When the selected power domain is in Active state.
+*              - FALSE: When the selected power domain is in OFF state.
+*
+*   This function checks whether the selected power domain is active or not.
+*
+*/
+boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
+{
+	boolean status;
+	if ((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+	{
+		status = FALSE;
+	}
+	else
+	{
+		status = TRUE;
+	}
+	return status;
+}
+
+/** @fn void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration register
+*	@param[in] *config_reg - pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type  - 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*/
+void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
+		config_reg->CONFIG_MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
+		config_reg->CONFIG_PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
+		config_reg->CONFIG_GLOBALCTRL1 = PMM_GLOBALCTRL1_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg->CONFIG_LOGICPDPWRCTRL0 = pmmREG->LOGICPDPWRCTRL0;
+		config_reg->CONFIG_MEMPDPWRCTRL0 = pmmREG->MEMPDPWRCTRL0;
+		config_reg->CONFIG_PDCLKDISREG = pmmREG->PDCLKDISREG;
+		config_reg->CONFIG_GLOBALCTRL1 = pmmREG->GLOBALCTRL1;
+	}
+}
+
+/** @fn void pmmSetMode(pmm_Mode_t mode)
+*   @brief Set PSCON Compare Block Mode
+*	@param[in] mode - PSCON Compare Block mode
+*				- LockStep				: PSCON compare block is set to Lock-Step mode
+*				- SelfTest				: PSCON compare block is set to Self-Test mode
+*				- ErrorForcing			: PSCON compare block is set to Error-Forcing mode
+*				- SelfTestErrorForcing	: PSCON compare block is set to Self-Test-Error-Forcing mode
+*
+*   This function sets the PSCON Compare block to the selected mode
+*
+*/
+void pmmSetMode(pmm_Mode_t mode)
+{
+	/* Set PSCON Compare Block Mode */
+	pmmREG->PRCKEYREG = mode;
+}
+
+/** @fn boolean pmmPerformSelfTest(void)
+*   @brief Perform self test and return the result
+*
+*	@return The function will return
+*			- TRUE if PSCON compare block passed self-test
+*			- FALSE if PSCON compare block failed in self-test
+*
+*   This function checks whether PSCON compare block passed the self-test or not.
+*
+*/
+boolean pmmPerformSelfTest(void)
+{
+	boolean status = TRUE;
+	/*Enter self-test mode*/
+	pmmREG->PRCKEYREG = SelfTest;
+	/*Wait till self test is completed*/
+	while ((pmmREG->LPDDCSTAT1 & 0xFU) != 0xFU)
+	{ 
+	}/* Wait */ 				
+	
+	while ((pmmREG->MPDDCSTAT1 & 0x7U) != 0x7U)
+	{ 
+	}/* Wait */ 				
+
+	/*Check whether self-test passed or not*/
+	if ((pmmREG->LPDDCSTAT2 & 0xFU) != 0U)
+	{
+		status = FALSE;
+	}
+	if ((pmmREG->MPDDCSTAT2 & 0x7U) != 0U)
+	{
+		status = FALSE;
+	}
+	/*Enter lock-step mode*/
+	pmmREG->PRCKEYREG = LockStep;
+
+	return status;
+}
diff --git a/bsp/rm48x50/HALCoGen/source/sys_pmu.asm b/bsp/rm48x50/HALCoGen/source/sys_pmu.asm
new file mode 100644
index 0000000000000000000000000000000000000000..c60bb91bf779125eef616c1d14594541673f2074
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_pmu.asm
@@ -0,0 +1,223 @@
+;-------------------------------------------------------------------------------
+; sys_pmu.asm
+;
+; (c) Texas Instruments 2009-2013, All rights reserved.
+;
+
+    .text
+    .arm
+
+
+;-------------------------------------------------------------------------------
+; Initialize Pmu
+; Note: It will reset all counters
+
+    .def     _pmuInit_
+    .asmfunc
+
+_pmuInit_
+
+        stmfd sp!, {r0}
+        ; set control register
+        mrc   p15, #0, r0, c9, c12, #0 
+        orr   r0,  r0, #(1 << 4) + 6 + 1
+        mcr   p15, #0, r0, c9, c12, #0
+        ; clear flags
+		mov   r0,  #0
+		sub   r1,  r1,  #1
+		mcr   p15, #0, r0, c9, c12, #3 
+        ; select counter 0 event
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mov   r0,  #0x11
+        mcr   p15, #0, r0, c9, c13, #1 ; select event
+        ; select counter 1 event
+		mov   r0,  #1
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mov   r0,  #0x11
+        mcr   p15, #0, r0, c9, c13, #1 ; select event
+        ; select counter 2 event
+		mov   r0,  #2
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mov   r0,  #0x11
+        mcr   p15, #0, r0, c9, c13, #1 ; select event
+        ldmfd sp!, {r0}
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Counters Global [Cycle, Event [0..2]]
+; Note: It will reset all counters
+
+    .def     _pmuEnableCountersGlobal_
+    .asmfunc
+
+_pmuEnableCountersGlobal_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0, c9, c12, #0 
+        orr   r0,  r0, #7
+        mcr   p15, #0, r0, c9, c12, #0
+        ldmfd sp!, {r0}		
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Disable Counters Global [Cycle, Event [0..2]]
+
+    .def     _pmuDisableCountersGlobal_
+    .asmfunc
+
+_pmuDisableCountersGlobal_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0, c9, c12, #0 
+        bic   r0,  r0, #1
+        mcr   p15, #0, r0, c9, c12, #0
+        ldmfd sp!, {r0}		
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Reset Cycle Counter
+
+    .def     _pmuResetCycleCounter_
+    .asmfunc
+
+_pmuResetCycleCounter_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0, c9, c12, #0 
+        orr   r0,  r0, #4
+        mcr   p15, #0, r0, c9, c12, #0
+        ldmfd sp!, {r0}		
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Reset Event Counters [0..2]
+
+    .def     _pmuResetEventCounters_
+    .asmfunc
+
+_pmuResetEventCounters_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0, c9, c12, #0 
+        orr   r0,  r0, #2
+        mcr   p15, #0, r0, c9, c12, #0
+        ldmfd sp!, {r0}		
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Reset Cycle Counter abd Event Counters [0..2]
+
+    .def     _pmuResetCounters_
+    .asmfunc
+
+_pmuResetCounters_
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0, c9, c12, #0 
+        orr   r0,  r0, #6
+        mcr   p15, #0, r0, c9, c12, #0
+        ldmfd sp!, {r0}		
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Start Counters [Cycle, 0..2]
+
+    .def     _pmuStartCounters_
+    .asmfunc
+
+_pmuStartCounters_
+
+        mcr   p15, #0, r0, c9, c12, #1
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Stop Counters [Cycle, 0..2]
+
+    .def     _pmuStopCounters_
+    .asmfunc
+
+_pmuStopCounters_
+
+        mcr   p15, #0, r0, c9, c12, #2
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Set Count event
+
+    .def     _pmuSetCountEvent_
+    .asmfunc
+
+_pmuSetCountEvent_
+ 
+        lsr   r0,  r0, #1
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mcr   p15, #0, r1, c9, c13, #1 ; select event
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Get Cycle Count
+
+    .def     _pmuGetCycleCount_
+    .asmfunc
+
+_pmuGetCycleCount_
+
+        mrc   p15, #0, r0, c9, c13, #0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Get Event Counter Count Value
+
+    .def     _pmuGetEventCount_
+    .asmfunc
+
+_pmuGetEventCount_
+
+        lsr   r0,  r0, #1
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mrc   p15, #0, r0, c9, c13, #2 ; read event counter
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Get Overflow Flags
+
+    .def     _pmuGetOverflow_
+    .asmfunc
+
+_pmuGetOverflow_
+
+        mrc   p15, #0, r0, c9, c12, #3 ; read overflow
+		mov   r1,  #0
+		sub   r1,  r1,  #1
+		mcr   p15, #0, r1, c9, c12, #3 ; clear flags
+        bx    lr
+
+    .endasmfunc
+
+    
+
+;-------------------------------------------------------------------------------
+
diff --git a/bsp/rm48x50/HALCoGen/source/sys_selftest.c b/bsp/rm48x50/HALCoGen/source/sys_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..ffc698c4709cdd256318ae0f5b22d0f2a8581bc6
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_selftest.c
@@ -0,0 +1,2178 @@
+/** @file sys_selftest.c 
+*   @brief Selftest Source File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*   This file contains:
+*   - Selftest API's
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_selftest.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void ccmSelfCheck(void)
+*   @brief CCM module self check Driver
+*
+*   This function self checks the CCM module.
+*/
+void ccmSelfCheck(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+	/* Run a diagnostic check on the CCM-R4F module */
+	/* This step ensures that the CCM-R4F can actually indicate an error */
+
+	/* Configure CCM in self-test mode */
+	CCMKEYR = 0x6U;								
+	/* Wait for CCM self-test to complete */
+	while ((CCMSR & 0x100U) != 0x100U)
+	{ 
+	}/* Wait */ 		
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+	
+	/* Check if there was an error during the self-test */
+	if ((CCMSR & 0x1U) == 0x1U)
+	{
+		/* STE is set */
+		ccmFail(0U);								
+	}
+	else
+	{
+		/* Check CCM-R4 self-test error flag by itself (without compare error) */
+		if ((esmREG->ESTATUS1[0U] & 0x80000000U) != 0x80000000U)
+		{
+			/* ESM flag is not set */
+			ccmFail(1U);						
+		}
+		else
+		{
+			/* clear ESM group1 channel 31 flag */
+			esmREG->ESTATUS1[0U] = 0x80000000U;	
+			
+			/* Configure CCM in error-forcing mode */
+			CCMKEYR = 0x9U;
+			
+            /* check if compare error flag is set */
+			if ((esmREG->ESTATUS1[1U] & 0x4U) != 0x4U)
+			{
+				/* ESM flag is not set */
+				ccmFail(2U);
+			}
+			else
+			{
+		        /* Check FIQIVEC to ESM High Interrupt flag is set */ 
+				if((vimREG->FIQINDEX & 0x000000FFU) != 1U)
+				{
+				   /* ESM High Interrupt flag is not set in VIM*/
+				   ccmFail(3U);				
+				}
+				/* clear ESM group2 channel 2 flag */ 
+				esmREG->ESTATUS1[1U] = 0x4U;
+				
+				/* clear ESM group2 shadow status flag */
+				esmREG->ESTATUS5EMU = 0x4U;				
+				
+				/* ESM self-test error needs to also be cleared */
+				esmREG->ESTATUS1[0U] = 0x80000000U;		
+				
+				/* Clear CCM-R4 CMPE flag */
+				CCMSR = 0x00010000U;
+
+				/* Return CCM-R4 to lock-step mode */
+				CCMKEYR = 0x0U;
+				
+				/* The nERROR pin will become inactive once the LTC counter expires */
+				esmREG->KEY = 0x5U;	
+			}
+		}
+	}
+}
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @fn void ccmFail(uint32 x)
+*   @brief CCM module fail service routine
+*
+*   This function is called if CCM module selftest fail.
+*/
+void ccmFail(uint32 x)
+{
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+	if (x == 0U)
+	{
+		/* CCM-R4 is not able to flag a compare error in self-test mode.
+		 * Lock-step operation cannot be verified.
+		 */
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+	}
+	else if (x == 1U)
+	{
+		/* CCM-R4 self-test error flag is not set in ESM register.
+		 * Could be due to a connection issue inside the part.
+		 */
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+	}
+	else if (x == 2U)
+	{
+		/* CCM-R4 compare error flag is not set in ESM.
+		 * Lock-step operation cannot be verified.
+		 */
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+	}
+	else if (x == 3U)
+	{
+		/* ESM High Interrupt Flag is not set in VIM.
+		 */
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+	}	
+	else
+	{
+		/*  */
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+	}	
+}
+
+/** @fn void memoryInit(uint32 ram)
+*   @brief Memory Initialization Driver
+*
+*   This function is called to perform Memory initialization of selected RAM's.
+*/
+void memoryInit(uint32 ram)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+	/* Enable Memory Hardware Initialization */
+	systemREG1->MINITGCR = 0xAU;	
+	
+    /* Enable Memory Hardware Initialization for selected RAM's */
+	systemREG1->MSINENA  = ram;
+    
+	/* Wait until Memory Hardware Initialization complete */
+	while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U)
+	{ 
+	}/* Wait */ 		
+	
+	/* Disable Memory Hardware Initialization */
+	systemREG1->MINITGCR = 0x5U;	
+	
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+/** @fn void stcSelfCheck(void)
+*   @brief STC module self check Driver
+*
+*   This function is called to perform STC module self check.
+*/
+void stcSelfCheck(void)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+	volatile uint32 i = 0U;
+
+	/* Run a diagnostic check on the CPU self-test controller */
+	/* First set up the STC clock divider as STC is only supported up to 90MHz */
+	
+	/* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */
+	systemREG2->STCCLKDIV = 0x01000000U;	
+	
+	/* Select one test interval, restart self-test next time, 0x00010001 */
+	stcREG->STCGCR0 = 0x00010001U;						
+	
+	/* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */
+	stcREG->STCSCSCR = 0x1AU;							
+	
+	/* Maximum time-out period */
+	stcREG->STCTPR = 0xFFFFFFFFU;						
+
+	/* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }								
+
+	/* Enable self-test */
+	stcREG->STCGCR1 = 0xAU;								
+	
+	/* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }	
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+	
+	/* Idle the CPU so that the self-test can start */
+	_gotoCPUIdle_();
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+}
+
+/** @fn void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test)
+*   @brief CPU self test Driver
+*   @param[in] no_of_intervals - Number of Test Intervals to be 
+*   @param[in] max_timeout     - Maximum Timeout to complete selected test Intervals
+*   @param[in] restart_test    - Restart the test from Interval 0 or Continue from where it stopped.
+*
+*   This function is called to perform CPU self test using STC module.
+*/
+void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test)
+{
+	volatile uint32 i = 0U;
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+	
+	/* Run specified no of test intervals starting from interval 0 */
+	/* Start test from interval 0 or continue the test. */ 
+	stcREG->STCGCR0 = (no_of_intervals << 16U)
+	                | (uint32) restart_test;						
+	
+	/* Configure Maximum time-out period */
+	stcREG->STCTPR = max_timeout;						
+	
+	/* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }								
+
+	/* Enable self-test */
+	stcREG->STCGCR1 = 0xAU;								
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+	/* Idle the CPU so that the self-test can start */
+	
+	_gotoCPUIdle_();
+	
+}
+
+/** @fn void pbistSelfCheck(void)
+*   @brief PBIST self test Driver
+*
+*   This function is called to perform PBIST self test.
+*/
+void pbistSelfCheck(void)
+{
+	volatile uint32 i = 0U;
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+	/* Run a diagnostic check on the memory self-test controller */
+	/* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */
+	
+	/* PBIST ROM clock frequency = HCLK frequency /2 */
+	systemREG1->MSTGCR |= 0x00000100U;				
+	
+	/* Enable PBIST controller */
+	systemREG1->MSINENA = 0x1U;							
+	
+	/* clear MSTGENA field */
+	systemREG1->MSTGCR &= ~(0xFU);						
+	
+	/* Enable PBIST self-test */
+	systemREG1->MSTGCR |= 0xAU;							
+	
+	/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }								
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+	
+	/* Enable PBIST clocks and ROM clock */
+	pbistREG->PACT = 0x3U;								
+	
+	/* Select algo#3, march13n to be run */
+	pbistREG->ALGO = 0x00000004U;						
+	
+	/* Select RAM Group 1, which is actually the PBIST ROM */
+	pbistREG->RINFOL = 0x1U;								
+	
+	/* ROM contents will not override ALGO and RINFOx settings */
+	pbistREG->OVER = 0x0U;								
+	
+	/* Algorithm code is loaded from ROM */
+	pbistREG->ROM = 0x3U;								
+	
+	/* Start PBIST */
+	pbistREG->DLR = 0x14U;								
+	
+	/* wait until memory self-test done is indicated */
+	while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U)
+	{ 
+	}/* Wait */ 				
+	
+	/* Check for the failure */
+	if (((pbistREG->FSRF0 & 0x1U) != 0x1U) & ((pbistREG->FSRF1 & 0x1U) != 0x1U))
+	{
+		/* no failure was indicated even if the march13n algorithm was run on a ROM */
+		pbistSelfCheckFail();
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+	}
+	else												
+	{
+	    /* PBIST self-check has passed */
+		
+		/* Disable PBIST clocks and ROM clock */
+		pbistREG->PACT = 0x0U;							
+		
+		/* Disable PBIST */
+		systemREG1->MSTGCR &= ~(0xFU);					
+		systemREG1->MSTGCR |= 0x5U;
+		
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+    }
+}
+
+/** @fn void pbistSelfCheckFail(void)
+*   @brief PBIST self test Driver failure service routine
+*
+*   This function is called on PBIST self test failure.
+*/
+void pbistSelfCheckFail(void)
+{
+	/* The PBIST controller is not capable of reporting a failure.
+	 * PBIST cannot be used to verify memory integrity.
+	 * Need custom handler here.
+	 */
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+}
+
+/** @fn void pbistRun(uint32 raminfoL, uint32 algomask)
+*   @brief CPU self test Driver
+*   @param[in] raminfoL   - Select the list of RAM to be tested.
+*   @param[in] algomask   - Select the list of Algorithm to be run.
+*
+*   This function performs Memory Built-in Self test using PBIST module.
+*/
+void pbistRun(uint32 raminfoL, uint32 algomask)
+{
+	volatile uint32 i = 0U;
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+	/* PBIST ROM clock frequency = HCLK frequency /2 */
+	systemREG1->MSTGCR |= 0x00000100U;					
+	
+	/* Enable PBIST controller */
+	systemREG1->MSINENA = 0x1U;							 
+	
+	/* clear MSTGENA field */
+	systemREG1->MSTGCR &= ~(0xFU);						 
+	
+	/* Enable PBIST self-test */
+	systemREG1->MSTGCR |= 0xAU;							 
+	
+	/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }							 
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+	
+	/* Enable PBIST clocks and ROM clock */
+	pbistREG->PACT = 0x3U;								 
+	
+	/* Select all algorithms to be tested */
+	pbistREG->ALGO = algomask;						     
+	
+	/* Select RAM groups */
+	pbistREG->RINFOL = raminfoL;						 
+	
+	/* Select all RAM groups */
+	pbistREG->RINFOU = 0x00000000U;						
+	
+	/* ROM contents will not override RINFOx settings */
+	pbistREG->OVER = 0x0U;								 
+	
+	/* Algorithm code is loaded from ROM */
+	pbistREG->ROM = 0x3U;								 
+	
+	/* Start PBIST */
+	pbistREG->DLR = 0x14U;								 
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+}
+
+/** @fn void pbistStop(void)
+*   @brief Routine to stop PBIST test enabled.
+*
+*   This function is called to stop PBIST after test is performed.
+*/
+void pbistStop(void)
+{
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+    /* disable pbist clocks and ROM clock */
+	pbistREG->PACT = 0x0U;							
+	systemREG1->MSTGCR &= ~(0xFU);
+	systemREG1->MSTGCR |= 0x5U;
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+
+/** @fn boolean pbistIsTestCompleted(void)
+*   @brief Checks to see if the PBIST test is completed.
+*   @return 1 if PBIST test completed, otherwise 0.
+*
+*   Checks to see if the PBIST test is completed.
+*/
+boolean pbistIsTestCompleted(void)
+{
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+	return ((systemREG1->MSTCGSTAT & 0x1U) != 0U);
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+/** @fn boolean pbistIsTestPassed(void)
+*   @brief Checks to see if the PBIST test is completed successfully.
+*   @return 1 if PBIST test passed, otherwise 0.
+*
+*   Checks to see if the PBIST test is completed successfully.
+*/
+boolean pbistIsTestPassed(void)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+	return (((pbistREG->FSRF0 ==0U) && (pbistREG->FSRF1 ==0U)) == TRUE);
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+/** @fn boolean pbistPortTestStatus(uint32 port)
+*   @brief Checks to see if the PBIST Port test is completed successfully.
+*   @param[in] port   - Select the port to get the status.
+*   @return 1 if PBIST Port test completed successfully, otherwise 0.
+*
+*   Checks to see if the selected PBIST Port test is completed successfully.
+*/
+boolean pbistPortTestStatus(uint32 port)
+{
+    boolean status;
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+    if(port == PBIST_PORT0)
+	{
+	  status =  ((boolean)pbistREG->FSRF0 == 0U);
+	}
+	else
+	{
+	  status =  ((boolean)pbistREG->FSRF1 == 0U);	
+	}
+	
+	return  status;
+}
+
+/** @fn void efcCheck(void)
+*   @brief EFUSE module self check Driver
+*
+*   This function self checks the EFSUE module.
+*/
+void efcCheck(void)
+{
+	uint32 efcStatus = 0U;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+	
+	/* read the EFC Error Status Register */
+	efcStatus = efcREG->ERROR;						
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+	
+	if (efcStatus == 0x0U)
+	{
+	    /* run stuck-at-zero test and check if it passed */
+		if (efcStuckZeroTest()== TRUE)						
+		{
+		    /* start EFC ECC logic self-test */
+			efcSelfTest();							
+		}
+		else
+		{
+		    /* EFC output is stuck-at-zero, device operation unreliable */
+			efcClass2Error();						
+		}
+	}
+	/* EFC Error Register is not zero */
+	else											
+	{
+		/* one-bit error detected during autoload */
+		if (efcStatus == 0x15U)						
+		{
+		    /* start EFC ECC logic self-test */
+			efcSelfTest();							
+		}
+		else
+		{
+		    /* Some other EFC error was detected */
+		    efcClass2Error();					
+		}
+	}
+}
+
+/** @fn boolean efcStuckZeroTest(void)
+*   @brief Checks to see if the EFUSE Stuck at zero test is completed successfully.
+*   @return 1 if EFUSE Stuck at zero test completed, otherwise 0.
+*
+*   Checks to see if the EFUSE Stuck at zero test is completed successfully.
+*/
+boolean efcStuckZeroTest(void)
+{
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+	boolean result = FALSE;
+  	uint32 error_checks = EFC_INSTRUCTION_INFO_EN  | 
+							  	EFC_INSTRUCTION_ERROR_EN | 
+							  	EFC_AUTOLOAD_ERROR_EN 	 | 
+							  	EFC_SELF_TEST_ERROR_EN   ;
+	
+	/* configure the output enable for auto load error , instruction info,
+  	   instruction error, and self test error using boundary register 
+  	   and drive values one across all the errors */
+  	efcREG->BOUNDARY = (OUTPUT_ENABLE | error_checks);
+  	
+	/* Read from the pin register. This register holds the current values 
+  	   of above errors. This value should be 0x5c00.If not at least one of
+  	   the above errors is stuck at 0. */
+	if ((efcREG->PINS & 0x5C00U) == 0x5C00U)
+	{
+		/* check if the ESM group1 channels 40 is set and group3 channel 2 is set */
+		if (((esmREG->ESTATUS4[0U] & 0x200U) == 0x200U) & ((esmREG->ESTATUS1[2U] & 0x2U) == 0x2U))
+		{
+           /* stuck-at-zero test passed */
+		   result = TRUE;									
+		}
+	}
+	
+	/* put the pins back low */
+	efcREG->BOUNDARY = OUTPUT_ENABLE;
+	
+	/* clear group1 flags */
+	esmREG->ESTATUS4[0U] = 0x300U;
+	
+	/* clear group3 flag */
+	esmREG->ESTATUS1[2U] = 0x2U;					
+	
+	/* The nERROR pin will become inactive once the LTC counter expires */
+	esmREG->KEY = 0x5U;							
+
+	return result;
+}
+
+/** @fn void efcSelfTest(void)
+*   @brief EFUSE module self check Driver
+*
+*   This function self checks the EFSUE module.
+*/
+void efcSelfTest(void)
+{
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+	/* configure self-test cycles */
+	efcREG->SELF_TEST_CYCLES = 0x258U;
+	
+	/* configure self-test signature */
+	efcREG->SELF_TEST_SIGN = 0x5362F97FU;
+	
+	/* configure boundary register to start ECC self-test */
+	efcREG->BOUNDARY = 0x0000200FU;
+}
+
+/** @fn boolean checkefcSelfTest(void)
+*   @brief EFUSE module self check Driver
+*
+*   This function self checks the EFSUE module.
+*/
+boolean checkefcSelfTest(void)
+{
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+	boolean result = FALSE;
+	
+	/* wait until EFC self-test is done */
+	while((!(efcREG->PINS & EFC_SELF_TEST_DONE)) != 0U)
+	{ 
+	}/* Wait */ 		
+	
+	/* check if EFC self-test error occurred */
+	if (((!(efcREG->PINS & EFC_SELF_TEST_ERROR)) & (!(efcREG->ERROR & SELF_TEST_ERROR))) !=0U)
+	{
+		/* check if EFC self-test error is set */
+		if ((esmREG->ESTATUS4[0U] & 0x100U) != 0x100U)		
+		{
+			result = TRUE;
+		}
+	}
+	return result;
+}
+
+/** @fn void efcClass1Error(void)
+*   @brief EFUSE Class1 Error service routine
+*
+*   This function is called if EFC ECC logic self-test.
+*/
+void efcClass1Error(void)
+{
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+	/* Autoload error was detected during device power-up, and device operation is not reliable. */
+	/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+}
+
+/** @fn void efcClass2Error(void)
+*   @brief EFUSE Class2 Error service routine
+*
+*   This function is called if EFC output is stuck-at-zero.
+*/
+void efcClass2Error(void)
+{
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+	/* The ECC logic inside the eFuse controller is not operational. Device operation is not reliable. */
+	/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+}
+
+/** @fn void fmcBus2Check(void)
+*   @brief Self Check Flash Bus2 Interface
+*
+*   This function self checks Flash Bus2 Interface
+*/
+void fmcBus2Check(void)
+{
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+    /* enable ECC logic inside FMC */
+	flashWREG->FEDACCTRL1 = 0x000A060AU;		
+
+	if ((esmREG->ESTATUS1[0U] & 0x40U) == 0x40U)
+	{
+		/* a 1-bit error was detected during flash OTP read by flash module
+		   run a self-check on ECC logic inside FMC */
+		
+		/* clear ESM group1 channel 6 flag */
+		esmREG->ESTATUS1[0U] = 0x40U;	
+		
+		fmcECCcheck();
+	}
+	
+	/* no 2-bit or 1-bit error detected during power-up */
+	else										
+	{
+		fmcECCcheck();
+	}
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+}
+
+/** @fn void fmcECCcheck(void)
+*   @brief Check Flash ECC Single Bit and multi Bit errors detection logic.
+*
+*   This function Checks Flash ECC Single Bit and multi Bit errors detection logic.
+*/
+void fmcECCcheck(void)
+{
+	volatile uint32 otpread;
+	volatile uint32 temp;
+
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+
+	/* read location with deliberate 1-bit error */
+	otpread = flash1bitError;				
+	if ((esmREG->ESTATUS1[0U] & 0x40U) == 0x40U)
+	{
+		/* 1-bit failure was indicated and corrected */
+		flashWREG->FEDACSTATUS = 0x00010006U;
+		
+		/* clear ESM group1 channel 6 flag */
+		esmREG->ESTATUS1[0U] = 0x40U;			
+		
+        /* read location with deliberate 2-bit error */
+		otpread = flash2bitError;			
+		if ((esmREG->ESTATUS1[2U] & 0x80U) == 0x80U)
+		{
+			/* 2-bit failure was detected correctly */
+			temp = flashWREG->FUNCERRADD;
+			flashWREG->FEDACSTATUS = 0x00020100U;
+			
+			/* clear ESM group3 channel 7 */
+			esmREG->ESTATUS1[2U] = 0x80U;		
+			
+			/* The nERROR pin will become inactive once the LTC counter expires */
+			esmREG->KEY = 0x5U;				
+
+		}
+		else
+		{
+		    /* ECC logic inside FMC cannot detect 2-bit error */
+			fmcClass2Error();				
+		}
+	}
+	else
+	{
+	    /* ECC logic inside FMC cannot detect 1-bit error */
+		fmcClass2Error();					
+	}
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+}
+
+/** @fn void fmcClass1Error(void)
+*   @brief Flash Multi bit ECC error service routine detected during reset configuration.
+*
+*   This function is called if Flash Multi bit ECC error detected during reset configuration.
+*/
+void fmcClass1Error(void)
+{
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+	/* there was a multi-bit error detected during the reset configuration word read from the OTP */
+	/* This affects the device power domains, endianness, and exception handling ISA */
+	/* Device operation is not reliable. */
+    /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+}
+
+/** @fn void fmcClass2Error(void)
+*   @brief Flash OTP or EEPROM read Multi bit ECC error service routine
+*
+*   This function is called if Flash OTP or EEPROM read Multi bit ECC error detected.
+*/
+void fmcClass2Error(void)
+{
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+	/* The ECC logic inside FMC used to protect against 1-bit and 2-bit errors in OTP and EEPROM banks */
+	/* is not operational. Device operation is not reliable. */
+	/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+}
+
+/** @fn void checkB0RAMECC(void)
+*   @brief Check TCRAM1 ECC error detection logic.
+*
+*   This function checks TCRAM1 ECC error detection logic.
+*/
+void checkB0RAMECC(void)
+{
+	volatile uint32 ramread = 0U;
+    volatile uint32 i;
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+
+	/* enable writes to ECC RAM, enable ECC error response */
+	tcram1REG->RAMCTRL = 0x0005010AU;			
+	tcram2REG->RAMCTRL = 0x0005010AU;
+
+	/* the first 1-bit error will cause an error response */
+	tcram1REG->RAMTHRESHOLD = 0x1U;				
+	tcram2REG->RAMTHRESHOLD = 0x1U;
+
+	/* allow SERR to be reported to ESM */
+	tcram1REG->RAMINTCTRL = 0x1U;				
+	tcram2REG->RAMINTCTRL = 0x1U;
+    
+	/* cause a 1-bit ECC error */
+	tcramA1bitError ^= 0x1U;		
+	
+	/* disable writes to ECC RAM */
+	tcram1REG->RAMCTRL = 0x0005000AU;			
+	tcram2REG->RAMCTRL = 0x0005000AU;
+
+	/* read from location with 1-bit ECC error */
+	ramread = tcramA1bit;		
+	
+	/* SERR not set in TCRAM1 or TCRAM2 modules */
+	if ((!(((tcram1REG->RAMERRSTATUS & 1U) == 1U) || ((tcram2REG->RAMERRSTATUS & 1U) == 1U))) !=0U)	
+	{
+		/* TCRAM module does not reflect 1-bit error reported by CPU */
+		tcramClass2Error();						
+	}
+	else
+	{
+	    /* clear SERR flag */
+		tcram1REG->RAMERRSTATUS = 0x1U;			
+		tcram2REG->RAMERRSTATUS = 0x1U;
+		
+		/* clear status flags for ESM group1 channels 26 and 28 */
+		esmREG->ESTATUS1[0U] = 0x14000000U;		
+	}
+
+	/* enable writes to ECC RAM, enable ECC error response */
+	tcram1REG->RAMCTRL = 0x0005010AU;			
+	tcram2REG->RAMCTRL = 0x0005010AU;
+
+	/* cause a 2-bit ECC error */
+	tcramA2bitError ^= 0x3U;						
+	ramread = tcram1REG->RAMCTRL;
+	ramread = tcram2REG->RAMCTRL;
+
+	/* read from location with 2-bit ECC error this will cause a data abort to be generated */
+	ramread = tcramA2bit;
+
+    /* delay before restoring the ram value */
+	for(i=0U;i<10U;i++)
+	{ 
+	}/* Wait */ 		   
+
+	/* disable RAM ECC Support */
+	_coreDisableRamEcc_();	
+	
+	/* enable writes to ECC RAM, enable ECC error response */
+	tcram1REG->RAMCTRL = 0x0005010AU;			
+	tcram2REG->RAMCTRL = 0x0005010AU;
+
+	/* revert back the flipped bits */
+	tcramA1bitError ^= 0x1U;	    
+	tcramA2bitError ^= 0x3U;						
+	
+	/* disable writes to ECC RAM */
+	tcram1REG->RAMCTRL = 0x0005000AU;			
+	tcram2REG->RAMCTRL = 0x0005000AU;
+
+	/* enable RAM ECC Support */
+	_coreEnableRamEcc_();
+	
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+}
+
+/** @fn void checkB1RAMECC(void)
+*   @brief Check TCRAM2 ECC error detection logic.
+*
+*   This function checks TCRAM2 ECC error detection logic.
+*/
+void checkB1RAMECC(void)
+{
+	volatile uint32 ramread = 0U;
+	volatile uint32 i;
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+	/* enable writes to ECC RAM, enable ECC error response */
+	tcram1REG->RAMCTRL = 0x0005010AU;			
+	tcram2REG->RAMCTRL = 0x0005010AU;
+    
+	/* the first 1-bit error will cause an error response */
+	tcram1REG->RAMTHRESHOLD = 0x1U;				
+	tcram2REG->RAMTHRESHOLD = 0x1U;
+
+	/* allow SERR to be reported to ESM */
+	tcram1REG->RAMINTCTRL = 0x1U;				 
+	tcram2REG->RAMINTCTRL = 0x1U;
+
+	/* cause a 1-bit ECC error */
+	tcramB1bitError ^= 0x1U;						 
+	
+	/* disable writes to ECC RAM */
+	tcram1REG->RAMCTRL = 0x0005000AU;			 
+	tcram2REG->RAMCTRL = 0x0005000AU;
+
+	/* read from location with 1-bit ECC error */
+	ramread = tcramB1bit;						 
+	
+	/* SERR not set in TCRAM1 or TCRAM2 modules */
+	if ((!(((tcram1REG->RAMERRSTATUS & 1U) == 1U) || ((tcram2REG->RAMERRSTATUS & 1U) == 1U))) !=0U)	
+	{
+		/* TCRAM module does not reflect 1-bit error reported by CPU */
+		tcramClass2Error();						
+	}
+	else
+	{
+		/* clear SERR flag */
+		tcram1REG->RAMERRSTATUS = 0x1U;			 
+		tcram2REG->RAMERRSTATUS = 0x1U;
+		
+		/* clear status flags for ESM group1 channels 26 and 28 */
+		esmREG->ESTATUS1[0U] = 0x14000000U;		 
+	}
+
+	/* enable writes to ECC RAM, enable ECC error response */
+	tcram1REG->RAMCTRL = 0x0005010AU;			 
+	tcram2REG->RAMCTRL = 0x0005010AU;
+	
+	/* cause a 2-bit ECC error */
+	tcramB2bitError ^= 0x3U;						 
+	
+	/* disable writes to ECC RAM */
+	tcram1REG->RAMCTRL = 0x0005000AU;			 
+	tcram2REG->RAMCTRL = 0x0005000AU;
+	
+    /* delay before restoring the ram value */
+	for(i=0U;i<10U;i++)
+	{ 
+	}/* Wait */ 		   
+
+	/* disable RAM ECC Support */
+	_coreDisableRamEcc_();	
+
+    /* enable writes to ECC RAM, enable ECC error response */
+	tcram1REG->RAMCTRL = 0x0005010AU;			 
+	tcram2REG->RAMCTRL = 0x0005010AU;
+
+	/* revert back the flipped bits */
+	tcramB1bitError ^= 0x1U;	    
+	tcramB2bitError ^= 0x3U;						
+	
+	/* disable writes to ECC RAM */
+	tcram1REG->RAMCTRL = 0x0005000AU;			 
+	tcram2REG->RAMCTRL = 0x0005000AU;
+
+	/* enable RAM ECC Support */
+	_coreEnableRamEcc_();	
+
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+}
+
+/** @fn void tcramClass1Error(void)
+*   @brief Error service routine called if TCRAM module cannot capture 2-bit error.
+*
+*   Error service routine called if TCRAM module cannot respond to 2-bit error.
+*/
+void tcramClass1Error(void)
+{
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+	/* TCRAM module is not capable of responding to 2-bit error indicated by CPU.
+	 * Device operation is not reliable and not recommended.
+	 */
+	/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ 
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+}
+
+/** @fn void tcramClass2Error(void)
+*   @brief Error service routine called if TCRAM module cannot capture 1-bit error.
+*
+*   Error service routine called if TCRAM module cannot respond to 1-bit error.
+*/
+void tcramClass2Error(void)
+{
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
+	/* TCRAM module is not capable of responding to 1-bit error indicated by CPU.
+	 * Device operation is possible, but is prone to future multi-bit errors not being detected.
+	 * Need custom handler here instead of the infinite loop.
+	 */
+	 /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+	 
+/* USER CODE BEGIN (62) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (63) */
+/* USER CODE END */
+}
+
+/** @fn void checkFlashECC(void)
+*   @brief Check Flash ECC error detection logic.
+*
+*   This function checks Flash ECC error detection logic.
+*/
+void checkFlashECC(void)
+{
+	/* Routine to check operation of ECC logic inside CPU for accesses to program flash */
+	volatile uint32 flashread = 0U;
+
+/* USER CODE BEGIN (64) */
+/* USER CODE END */
+	
+	/* Flash Module ECC Response enabled */
+	flashWREG->FEDACCTRL1 = 0x000A060AU;			
+    
+	/* Enable diagnostic mode and select diag mode 7 */
+	flashWREG->FDIAGCTRL = 0x00050007U;			
+	
+	/* Select ECC diagnostic mode, single-bit to be corrupted */
+	flashWREG->FPAROVR = 0x00005A01U;			
+	
+	/* Set the trigger for the diagnostic mode */
+	flashWREG->FDIAGCTRL |= 0x01000000U;			
+    
+	/* read a flash location from the mirrored memory map */
+	flashread = flashBadECC;	
+	
+	/* disable diagnostic mode */
+	flashWREG->FDIAGCTRL = 0x000A0007U;			
+
+	/* this will have caused a single-bit error to be generated and corrected by CPU */
+	/* single-bit error not captured in flash module */
+	if ((!(flashWREG->FEDACSTATUS & 0x2U)) !=0U)		
+	{
+		flashClass2Error();
+	}
+	else
+	{
+        /* clear single-bit error flag */
+		flashWREG->FEDACSTATUS = 0x2U;				
+
+		/* clear ESM flag */
+		esmREG->ESTATUS1[0U] = 0x40U;					
+
+		/* Enable diagnostic mode and select diag mode 7 */
+		flashWREG->FDIAGCTRL = 0x00050007U;			
+		
+		/* Select ECC diagnostic mode, two bits of ECC to be corrupted */
+		flashWREG->FPAROVR = 0x00005A03U;			
+		
+		/* Set the trigger for the diagnostic mode */
+		flashWREG->FDIAGCTRL |= 0x01000000U;			
+
+		/* read from flash location from mirrored memory map this will cause a data abort */
+		flashread = flashBadECC;
+
+		/* disable diagnostic mode */
+		flashWREG->FDIAGCTRL = 0x000A0007U;			
+	}
+
+/* USER CODE BEGIN (65) */
+/* USER CODE END */
+}
+
+/** @fn void flashClass1Error(void)
+*   @brief Error service routine called if Flash module cannot capture 2-bit error.
+*
+*   Error service routine called if Flash module cannot capture 2-bit error.
+*/
+void flashClass1Error(void)
+{
+/* USER CODE BEGIN (66) */
+/* USER CODE END */
+	/* Flash module not able to capture 2-bit error from CPU.
+	 * Device operation not reliable.
+	 */
+	/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (67) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (68) */
+/* USER CODE END */
+
+}
+
+/** @fn void flashClass2Error(void)
+*   @brief Error service routine called if Flash module cannot capture 1-bit error.
+*
+*   Error service routine called if Flash module cannot capture 1-bit error.
+*/
+void flashClass2Error(void)
+{
+	/* Flash module not able to capture 1-bit error from CPU.
+	 * Device operation possible if this weakness in diagnostic is okay.
+	 */
+/* USER CODE BEGIN (69) */
+/* USER CODE END */
+}
+
+/** @fn void custom_dabort(void)
+*   @brief Custom Data abort routine for the application.
+*
+*   Custom Data abort routine for the application.
+*/
+void custom_dabort(void)
+{
+	/* Need custom data abort handler here.
+	 * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC logic.
+	 */
+/* USER CODE BEGIN (70) */
+/* USER CODE END */
+}
+
+/** @fn void stcSelfCheckFail(void)
+*   @brief STC Self test check fail service routine
+*
+*   This function is called if STC Self test check fail.
+*/
+void stcSelfCheckFail(void)
+{
+/* USER CODE BEGIN (71) */
+/* USER CODE END */
+	/* CPU self-test controller's own self-test failed.
+	 * It is not possible to verify that STC is capable of indicating a CPU self-test error.
+	 * It is not recommended to continue operation.
+	 */
+	 
+	/* User can add small piece of code to take system to Safe state using user code section.
+	 * Note: Just removing the for(;;) will take the system to unknown state under ST failure,
+     * since it is not handled by HALCogen driver */
+/* USER CODE BEGIN (72) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (73) */
+/* USER CODE END */
+}
+
+/** @fn void cpuSelfTestFail(void)
+*   @brief CPU Self test check fail service routine
+*
+*   This function is called if CPU Self test check fail.
+*/
+void cpuSelfTestFail(void)
+{
+/* USER CODE BEGIN (74) */
+/* USER CODE END */
+	/* CPU self-test has failed.
+	 * CPU operation is not reliable.
+	 */
+	/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (75) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (76) */
+/* USER CODE END */
+}
+
+
+/** @fn void vimParityCheck(void)
+*   @brief Routine to check VIM RAM parity error detection and signaling mechanism
+*
+*   Routine to check VIM RAM parity error detection and signaling mechanism
+*/
+void vimParityCheck(void)
+{
+	volatile uint32 vimramread = 0U;
+
+/* USER CODE BEGIN (77) */
+/* USER CODE END */
+	
+	/* Enable parity checking and parity test mode */
+	VIM_PARCTL = 0x0000010AU;
+	
+	/* flip a bit in the VIM RAM parity location */
+	VIMRAMPARLOC ^= 0x1U;					
+	
+	/* disable parity test mode */
+	VIM_PARCTL = 0x0000000AU;				
+
+	/* cause parity error */
+	vimramread = VIMRAMLOC;					
+   
+    /* check if ESM group1 channel 15 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x8000U))	!=0U)
+	{
+		/* VIM RAM parity error was not flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop. */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (78) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (79) */
+/* USER CODE END */
+
+	}
+	else
+	{
+	    /* clear VIM RAM parity error flag in VIM */
+		VIM_PARFLG = 0x1U;					
+		
+		/* clear ESM group1 channel 15 flag */
+		esmREG->ESTATUS1[0U] = 0x8000U;		
+		
+		/* Enable parity checking and parity test mode */
+		VIM_PARCTL = 0x0000010AU;
+	
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		VIMRAMPARLOC ^= 0x1U;					
+	
+		/* disable parity test mode */
+		VIM_PARCTL = 0x0000000AU;		
+	}
+/* USER CODE BEGIN (80) */
+/* USER CODE END */
+}
+
+/** @fn void dmaParityCheck(void)
+*   @brief Routine to check DMA control packet RAM parity error detection and signaling mechanism
+*
+*   Routine to check DMA control packet RAM parity error detection and signaling mechanism
+*/
+void dmaParityCheck(void)
+{
+	volatile uint32 dmaread = 0U;
+
+/* USER CODE BEGIN (81) */
+/* USER CODE END */
+	
+	/* Enable parity checking and parity test mode */
+	DMA_PARCR = 0x0000010AU;			
+	
+	/* Flip a bit in DMA RAM parity location */
+	DMARAMPARLOC ^= 0x1U;					
+	
+	/* Disable parity test mode */
+	DMA_PARCR = 0x0000000AU;					
+    
+	/* Cause parity error */
+	dmaread = DMARAMLOC;					
+    
+	/* Check if ESM group1 channel 3 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x8U)) != 0U)		
+	{
+		/* DMA RAM parity error was not flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop. */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (82) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (83) */
+/* USER CODE END */
+	}
+	else
+	{
+		/* clear DMA parity error flag in DMA */
+		DMA_PARADDR = 0x01000000U;			
+		
+		/* clear ESM group1 channel 3 flag */
+		esmREG->ESTATUS1[0U] = 0x8U;	
+
+		/* Enable parity checking and parity test mode */
+		DMA_PARCR = 0x0000010AU;			
+	
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		DMARAMPARLOC ^= 0x1U;					
+	
+		/* Disable parity test mode */
+		DMA_PARCR = 0x0000000AU;		
+	}
+/* USER CODE BEGIN (84) */
+/* USER CODE END */
+}
+
+/** @fn void het1ParityCheck(void)
+*   @brief Routine to check HET1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check HET1 RAM parity error detection and signaling mechanism
+*/
+void het1ParityCheck(void)
+{
+	volatile uint32 nhetread = 0U;
+
+/* USER CODE BEGIN (85) */
+/* USER CODE END */
+	
+	/* Set TEST mode and enable parity checking */
+	hetREG1->PCR = 0x0000010AU;			
+	
+	/* flip parity bit */
+	NHET1RAMPARLOC ^= 0x1U;					
+	
+	/* Disable TEST mode */
+	hetREG1->PCR = 0x0000000AU;			
+
+	/* read to cause parity error */
+	nhetread = NHET1RAMLOC;					
+
+	/* check if ESM group1 channel 7 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x80U)) !=0U)
+	{
+		/* NHET1 RAM parity error was not flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop. */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (86) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (87) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear ESM group1 channel 7 flag */
+		esmREG->ESTATUS1[0U] = 0x80U;	
+
+		/* Set TEST mode and enable parity checking */
+		hetREG1->PCR = 0x0000010AU;			
+	
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		NHET1RAMPARLOC ^= 0x1U;					
+	
+		/* Disable TEST mode */
+		hetREG1->PCR = 0x0000000AU;			
+	}
+/* USER CODE BEGIN (88) */
+/* USER CODE END */
+}
+
+/** @fn void htu1ParityCheck(void)
+*   @brief Routine to check HTU1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check HTU1 RAM parity error detection and signaling mechanism
+*/
+void htu1ParityCheck(void)
+{
+	volatile uint32 hturead = 0U;
+
+/* USER CODE BEGIN (89) */
+/* USER CODE END */
+
+    /* Enable parity and TEST mode */
+	htuREG1->PCR = 0x0000010AU;	
+	
+	/* flip parity bit */	
+	HTU1PARLOC ^= 0x1U;			
+	
+	/* Disable parity RAM test mode */
+	htuREG1->PCR = 0x0000000AU;	
+	
+	/* read to cause parity error */
+	hturead = HTU1RAMLOC;		
+   
+    /* check if ESM group1 channel 8 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x100U)) != 0U)		 
+	{
+		/* HTU1 RAM parity error was not flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop. */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (90) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (91) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* Clear HTU parity error flag */
+		htuREG1->PAR = 0x00010000U;			
+		esmREG->ESTATUS1[0U] = 0x100U;
+
+		/* Enable parity and TEST mode */
+		htuREG1->PCR = 0x0000010AU;	
+	
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		HTU1PARLOC ^= 0x1U;			
+	
+		/* Disable parity RAM test mode */
+		htuREG1->PCR = 0x0000000AU;	
+		
+	}
+
+/* USER CODE BEGIN (92) */
+/* USER CODE END */
+
+}
+
+/** @fn void het2ParityCheck(void)
+*   @brief Routine to check HET2 RAM parity error detection and signaling mechanism
+*
+*   Routine to check HET2 RAM parity error detection and signaling mechanism
+*/
+void het2ParityCheck(void)
+{
+	volatile uint32 nhetread = 0U;
+
+/* USER CODE BEGIN (93) */
+/* USER CODE END */
+    
+	/* Set TEST mode and enable parity checking */
+	hetREG2->PCR = 0x0000010AU;			
+	
+	/* flip parity bit */
+	NHET2RAMPARLOC ^= 0x1U;					
+	
+	/* Disable TEST mode */
+	hetREG2->PCR = 0x0000000AU;			
+
+	/* read to cause parity error */
+	nhetread = NHET2RAMLOC;					
+
+	/* check if ESM group1 channel 7 or 34 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x80U) != 0U) && (!(esmREG->ESTATUS4[0U] & 0x4U) !=0U))		
+	{
+		/* NHET2 RAM parity error was not flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop. */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (94) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (95) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear ESM group1 channel 7 flag */
+		esmREG->ESTATUS1[0U] = 0x80U;			
+		
+		/* clear ESM group1 channel 34 flag */
+		esmREG->ESTATUS4[0U] = 0x4U;	
+
+		/* Set TEST mode and enable parity checking */
+		hetREG2->PCR = 0x0000010AU;			
+	
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		NHET2RAMPARLOC ^= 0x1U;					
+	
+		/* Disable TEST mode */
+		hetREG2->PCR = 0x0000000AU;			
+	}
+	
+/* USER CODE BEGIN (96) */
+/* USER CODE END */
+}
+
+/** @fn void htu2ParityCheck(void)
+*   @brief Routine to check HTU2 RAM parity error detection and signaling mechanism
+*
+*   Routine to check HTU2 RAM parity error detection and signaling mechanism
+*/
+void htu2ParityCheck(void)
+{
+	volatile uint32 hturead = 0U;
+
+/* USER CODE BEGIN (97) */
+/* USER CODE END */
+	
+	/* Enable parity and TEST mode */
+	htuREG2->PCR = 0x0000010AU;		
+	
+	/* flip parity bit */
+	HTU2PARLOC ^= 0x1U;						
+	
+	/* Disable parity RAM test mode */
+	htuREG2->PCR = 0x0000000AU;				
+
+	/* read to cause parity error */
+	hturead = HTU2RAMLOC;					
+
+	/* check if ESM group1 channel 8 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x100U)) != 0U)		
+	{
+		/* HTU2 RAM parity error was not flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop. */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (98) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (99) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* Clear HTU parity error flag */
+		htuREG2->PAR = 0x00010000U;			
+		esmREG->ESTATUS1[0U] = 0x100U;
+		
+		/* Enable parity and TEST mode */
+		htuREG2->PCR = 0x0000010AU;		
+	
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		HTU2PARLOC ^= 0x1U;						
+	
+		/* Disable parity RAM test mode */
+		htuREG2->PCR = 0x0000000AU;				
+	}
+	
+/* USER CODE BEGIN (100) */
+/* USER CODE END */
+}
+
+/** @fn void adc1ParityCheck(void)
+*   @brief Routine to check ADC1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check ADC1 RAM parity error detection and signaling mechanism
+*/
+void adc1ParityCheck(void)
+{
+	volatile uint32 adcramread = 0U;
+
+/* USER CODE BEGIN (101) */
+/* USER CODE END */
+	
+	/* Set the TEST bit in the PARCR and enable parity checking */
+	adcREG1->PARCR = 0x10AU;				
+	
+	/* Invert the parity bits inside the ADC1 RAM's first location */
+	adcPARRAM1 = ~(adcPARRAM1);				
+
+	/* clear the TEST bit */
+	adcREG1->PARCR = 0x00AU;				
+
+	/* This read is expected to trigger a parity error */
+	adcramread = adcRAM1;					
+
+	/* Check for ESM group1 channel 19 to be flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x80000U)) !=0U)	
+	{
+		/* no ADC1 RAM parity error was flagged to ESM */
+		/* Need custom routine to handle this failure instead of the infinite loop */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (102) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (103) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear ADC1 RAM parity error flag */
+		esmREG->ESTATUS1[0U] = 0x80000U;	
+
+		/* Set the TEST bit in the PARCR and enable parity checking */
+		adcREG1->PARCR = 0x10AU;				
+	
+		/* Revert back the parity bits to correct data */
+		adcPARRAM1 = ~(adcPARRAM1);				
+
+		/* clear the TEST bit */
+		adcREG1->PARCR = 0x00AU;			
+	}
+	
+/* USER CODE BEGIN (104) */
+/* USER CODE END */
+}
+
+/** @fn void adc2ParityCheck(void)
+*   @brief Routine to check ADC2 RAM parity error detection and signaling mechanism
+*
+*   Routine to check ADC2 RAM parity error detection and signaling mechanism
+*/
+void adc2ParityCheck(void)
+{
+	volatile uint32 adcramread = 0U;
+
+/* USER CODE BEGIN (105) */
+/* USER CODE END */
+	
+	/* Set the TEST bit in the PARCR and enable parity checking */
+	adcREG2->PARCR = 0x10AU;				
+	
+	/* Invert the parity bits inside the ADC2 RAM's first location */
+	adcPARRAM2 = ~(adcPARRAM2);				
+
+	/* clear the TEST bit */
+	adcREG2->PARCR = 0x00AU;				
+
+	/* This read is expected to trigger a parity error */
+	adcramread = adcRAM2;					
+
+	/* Check for ESM group1 channel 1 to be flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x2U)) != 0U)		
+	{
+		/* no ADC2 RAM parity error was flagged to ESM */
+		/* Need custom routine to handle this failure instead of the infinite loop */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (106) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (107) */
+/* USER CODE END */
+	}
+	else
+	{
+        /* clear ADC2 RAM parity error flag */	
+		esmREG->ESTATUS1[0U] = 0x2U;	
+
+		/* Set the TEST bit in the PARCR and enable parity checking */
+		adcREG2->PARCR = 0x10AU;				
+	
+		/* Revert back the parity bits to correct data */
+		adcPARRAM2 = ~(adcPARRAM2);				
+
+		/* clear the TEST bit */
+		adcREG2->PARCR = 0x00AU;			
+	}
+	
+/* USER CODE BEGIN (108) */
+/* USER CODE END */
+}
+
+/** @fn void can1ParityCheck(void)
+*   @brief Routine to check CAN1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check CAN1 RAM parity error detection and signaling mechanism
+*/
+void can1ParityCheck(void)
+{
+	volatile uint32 canread = 0U;
+
+/* USER CODE BEGIN (109) */
+/* USER CODE END */
+	
+	/* Disable parity, init mode, TEST mode */
+	canREG1->CTL = 0x00001481U;				
+	
+	/* Enable RAM Direct Access mode */
+	canREG1->TEST = 0x00000200U;			
+
+	/* flip the parity bit */
+	canPARRAM1 ^= 0x00001000U;				
+
+	/* Enable parity, disable init, still TEST mode */
+	canREG1->CTL = 0x00002880U;				
+
+	/* Read location with parity error */
+	canread = canRAM1;					
+
+	/* check if ESM group1 channel 21 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x00200000U))	!= 0U)
+	{
+		/* No DCAN1 RAM parity error was flagged to ESM */
+		/* Need custom routine to handle this failure instead of the infinite loop */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (110) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (111) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear ESM group1 channel 21 flag */
+		esmREG->ESTATUS1[0U] = 0x00200000U;	
+		
+		/* Disable parity, init mode, TEST mode */
+		canREG1->CTL = 0x00001481U;
+
+		/* Enable RAM Direct Access mode */
+		canREG1->TEST = 0x00000200U;
+
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		canPARRAM1 ^= 0x00001000U;
+		
+		/* disable TEST mode */
+		canREG1->CTL = 0x00002800U;			
+	}
+	
+/* USER CODE BEGIN (112) */
+/* USER CODE END */
+}
+
+/** @fn void can2ParityCheck(void)
+*   @brief Routine to check CAN2 RAM parity error detection and signaling mechanism
+*
+*   Routine to check CAN2 RAM parity error detection and signaling mechanism
+*/
+void can2ParityCheck(void)
+{
+	volatile uint32 canread = 0U;
+
+/* USER CODE BEGIN (113) */
+/* USER CODE END */
+	
+	/* Disable parity, init mode, TEST mode */
+	canREG2->CTL = 0x00001481U;			
+
+	/* Enable RAM Direct Access mode */	
+	canREG2->TEST = 0x00000200U;			
+
+	/* flip the parity bit */
+	canPARRAM2 ^= 0x00001000U;				
+
+	/* Enable parity, disable init, still TEST mode */
+	canREG2->CTL = 0x00002880U;				
+
+	/* Read location with parity error */
+	canread = canRAM2;					
+	
+	/* check if ESM group1 channel 23 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x00800000U)) != 0U)	
+	{
+		/* No DCAN2 RAM parity error was flagged to ESM */
+		/* Need custom routine to handle this failure instead of the infinite loop */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (114) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (115) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear ESM group1 channel 23 flag */
+		esmREG->ESTATUS1[0U] = 0x00800000U;	
+
+		/* Disable parity, init mode, TEST mode */
+		canREG2->CTL = 0x00001481U;			
+
+		/* Enable RAM Direct Access mode */	
+		canREG2->TEST = 0x00000200U;			
+
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		canPARRAM2 ^= 0x00001000U;				
+		
+		/* disable TEST mode */
+		canREG2->CTL = 0x00002800U;			
+	}
+	
+/* USER CODE BEGIN (116) */
+/* USER CODE END */
+}
+
+/** @fn void can3ParityCheck(void)
+*   @brief Routine to check CAN3 RAM parity error detection and signaling mechanism
+*
+*   Routine to check CAN3 RAM parity error detection and signaling mechanism
+*/
+void can3ParityCheck(void)
+{
+	volatile uint32 canread = 0U;
+
+/* USER CODE BEGIN (117) */
+/* USER CODE END */
+	
+	/* Disable parity, init mode, TEST mode */
+	canREG3->CTL = 0x00001481U;			
+
+    /* Enable RAM Direct Access mode */	
+	canREG3->TEST = 0x00000200U;			
+
+	/* flip the parity bit */
+	canPARRAM3 ^= 0x00001000U;				
+
+	/* Enable parity, disable init, still TEST mode */
+	canREG3->CTL = 0x00002880U;				
+
+	/* Read location with parity error */
+	canread = canRAM3;					
+
+	/* check if ESM group1 channel 22 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x00400000U)) != 0U)	
+	{
+		/* No DCAN3 RAM parity error was flagged to ESM */
+		/* Need custom routine to handle this failure instead of the infinite loop */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (118) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (119) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear ESM group1 channel 22 flag */
+		esmREG->ESTATUS1[0U] = 0x00400000U;	
+
+		/* Disable parity, init mode, TEST mode */
+		canREG3->CTL = 0x00001481U;			
+
+		/* Enable RAM Direct Access mode */	
+		canREG3->TEST = 0x00000200U;			
+
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		canPARRAM3 ^= 0x00001000U;				
+		
+		/* disable TEST mode */
+		canREG3->CTL = 0x00002800U;			
+	}
+	
+/* USER CODE BEGIN (120) */
+/* USER CODE END */
+}
+
+/** @fn void mibspi1ParityCheck(void)
+*   @brief Routine to check MIBSPI1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check MIBSPI1 RAM parity error detection and signaling mechanism
+*/
+void mibspi1ParityCheck(void)
+{
+	volatile uint32 spiread = 0U;
+
+/* USER CODE BEGIN (121) */
+/* USER CODE END */
+
+	/* enable multi-buffered mode */
+	mibspiREG1->MIBSPIE = 0x1U;				
+
+	/* enable parity error detection */
+    mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0xAU);
+	
+	/* enable parity test mode */
+	mibspiREG1->UERRCTRL |= 1U << 8U;				
+	
+	/* flip bit 0 of the parity location */
+	mibspiPARRAM1 ^= 0x1U;					
+
+	/* disable parity test mode */
+	mibspiREG1->UERRCTRL &= ~(1U << 8U);				
+
+	/* read from MibSPI1 RAM to cause parity error */
+	spiread = *(uint32 *) mibspiRAM1;	
+
+	/* check if ESM group1 channel 17 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x20000U))	!= 0U)
+	{
+		/* No MibSPI1 RAM parity error was flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (122) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (123) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear parity error flags */
+		mibspiREG1->UERRSTAT = 0x3U;			
+		
+		/* clear ESM group1 channel 17 flag */
+		esmREG->ESTATUS1[0U] = 0x20000U;		
+		
+		/* enable parity test mode */
+	    mibspiREG1->UERRCTRL |= 1U << 8U;			
+		
+		/* Revert back to correct data, flip bit 0 of the parity location */
+	    mibspiPARRAM1 ^= 0x1U;				
+		
+		/* disable parity test mode */
+	    mibspiREG1->UERRCTRL &= ~(1U << 8U);	
+
+    	/* revert multi-buffered mode */
+	    mibspiREG1->MIBSPIE = 0x0U;			
+	}
+
+/* USER CODE BEGIN (124) */
+/* USER CODE END */
+}
+
+/** @fn void mibspi3ParityCheck(void)
+*   @brief Routine to check MIBSPI3 RAM parity error detection and signaling mechanism
+*
+*   Routine to check MIBSPI3 RAM parity error detection and signaling mechanism
+*/
+void mibspi3ParityCheck(void)
+{
+	volatile uint32 spiread = 0U;
+
+/* USER CODE BEGIN (125) */
+/* USER CODE END */
+	
+	/* enable multi-buffered mode */
+	mibspiREG3->MIBSPIE = 0x1U;				
+
+	/* enable parity test mode */
+	mibspiREG3->UERRCTRL |= 1U << 8U;				
+	
+	/* flip bit 0 of the parity location */
+	mibspiPARRAM3 ^= 0x1U;					
+
+	/* enable parity error detection */
+    mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0xAU);
+	
+	/* disable parity test mode */
+	mibspiREG3->UERRCTRL &= ~(1U << 8U);				
+
+	/* read from MibSPI3 RAM to cause parity error */
+	spiread = *(uint32 *) mibspiRAM3;	
+
+	/* check if ESM group1 channel 18 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x40000U))	!= 0U)
+	{
+		/* No MibSPI3 RAM parity error was flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (126) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (127) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear parity error flags */
+		mibspiREG3->UERRSTAT = 0x3U;			
+		
+		/* clear ESM group1 channel 18 flag */
+		esmREG->ESTATUS1[0U] = 0x40000U;		
+		
+		/* enable parity test mode */
+	    mibspiREG3->UERRCTRL |= 1U << 8U;			
+		
+		/* Revert back to correct data, flip bit 0 of the parity location */
+	    mibspiPARRAM3 ^= 0x1U;				
+		
+		/* disable parity test mode */
+	    mibspiREG3->UERRCTRL &= ~(1U << 8U);	
+
+    	/* revert multi-buffered mode */
+	    mibspiREG3->MIBSPIE = 0x0U;			
+	}
+	
+/* USER CODE BEGIN (128) */
+/* USER CODE END */
+}
+
+/** @fn void mibspi5ParityCheck(void)
+*   @brief Routine to check MIBSPI5 RAM parity error detection and signaling mechanism
+*
+*   Routine to check MIBSPI5 RAM parity error detection and signaling mechanism
+*/
+void mibspi5ParityCheck(void)
+{
+	volatile uint32 spiread = 0U;
+
+/* USER CODE BEGIN (129) */
+/* USER CODE END */
+	
+	/* enable multi-buffered mode */
+	mibspiREG5->MIBSPIE = 0x1U;				
+
+	/* enable parity test mode */
+	mibspiREG5->UERRCTRL |= 1U << 8U;	
+    
+	/* flip bit 0 of the parity location */	
+	mibspiPARRAM5 ^= 0x1U;					
+
+	/* enable parity error detection */
+    mibspiREG5->UERRCTRL = (mibspiREG5->UERRCTRL & 0xFFFFFFF0U) | (0xAU);
+	
+	/* disable parity test mode */
+	mibspiREG5->UERRCTRL &= ~(1U << 8U);				
+
+	/* read from MibSPI5 RAM to cause parity error */
+	spiread = *(uint32 *) mibspiRAM5;	
+
+	/* check if ESM group1 channel 24 is flagged */
+	if ((!(esmREG->ESTATUS1[0U] & 0x01000000U)) != 0U)
+	{
+		/* No MibSPI5 RAM parity error was flagged to ESM. */
+		/* Need custom routine to handle this failure instead of the infinite loop */
+		/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (130) */
+/* USER CODE END */
+	for(;;)
+	{ 
+	}/* Wait */ 		
+/* USER CODE BEGIN (131) */
+/* USER CODE END */
+	}
+	else
+	{
+	    /* clear parity error flags */
+		mibspiREG5->UERRSTAT = 0x3U;			
+		
+		/* clear ESM group1 channel 24 flag */
+		esmREG->ESTATUS1[0U] = 0x01000000U;	
+		
+	    /* enable parity test mode */
+		mibspiREG5->UERRCTRL |= 1U << 8U;			
+	    
+		/* Revert back to correct data, flip bit 0 of the parity location */
+		mibspiPARRAM5 ^= 0x1U;				
+	    
+		/* disable parity test mode */
+		mibspiREG5->UERRCTRL &= ~(1U << 8U);	
+
+    	/* revert multi-buffered mode */
+	    mibspiREG5->MIBSPIE = 0x0U;			
+	}
+	
+/* USER CODE BEGIN (132) */
+/* USER CODE END */
+}
+
+
+/** @fn void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_RAMT = PBIST_RAMT_CONFIGVALUE;
+		config_reg->CONFIG_DLR = PBIST_DLR_CONFIGVALUE;
+		config_reg->CONFIG_PACT = PBIST_PACT_CONFIGVALUE;
+		config_reg->CONFIG_PBISTID = PBIST_PBISTID_CONFIGVALUE;
+		config_reg->CONFIG_OVER = PBIST_OVER_CONFIGVALUE;
+		config_reg->CONFIG_FSRDL1 = PBIST_FSRDL1_CONFIGVALUE;
+		config_reg->CONFIG_ROM = PBIST_ROM_CONFIGVALUE;
+		config_reg->CONFIG_ALGO = PBIST_ALGO_CONFIGVALUE;
+		config_reg->CONFIG_RINFOL = PBIST_RINFOL_CONFIGVALUE;
+		config_reg->CONFIG_RINFOU = PBIST_RINFOU_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg->CONFIG_RAMT = pbistREG->RAMT;
+		config_reg->CONFIG_DLR = pbistREG->DLR;
+		config_reg->CONFIG_PACT = pbistREG->PACT;
+		config_reg->CONFIG_PBISTID = pbistREG->PBISTID;
+		config_reg->CONFIG_OVER = pbistREG->OVER;
+		config_reg->CONFIG_FSRDL1 = pbistREG->FSRDL1;
+		config_reg->CONFIG_ROM = pbistREG->ROM;
+		config_reg->CONFIG_ALGO = pbistREG->ALGO;
+		config_reg->CONFIG_RINFOL = pbistREG->RINFOL;
+		config_reg->CONFIG_RINFOU = pbistREG->RINFOU;
+	}
+}
+
+/** @fn void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_STCGCR0 = STC_STCGCR0_CONFIGVALUE;
+		config_reg->CONFIG_STCGCR1 = STC_STCGCR1_CONFIGVALUE;
+		config_reg->CONFIG_STCTPR = STC_STCTPR_CONFIGVALUE;
+		config_reg->CONFIG_STCSCSCR = STC_STCSCSCR_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg->CONFIG_STCGCR0 = stcREG->STCGCR0;
+		config_reg->CONFIG_STCGCR1 = stcREG->STCGCR1;
+		config_reg->CONFIG_STCTPR = stcREG->STCTPR;
+		config_reg->CONFIG_STCSCSCR = stcREG->STCSCSCR;
+	}
+}
+
+
+/** @fn void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_BOUNDARY = EFC_BOUNDARY_CONFIGVALUE;
+		config_reg->CONFIG_PINS = EFC_PINS_CONFIGVALUE;
+		config_reg->CONFIG_SELFTESTCYCLES = EFC_SELFTESTCYCLES_CONFIGVALUE;
+		config_reg->CONFIG_SELFTESTSIGN = EFC_SELFTESTSIGN_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg->CONFIG_BOUNDARY = efcREG->BOUNDARY;
+		config_reg->CONFIG_PINS = efcREG->PINS;
+		config_reg->CONFIG_SELFTESTCYCLES = efcREG->SELF_TEST_CYCLES;
+		config_reg->CONFIG_SELFTESTSIGN = efcREG->SELF_TEST_SIGN;
+	}
+}
+
+
+/** @fn void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_CCMKEYR = CCMR4_CCMKEYR_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg->CONFIG_CCMKEYR = CCMKEYR;
+	}
+}
diff --git a/bsp/rm48x50/HALCoGen/source/sys_startup.c b/bsp/rm48x50/HALCoGen/source/sys_startup.c
new file mode 100644
index 0000000000000000000000000000000000000000..88af20646346861a5b938403b252f7fdf50c0369
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_startup.c
@@ -0,0 +1,652 @@
+/** @file sys_startup.c 
+*   @brief Startup Source File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*   This file contains:
+*   - Include Files
+*   - Type Definitions
+*   - External Functions
+*   - VIM RAM Setup
+*   - Startup Routine
+*   .
+*   which are relevant for the Startup.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Include Files */
+
+#include "sys_common.h"
+#include "system.h"
+#include "sys_vim.h"
+#include "sys_core.h"
+#include "sys_selftest.h"
+#include "esm.h"
+#include "mibspi.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* Type Definitions */
+
+typedef void (*handler_fptr)(const uint8 * in, uint8 * out);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+/* External Functions */
+
+/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
+/*SAFETYMCUSW 122 S MR:20.11 <REVIEWED> "Startup code(exit and abort need to be present)" */
+/*SAFETYMCUSW 296 S MR:8.6 <REVIEWED> "Startup code(library functions at block scope)" */
+/*SAFETYMCUSW 298 S MR:  <REVIEWED> "Startup code(handler pointers)" */
+/*SAFETYMCUSW 299 S MR:  <REVIEWED> "Startup code(typedef for handler pointers in library )" */
+/*SAFETYMCUSW 326 S MR:8.2 <REVIEWED> "Startup code(Declaration for main in library)" */
+/*SAFETYMCUSW 60 D MR:8.8 <REVIEWED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
+/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
+/*SAFETYMCUSW 354 S MR:1.4 <REVIEWED> " Startup code(Extern declaration present in the library)" */
+
+/*SAFETYMCUSW 218 S MR:20.2 <REVIEWED> "Functions from library" */
+
+#pragma WEAK(__TI_Handler_Table_Base)
+#pragma WEAK(__TI_Handler_Table_Limit)
+#pragma WEAK(__TI_CINIT_Base)
+#pragma WEAK(__TI_CINIT_Limit)
+
+extern uint32   __TI_Handler_Table_Base;
+extern uint32   __TI_Handler_Table_Limit;
+extern uint32   __TI_CINIT_Base;
+extern uint32   __TI_CINIT_Limit;
+extern uint32   __TI_PINIT_Base;
+extern uint32   __TI_PINIT_Limit;
+extern uint32 * __binit__;
+
+extern void main(void);
+extern void exit(void);
+
+extern void muxInit(void);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/* Startup Routine */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+#pragma CODE_STATE(_c_int00, 32)
+#pragma INTERRUPT(_c_int00, RESET)
+
+void _c_int00(void)
+{
+    
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+    /* Initialize Core Registers to avoid CCM Error */
+    _coreInitRegisters_();
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    /* Initialize Stack Pointers */
+    _coreInitStackPointer_();
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    /* Work Around for Errata DEVICE#140: ( Only on Rev A silicon) 
+     *
+     * Errata Description:
+     *            The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
+     * Workaround:
+     *            Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register */
+    if (DEVICE_ID_REV == 0x802AAD05U)
+    {
+        _esmCcmErrorsClear_();
+    }
+    
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+    /* Enable CPU Event Export */
+    /* This allows the CPU to signal any single-bit or double-bit errors detected
+     * by its ECC logic for accesses to program flash or data RAM.
+     */
+    _coreEnableEventBusExport_();
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    /* Reset handler: the following instructions read from the system exception status register
+     * to identify the cause of the CPU reset.
+     */
+
+    /* check for power-on reset condition */
+    if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
+    {
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+        
+        /* clear all reset status flags */
+        SYS_EXCEPTION = 0xFFFFU;
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    _errata_CORTEXR4_66_();
+    
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+    _errata_CORTEXR4_57_();
+    
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+        /* continue with normal start-up sequence */
+    }
+    else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
+    {
+        /* Reset caused due to oscillator failure.
+        Add user code here to handle oscillator failure */
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+    }
+    else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
+    {
+        /* Reset caused due 
+         *  1) windowed watchdog violation - Add user code here to handle watchdog violation.
+         *  2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
+         */
+        /* Check the WatchDog Status register */
+        if(WATCHDOG_STATUS != 0U)
+        {
+            /* Add user code here to handle watchdog violation. */ 
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+            /* Clear the Watchdog reset flag in Exception Status register */ 
+            SYS_EXCEPTION = WATCHDOG_RESET;
+        
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+        }
+        else
+        {
+            /* Clear the ICEPICK reset flag in Exception Status register */ 
+            SYS_EXCEPTION = ICEPICK_RESET;
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+        }
+    }
+    else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
+    {
+        /* Reset caused due to CPU reset.
+        CPU reset can be caused by CPU self-test completion, or
+        by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+        /* clear all reset status flags */
+        SYS_EXCEPTION = CPU_RESET;
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+    }
+    else if ((SYS_EXCEPTION & SW_RESET) != 0U)
+    {
+        /* Reset caused due to software reset.
+        Add user code to handle software reset. */
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+    }
+    else
+    {
+        /* Reset caused by nRST being driven low externally.
+        Add user code to handle external reset. */
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+    }
+
+    /* Check if there were ESM group3 errors during power-up.
+     * These could occur during eFuse auto-load or during reads from flash OTP
+     * during power-up. Device operation is not reliable and not recommended
+     * in this case.
+     * An ESM group3 error only drives the nERROR pin low. An external circuit
+     * that monitors the nERROR pin must take the appropriate action to ensure that
+     * the system is placed in a safe state, as determined by the application.
+     */
+    if ((esmREG->ESTATUS1[2]) != 0U)
+    {
+    /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+        for(;;)
+        { 
+        }/* Wait */                 
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+    }
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+    /* Initialize System - Clock, Flash settings with Efuse self check */
+    systemInit();
+
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+
+    /* Run a diagnostic check on the memory self-test controller.
+     * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
+     * The memory self-test is expected to fail. The function ensures that the PBIST controller
+     * is capable of detecting and indicating a memory self-test failure.
+     */
+    pbistSelfCheck();
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+
+    /* Run PBIST on CPU RAM.
+     * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
+     * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
+     * device datasheet.
+     */
+    pbistRun(0x08300020U, /* ESRAM Single Port PBIST */
+             (uint32)PBIST_March13N_SP);
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+    /* Wait for PBIST for CPU RAM to be completed */
+    while((!pbistIsTestCompleted()) == TRUE)
+    { 
+    }/* Wait */                 
+    
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+    /* Check if CPU RAM passed the self-test */
+    if( pbistIsTestPassed() != TRUE)
+    {
+        /* CPU RAM failed the self-test.
+         * Need custom handler to check the memory failure
+         * and to take the appropriate next step.
+         */
+        if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
+        {
+            memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0);
+        }
+        else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE)
+        {
+            memoryPort1TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U),(uint32)pbistREG->FSRA1, (uint32)pbistREG->FSRDL1);
+        }
+        else
+        {
+        /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+           for(;;)
+           { 
+           }/* Wait */                 
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+        }
+    }
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+    /* Disable PBIST clocks and disable memory self-test mode */
+    pbistStop();
+    
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
+
+    /* Initialize CPU RAM.
+     * This function uses the system module's hardware for auto-initialization of memories and their
+     * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
+     * Hence the value 0x1 passed to the function.
+     * This function will initialize the entire CPU RAM and the corresponding ECC locations.
+     */
+    memoryInit(0x1U);
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+    
+    /* Enable ECC checking for TCRAM accesses.
+     * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
+     */
+    _coreEnableRamEcc_();
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+
+    /* Start PBIST on all dual-port memories */
+    /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
+       PBIST test perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
+     */
+    
+    pbistRun(  0x00000000U   
+             | 0x00000000U         
+             | 0x00000800U    
+             | 0x00000200U   
+             | 0x00000040U
+             | 0x00000080U
+             | 0x00000100U
+             | 0x00000004U   
+             | 0x00000008U   
+             | 0x00000010U   
+             | 0x00000400U   
+             | 0x00020000U   
+             | 0x00001000U   
+             | 0x00040000U   
+             | 0x00002000U   
+             | 0x00080000U   
+             | 0x00004000U    
+             | 0x00000000U    
+             | 0x00000000U   
+             ,(uint32) PBIST_March13N_DP);
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+
+
+    /* Test the CPU ECC mechanism for RAM accesses.
+     * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
+     * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
+     * in the ECC causes a data abort exception. The data abort handler is written to look for
+     * deliberately caused exception and to return the code execution to the instruction
+     * following the one that caused the abort.
+     */
+    checkB0RAMECC();
+    tcram1REG->RAMCTRL &= ~(0x00000100U);                /* disable writes to ECC RAM */
+    tcram2REG->RAMCTRL &= ~(0x00000100U);
+
+    checkB1RAMECC();
+    tcram1REG->RAMCTRL &= ~(0x00000100U);                /* disable writes to ECC RAM */
+    tcram2REG->RAMCTRL &= ~(0x00000100U);
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+    /* Wait for PBIST for CPU RAM to be completed */
+    while((!pbistIsTestCompleted()) == TRUE)
+    { 
+    }/* Wait */                 
+    
+
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+
+    /* Check if CPU RAM passed the self-test */
+    if( pbistIsTestPassed() != TRUE)
+    {
+
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+
+        /* CPU RAM failed the self-test.
+         * Need custom handler to check the memory failure
+         * and to take the appropriate next step.
+         */
+        if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
+        {
+            memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U),(uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0);
+        }
+        else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE)
+        {
+            memoryPort1TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA1, (uint32)pbistREG->FSRDL1);
+        }
+        else
+        {
+        /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+           for(;;)
+            { 
+           }/* Wait */                 
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+        }
+    }
+
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+
+    /* Disable PBIST clocks and disable memory self-test mode */
+    pbistStop();
+    
+
+
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+    /* Release the MibSPI1 modules from local reset.
+     * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
+     */
+     mibspiREG1->GCR0 = 0x1U;
+     
+    /* Release the MibSPI3 modules from local reset.
+     * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
+     */
+    mibspiREG3->GCR0 = 0x1U;
+    
+    /* Release the MibSPI5 modules from local reset.
+     * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
+     */
+    mibspiREG5->GCR0 = 0x1U;
+    
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+
+    /* Initialize all on-chip SRAMs except for MibSPIx RAMs
+     * The MibSPIx modules have their own auto-initialization mechanism which is triggered
+     * as soon as the modules are brought out of local reset.
+     */
+    /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
+     */
+    /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
+              Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
+     */
+    memoryInit(  (1U << 1U)   
+                 | (1U << 2U)  
+                 | (1U << 5U)  
+                 | (1U << 6U)  
+                 | (1U << 10U) 
+                 | (1U << 8U)  
+                 | (1U << 14U) 
+                 | (1U << 3U)  
+                 | (1U << 4U)  
+                 | (1U << 15U) 
+                 | (1U << 16U) 
+                 | (0U << 13U) );
+
+    /* Test the parity protection mechanism for peripheral RAMs
+       NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
+                 Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
+    */
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+     
+    het1ParityCheck();
+    
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+    htu1ParityCheck();
+    
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+
+    het2ParityCheck();
+    
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
+
+    htu2ParityCheck();
+    
+/* USER CODE BEGIN (62) */
+/* USER CODE END */
+
+    adc1ParityCheck();
+    
+/* USER CODE BEGIN (63) */
+/* USER CODE END */
+
+    adc2ParityCheck();
+    
+/* USER CODE BEGIN (64) */
+/* USER CODE END */
+
+    can1ParityCheck();
+    
+/* USER CODE BEGIN (65) */
+/* USER CODE END */
+
+    can2ParityCheck();
+    
+/* USER CODE BEGIN (66) */
+/* USER CODE END */
+
+    can3ParityCheck();
+    
+/* USER CODE BEGIN (67) */
+/* USER CODE END */
+
+    vimParityCheck();
+    
+/* USER CODE BEGIN (68) */
+/* USER CODE END */
+
+    dmaParityCheck();
+
+
+/* USER CODE BEGIN (69) */
+/* USER CODE END */
+
+    while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
+    { 
+    }/* Wait */                 
+    /* wait for MibSPI1 RAM to complete initialization */
+    while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
+    { 
+    }/* Wait */                 
+    /* wait for MibSPI3 RAM to complete initialization */ 
+    while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
+    { 
+    }/* Wait */                 
+    /* wait for MibSPI5 RAM to complete initialization */
+
+/* USER CODE BEGIN (70) */
+/* USER CODE END */
+
+    mibspi1ParityCheck();
+    
+/* USER CODE BEGIN (71) */
+/* USER CODE END */
+
+    mibspi3ParityCheck();
+    
+/* USER CODE BEGIN (72) */
+/* USER CODE END */
+    
+    mibspi5ParityCheck();
+    
+
+/* USER CODE BEGIN (73) */
+/* USER CODE END */
+    
+
+/* USER CODE BEGIN (74) */
+/* USER CODE END */
+
+    /* Initialize VIM table */
+    vimInit();    
+
+/* USER CODE BEGIN (75) */
+/* USER CODE END */
+
+    /* Configure system response to error conditions signaled to the ESM group1 */
+    /* This function can be configured from the ESM tab of HALCoGen */
+    esmInit();
+
+    /* initialize copy table */
+    if ((uint32 *)&__binit__ != (uint32 *)0xFFFFFFFFU)
+    {
+        extern void copy_in(void * binit);
+        copy_in((void *)&__binit__);
+    }
+
+    /* initialize the C global variables */
+    if (&__TI_Handler_Table_Base < &__TI_Handler_Table_Limit)
+    {
+        uint8 **tablePtr   = (uint8 **)&__TI_CINIT_Base;
+        uint8 **tableLimit = (uint8 **)&__TI_CINIT_Limit;
+
+        while (tablePtr < tableLimit)
+        {
+            uint8 * loadAdr = *tablePtr++;
+            uint8 * runAdr  = *tablePtr++;
+            uint8  idx     = *loadAdr++;
+            handler_fptr   handler = (handler_fptr)(&__TI_Handler_Table_Base)[idx];
+
+            (*handler)((const uint8 *)loadAdr, runAdr);
+        }
+    }
+
+    /* initialize constructors */
+    if (__TI_PINIT_Base < __TI_PINIT_Limit)
+    {
+        void (**p0)(void) = (void *)__TI_PINIT_Base;
+
+        while ((uint32)p0 < __TI_PINIT_Limit)
+        {
+            void (*p)(void) = *p0++;
+            p();
+        }
+    }
+
+/* USER CODE BEGIN (76) */
+/* USER CODE END */
+    
+    /* call the application */
+    main();
+
+/* USER CODE BEGIN (77) */
+/* USER CODE END */
+
+    exit();
+/* USER CODE BEGIN (78) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (79) */
+/* USER CODE END */
diff --git a/bsp/rm48x50/HALCoGen/source/sys_vim.c b/bsp/rm48x50/HALCoGen/source/sys_vim.c
new file mode 100644
index 0000000000000000000000000000000000000000..e48b9f1e819bedbf6d41dd19f249b899a39adcf7
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/sys_vim.c
@@ -0,0 +1,676 @@
+/** @file sys_vim.c 
+*   @brief VIM Driver Inmplmentation File
+*   @date 
+*   @version 03.05.02
+*
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+
+#include "sys_vim.h"
+#include "system.h"
+
+
+/* Vim Ram Definition */
+/** @struct vimRam
+*   @brief Vim Ram Definition
+*
+*   This type is used to access the Vim Ram.
+*/
+/** @typedef vimRAM_t
+*   @brief Vim Ram Type Definition
+*
+*   This type is used to access the Vim Ram.
+*/
+typedef volatile struct vimRam
+{
+    t_isrFuncPTR ISR[VIM_CHANNELS + 1U];
+} vimRAM_t;
+
+#define vimRAM ((vimRAM_t *)0xFFF82000U)
+
+static const t_isrFuncPTR s_vim_init[129] =
+{
+    &phantomInterrupt,
+    &esmHighInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &rtiCompare3Interrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &linHighLevelInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+    &phantomInterrupt,
+};
+void vimParityErrorHandler(void);
+
+/** @fn void vimInit(void)
+*   @brief Initializes VIM module
+*
+*   This function initializes VIM RAM and registers
+*/
+
+void vimInit(void)
+{
+/* Initialize VIM table */
+    {
+        uint32 i;
+
+        for (i = 0U; i < (VIM_CHANNELS + 1U); i++)
+        {
+            vimRAM->ISR[i] = s_vim_init[i];
+        }
+    }
+	
+	/* Set Fall-Back Address Parity Error Register */
+    VIM_FBPARERR = (uint32)&vimParityErrorHandler;
+
+    /* set IRQ/FIQ priorities */
+    vimREG->FIRQPR0 =  SYS_FIQ
+                    | (SYS_FIQ <<  1U)
+                    | (SYS_IRQ <<  2U)
+                    | (SYS_IRQ <<  3U)
+                    | (SYS_IRQ <<  4U)
+                    | (SYS_IRQ <<  5U)
+                    | (SYS_IRQ <<  6U)
+                    | (SYS_IRQ <<  7U)
+                    | (SYS_IRQ <<  8U)
+                    | (SYS_IRQ <<  9U)
+                    | (SYS_IRQ << 10U)
+                    | (SYS_IRQ << 11U)
+                    | (SYS_IRQ << 12U)
+                    | (SYS_IRQ << 13U)
+                    | (SYS_IRQ << 14U)
+                    | (SYS_IRQ << 15U)
+                    | (SYS_IRQ << 16U)
+                    | (SYS_IRQ << 17U)
+                    | (SYS_IRQ << 18U)
+                    | (SYS_IRQ << 19U)
+                    | (SYS_IRQ << 20U)
+                    | (SYS_IRQ << 21U)
+                    | (SYS_IRQ << 22U)
+                    | (SYS_IRQ << 23U)
+                    | (SYS_IRQ << 24U)
+                    | (SYS_IRQ << 25U)
+                    | (SYS_IRQ << 26U)
+                    | (SYS_IRQ << 27U)
+                    | (SYS_IRQ << 28U)
+                    | (SYS_IRQ << 29U)
+                    | (SYS_IRQ << 30U)
+                    | (SYS_IRQ << 31U);
+
+    vimREG->FIRQPR1 =  SYS_IRQ
+                    | (SYS_IRQ <<  1U)
+                    | (SYS_IRQ <<  2U)
+                    | (SYS_IRQ <<  3U)
+                    | (SYS_IRQ <<  4U)
+                    | (SYS_IRQ <<  5U)
+                    | (SYS_IRQ <<  6U)
+                    | (SYS_IRQ <<  7U)
+                    | (SYS_IRQ <<  8U)
+                    | (SYS_IRQ <<  9U)
+                    | (SYS_IRQ << 10U)
+                    | (SYS_IRQ << 11U)
+                    | (SYS_IRQ << 12U)
+                    | (SYS_IRQ << 13U)
+                    | (SYS_IRQ << 14U)
+                    | (SYS_IRQ << 15U)
+                    | (SYS_IRQ << 16U)
+                    | (SYS_IRQ << 17U)
+                    | (SYS_IRQ << 18U)
+                    | (SYS_IRQ << 19U)
+                    | (SYS_IRQ << 20U)
+                    | (SYS_IRQ << 21U)
+                    | (SYS_IRQ << 22U)
+                    | (SYS_IRQ << 23U)
+                    | (SYS_IRQ << 24U)
+                    | (SYS_IRQ << 25U)
+                    | (SYS_IRQ << 26U)
+                    | (SYS_IRQ << 27U)
+                    | (SYS_IRQ << 28U)
+                    | (SYS_IRQ << 29U)
+                    | (SYS_IRQ << 30U)
+                    | (SYS_IRQ << 31U);
+
+
+    vimREG->FIRQPR2 =  SYS_IRQ
+                    | (SYS_IRQ << 1U)
+                    | (SYS_IRQ << 2U)
+                    | (SYS_IRQ << 3U)
+                    | (SYS_IRQ << 4U)
+                    | (SYS_IRQ << 5U)
+                    | (SYS_IRQ << 6U)
+                    | (SYS_IRQ << 7U)
+                    | (SYS_IRQ << 8U)
+                    | (SYS_IRQ << 9U)
+                    | (SYS_IRQ << 10U)
+                    | (SYS_IRQ << 11U)
+                    | (SYS_IRQ << 12U)
+                    | (SYS_IRQ << 13U)
+                    | (SYS_IRQ << 14U)
+                    | (SYS_IRQ << 15U)
+                    | (SYS_IRQ << 16U)
+                    | (SYS_IRQ << 17U)
+                    | (SYS_IRQ << 18U)
+                    | (SYS_IRQ << 19U)
+                    | (SYS_IRQ << 20U)
+                    | (SYS_IRQ << 21U)
+                    | (SYS_IRQ << 22U)
+                    | (SYS_IRQ << 23U)
+                    | (SYS_IRQ << 24U)
+                    | (SYS_IRQ << 25U)
+					| (SYS_IRQ << 26U)
+                    | (SYS_IRQ << 27U)
+                    | (SYS_IRQ << 28U)
+                    | (SYS_IRQ << 29U)
+                    | (SYS_IRQ << 30U)
+                    | (SYS_IRQ << 31U);
+
+    vimREG->FIRQPR3 =  SYS_IRQ
+                    | (SYS_IRQ << 1U)
+                    | (SYS_IRQ << 2U)
+                    | (SYS_IRQ << 3U)
+                    | (SYS_IRQ << 4U)
+                    | (SYS_IRQ << 5U)
+                    | (SYS_IRQ << 6U)
+                    | (SYS_IRQ << 7U)
+                    | (SYS_IRQ << 8U)
+                    | (SYS_IRQ << 9U)
+                    | (SYS_IRQ << 10U)
+                    | (SYS_IRQ << 11U)
+                    | (SYS_IRQ << 12U)
+                    | (SYS_IRQ << 13U)
+                    | (SYS_IRQ << 14U)
+                    | (SYS_IRQ << 15U)
+                    | (SYS_IRQ << 16U)
+                    | (SYS_IRQ << 17U)
+                    | (SYS_IRQ << 18U)
+                    | (SYS_IRQ << 19U)
+                    | (SYS_IRQ << 20U)
+                    | (SYS_IRQ << 21U)
+                    | (SYS_IRQ << 22U)
+                    | (SYS_IRQ << 23U)
+                    | (SYS_IRQ << 24U)
+                    | (SYS_IRQ << 25U)
+					| (SYS_IRQ << 26U)
+                    | (SYS_IRQ << 27U)
+                    | (SYS_IRQ << 28U)
+                    | (SYS_IRQ << 29U)
+                    | (SYS_IRQ << 30U)
+                    | (SYS_IRQ << 31U);
+
+					
+    /* enable interrupts */
+    vimREG->REQMASKSET0 = 1U
+                        | (1U << 1U)
+                        | (0U << 2U)
+                        | (0U << 3U)
+                        | (0U << 4U)
+                        | (1U << 5U)
+                        | (0U << 6U)
+                        | (0U << 7U)
+                        | (0U << 8U)
+                        | (0U << 9U)
+                        | (0U << 10U)
+                        | (0U << 11U)
+                        | (0U << 12U)
+                        | (1U << 13U)
+                        | (0U << 14U)
+                        | (0U << 15U)
+                        | (0U << 16U)
+                        | (0U << 17U)
+                        | (0U << 18U)
+                        | (0U << 19U)
+                        | (0U << 20U)
+                        | (0U << 21U)
+                        | (0U << 22U)
+                        | (0U << 23U)
+                        | (0U << 24U)
+                        | (0U << 25U)
+                        | (0U << 26U)
+                        | (0U << 27U)
+                        | (0U << 28U)
+                        | (0U << 29U)
+                        | (0U << 30U)
+                        | (0U << 31U);
+
+    vimREG->REQMASKSET1 = 0U
+                        | (0U << 1U)
+                        | (0U << 2U)
+                        | (0U << 3U)
+                        | (0U << 4U)
+                        | (0U << 5U)
+                        | (0U << 6U)
+                        | (0U << 7U)
+                        | (0U << 8U)
+                        | (0U << 9U)
+                        | (0U << 10U)
+                        | (0U << 11U)
+                        | (0U << 12U)
+                        | (0U << 13U)
+                        | (0U << 14U)
+                        | (0U << 15U)
+                        | (0U << 16U)
+                        | (0U << 17U)
+                        | (0U << 18U)
+                        | (0U << 19U)
+                        | (0U << 20U)
+                        | (0U << 21U)
+                        | (0U << 22U)
+                        | (0U << 23U)
+                        | (0U << 24U)
+                        | (0U << 25U)
+                        | (0U << 26U)
+                        | (0U << 27U)
+                        | (0U << 28U)
+                        | (0U << 29U)
+                        | (0U << 30U)
+                        | (0U << 31U);
+
+    vimREG->REQMASKSET2 = 0U
+                        | (0U << 1U)
+                        | (0U << 2U)
+                        | (0U << 3U)
+                        | (0U << 4U)
+                        | (0U << 5U)
+                        | (0U << 6U)
+                        | (0U << 7U)
+                        | (0U << 8U)
+                        | (0U << 9U)
+                        | (0U << 10U)
+                        | (0U << 11U)
+                        | (0U << 12U)
+                        | (0U << 13U)
+                        | (0U << 14U)
+                        | (0U << 15U)
+                        | (0U << 16U)
+                        | (0U << 17U)
+                        | (0U << 18U)
+                        | (0U << 19U)
+                        | (0U << 20U)
+                        | (0U << 21U)
+                        | (0U << 22U)
+                        | (0U << 23U)
+                        | (0U << 24U)
+                        | (0U << 25U)
+					    | (0U << 26U)
+                        | (0U << 27U)
+                        | (0U << 28U)
+                        | (0U << 29U)
+                        | (0U << 30U)
+                        | (0U << 31U);
+						
+    vimREG->REQMASKSET3 =  0U
+                        | (0U << 1U)
+                        | (0U << 2U)
+                        | (0U << 3U)
+                        | (0U << 4U)
+                        | (0U << 5U)
+                        | (0U << 6U)
+                        | (0U << 7U)
+                        | (0U << 8U)
+                        | (0U << 9U)
+                        | (0U << 10U)
+                        | (0U << 11U)
+                        | (0U << 12U)
+                        | (0U << 13U)
+                        | (0U << 14U)
+                        | (0U << 15U)
+                        | (0U << 16U)
+                        | (0U << 17U)
+                        | (0U << 18U)
+                        | (0U << 19U)
+                        | (0U << 20U)
+                        | (0U << 21U)
+                        | (0U << 22U)
+                        | (0U << 23U)
+                        | (0U << 24U)
+                        | (0U << 25U)
+						| (0U << 26U)
+                        | (0U << 27U)
+                        | (0U << 28U)
+                        | (0U << 29U)
+                        | (0U << 30U)
+                        | (0U << 31U);	
+}
+
+/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
+*   @brief Map selected interrupt request to the selected channel
+*
+*	@param[in] request: Interrupt request number 2..95
+*	@param[in] channel: VIM Channel number 2..95
+*	@param[in] handler: Address of the interrupt handler
+*
+*   This function will map selected interrupt request to the selected channel.
+*
+*/
+void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
+{
+	uint32 i,j;
+    i = channel >> 2U;              /* Find the register to configure */
+    j = channel -(i<<2U);           /* Find the offset of the type    */
+    j = 3U-j;                       /* reverse the byte order         */
+    j = j<<3U;                      /* find the bit location          */
+
+    /*Mapping the required interrupt request to the required channel*/
+    vimREG->CHANCTRL[i] &= ~(0xFFU << j);
+    vimREG->CHANCTRL[i] |= (request << j);
+
+    /*Updating VIMRAM*/
+    vimRAM->ISR[channel+1] = handler;
+}
+
+/** @fn void vimEnableInterrupt(uint32 channel, boolean inttype)
+*   @brief Enable interrupt for the the selected channel
+*
+*	@param[in] channel: VIM Channel number 2..95
+*	@param[in] handler: Interrupt type
+*						- SYS_IRQ: Selected channel will be enabled as IRQ
+*						- SYS_FIQ: Selected channel will be enabled as FIQ
+*
+*   This function will enable interrupt for the selected channel.
+*
+*/
+void vimEnableInterrupt(uint32 channel, boolean inttype)
+{
+	if (channel >= 64)
+	{
+		if(inttype == SYS_IRQ)
+		{
+			vimREG->FIRQPR2 &= ~(1 << (channel-64));
+		}
+		else
+		{
+			vimREG->FIRQPR2 |= 1 << (channel-64);
+		}
+		vimREG->REQMASKSET2 = 1 << (channel-64);
+	}
+	else if (channel >= 32)
+	{
+		if(inttype == SYS_IRQ)
+		{
+			vimREG->FIRQPR1 &= ~(1 << (channel-32));
+		}
+		else
+		{
+			vimREG->FIRQPR1 |= 1 << (channel-32);
+		}
+		vimREG->REQMASKSET1 = 1 << (channel-32);
+	}
+	else if (channel >= 2)
+	{
+		if(inttype == SYS_IRQ)
+		{
+			vimREG->FIRQPR0 &= ~(1 << channel);
+		}
+		else
+		{
+			vimREG->FIRQPR0 |= 1 << channel;
+		}
+		vimREG->REQMASKSET0 = 1 << channel;
+	}
+	else
+	{
+
+	}
+}
+
+/** @fn void vimDisableInterrupt(uint32 channel)
+*   @brief Disable interrupt for the the selected channel
+*
+*	@param[in] channel: VIM Channel number 2..95
+*
+*   This function will disable interrupt for the selected channel.
+*
+*/
+void vimDisableInterrupt(uint32 channel)
+{
+	if (channel >= 64)
+	{
+		vimREG->REQMASKCLR2 = 1 << (channel-64);
+	}
+	else if (channel >=32)
+	{
+		vimREG->REQMASKCLR1 = 1 << (channel-32);
+	}
+	else if (channel >= 2)
+	{
+		vimREG->REQMASKCLR0 = 1 << channel;
+	}
+	else
+	{
+
+	}
+}
+
+/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
+{
+	uint32 temp[24U] = VIM_CHANCTRL_CONFIGVALUE;
+	uint32 i;
+	
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE;
+		config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE;
+		config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE;
+		config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE;
+		config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE;
+		config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE;
+		config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE;
+		config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE;
+		config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE;
+		config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE;
+		config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE;
+		config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE;
+		config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE;
+
+		for (i=0U; i<24U;i++)
+		{
+			config_reg->CONFIG_CHANCTRL[i] = temp[i];
+		}
+	}
+	else
+	{
+		config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0;
+		config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1;
+		config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2;
+		config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3;
+		config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0;
+		config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1;
+		config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2;
+		config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3;
+		config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0;
+		config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1;
+		config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2;
+		config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3;
+		config_reg->CONFIG_CAPEVT = vimREG->CAPEVT;
+
+		for (i=0U; i<24U; i++)
+		{
+				config_reg->CONFIG_CHANCTRL[i] = vimREG->CHANCTRL[i];
+		}
+
+		
+	}
+}
+
+
+#pragma CODE_STATE(vimParityErrorHandler, 32)
+#pragma INTERRUPT(vimParityErrorHandler, IRQ)
+
+void vimParityErrorHandler(void)
+{
+	/* Identify the corrupted address */
+	uint32 error_addr = VIM_ADDERR;
+
+	/* Identify the channel number */
+	uint32 error_channel = ((error_addr & 0x1FF) >> 2) - 1;
+
+	/* Correct the corrupted location */
+	vimRAM->ISR[error_channel + 1] = s_vim_init[error_channel + 1];
+
+	/* Clear Parity Error Flag */
+	VIM_PARFLG = 1;
+
+	/* Disable and enable the highest priority pending channel */
+	sint32 channel;
+	channel = vimREG->FIQINDEX - 1;
+	if (vimREG->FIQINDEX != 0)
+	{
+		channel = vimREG->FIQINDEX - 1;
+	}
+	else 
+	{
+		channel = vimREG->IRQINDEX - 1;
+	}
+	if (channel >= 0)
+	{
+		if (channel < 32)
+		{
+			vimREG->REQMASKCLR0 = 1 << channel;
+			vimREG->REQMASKSET0 = 1 << channel;
+		}
+		else if (channel < 64)
+		{
+			vimREG->REQMASKCLR1 = 1 << (channel-32);
+			vimREG->REQMASKSET1 = 1 << (channel-32);
+		}
+		else
+		{
+			vimREG->REQMASKCLR2 = 1 << (channel-64);
+			vimREG->REQMASKSET2 = 1 << (channel-64);
+		}
+	}
+}
diff --git a/bsp/rm48x50/HALCoGen/source/system.c b/bsp/rm48x50/HALCoGen/source/system.c
new file mode 100644
index 0000000000000000000000000000000000000000..49ddb1d786b2dc145f221a8045e9928ce4e00c3b
--- /dev/null
+++ b/bsp/rm48x50/HALCoGen/source/system.c
@@ -0,0 +1,576 @@
+/** @file system.c 
+*   @brief System Driver Source File
+*   @date 29.May.2013
+*   @version 03.05.02
+*
+*   This file contains:
+*   - API Functions
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2013, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Include Files */
+
+#include "system.h"
+#include "sys_selftest.h"
+#include "sys_pcr.h"
+#include "pinmux.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void systemInit(void)
+*   @brief Initializes System Driver
+*
+*   This function initializes the System driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+void setupPLL(void)
+{
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /** - Configure PLL control registers */
+    /** @b Initialize @b Pll1: */
+
+    /**   - Setup pll control register 1:
+    *     - Setup reset on oscillator slip 
+    *     - Setup bypass on pll slip
+    *     - setup Pll output clock divider to max before Lock
+    *     - Setup reset on oscillator fail
+    *     - Setup reference clock divider 
+    *     - Setup Pll multiplier          
+    */
+    systemREG1->PLLCTL1 =  0x00000000U 
+                        |  0x20000000U 
+                        | ((0x1FU)<< 24U) 
+                        |  0x00000000U 
+                        | ((6U - 1U)<< 16U) 
+                        | ((150U - 1U)<< 8U);
+
+    /**   - Setup pll control register 2
+    *     - Enable/Disable frequency modulation
+    *     - Setup spreading rate
+    *     - Setup bandwidth adjustment
+    *     - Setup internal Pll output divider
+    *     - Setup spreading amount
+    */
+    systemREG1->PLLCTL2 =  0x00000000U
+                        | (255U << 22U)
+                        | (7U << 12U)
+                        | ((2U - 1U)<< 9U)
+                        |  61U;
+
+    /** @b Initialize @b Pll2: */
+
+    /**   - Setup pll2 control register :
+    *     - setup Pll output clock divider to max before Lock
+    *     - Setup reference clock divider 
+    *     - Setup internal Pll output divider
+    *     - Setup Pll multiplier          
+    */
+    systemREG2->PLLCTL3 = ((2U - 1U) << 29U)
+                        | ((0x1FU)<< 24U) 
+                        | ((6U - 1U)<< 16U) 
+                        | ((150U - 1U) << 8U);
+
+	/** - Enable PLL(s) to start up or Lock */
+    systemREG1->CSDIS = 0x00000000U	
+                      | 0x00000000U 
+                      | 0x00000008U 
+                      | 0x00000080U 
+                      | 0x00000000U 
+                      | 0x00000000U 
+                      | 0x00000000U;
+}
+
+void trimLPO(void)
+{
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+    /** @b Initialize Lpo: */
+    /** Load TRIM values from OTP if present else load user defined values */
+    if(LPO_TRIM_VALUE != 0xFFFFU)
+    {
+    
+        systemREG1->LPOMONCTL  = (1U << 24U)
+                                | LPO_TRIM_VALUE;
+    }
+    else
+    {
+
+    	systemREG1->LPOMONCTL 	= (1U << 24U)
+                                 | (16U << 8U)
+                                 | 8U;
+    }
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+}
+
+void setupFlash(void)
+{
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    /** - Setup flash read mode, address wait states and data wait states */
+    flashWREG->FRDCNTL =  0x00000000U 
+                       | (3U << 8U) 
+                       | (1U << 4U) 
+                       |  1U;
+
+    /** - Setup flash access wait states for bank 7 */
+    FSM_WR_ENA_HL    = 0x5U;
+    EEPROM_CONFIG_HL = 0x00000002U
+	                 | (3U << 16U) ;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    /** - Disable write access to flash state machine registers */
+    FSM_WR_ENA_HL    = 0xAU;
+
+    /** - Setup flash bank power modes */
+    flashWREG->FBFALLBACK = 0x00000000U
+                          | (SYS_ACTIVE << 14U) 
+                          | (SYS_SLEEP << 12U) 
+                          | (SYS_SLEEP << 10U) 
+                          | (SYS_SLEEP << 8U) 
+                          | (SYS_SLEEP << 6U) 
+                          | (SYS_SLEEP << 4U) 
+                          | (SYS_ACTIVE << 2U) 
+                          |  SYS_ACTIVE;
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+}
+
+void periphInit(void)
+{
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    /** - Disable Peripherals before peripheral powerup*/
+    systemREG1->CLKCNTL &= 0xFFFFFEFFU;
+
+	/** - Release peripherals from reset and enable clocks to all peripherals */
+    /** - Power-up all peripherals */
+    pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;
+    pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;
+    pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;
+    pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;
+
+    /** - Enable Peripherals */
+    systemREG1->CLKCNTL |= 1U << 8U;
+	
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+}
+
+void mapClocks(void)
+{
+	
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    /** @b Initialize @b Clock @b Tree: */
+    /** - Disable / Enable clock domain */
+    systemREG1->CDDIS= (FALSE << 4U ) /* AVCLK 1 OFF */
+                      |(TRUE << 5U ) /* AVCLK 2 OFF */
+	                  |(FALSE << 8U ) /* VCLK3 OFF */
+					  |(FALSE << 9U ) /* VCLK4 OFF */
+	                  |(FALSE << 10U) /* AVCLK 3 OFF */
+                      |(FALSE << 11U); /* AVCLK 4 OFF */
+
+
+    /* Work Around for Errata SYS#46:
+     * 
+     * Errata Description:            
+     *            Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
+     * Workaround:
+     *            Always check the CSDIS register to make sure the clock source is turned on and check 
+     * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
+     */
+	/** - Wait for until clocks are locked */
+    while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFFU) & 0xFFU)) != ((systemREG1->CSDIS ^ 0xFFU) & 0xFFU))
+    { 
+	} /* Wait */
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+	/* Now the PLLs are locked and the PLL outputs can be sped up */
+	/* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
+    systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFFU)|((1U - 1U)<< 24U);
+    systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFFU)|((1U - 1U)<< 24U);
+
+	/** - Map device clock domains to desired sources and configure top-level dividers */
+	/** - All clock domains are working off the default clock sources until now */
+	/** - The below assignments can be easily modified using the HALCoGen GUI */
+    
+    /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
+    systemREG1->GHVSRC = (SYS_PLL1 << 24U) 
+                       | (SYS_PLL1 << 16U) 
+                       |  SYS_PLL1;
+                       
+    /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
+    systemREG1->CLKCNTL  = (systemREG1->CLKCNTL & 0xF0F0FFFFU) 
+						 | (1U << 24U)  
+						 | (1U << 16U);  
+	systemREG2->CLK2CNTL = (systemREG2->CLK2CNTL & 0xFFFFF0F0U)
+	                     | (1U) << 8U
+						 | (1U);
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+	
+    /** - Setup RTICLK1 and RTICLK2 clocks */
+    systemREG1->RCLKSRC = (1U << 24U)
+                        | (SYS_VCLK << 16U) 
+                        | (1U << 8U)  
+                        |  SYS_VCLK;
+
+    /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
+    systemREG1->VCLKASRC = (SYS_VCLK << 8U)
+                          |  SYS_VCLK;
+
+    systemREG2->VCLKACON1 = ((1U - 1U ) << 24U) 
+                           | (0U << 20U) 
+                           | (SYS_VCLK << 16U)
+                           | ((1U - 1U ) << 8U)
+                           | (0U << 4U) 
+                           | SYS_VCLK;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+}
+
+void systemInit(void)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+	/* Configure PLL control registers and enable PLLs.
+	 * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
+	 * This initialization sequence performs all the tasks that are not
+	 * required to be done at full application speed while the PLL locks.
+	 */
+	setupPLL();
+	
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+	/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
+	 * This includes a check for the eFuse controller error outputs to be stuck-at-zero.
+	 */
+	efcCheck();
+	
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+	
+	/* Enable clocks to peripherals and release peripheral reset */
+	periphInit();
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+	/* Configure device-level multiplexing and I/O multiplexing */
+	muxInit();
+	
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+	/* Wait for eFuse controller self-test to complete and check results */
+	if ((!checkefcSelfTest()) !=0U)							/* eFuse controller ECC logic self-test failed */
+	{
+		efcClass2Error();								/* device operation is not reliable */
+	}
+	
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+	/** - Set up flash address and data wait states based on the target CPU clock frequency
+	 * The number of address and data wait states for the target CPU clock frequency are specified
+	 * in the specific part's datasheet.
+	 */
+	setupFlash();
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+	/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
+	trimLPO();
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+	/** - Wait for PLLs to start up and map clock domains to desired clock sources */
+	mapClocks();
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+	/** - set ECLK pins functional mode */
+    systemREG1->SYSPC1 = 0U;
+
+    /** - set ECLK pins default output value */
+    systemREG1->SYSPC4 = 0U;
+
+    /** - set ECLK pins output direction */
+    systemREG1->SYSPC2 = 1U;
+
+    /** - set ECLK pins open drain enable */
+    systemREG1->SYSPC7 = 0U;
+
+    /** - set ECLK pins pullup/pulldown enable */
+    systemREG1->SYSPC8 = 0U;   
+
+    /** - set ECLK pins pullup/pulldown select */
+    systemREG1->SYSPC9 = 1U;
+
+    /** - Setup ECLK */
+    systemREG1->ECPCNTL = (0U << 24U)
+                        | (0U << 23U)
+                        | ((8U - 1U) & 0xFFFFU);
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+}
+
+void systemPowerDown(uint32 mode)
+{
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+    /* Disable clock sources */
+    systemREG1->CSDISSET = mode & 0x000000FFU;
+
+    /* Disable clock domains */
+    systemREG1->CDDIS = (mode >> 8U) & 0x00000FFFU;
+
+    /* Idle CPU */
+	/*SAFETYMCUSW 88 S MR:2.1 <REVIEWED> "Assembly in C needed" */
+    asm(" wfi");
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+/** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE;
+		config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE;
+		config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE;
+		config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE;
+		config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE;
+		config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE;
+		config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE;
+		config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE;
+		config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE;
+		config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE;
+		config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE;
+		config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE;
+		config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE;
+		config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2;
+		config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE;
+		config_reg->CONFIG_UERFLAG = SYS_UERFLAG_CONFIGVALUE;
+		if(LPO_TRIM_VALUE != 0xFFFFU)
+		{
+			config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1;
+		}
+		else
+		{
+			config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2;
+		}
+		config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE;
+		config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE;
+		config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE;
+		config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE;
+		config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE;
+		config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE;
+		config_reg->CONFIG_MMUGCR = SYS_MMUGCR_CONFIGVALUE;
+		config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE;
+		config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE;
+		config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE;
+		config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE;
+
+		config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2;
+		config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE;
+		config_reg->CONFIG_CLK2CNTL = SYS2_CLK2CNTL_CONFIGVALUE;
+		config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE;
+		config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE;
+		config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1;
+		config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2;
+		config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7;
+		config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8;
+		config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9;
+		config_reg->CONFIG_CSDIS = systemREG1->CSDIS;
+		config_reg->CONFIG_CDDIS = systemREG1->CDDIS;
+		config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC;
+		config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC;
+		config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC;
+		config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR;
+		config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR;
+		config_reg->CONFIG_MSINENA = systemREG1->MSINENA;
+		config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1;
+		config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2;
+		config_reg->CONFIG_UERFLAG = systemREG1->UERFLAG;
+		config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL;
+		config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST;
+		config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1;
+		config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2;
+		config_reg->CONFIG_GPREG1 = systemREG1->GPREG1;
+		config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR;
+		config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1;
+		config_reg->CONFIG_MMUGCR = systemREG1->MMUGCR;
+		config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL;
+		config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL;
+		config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1;
+		config_reg->CONFIG_SYSECR = systemREG1->SYSECR;
+		
+		config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3;
+		config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV;
+		config_reg->CONFIG_CLK2CNTL = systemREG2->CLK2CNTL;
+		config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1;
+		config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP;
+		config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN;
+	}
+}
+
+/** @fn void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg-> CONFIG_FRDCNTL = TCMFLASH_FRDCNTL_CONFIGVALUE;
+		config_reg-> CONFIG_FEDACCTRL1 = TCMFLASH_FEDACCTRL1_CONFIGVALUE;
+		config_reg-> CONFIG_FEDACCTRL2 = TCMFLASH_FEDACCTRL2_CONFIGVALUE;
+		config_reg-> CONFIG_FEDACSDIS = TCMFLASH_FEDACSDIS_CONFIGVALUE;
+		config_reg-> CONFIG_FBPROT = TCMFLASH_FBPROT_CONFIGVALUE;
+		config_reg-> CONFIG_FBSE = TCMFLASH_FBSE_CONFIGVALUE;
+		config_reg-> CONFIG_FBAC = TCMFLASH_FBAC_CONFIGVALUE;
+		config_reg-> CONFIG_FBFALLBACK = TCMFLASH_FBFALLBACK_CONFIGVALUE;
+		config_reg-> CONFIG_FPAC1 = TCMFLASH_FPAC1_CONFIGVALUE;
+		config_reg-> CONFIG_FPAC2 = TCMFLASH_FPAC2_CONFIGVALUE;
+		config_reg-> CONFIG_FMAC = TCMFLASH_FMAC_CONFIGVALUE;
+		config_reg-> CONFIG_FLOCK = TCMFLASH_FLOCK_CONFIGVALUE;
+		config_reg-> CONFIG_FDIAGCTRL = TCMFLASH_FDIAGCTRL_CONFIGVALUE;
+		config_reg-> CONFIG_FEDACSDIS2 = TCMFLASH_FEDACSDIS2_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg-> CONFIG_FRDCNTL = flashWREG->FRDCNTL;
+		config_reg-> CONFIG_FEDACCTRL1 = flashWREG->FEDACCTRL1;
+		config_reg-> CONFIG_FEDACCTRL2 = flashWREG->FEDACCTRL2;
+		config_reg-> CONFIG_FEDACSDIS = flashWREG->FEDACSDIS;
+		config_reg-> CONFIG_FBPROT = flashWREG->FBPROT;
+		config_reg-> CONFIG_FBSE = flashWREG->FBSE;
+		config_reg-> CONFIG_FBAC = flashWREG->FBAC;
+		config_reg-> CONFIG_FBFALLBACK = flashWREG->FBFALLBACK;
+		config_reg-> CONFIG_FPAC1 = flashWREG->FPAC1;
+		config_reg-> CONFIG_FPAC2 = flashWREG->FPAC2;
+		config_reg-> CONFIG_FMAC = flashWREG->FMAC;
+		config_reg-> CONFIG_FLOCK = flashWREG->FLOCK;
+		config_reg-> CONFIG_FDIAGCTRL = flashWREG->FDIAGCTRL;
+		config_reg-> CONFIG_FEDACSDIS2 = flashWREG->FEDACSDIS2;
+	}
+}
+
+
+
+/** @fn void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+
+void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_RAMCTRL[0U] = SRAM_RAMCTRL_CONFIGVALUE;
+		config_reg->CONFIG_RAMTHRESHOLD[0U] = SRAM_RAMTHRESHOLD_CONFIGVALUE;
+		config_reg->CONFIG_RAMINTCTRL[0U] = SRAM_RAMINTCTRL_CONFIGVALUE;
+		config_reg->CONFIG_RAMTEST[0U] = SRAM_RAMTEST_CONFIGVALUE;
+		config_reg->CONFIG_RAMADDRDECVECT[0U] = SRAM_RAMADDRDECVECT_CONFIGVALUE;
+		
+		config_reg->CONFIG_RAMCTRL[1U] = SRAM_RAMCTRL_CONFIGVALUE;
+		config_reg->CONFIG_RAMTHRESHOLD[1U] = SRAM_RAMTHRESHOLD_CONFIGVALUE;
+		config_reg->CONFIG_RAMINTCTRL[1U] = SRAM_RAMINTCTRL_CONFIGVALUE;
+		config_reg->CONFIG_RAMTEST[1U] = SRAM_RAMTEST_CONFIGVALUE;
+		config_reg->CONFIG_RAMADDRDECVECT[1U] = SRAM_RAMADDRDECVECT_CONFIGVALUE;
+	}
+	else
+	{
+		config_reg->CONFIG_RAMCTRL[0U] = tcram1REG->RAMCTRL;
+		config_reg->CONFIG_RAMTHRESHOLD[0U] = tcram1REG->RAMTHRESHOLD;
+		config_reg->CONFIG_RAMINTCTRL[0U] = tcram1REG->RAMINTCTRL;
+		config_reg->CONFIG_RAMTEST[0U] = tcram1REG->RAMTEST;
+		config_reg->CONFIG_RAMADDRDECVECT[0U] = tcram1REG->RAMADDRDECVECT;
+	
+		config_reg->CONFIG_RAMCTRL[1U] = tcram2REG->RAMCTRL;
+		config_reg->CONFIG_RAMTHRESHOLD[1U] = tcram2REG->RAMTHRESHOLD;
+		config_reg->CONFIG_RAMINTCTRL[1U] = tcram2REG->RAMINTCTRL;
+		config_reg->CONFIG_RAMTEST[1U] = tcram2REG->RAMTEST;
+		config_reg->CONFIG_RAMADDRDECVECT[1U] = tcram2REG->RAMADDRDECVECT;
+	}
+}
diff --git a/bsp/rm48x50/application/application.c b/bsp/rm48x50/application/application.c
new file mode 100644
index 0000000000000000000000000000000000000000..d9ffaf4754a0d138acf36e7e2d39592e6bb3d3f8
--- /dev/null
+++ b/bsp/rm48x50/application/application.c
@@ -0,0 +1,62 @@
+/*
+ * File      : app.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-24     Grissiom     first version
+ */
+
+#include <rtthread.h>
+
+#include "system.h"
+#include "het.h"
+
+int ulRegTest1Counter;
+int ulRegTest2Counter;
+
+static rt_uint8_t user_thread_stack[512];
+static struct rt_thread user_thread;
+static void user_thread_entry(void *p)
+{
+    int i;
+
+    gioSetDirection(hetPORT1, 0xFFFFFFFF);
+
+    for(i = 0; ;i++)
+    {
+        gioSetBit(hetPORT1, 17, gioGetBit(hetPORT1, 17) ^ 1);
+        rt_thread_delay(100);
+    }
+}
+
+static rt_uint8_t test_thread_stack[512];
+static struct rt_thread test_thread;
+void vRegTestTask1(void*);
+
+static rt_uint8_t test_thread_stack2[512];
+static struct rt_thread test_thread2;
+void vRegTestTask2(void*);
+
+int rt_application_init()
+{
+    rt_thread_init(&user_thread, "user1", user_thread_entry, RT_NULL,
+            user_thread_stack, sizeof(user_thread_stack), 21, 20);
+    rt_thread_startup(&user_thread);
+
+    rt_thread_init(&test_thread, "test1", vRegTestTask1, RT_NULL,
+            test_thread_stack, sizeof(test_thread_stack), 21, 20);
+    rt_thread_startup(&test_thread);
+
+    rt_thread_init(&test_thread2, "test2", vRegTestTask2, RT_NULL,
+            test_thread_stack2, sizeof(test_thread_stack2), 22, 20);
+    rt_thread_startup(&test_thread2);
+
+    return 0;
+}
+
diff --git a/bsp/rm48x50/application/reg_test.asm b/bsp/rm48x50/application/reg_test.asm
new file mode 100644
index 0000000000000000000000000000000000000000..6b6816460419bcf96679802de8eb03ca5ea1b744
--- /dev/null
+++ b/bsp/rm48x50/application/reg_test.asm
@@ -0,0 +1,472 @@
+;/*
+;    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+;
+;
+;    ***************************************************************************
+;     *                                                                       *
+;     *    FreeRTOS tutorial books are available in pdf and paperback.        *
+;     *    Complete, revised, and edited pdf reference manuals are also       *
+;     *    available.                                                         *
+;     *                                                                       *
+;     *    Purchasing FreeRTOS documentation will not only help you, by       *
+;     *    ensuring you get running as quickly as possible and with an        *
+;     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
+;     *    the FreeRTOS project to continue with its mission of providing     *
+;     *    professional grade, cross platform, de facto standard solutions    *
+;     *    for microcontrollers - completely free of charge!                  *
+;     *                                                                       *
+;     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
+;     *                                                                       *
+;     *    Thank you for using FreeRTOS, and thank you for your support!      *
+;     *                                                                       *
+;    ***************************************************************************
+;
+;
+;    This file is part of the FreeRTOS distribution.
+;
+;    FreeRTOS is free software; you can redistribute it and/or modify it under
+;    the terms of the GNU General Public License (version 2) as published by the
+;    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+;    >>>NOTE<<< The modification to the GPL is included to allow you to
+;    distribute a combined work that includes FreeRTOS without being obliged to
+;    provide the source code for proprietary components outside of the FreeRTOS
+;    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
+;    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+;    more details. You should have received a copy of the GNU General Public
+;    License and the FreeRTOS license exception along with FreeRTOS; if not it
+;    can be viewed here: http://www.freertos.org/a00114.html and also obtained
+;    by writing to Richard Barry, contact details for whom are available on the
+;    FreeRTOS WEB site.
+;
+;    1 tab == 4 spaces!
+;    
+;    ***************************************************************************
+;     *                                                                       *
+;     *    Having a problem?  Start by reading the FAQ "My application does   *
+;     *    not run, what could be wrong?                                      *
+;     *                                                                       *
+;     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+;     *                                                                       *
+;    ***************************************************************************
+;
+;    
+;    http://www.FreeRTOS.org - Documentation, training, latest information, 
+;    license and contact details.
+;    
+;    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+;    including FreeRTOS+Trace - an indispensable productivity tool.
+;
+;    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
+;    the code with commercial support, indemnification, and middleware, under 
+;    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
+;    provide a safety engineered and independently SIL3 certified version under 
+;    the SafeRTOS brand: http://www.SafeRTOS.com.
+;*/
+
+;-------------------------------------------------
+; port to RT-Thread by Grissiom
+;
+		.def	vRegTestTask1
+		.ref	ulRegTest1Counter
+        .ref    rt_thread_delay
+
+		.text
+		.arm
+
+vRegTestTask1:
+		; Fill each general purpose register with a known value.
+		mov		r0,  #0xFF
+		mov		r1,  #0x11
+		mov		r2,  #0x22
+		mov		r3,  #0x33
+		mov     r4,  #0x44		
+		mov     r5,  #0x55
+		mov     r6,  #0x66
+		mov     r7,  #0x77
+		mov     r8,  #0x88
+		mov     r9,  #0x99
+		mov     r10, #0xAA
+		mov     r11, #0xBB
+		mov     r12, #0xCC
+		mov		r14, #0xEE
+
+	.if (__TI_VFP_SUPPORT__)
+		; Fill each FPU register with a known value.
+		vmov 	d0, r0, r1
+		vmov 	d1, r2, r3
+		vmov 	d2, r4, r5
+		vmov 	d3, r6, r7
+		vmov 	d4, r8, r9
+		vmov 	d5, r10, r11
+		vmov 	d6, r0, r1
+		vmov 	d7, r2, r3
+		vmov 	d8, r4, r5
+		vmov 	d9, r6, r7
+		vmov 	d10, r8, r9
+		vmov 	d11, r10, r11
+		vmov 	d12, r0, r1
+		vmov 	d13, r2, r3
+		vmov 	d14, r4, r5
+		vmov 	d15, r6, r7
+	.endif
+
+	
+vRegTestLoop1:
+
+        STMFD  sp!, {r0-r3, r12}
+		; Force yeild
+        MOV r0, #5
+		BL rt_thread_delay
+        LDMFD  sp!, {r0-r3, r12}
+
+	.if (__TI_VFP_SUPPORT__)
+		; Check all the VFP registers still contain the values set above.
+		; First save registers that are clobbered by the test.
+		STMFD sp!, { r0-r1 }
+
+		vmov 	r0, r1, d0
+		cmp 	r0, #0xFF
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x11
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d1
+		cmp 	r0, #0x22
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x33
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d2
+		cmp 	r0, #0x44
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x55
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d3
+		cmp 	r0, #0x66
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x77
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d4
+		cmp 	r0, #0x88
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x99
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d5
+		cmp 	r0, #0xAA
+		bne 	reg1_error_loopf
+		cmp 	r1, #0xBB
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d6
+		cmp 	r0, #0xFF
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x11
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d7
+		cmp 	r0, #0x22
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x33
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d8
+		cmp 	r0, #0x44
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x55
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d9
+		cmp 	r0, #0x66
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x77
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d10
+		cmp 	r0, #0x88
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x99
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d11
+		cmp 	r0, #0xAA
+		bne 	reg1_error_loopf
+		cmp 	r1, #0xBB
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d12
+		cmp 	r0, #0xFF
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x11
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d13
+		cmp 	r0, #0x22
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x33
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d14
+		cmp 	r0, #0x44
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x55
+		bne 	reg1_error_loopf
+		vmov 	r0, r1, d15
+		cmp 	r0, #0x66
+		bne 	reg1_error_loopf
+		cmp 	r1, #0x77
+		bne 	reg1_error_loopf
+
+		; Restore the registers that were clobbered by the test.
+		LDMFD sp!, 	{r0-r1}
+
+		; VFP register test passed.  Jump to the core register test.
+		b 		reg1_loopf_pass
+
+reg1_error_loopf:
+		; If this line is hit then a VFP register value was found to be
+		; incorrect.
+		b reg1_error_loopf
+
+reg1_loopf_pass:
+
+	.endif ;__TI_VFP_SUPPORT__
+
+		; Test each general purpose register to check that it still contains the
+		; expected known value, jumping to vRegTestError1 if any register contains
+		; an unexpected value.
+		cmp		r0, #0xFF
+		bne		vRegTestError1		
+		cmp		r1, #0x11
+		bne		vRegTestError1		
+		cmp		r2, #0x22
+		bne		vRegTestError1		
+		cmp		r3, #0x33
+		bne		vRegTestError1		
+		cmp		r4, #0x44
+		bne		vRegTestError1		
+		cmp		r5, #0x55
+		bne		vRegTestError1		
+		cmp		r6, #0x66
+		bne		vRegTestError1		
+		cmp		r7, #0x77
+		bne		vRegTestError1		
+		cmp		r8, #0x88
+		bne		vRegTestError1		
+		cmp		r9, #0x99
+		bne		vRegTestError1		
+		cmp		r10, #0xAA
+		bne		vRegTestError1		
+		cmp		r11, #0xBB
+		bne		vRegTestError1		
+		cmp		r12, #0xCC
+		bne		vRegTestError1		
+	
+		; This task is still running without jumping to vRegTestError1, so increment
+		; the loop counter so the check task knows the task is running error free.
+		stmfd   sp!, { r0-r1 }
+		ldr		r0, Count1Const
+		ldr		r1, [r0]
+		add		r1, r1, #1
+		str     r1, [r0]
+		ldmfd   sp!, { r0-r1 }
+		
+		; Loop again, performing the same tests.
+		b		vRegTestLoop1
+
+Count1Const	.word	ulRegTest1Counter
+	
+vRegTestError1:
+		b       vRegTestError1
+
+
+;-------------------------------------------------
+;
+		.def	vRegTestTask2
+		.ref	ulRegTest2Counter
+		.text
+		.arm
+;
+vRegTestTask2:
+		; Fill each general purpose register with a known value.
+		mov		r0,  #0xFF000000
+		mov		r1,  #0x11000000
+		mov		r2,  #0x22000000
+		mov		r3,  #0x33000000
+		mov     r4,  #0x44000000		
+		mov     r5,  #0x55000000
+		mov     r6,  #0x66000000
+		mov     r7,  #0x77000000
+		mov     r8,  #0x88000000
+		mov     r9,  #0x99000000
+		mov     r10, #0xAA000000
+		mov     r11, #0xBB000000
+		mov     r12, #0xCC000000
+		mov     r14, #0xEE000000
+	
+	.if (__TI_VFP_SUPPORT__)
+
+		; Fill each FPU register with a known value.
+		vmov 	d0, r0, r1
+		vmov 	d1, r2, r3
+		vmov 	d2, r4, r5
+		vmov 	d3, r6, r7
+		vmov 	d4, r8, r9
+		vmov 	d5, r10, r11
+		vmov 	d6, r0, r1
+		vmov 	d7, r2, r3
+		vmov 	d8, r4, r5
+		vmov 	d9, r6, r7
+		vmov 	d10, r8, r9
+		vmov 	d11, r10, r11
+		vmov 	d12, r0, r1
+		vmov 	d13, r2, r3
+		vmov 	d14, r4, r5
+		vmov 	d15, r6, r7
+	.endif
+
+vRegTestLoop2:
+
+	.if (__TI_VFP_SUPPORT__)
+		; Check all the VFP registers still contain the values set above.
+		; First save registers that are clobbered by the test.
+		STMFD sp!, { r0-r1 }
+
+		vmov r0, r1, d0
+		cmp r0, #0xFF000000
+		bne reg2_error_loopf
+		cmp r1, #0x11000000
+		bne reg2_error_loopf
+		vmov r0, r1, d1
+		cmp r0, #0x22000000
+		bne reg2_error_loopf
+		cmp r1, #0x33000000
+		bne reg2_error_loopf
+		vmov r0, r1, d2
+		cmp r0, #0x44000000
+		bne reg2_error_loopf
+		cmp r1, #0x55000000
+		bne reg2_error_loopf
+		vmov r0, r1, d3
+		cmp r0, #0x66000000
+		bne reg2_error_loopf
+		cmp r1, #0x77000000
+		bne reg2_error_loopf
+		vmov r0, r1, d4
+		cmp r0, #0x88000000
+		bne reg2_error_loopf
+		cmp r1, #0x99000000
+		bne reg2_error_loopf
+		vmov r0, r1, d5
+		cmp r0, #0xAA000000
+		bne reg2_error_loopf
+		cmp r1, #0xBB000000
+		bne reg2_error_loopf
+		vmov r0, r1, d6
+		cmp r0, #0xFF000000
+		bne reg2_error_loopf
+		cmp r1, #0x11000000
+		bne reg2_error_loopf
+		vmov r0, r1, d7
+		cmp r0, #0x22000000
+		bne reg2_error_loopf
+		cmp r1, #0x33000000
+		bne reg2_error_loopf
+		vmov r0, r1, d8
+		cmp r0, #0x44000000
+		bne reg2_error_loopf
+		cmp r1, #0x55000000
+		bne reg2_error_loopf
+		vmov r0, r1, d9
+		cmp r0, #0x66000000
+		bne reg2_error_loopf
+		cmp r1, #0x77000000
+		bne reg2_error_loopf
+		vmov r0, r1, d10
+		cmp r0, #0x88000000
+		bne reg2_error_loopf
+		cmp r1, #0x99000000
+		bne reg2_error_loopf
+		vmov r0, r1, d11
+		cmp r0, #0xAA000000
+		bne reg2_error_loopf
+		cmp r1, #0xBB000000
+		bne reg2_error_loopf
+		vmov r0, r1, d12
+		cmp r0, #0xFF000000
+		bne reg2_error_loopf
+		cmp r1, #0x11000000
+		bne reg2_error_loopf
+		vmov r0, r1, d13
+		cmp r0, #0x22000000
+		bne reg2_error_loopf
+		cmp r1, #0x33000000
+		bne reg2_error_loopf
+		vmov r0, r1, d14
+		cmp r0, #0x44000000
+		bne reg2_error_loopf
+		cmp r1, #0x55000000
+		bne reg2_error_loopf
+		vmov r0, r1, d15
+		cmp r0, #0x66000000
+		bne reg2_error_loopf
+		cmp r1, #0x77000000
+		bne reg2_error_loopf
+
+		; Restore the registers that were clobbered by the test.
+		LDMFD sp!, {r0-r1}
+
+		; VFP register test passed.  Jump to the core register test.
+		b reg2_loopf_pass
+
+reg2_error_loopf:
+		; If this line is hit then a VFP register value was found to be
+		; incorrect.
+		b 	reg2_error_loopf
+
+reg2_loopf_pass:
+
+	.endif ;__TI_VFP_SUPPORT__
+
+		; Test each general purpose register to check that it still contains the
+		; expected known value, jumping to vRegTestError2 if any register contains
+		; an unexpected value.
+		cmp		r0, #0xFF000000
+		bne		vRegTestError2		
+		cmp		r1, #0x11000000
+		bne		vRegTestError2	
+		cmp		r2, #0x22000000
+		bne		vRegTestError2	
+		cmp		r3, #0x33000000
+		bne		vRegTestError2	
+		cmp		r4, #0x44000000
+		bne		vRegTestError2	
+		cmp		r5, #0x55000000
+		bne		vRegTestError2	
+		cmp		r6, #0x66000000
+		bne		vRegTestError2	
+		cmp		r7, #0x77000000
+		bne		vRegTestError2	
+		cmp		r8, #0x88000000
+		bne		vRegTestError2	
+		cmp		r9, #0x99000000
+		bne		vRegTestError2	
+		cmp		r10, #0xAA000000
+		bne		vRegTestError2	
+		cmp		r11, #0xBB000000
+		bne		vRegTestError2	
+		cmp		r12, #0xCC000000
+		bne		vRegTestError2	
+		cmp     r14, #0xEE000000
+		bne		vRegTestError2	
+	
+		; This task is still running without jumping to vRegTestError2, so increment
+		; the loop counter so the check task knows the task is running error free.
+		stmfd   sp!, { r0-r1 }
+		ldr		r0, Count2Const
+		ldr		r1, [r0]
+		add		r1, r1, #1
+		str     r1, [r0]
+		ldmfd   sp!, { r0-r1 }
+		
+		; Loop again, performing the same tests.
+		b		vRegTestLoop2
+
+Count2Const	.word	ulRegTest2Counter
+	
+vRegTestError2:
+		b       vRegTestError2
+
+;-------------------------------------------------
+	
+	
+	
diff --git a/bsp/rm48x50/application/startup.c b/bsp/rm48x50/application/startup.c
new file mode 100644
index 0000000000000000000000000000000000000000..72d4ed795b34b729acf13b8f27a78f88ea2de629
--- /dev/null
+++ b/bsp/rm48x50/application/startup.c
@@ -0,0 +1,117 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2008-12-11     xuxinming    first version
+ * 2010-4-3       LiJin        add init soft timer thread
+ * 2013-05-24     Grissiom     port to RM48x50
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+extern void finsh_system_init(void);
+#endif
+
+#include <board.h>
+
+/**
+ * @addtogroup LPC2478
+ */
+/*@{*/
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_DEVICE
+extern rt_err_t rt_hw_serial_init(void);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif defined(__GNUC__)
+extern int __bss_end;
+#elif defined(__TI_COMPILER_VERSION__)
+extern unsigned char * const system_data_end;
+#endif
+#define MEMEND 0x08040000
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init hardware interrupt */
+	rt_hw_interrupt_init();
+
+	/* init board */
+	rt_hw_board_init();
+
+	/* init tick */
+	rt_system_tick_init();
+
+	/* init kernel object */
+	rt_system_object_init();
+
+	rt_show_version();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+	/* init memory system */
+#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)MEMEND);
+#elif defined(__GNUC__)
+    rt_system_heap_init((void*)&__bss_end, (void*)MEMEND);
+#elif defined(__TI_COMPILER_VERSION__)
+    rt_system_heap_init((void*)&system_data_end, (void*)MEMEND);
+#else
+#error Unkown compiler
+#endif
+#endif
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+	/* init application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* init finsh */
+	finsh_system_init();
+	finsh_set_device("sci2");
+#endif
+
+	/* init soft timer thread */
+	rt_system_timer_thread_init();
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}
+
+int main(void)
+{
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+	/* invoke rtthread_startup */
+	rtthread_startup();
+
+	return 0;
+}
+
+/*@}*/
diff --git a/bsp/rm48x50/drivers/SConscript b/bsp/rm48x50/drivers/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..a630c8a7c407f13071e80ddbae48db5b12a32046
--- /dev/null
+++ b/bsp/rm48x50/drivers/SConscript
@@ -0,0 +1,22 @@
+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_LWIP') == False:
+    src_need_remove = ['dm9000.c'] # need remove file list.
+    SrcRemove(src, src_need_remove)
+
+if GetDepend('RT_USING_DFS') == False:
+    src_need_remove = ['sd.c'] # need remove file list.
+    SrcRemove(src, src_need_remove)
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/rm48x50/drivers/board.c b/bsp/rm48x50/drivers/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..2ff930ce1108823795736912dacb2353263d0fe3
--- /dev/null
+++ b/bsp/rm48x50/drivers/board.c
@@ -0,0 +1,47 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-27     Grissiom     port to RM48x50
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "sys_common.h"
+#include "system.h"
+#include "rti.h"
+
+#include "board.h"
+
+#include "drv_uart.h"
+
+#define RTI_INT_VEC 6
+
+void rt_timer_handler(int vector, void* param)
+{
+    rtiREG1->INTFLAG = 8U; /* clear interrupt flag */
+	rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    rtiInit();
+
+	rt_hw_interrupt_install(RTI_INT_VEC, rt_timer_handler, RT_NULL, "tick");
+    rt_hw_interrupt_umask(RTI_INT_VEC);
+
+    rtiStartCounter(rtiCOUNTER_BLOCK1);
+    rtiEnableNotification(rtiNOTIFICATION_COMPARE3);
+
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
diff --git a/bsp/rm48x50/drivers/board.h b/bsp/rm48x50/drivers/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..6271d451404e4c8b7218d57eceb2eda73d27bdcd
--- /dev/null
+++ b/bsp/rm48x50/drivers/board.h
@@ -0,0 +1,123 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2008-12-11     xuxinming    first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+/* RT_USING_UART */
+#define RT_USING_UART1
+#define RT_USING_UART2
+#define RT_UART_RX_BUFFER_SIZE	64
+void rt_hw_board_init(void);
+void rt_hw_led_set(rt_uint32_t led);
+void rt_hw_led_flash(void);
+
+#ifdef RT_USING_FINSH
+void rt_hw_finsh_init(void);
+#endif
+
+#define	USE_USB					0
+
+#if USE_USB		/* 1 is USB, 0 is non-USB related */  
+#define PLL_MValue			11
+#define PLL_NValue			0
+#define CCLKDivValue		4
+#define USBCLKDivValue		5
+
+#define Fosc	12000000
+#define Fcclk	57600000
+#define Fcco	288000000
+#else
+
+#define PLL_MValue			12
+#define PLL_NValue			1
+#define CCLKDivValue		5
+
+#define Fosc	12000000
+#define Fcclk	72000000
+#define Fcco	360000000
+
+#endif
+
+#if USE_USB
+#define Fpclk	(Fcclk / 2)
+#else
+#define Fpclk	(Fcclk / 4)
+#endif
+
+/* IRQ define */
+#define SYS32Mode		0x1F
+#define IRQ32Mode		0x12
+#define FIQ32Mode		0x11
+
+#define HIGHEST_PRIORITY	0x01
+#define LOWEST_PRIORITY		0x0F
+
+#define	WDT_INT			0
+#define SWI_INT			1
+#define ARM_CORE0_INT	2
+#define	ARM_CORE1_INT	3
+#define	TIMER0_INT		4
+#define TIMER1_INT		5
+#define UART0_INT		6
+#define	UART1_INT		7
+#define	PWM0_1_INT		8
+#define I2C0_INT		9
+#define SPI0_INT		10			/* SPI and SSP0 share VIC slot */
+#define SSP0_INT		10
+#define	SSP1_INT		11
+#define	PLL_INT			12
+#define RTC_INT			13
+#define EINT0_INT		14
+#define EINT1_INT		15
+#define EINT2_INT		16
+#define EINT3_INT		17
+#define	ADC0_INT		18
+#define I2C1_INT		19
+#define BOD_INT			20
+#define EMAC_INT		21
+#define USB_INT			22
+#define CAN_INT			23
+#define MCI_INT			24
+#define GPDMA_INT		25
+#define TIMER2_INT		26
+#define TIMER3_INT		27
+#define UART2_INT		28
+#define UART3_INT		29
+#define I2C2_INT		30
+#define I2S_INT			31
+
+#define VIC_SIZE		32
+
+#define VECT_ADDR_INDEX	0x100
+#define VECT_CNTL_INDEX 0x200
+
+#define CCLK	60000000	/* Fosc = 12MHz, M = 5 */
+#define PCLK	15000000	/* CCLK/4, use default */
+
+/******************************************************************************
+** Function name:		TargetInit
+**
+** Descriptions:		Initialize the target board; it is called in a 
+**				necessary place, change it as needed
+**
+** parameters:			None
+** Returned value:		None
+**
+******************************************************************************/
+extern void TargetInit(void);
+extern void ConfigurePLL( void );
+extern void TargetResetInit(void);
+
+#endif
diff --git a/bsp/rm48x50/drivers/drv_uart.c b/bsp/rm48x50/drivers/drv_uart.c
new file mode 100644
index 0000000000000000000000000000000000000000..3f0237e64851b2335e489c2c7f0b87ea937e747d
--- /dev/null
+++ b/bsp/rm48x50/drivers/drv_uart.c
@@ -0,0 +1,210 @@
+/*
+ * File      : uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-27     Grissiom     port to RM48x50
+ */
+
+/* welcome, if you open this file, you may want to see uart driver code.
+ * However, TI call it Serial Communication Interface(SCI) and all the low
+ * level API is prefixed by "sci". To avoid messive renaming, I want to keep
+ * with TI and call all the things SCI. You could safely substitude the word
+ * "sci" with "uart". Enjoy. */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <reg_sci.h>
+
+/* bring from sci.h */
+enum sciIntFlags
+{
+    SCI_FE_INT    = 0x04000000U,  /* framing error */
+    SCI_OE_INT    = 0x02000000U,  /* overrun error */
+    SCI_PE_INT    = 0x01000000U,  /* parity error */
+    SCI_RX_INT    = 0x00000200U,  /* receive buffer ready */
+    SCI_TX_INT    = 0x00000100U,  /* transmit buffer ready */
+    SCI_WAKE_INT  = 0x00000002U,  /* wakeup */
+    SCI_BREAK_INT = 0x00000001U   /* break detect */
+};
+
+/* LIN1 High level interrupt. Change this if you set a different channel in
+ * HALCoGen. */
+#define SCI_INT_VEC 14
+
+#define VCLK_HZ 100000000L
+
+static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    /** - global control 1 */
+    rt_uint32_t gcr1 = (1U << 25U)  /* enable transmit */
+                       | (1U << 24U)  /* enable receive */
+                       | (1U << 5U)   /* internal clock (device has no clock pin) */
+                       | (1U << 1U);  /* asynchronous timing mode */
+    if (cfg->stop_bits == STOP_BITS_2)
+        gcr1 |= (1U << 4U);  /* number of stop bits */
+    else if (cfg->stop_bits != STOP_BITS_1)
+        return -RT_ERROR;
+
+    if (cfg->parity == PARITY_EVEN)
+    {
+        gcr1 |= (1U << 3U) | (1U << 2U);
+    }
+    else if (cfg->parity == PARITY_ODD)
+    {
+        gcr1 |= (0U << 3U) | (1U << 2U);
+    }
+
+    /** - bring SCI out of reset */
+    scilinREG->GCR0 = 1U;
+
+    /** - Disable all interrupts */
+    scilinREG->CLRINT    = 0xFFFFFFFFU;
+    scilinREG->CLRINTLVL = 0xFFFFFFFFU;
+
+    scilinREG->GCR1 = gcr1;
+
+    /** - set baudrate */
+    scilinREG->BRS = VCLK_HZ/16/cfg->baud_rate - 1;  /* baudrate */
+
+    /** - transmission length */
+    scilinREG->FORMAT = cfg->data_bits - 1;  /* length */
+
+    /** - set SCI pins functional mode */
+    scilinREG->FUN = (1U << 2U)  /* tx pin */
+                 | (1U << 1U)  /* rx pin */
+                 | (0U);  /* clk pin */
+
+    /** - set SCI pins default output value */
+    scilinREG->DOUT = (0U << 2U)  /* tx pin */
+                  | (0U << 1U)  /* rx pin */
+                  | (0U);  /* clk pin */
+
+    /** - set SCI pins output direction */
+    scilinREG->DIR = (0U << 2U)  /* tx pin */
+                 | (0U << 1U)  /* rx pin */
+                 | (0U);  /* clk pin */
+
+    /** - set SCI pins open drain enable */
+    scilinREG->ODR = (0U << 2U)  /* tx pin */
+                 | (0U << 1U)  /* rx pin */
+                 | (0U);  /* clk pin */
+
+    /** - set SCI pins pullup/pulldown enable */
+    scilinREG->PD = (0U << 2U)  /* tx pin */
+                | (0U << 1U)  /* rx pin */
+                | (0U);  /* clk pin */
+
+    /** - set SCI pins pullup/pulldown select */
+    scilinREG->PSL = (1U << 2U)  /* tx pin */
+                 | (1U << 1U)  /* rx pin */
+                 | (1U);  /* clk pin */
+
+    /** - set interrupt level */
+    scilinREG->SETINTLVL = (0U << 26U)  /* Framing error */
+                       | (0U << 25U)  /* Overrun error */
+                       | (0U << 24U)  /* Parity error */
+                       | (0U << 9U)  /* Receive */
+                       | (0U << 8U)  /* Transmit */
+                       | (0U << 1U)  /* Wakeup */
+                       | (0U);  /* Break detect */
+
+    /** - set interrupt enable */
+    scilinREG->SETINT = (0U << 26U)  /* Framing error */
+                    | (0U << 25U)  /* Overrun error */
+                    | (0U << 24U)  /* Parity error */
+                    | (1U << 9U)  /* Receive */
+                    | (0U << 1U)  /* Wakeup */
+                    | (0U);  /* Break detect */
+
+    /** - Finaly start SCILIN */
+    scilinREG->GCR1 |= (1U << 7U);
+
+    return RT_EOK;
+}
+
+static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    sciBASE_t *sci = (sciBASE_t*)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        sci->CLRINT = SCI_RX_INT;
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        sci->SETINT = SCI_RX_INT;
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int _putc(struct rt_serial_device *serial, char c)
+{
+    sciBASE_t *sci = (sciBASE_t*)serial->parent.user_data;
+    while ((sci->FLR & SCI_TX_INT) == 0U)
+        ;
+    sci->TD = c;
+    return 1;
+}
+
+static int _getc(struct rt_serial_device *serial)
+{
+    sciBASE_t *sci = (sciBASE_t*)serial->parent.user_data;
+    if (sci->FLR & (1<<9))
+        return (sci->RD & 0x000000FFU);
+    else
+        return -1;
+}
+
+static const struct rt_uart_ops _sci_ops =
+{
+    _configure,
+    _control,
+    _putc,
+    _getc,
+};
+
+static void _irq_wrapper(int vector, void *param)
+{
+    rt_hw_serial_isr((struct rt_serial_device*)param);
+}
+
+static struct rt_serial_device _sci2_serial;
+static struct serial_ringbuffer _sci2_int_rx;
+
+void rt_hw_uart_init(void)
+{
+    struct serial_configure config;
+
+    /* fake configuration */
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    _sci2_serial.ops    = &_sci_ops;
+    _sci2_serial.int_rx = &_sci2_int_rx;
+    _sci2_serial.config = config;
+
+    rt_hw_serial_register(&_sci2_serial, "sci2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          (void*)scilinREG);
+
+    rt_device_control(&_sci2_serial.parent, RT_DEVICE_CTRL_SET_INT, 0);
+    rt_hw_interrupt_install(SCI_INT_VEC, _irq_wrapper, &_sci2_serial, "sci2");
+    rt_hw_interrupt_umask(SCI_INT_VEC);
+}
diff --git a/bsp/rm48x50/drivers/drv_uart.h b/bsp/rm48x50/drivers/drv_uart.h
new file mode 100644
index 0000000000000000000000000000000000000000..8bfa1489e518d6f66e66a97549554a0aae4a10f4
--- /dev/null
+++ b/bsp/rm48x50/drivers/drv_uart.h
@@ -0,0 +1,6 @@
+#ifndef DRV_UART_H
+#define DRV_UART_H
+
+void rt_hw_uart_init(void);
+
+#endif /* end of include guard: DRV_UART_H */
diff --git a/bsp/rm48x50/rtconfig.h b/bsp/rm48x50/rtconfig.h
new file mode 100644
index 0000000000000000000000000000000000000000..86fc630c8cd86e157987012899fc5ace7a96ef53
--- /dev/null
+++ b/bsp/rm48x50/rtconfig.h
@@ -0,0 +1,217 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX	6
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE	4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX	32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
+#define RT_TICK_PER_SECOND	100
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE	512
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
+// #define RT_THREAD_DEBUG
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+// #define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO	4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE	512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND	10
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+#define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    64
+// </section>
+
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME	"sci2"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE	4096
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
+// #define RT_USING_NEWLIB
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+// #define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+// #define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+// #define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX	2
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX	4
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN1">1</item>
+// <item description="LFN1">2</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN	1
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
+#define RT_DFS_ELM_MAX_LFN	64
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+// #define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
+// #define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
+#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+// </section>
+
+// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
+#define RT_USING_LWIP
+// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
+#define RT_USING_LWIP141
+// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_LWIP_ICMP
+// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
+// #define RT_LWIP_IGMP
+// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_UDP
+// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
+#define RT_LWIP_TCP
+// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
+#define RT_LWIP_DNS
+// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
+#define RT_LWIP_PBUF_NUM	4
+// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
+#define RT_LWIP_TCP_PCB_NUM	3
+// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
+#define RT_LWIP_TCP_SND_BUF	2048
+// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
+#define RT_LWIP_TCP_WND	2048
+// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
+// #define RT_LWIP_SNMP
+// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
+// #define RT_LWIP_DHCP
+// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
+#define RT_LWIP_TCP_SEG_NUM	4
+// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
+#define RT_LWIP_TCPTHREAD_PRIORITY	12
+// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
+#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
+#define RT_LWIP_ETHTHREAD_PRIORITY	14
+// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
+#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+// </section>
+
+// <section name="RT_USING_RTGUI" description="RT-Thread/GUI" default="true" >
+// #define RT_USING_RTGUI
+// <integer name="RTGUI_NAME_MAX" description="the name size of RT-Thread/GUI widget/objects" default="12" />
+#define RTGUI_NAME_MAX	12
+// <bool name="RTGUI_USING_SMALL_SIZE" description="use small size in RT-Thread/GUI" default="true" />
+#define RTGUI_USING_SMALL_SIZE
+// <bool name="RTGUI_USING_FONT16" description="support 16 weight font" default="true" />
+#define RTGUI_USING_FONT16
+// <bool name="RTGUI_USING_FONT12" description="support 12 weight font" default="true" />
+// #define RTGUI_USING_FONT12
+// <bool name="RTGUI_USING_FONTHZ" description="support Chinese font" default="true" />
+#define RTGUI_USING_FONTHZ
+// <integer name="RTGUI_DEFAULT_FONT_SIZE" description="default font size in RT-Thread/GUI" default="16" />
+#define RTGUI_DEFAULT_FONT_SIZE	16
+// <bool name="RTGUI_USING_DFS_FILERW" description="use RT-Thread/DFS as file interface" default="true" />
+// #define RTGUI_USING_DFS_FILERW
+// <bool name="RTGUI_USING_HZ_BMP" description="use Chinese font bitmap engine" default="true" />
+#define RTGUI_USING_HZ_BMP
+// <bool name="RTGUI_USING_HZ_FILE" description="use font file as Chinese font" default="false" />
+// #define RTGUI_USING_HZ_FILE
+// <bool name="RTGUI_USING_MOUSE_CURSOR" description="use mouse cursor" default="false" />
+// #define RTGUI_USING_MOUSE_CURSOR
+// </section>
+
+#define RT_VFP_LAZY_STACKING
+// </RDTConfigurator>
+
+#endif
diff --git a/components/finsh/finsh.h b/components/finsh/finsh.h
index adb2f096250961284eb3e7a1fba62437bd32a7f0..99851e8d36b9a51a49b9d4c73d16de5707d6bfef 100644
--- a/components/finsh/finsh.h
+++ b/components/finsh/finsh.h
@@ -176,6 +176,13 @@ extern struct finsh_sysvar_item* global_sysvar_list;
 struct finsh_sysvar* finsh_sysvar_lookup(const char* name);
 
 #ifdef FINSH_USING_SYMTAB
+
+#ifdef __TI_COMPILER_VERSION__
+#define _EMIT_PRAGMA(x)                _Pragma(#x)
+#define __TI_FINSH_EXPORT_FUNCTION(f)  _EMIT_PRAGMA(DATA_SECTION(f,"FSymTab"))
+#define __TI_FINSH_EXPORT_VAR(v)       _EMIT_PRAGMA(DATA_SECTION(v,"VSymTab"))
+#endif
+
 	#ifdef FINSH_USING_DESCRIPTION
 		/**
 		 * @ingroup finsh
@@ -185,28 +192,39 @@ struct finsh_sysvar* finsh_sysvar_lookup(const char* name);
 		 * @param name the name of function.
 		 * @param desc the description of function, which will show in help.
 		 */
-#ifdef _MSC_VER
-		#define FINSH_FUNCTION_EXPORT(name, desc)					 \
-		const char __fsym_##name##_name[] = #name;					 \
-		const char __fsym_##name##_desc[] = #desc;					 \
-		__declspec(allocate("FSymTab$f")) const struct finsh_syscall __fsym_##name = \
-		{							\
-			__fsym_##name##_name,	\
-			__fsym_##name##_desc,	\
-			(syscall_func)&name		\
-		};
-		#pragma comment(linker, "/merge:FSymTab=mytext")
-#else
-		#define FINSH_FUNCTION_EXPORT(name, desc)					 \
-		const char __fsym_##name##_name[] = #name;					 \
-		const char __fsym_##name##_desc[] = #desc;					 \
-		const struct finsh_syscall __fsym_##name SECTION("FSymTab")= \
-		{							\
-			__fsym_##name##_name,	\
-			__fsym_##name##_desc,	\
-			(syscall_func)&name		\
-		};
-#endif
+        #ifdef _MSC_VER
+            #define FINSH_FUNCTION_EXPORT(name, desc)					 \
+            const char __fsym_##name##_name[] = #name;					 \
+            const char __fsym_##name##_desc[] = #desc;					 \
+            __declspec(allocate("FSymTab$f")) const struct finsh_syscall __fsym_##name = \
+            {							\
+                __fsym_##name##_name,	\
+                __fsym_##name##_desc,	\
+                (syscall_func)&name		\
+            };
+            #pragma comment(linker, "/merge:FSymTab=mytext")
+        #elif defined(__TI_COMPILER_VERSION__)
+            #define FINSH_FUNCTION_EXPORT(name, desc)     \
+            __TI_FINSH_EXPORT_FUNCTION(__fsym_##name);             \
+            const char __fsym_##name##_name[] = #name;				   \
+            const char __fsym_##name##_desc[] = #desc;				   \
+            const struct finsh_syscall __fsym_##name = \
+            {							\
+                __fsym_##name##_name,	\
+                __fsym_##name##_desc,	\
+                (syscall_func)&name		\
+            };
+        #else
+            #define FINSH_FUNCTION_EXPORT(name, desc)					 \
+            const char __fsym_##name##_name[] = #name;					 \
+            const char __fsym_##name##_desc[] = #desc;					 \
+            const struct finsh_syscall __fsym_##name SECTION("FSymTab")= \
+            {							\
+                __fsym_##name##_name,	\
+                __fsym_##name##_desc,	\
+                (syscall_func)&name		\
+            };
+        #endif /* FINSH_FUNCTION_EXPORT defines */
 
 		/**
 		 * @ingroup finsh
@@ -217,27 +235,38 @@ struct finsh_sysvar* finsh_sysvar_lookup(const char* name);
 		 * @param alias the alias name of function.
 		 * @param desc the description of function, which will show in help.
 		 */
-#ifdef _MSC_VER
-		#define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)		\
-		const char __fsym_##name##_name[] = #alias;					 \
-		const char __fsym_##name##_desc[] = #desc;					 \
-		__declspec(allocate("FSymTab$f")) const struct finsh_syscall __fsym_##name = \
-		{							\
-			__fsym_##name##_name,	\
-			__fsym_##name##_desc,	\
-			(syscall_func)&name		\
-		};
-#else
-		#define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)		\
-		const char __fsym_##name##_name[] = #alias;					 \
-		const char __fsym_##name##_desc[] = #desc;					 \
-		const struct finsh_syscall __fsym_##name SECTION("FSymTab")= \
-		{							\
-			__fsym_##name##_name,	\
-			__fsym_##name##_desc,	\
-			(syscall_func)&name		\
-		};
-#endif
+        #ifdef _MSC_VER
+            #define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)		\
+            const char __fsym_##name##_name[] = #alias;					 \
+            const char __fsym_##name##_desc[] = #desc;					 \
+            __declspec(allocate("FSymTab$f")) const struct finsh_syscall __fsym_##name = \
+            {							\
+                __fsym_##name##_name,	\
+                __fsym_##name##_desc,	\
+                (syscall_func)&name		\
+            };
+        #elif defined(__TI_COMPILER_VERSION__)
+            #define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)     \
+            __TI_FINSH_EXPORT_FUNCTION(__fsym_##name);             \
+            const char __fsym_##name##_name[] = #alias;				   \
+            const char __fsym_##name##_desc[] = #desc;				   \
+            const struct finsh_syscall __fsym_##name = \
+            {							\
+                __fsym_##name##_name,	\
+                __fsym_##name##_desc,	\
+                (syscall_func)&name		\
+            };
+        #else
+            #define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)		\
+            const char __fsym_##name##_name[] = #alias;					 \
+            const char __fsym_##name##_desc[] = #desc;					 \
+            const struct finsh_syscall __fsym_##name SECTION("FSymTab")= \
+            {							\
+                __fsym_##name##_name,	\
+                __fsym_##name##_desc,	\
+                (syscall_func)&name		\
+            };
+        #endif /* FINSH_FUNCTION_EXPORT_ALIAS defines */
 		/**
 		 * @ingroup finsh
 		 *
@@ -247,55 +276,98 @@ struct finsh_sysvar* finsh_sysvar_lookup(const char* name);
 		 * @param type the type of variable.
 		 * @param desc the description of function, which will show in help.
 		 */
-#ifdef _MSC_VER
-		#define FINSH_VAR_EXPORT(name, type, desc)					\
-		const char __vsym_##name##_name[] = #name;					\
-		const char __vsym_##name##_desc[] = #desc;					\
-		__declspec(allocate("VSymTab")) const struct finsh_sysvar __vsym_##name = \
-		{							\
-			__vsym_##name##_name,	\
-			__vsym_##name##_desc,	\
-			type, 					\
-			(void*)&name			\
-		};
-#else
-		#define FINSH_VAR_EXPORT(name, type, desc)					\
-		const char __vsym_##name##_name[] = #name;					\
-		const char __vsym_##name##_desc[] = #desc;					\
-		const struct finsh_sysvar __vsym_##name SECTION("VSymTab")=	\
-		{							\
-			__vsym_##name##_name,	\
-			__vsym_##name##_desc,	\
-			type, 					\
-			(void*)&name			\
-		};
-#endif
-	#else
-		#define FINSH_FUNCTION_EXPORT(name, desc)					 \
-		const char __fsym_##name##_name[] = #name;					 \
-		const struct finsh_syscall __fsym_##name SECTION("FSymTab")= \
-		{							\
-			__fsym_##name##_name,	\
-			(syscall_func)&name		\
-		};
-
-		#define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)		\
-		const char __fsym_##name##_name[] = #alias;					 \
-		const struct finsh_syscall __fsym_##name SECTION("FSymTab")= \
-		{							\
-			__fsym_##name##_name,	\
-			(syscall_func)&name		\
-		};
-
-		#define FINSH_VAR_EXPORT(name, type, desc)					\
-		const char __vsym_##name##_name[] = #name;					\
-		const struct finsh_sysvar __vsym_##name SECTION("VSymTab")=	\
-		{							\
-			__vsym_##name##_name,	\
-			type, 					\
-			(void*)&name			\
-		};
-	#endif
+        #ifdef _MSC_VER
+            #define FINSH_VAR_EXPORT(name, type, desc)					\
+            const char __vsym_##name##_name[] = #name;					\
+            const char __vsym_##name##_desc[] = #desc;					\
+            __declspec(allocate("VSymTab")) const struct finsh_sysvar __vsym_##name = \
+            {							\
+                __vsym_##name##_name,	\
+                __vsym_##name##_desc,	\
+                type, 					\
+                (void*)&name			\
+            };
+        #elif defined(__TI_COMPILER_VERSION__)
+            #define FINSH_VAR_EXPORT(name, type, desc)					\
+            __TI_FINSH_EXPORT_VAR(__vsym_##name);              \
+            const char __vsym_##name##_name[] = #name;					\
+            const char __vsym_##name##_desc[] = #desc;					\
+            const struct finsh_sysvar __vsym_##name = \
+            {							\
+                __vsym_##name##_name,	\
+                __vsym_##name##_desc,	\
+                type,					\
+                (void*)&name			\
+            };
+        #else
+            #define FINSH_VAR_EXPORT(name, type, desc)					\
+            const char __vsym_##name##_name[] = #name;					\
+            const char __vsym_##name##_desc[] = #desc;					\
+            const struct finsh_sysvar __vsym_##name SECTION("VSymTab")=	\
+            {							\
+                __vsym_##name##_name,	\
+                __vsym_##name##_desc,	\
+                type, 					\
+                (void*)&name			\
+            };
+        #endif /* FINSH_VAR_EXPORT defines */
+	#else /* FINSH_USING_DESCRIPTION */
+        #if defined(__TI_COMPILER_VERSION__)
+            #define FINSH_FUNCTION_EXPORT(name, desc)     \
+            __TI_FINSH_EXPORT_FUNCTION(__fsym_##name);             \
+            const char __fsym_##name##_name[] = #name;				   \
+            const char __fsym_##name##_desc[] = #desc;				   \
+            const struct finsh_syscall __fsym_##name = \
+            {							\
+                __fsym_##name##_name,	\
+                __fsym_##name##_desc,	\
+                (syscall_func)&name		\
+            };
+            #define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)		\
+            const char __fsym_##name##_name[] = #alias;					 \
+            __TI_FINSH_EXPORT_FUNCTION(__fsym_##name);             \
+            const struct finsh_syscall __fsym_##name = \
+            {							\
+                __fsym_##name##_name,	\
+                (syscall_func)&name		\
+            };
+
+            #define FINSH_VAR_EXPORT(name, type, desc)					\
+            __TI_FINSH_EXPORT_VAR(__vsym_##name);             \
+            const char __vsym_##name##_name[] = #name;					\
+            const struct finsh_sysvar __vsym_##name =	\
+            {							\
+                __vsym_##name##_name,	\
+                type,					\
+                (void*)&name			\
+            };
+        #else
+            #define FINSH_FUNCTION_EXPORT(name, desc)					 \
+            const char __fsym_##name##_name[] = #name;					 \
+            const struct finsh_syscall __fsym_##name SECTION("FSymTab")= \
+            {							\
+                __fsym_##name##_name,	\
+                (syscall_func)&name		\
+            };
+
+            #define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)		\
+            const char __fsym_##name##_name[] = #alias;					 \
+            const struct finsh_syscall __fsym_##name SECTION("FSymTab")= \
+            {							\
+                __fsym_##name##_name,	\
+                (syscall_func)&name		\
+            };
+
+            #define FINSH_VAR_EXPORT(name, type, desc)					\
+            const char __vsym_##name##_name[] = #name;					\
+            const struct finsh_sysvar __vsym_##name SECTION("VSymTab")=	\
+            {							\
+                __vsym_##name##_name,	\
+                type,					\
+                (void*)&name			\
+            };
+        #endif /* __TI_COMPILER_VERSION__ */
+    #endif /* FINSH_USING_DESCRIPTION */
 #else
 	#define FINSH_FUNCTION_EXPORT(name, desc)
 	#define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc)
diff --git a/components/finsh/shell.c b/components/finsh/shell.c
index de6132c1aba55b3ee2b8f54195113d43af34a529..08dfc2b21a2c5824573f6bcb2784464fc11d46a9 100644
--- a/components/finsh/shell.c
+++ b/components/finsh/shell.c
@@ -528,7 +528,8 @@ void finsh_system_init(void)
                                __section_end("FSymTab"));
     finsh_system_var_init(__section_begin("VSymTab"),
                           __section_end("VSymTab"));
-#elif defined (__GNUC__)        /* GNU GCC Compiler */
+#elif defined (__GNUC__) || defined(__TI_COMPILER_VERSION__)
+    /* GNU GCC Compiler and TI CCS */
 	extern const int __fsymtab_start;
 	extern const int __fsymtab_end;
 	extern const int __vsymtab_start;
diff --git a/include/rtdef.h b/include/rtdef.h
index a0497517b11659c673e7671527b1b47cc9168ec3..b2267292cc21cd2451be03a78fc6bf53eac070ae 100644
--- a/include/rtdef.h
+++ b/include/rtdef.h
@@ -145,6 +145,17 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define ALIGN(n)                    __declspec(align(n))
     #define rt_inline                   static __inline
     #define RTT_API
+#elif defined (__TI_COMPILER_VERSION__)
+    /* The way that TI compiler set section is different from other(at least
+     * GCC and MDK) compilers. See ARM Optimizing C/C++ Compiler 5.9.3 for more
+     * details. */
+    #define SECTION(x)
+    #define UNUSED
+    #define ALIGN(n)
+    #define rt_inline                   static inline
+    #define RTT_API
+#else
+    #error not supported tool chain
 #endif
 
 /* event length */
diff --git a/include/rtthread.h b/include/rtthread.h
index 4b81464f181f6c2e9ce86546efc2918dab08768a..cc1d90fe91147f95113dc5083af2af8f8586f9c1 100644
--- a/include/rtthread.h
+++ b/include/rtthread.h
@@ -19,7 +19,7 @@
 
 #ifndef __RT_THREAD_H__
 #define __RT_THREAD_H__
-
+    #include <stdarg.h>
 #include <rtdef.h>
 #include <rtdebug.h>
 #include <rtservice.h>
diff --git a/libcpu/arm/cortex-r4/RM48x50.h b/libcpu/arm/cortex-r4/RM48x50.h
new file mode 100644
index 0000000000000000000000000000000000000000..9f4bcc976fd00ff9ec637226e67ce6e5d76116d0
--- /dev/null
+++ b/libcpu/arm/cortex-r4/RM48x50.h
@@ -0,0 +1,39 @@
+#ifndef RM48X50_H
+#define RM48X50_H
+
+#include <system.h>
+#include <sys_vim.h>
+
+#define USERMODE	0x10
+#define FIQMODE		0x11
+#define IRQMODE		0x12
+#define SVCMODE		0x13
+#define ABORTMODE	0x17
+#define UNDEFMODE	0x1b
+#define MODEMASK	0x1f
+#define NOINT		0xc0
+
+struct rt_hw_register
+{
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long sp;
+	unsigned long lr;
+	unsigned long pc;
+	unsigned long cpsr;
+	unsigned long ORIG_r0;
+};
+
+#endif /* end of include guard: RM48X50_H */
+
diff --git a/libcpu/arm/cortex-r4/context_ccs.asm b/libcpu/arm/cortex-r4/context_ccs.asm
new file mode 100644
index 0000000000000000000000000000000000000000..dc4113f5e47bb7b8f4afc46b0d93dbb6639436e6
--- /dev/null
+++ b/libcpu/arm/cortex-r4/context_ccs.asm
@@ -0,0 +1,254 @@
+;/*
+; * File      : context_ccs.asm
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date       Author       Notes
+; * 2009-01-20     Bernard      first version
+; * 2011-07-22     Bernard      added thumb mode porting
+; * 2013-05-24     Grissiom     port to CCS
+; * 2013-05-26     Grissiom     optimize for ARMv7
+; */
+
+   .text
+   .arm
+   .ref rt_thread_switch_interrupt_flag
+   .ref rt_interrupt_from_thread
+   .ref rt_interrupt_to_thread
+   .ref rt_interrupt_enter
+   .ref rt_interrupt_leave
+   .ref rt_hw_trap_irq
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+    .def rt_hw_interrupt_disable
+rt_hw_interrupt_disable
+    MRS r0, cpsr
+    CPSID IF
+    BX  lr
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+    .def rt_hw_interrupt_enable
+rt_hw_interrupt_enable
+    MSR cpsr_c, r0
+    BX  lr
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+    .def rt_hw_context_switch
+rt_hw_context_switch
+    STMDB   sp!, {lr}           ; push pc (lr should be pushed in place of PC)
+    STMDB   sp!, {r0-r12, lr}   ; push lr & register file
+
+    MRS     r4, cpsr
+    TST     lr, #0x01
+    ORRNE   r4, r4, #0x20       ; it's thumb code
+
+    STMDB   sp!, {r4}           ; push cpsr
+
+    .if (__TI_VFP_SUPPORT__)
+		VMRS    r4,  fpexc
+        TST     r4,  #0x40000000
+        BEQ     __no_vfp_frame1
+		VSTMDB  sp!, {d0-d15}
+        VMRS    r5, fpscr
+        ; TODO: add support for Common VFPv3.
+        ;       Save registers like FPINST, FPINST2
+        STMDB   sp!, {r5}
+__no_vfp_frame1
+        STMDB   sp!, {r4}
+	.endif
+
+    STR     sp, [r0]            ; store sp in preempted tasks TCB
+    LDR     sp, [r1]            ; get new task stack pointer
+
+    .if (__TI_VFP_SUPPORT__)
+        LDMIA   sp!, {r0}       ; get fpexc
+        VMSR    fpexc,  r0      ; restore fpexc
+        TST     r0,  #0x40000000
+        BEQ     __no_vfp_frame2
+        LDMIA   sp!, {r1}       ; get fpscr
+        VMSR    fpscr, r1
+		VLDMIA  sp!, {d0-d15}
+__no_vfp_frame2
+    .endif
+
+    LDMIA   sp!, {r4}           ; pop new task cpsr to spsr
+    MSR     spsr_cxsf, r4
+
+    LDMIA   sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; */
+    .def rt_hw_context_switch_to
+rt_hw_context_switch_to
+    LDR     sp, [r0]            ; get new task stack pointer
+
+    .if (__TI_VFP_SUPPORT__)
+        LDMIA   sp!, {r0}       ; get fpexc
+        VMSR    fpexc, r0
+        TST     r0,  #0x40000000
+        BEQ     __no_vfp_frame_to
+        LDMIA   sp!, {r1}       ; get fpscr
+        VMSR    fpscr, r1
+		VLDMIA  sp!, {d0-d15}
+__no_vfp_frame_to
+    .endif
+
+    LDMIA   sp!, {r4}           ; pop new task cpsr to spsr
+    MSR     spsr_cxsf, r4
+
+    LDMIA   sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+;/*
+; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+; */
+
+    .def rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt
+    LDR r2, pintflag
+    LDR r3, [r2]
+    CMP r3, #1
+    BEQ _reswitch
+    MOV r3, #1              ; set rt_thread_switch_interrupt_flag to 1
+    STR r3, [r2]
+    LDR r2, pfromthread     ; set rt_interrupt_from_thread
+    STR r0, [r2]
+_reswitch
+    LDR r2, ptothread       ; set rt_interrupt_to_thread
+    STR r1, [r2]
+    BX  lr
+
+    .def IRQ_Handler
+IRQ_Handler
+    STMDB   sp!, {r0-r12,lr}
+
+    .if (__TI_VFP_SUPPORT__)
+		VMRS    r0,  fpexc
+        TST     r0,  #0x40000000
+        BEQ     __no_vfp_frame_str_irq
+		VSTMDB  sp!, {d0-d15}
+        VMRS    r1, fpscr
+        ; TODO: add support for Common VFPv3.
+        ;       Save registers like FPINST, FPINST2
+        STMDB   sp!, {r1}
+__no_vfp_frame_str_irq
+        STMDB   sp!, {r0}
+	.endif
+
+    BL  rt_interrupt_enter
+    BL  rt_hw_trap_irq
+    BL  rt_interrupt_leave
+
+    ; if rt_thread_switch_interrupt_flag set, jump to
+    ; rt_hw_context_switch_interrupt_do and don't return
+    LDR r0, pintflag
+    LDR r1, [r0]
+    CMP r1, #1
+    BEQ rt_hw_context_switch_interrupt_do
+
+    .if (__TI_VFP_SUPPORT__)
+        LDMIA   sp!, {r0}       ; get fpexc
+        VMSR    fpexc, r0
+        TST     r0,  #0x40000000
+        BEQ     __no_vfp_frame_ldr_irq
+        LDMIA   sp!, {r1}       ; get fpscr
+        VMSR    fpscr, r1
+		VLDMIA  sp!, {d0-d15}
+__no_vfp_frame_ldr_irq
+    .endif
+
+    LDMIA   sp!, {r0-r12,lr}
+    SUBS    pc, lr, #4
+
+; /*
+; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
+; */
+    .def rt_hw_context_switch_interrupt_do
+rt_hw_context_switch_interrupt_do
+    MOV     r1,  #0           ; clear flag
+    STR     r1,  [r0]
+
+    .if (__TI_VFP_SUPPORT__)
+        LDMIA   sp!, {r0}       ; get fpexc
+        VMSR    fpexc, r0
+        TST     r0,  #0x40000000
+        BEQ     __no_vfp_frame_do1
+        LDMIA   sp!, {r1}       ; get fpscr
+        VMSR    fpscr, r1
+		VLDMIA  sp!, {d0-d15}
+__no_vfp_frame_do1
+    .endif
+
+    LDMIA   sp!, {r0-r12,lr}  ; reload saved registers
+    STMDB   sp, {r0-r3}       ; save r0-r3. We will restore r0-r3 in the SVC
+                              ; mode so there is no need to update SP.
+    SUB     r1,  sp, #16      ; save the right SP value in r1, so we could restore r0-r3.
+    SUB     r2,  lr, #4       ; save old task's pc to r2
+
+    MRS     r3,  spsr         ; get cpsr of interrupt thread
+
+    ; switch to SVC mode and no interrupt
+    CPSID   IF, #0x13
+
+    STMDB   sp!, {r2}         ; push old task's pc
+    STMDB   sp!, {r4-r12,lr}  ; push old task's lr,r12-r4
+    LDMIA   r1!, {r4-r7}      ; restore r0-r3 of the interrupted thread
+    STMDB   sp!, {r4-r7}      ; push old task's r3-r0. We don't need to push/pop them to
+                              ; r0-r3 because we just want to transfer the data and don't
+                              ; use them here.
+    STMDB   sp!, {r3}         ; push old task's cpsr
+
+    .if (__TI_VFP_SUPPORT__)
+		VMRS    r0,  fpexc
+        TST     r0,  #0x40000000
+        BEQ     __no_vfp_frame_do2
+        VSTMDB  sp!, {d0-d15}
+        VMRS    r1, fpscr
+        ; TODO: add support for Common VFPv3.
+        ;       Save registers like FPINST, FPINST2
+        STMDB   sp!, {r1}
+__no_vfp_frame_do2
+        STMDB   sp!, {r0}
+	.endif
+
+    LDR     r4,  pfromthread
+    LDR     r5,  [r4]
+    STR     sp,  [r5]         ; store sp in preempted tasks's TCB
+
+    LDR     r6,  ptothread
+    LDR     r6,  [r6]
+    LDR     sp,  [r6]         ; get new task's stack pointer
+
+    .if (__TI_VFP_SUPPORT__)
+        LDMIA   sp!, {r0}       ; get fpexc
+        VMSR    fpexc, r0
+        TST     r0,  #0x40000000
+        BEQ     __no_vfp_frame_do3
+        LDMIA   sp!, {r1}       ; get fpscr
+        VMSR    fpscr, r1
+		VLDMIA  sp!, {d0-d15}
+__no_vfp_frame_do3
+    .endif
+
+    LDMIA   sp!, {r4}         ; pop new task's cpsr to spsr
+    MSR     spsr_cxsf, r4
+
+    LDMIA   sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+pintflag     .word   rt_thread_switch_interrupt_flag
+pfromthread  .word   rt_interrupt_from_thread
+ptothread    .word   rt_interrupt_to_thread
diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c
new file mode 100644
index 0000000000000000000000000000000000000000..569f7d0c2946ae44d89a6cd09f1b7e0e9cc8bafd
--- /dev/null
+++ b/libcpu/arm/cortex-r4/cpu.c
@@ -0,0 +1,42 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2008-12-11     XuXinming    first version
+ * 2013-05-24     Grissiom     port to RM48x50
+ */
+
+#include <rtthread.h>
+
+/**
+ * @addtogroup RM48x50
+ */
+/*@{*/
+
+/**
+ * this function will reset CPU
+ *
+ */
+void rt_hw_cpu_reset()
+{
+}
+
+/**
+ * this function will shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+	rt_kprintf("shutdown...\n");
+
+	while (1);
+}
+
+/*@}*/
diff --git a/libcpu/arm/cortex-r4/interrupt.c b/libcpu/arm/cortex-r4/interrupt.c
new file mode 100644
index 0000000000000000000000000000000000000000..8d0a977db9b3915ebf375074594292c675579e6e
--- /dev/null
+++ b/libcpu/arm/cortex-r4/interrupt.c
@@ -0,0 +1,106 @@
+/*
+ * File      : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2008-12-11     XuXinming    first version
+ * 2013-03-29     aozima       Modify the interrupt interface implementations.
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include "RM48x50.h"
+
+#define MAX_HANDLERS	96
+
+/* exception and interrupt handler table */
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
+
+extern rt_uint32_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+/**
+ * @addtogroup RM48x50
+ */
+
+/*@{*/
+
+static void rt_hw_int_not_handle(int vector, void *param)
+{
+	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+#define vimRAM (0xFFF82000U)
+
+void rt_hw_interrupt_init(void)
+{
+	register int i;
+
+	rt_uint32_t *vect_addr;
+
+    /* the initialization is done in sys_startup.c */
+
+    /* init exceptions table */
+    rt_memset(irq_desc, 0x00, sizeof(irq_desc));
+    for(i=0; i < MAX_HANDLERS; i++)
+    {
+        irq_desc[i].handler = rt_hw_int_not_handle;
+
+		vect_addr  = (rt_uint32_t *)(vimRAM + i*4);
+		*vect_addr = (rt_uint32_t)&irq_desc[i];
+    }
+
+	/* init interrupt nest, and context in thread sp */
+	rt_interrupt_nest = 0;
+	rt_interrupt_from_thread = 0;
+	rt_interrupt_to_thread = 0;
+	rt_thread_switch_interrupt_flag = 0;
+}
+
+void rt_hw_interrupt_mask(int vector)
+{
+    vimDisableInterrupt(vector);
+}
+
+void rt_hw_interrupt_umask(int vector)
+{
+    vimEnableInterrupt(vector, SYS_IRQ);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param handler the interrupt service routine to be installed
+ * @param param the parameter for interrupt service routine
+ * @name unused.
+ *
+ * @return the old handler
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+									void *param, char *name)
+{
+	rt_isr_handler_t old_handler = RT_NULL;
+
+	if(vector >= 0 && vector < MAX_HANDLERS)
+	{
+		old_handler = irq_desc[vector].handler;
+		if (handler != RT_NULL)
+		{
+			irq_desc[vector].handler = handler;
+			irq_desc[vector].param = param;
+		}
+	}
+
+	return old_handler;
+}
+
+/*@}*/
diff --git a/libcpu/arm/cortex-r4/stack.c b/libcpu/arm/cortex-r4/stack.c
new file mode 100644
index 0000000000000000000000000000000000000000..02dc84e6f10449e1886063c487fc4010da5b8008
--- /dev/null
+++ b/libcpu/arm/cortex-r4/stack.c
@@ -0,0 +1,85 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2008-12-11     XuXinming    first version
+ * 2013-05-24     Grissiom     port to RM48x50
+ */
+#include <rtthread.h>
+#include "RM48x50.h"
+/**
+ * @addtogroup RM48x50
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	unsigned long *stk;
+
+	    stk  = (unsigned long*)stack_addr;
+	*(  stk) = (unsigned long) tentry;		/* entry point */
+	*(--stk) = (unsigned long) texit;		/* lr */
+	*(--stk) = 0;							/* r12 */
+	*(--stk) = 0;							/* r11 */
+	*(--stk) = 0;							/* r10 */
+	*(--stk) = 0;							/* r9 */
+	*(--stk) = 0;							/* r8 */
+	*(--stk) = 0;							/* r7 */
+	*(--stk) = 0;							/* r6 */
+	*(--stk) = 0;							/* r5 */
+	*(--stk) = 0;							/* r4 */
+	*(--stk) = 0;							/* r3 */
+	*(--stk) = 0;							/* r2 */
+	*(--stk) = 0;							/* r1 */
+	*(--stk) = (unsigned long)parameter;	/* r0 : argument */
+
+	/* cpsr */
+	if ((rt_uint32_t)tentry & 0x01)
+		*(--stk) = SVCMODE | 0x20;			/* thumb mode */
+	else
+		*(--stk) = SVCMODE;					/* arm mode   */
+
+#ifdef __TI_VFP_SUPPORT__
+#ifndef RT_VFP_LAZY_STACKING
+    {
+        #define VFP_DATA_NR 32
+        int i;
+
+        for (i = 0; i < VFP_DATA_NR; i++)
+        {
+            *(--stk) = 0;
+        }
+        /* FPSCR TODO: do we need to set the values other than 0? */
+        *(--stk) = 0;
+        /* FPEXC. Enable the FVP if no lazy stacking. */
+        *(--stk) = 0x40000000;
+    }
+#else
+        /* FPEXC. Disable the FVP by default. */
+        *(--stk) = 0x00000000;
+#endif
+#endif
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/libcpu/arm/cortex-r4/trap.c b/libcpu/arm/cortex-r4/trap.c
new file mode 100644
index 0000000000000000000000000000000000000000..d77f9734daf9dea0a7d7b2601299148f05f43b86
--- /dev/null
+++ b/libcpu/arm/cortex-r4/trap.c
@@ -0,0 +1,150 @@
+/*
+ * File      : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2008-12-11     XuXinming    first version
+ * 2013-05-24     Grissiom     port to RM48x50
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include "RM48x50.h"
+//#define BSP_INT_DEBUG
+
+/**
+ * @addtogroup RM48x50
+ */
+/*@{*/
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register (struct rt_hw_register *regs)
+{
+	rt_kprintf("Execption:\n");
+	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When ARM7TDMI comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_udef(struct rt_hw_register *regs)
+{
+    rt_kprintf("undefined instruction\n");
+    rt_hw_show_register(regs);
+	if (rt_thread_self() != RT_NULL)
+		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_register *regs)
+{
+    rt_kprintf("software interrupt\n");
+    rt_hw_show_register(regs);
+	if (rt_thread_self() != RT_NULL)
+		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_register *regs)
+{
+    rt_kprintf("prefetch abort\n");
+    rt_hw_show_register(regs);
+	if (rt_thread_self() != RT_NULL)
+		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_register *regs)
+{
+    rt_kprintf("Data Abort ");
+    rt_hw_show_register(regs);
+	if (rt_thread_self() != RT_NULL)
+		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_register *regs)
+{
+    rt_kprintf("not used\n");
+    rt_hw_show_register(regs);
+	if (rt_thread_self() != RT_NULL)
+		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    rt_hw_cpu_shutdown();
+}
+
+/*
+ *#pragma CODE_STATE(rt_hw_trap_irq, 32)
+ *#pragma INTERRUPT(rt_hw_trap_irq, IRQ)
+ */
+extern rt_isr_handler_t isr_table[];
+void rt_hw_trap_irq(void)
+{
+	int irqno;
+	struct rt_irq_desc* irq;
+	extern struct rt_irq_desc irq_desc[];
+
+	irq = (struct rt_irq_desc*) vimREG->IRQVECREG;
+	irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
+
+	/* invoke isr */
+	irq->handler(irqno, irq->param);
+}
+
+void rt_hw_trap_fiq(void)
+{
+    rt_kprintf("fast interrupt request\n");
+}
+
+/*@}*/