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提交 7c83c7da 编写于 作者: qiuyiuestc's avatar qiuyiuestc
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update mini2440 bsp 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1239 bbd45198-f89e-11dd-88c7-29a3b14d5316
上级 50bd74d3
隐藏空白更改
内联 并排
Showing with 764 addition and 501 deletion
bsp/mini2440/application.c
浏览文件 @ 7c83c7da
......@@ -105,6 +105,9 @@ void rt_init_thread_entry(void* parameter)
/* init touch panel */
rtgui_touch_hw_init();
/* init keypad */
rt_hw_key_init();
/* re-init device driver */
rt_device_init_all();
......@@ -143,6 +146,9 @@ void rt_init_thread_entry(void* parameter)
/* init touch panel */
rtgui_touch_hw_init();
/* init keypad */
rt_hw_key_init();
/* re-init device driver */
rt_device_init_all();
......
bsp/mini2440/board.c
浏览文件 @ 7c83c7da
......@@ -29,16 +29,12 @@
extern rt_uint32_t PCLK, FCLK, HCLK, UCLK;
extern void rt_hw_clock_init(void);
extern void rt_hw_lcd_init(void);
extern void rt_hw_mmu_init(void);
extern void rt_hw_touch_init(void);
extern void rt_hw_key_init(void);
extern void rt_hw_get_clock(void);
extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
#define UART0 ((struct uartport *)&U0BASE)
struct serial_int_rx uart0_int_rx;
struct serial_device uart0 =
......@@ -49,10 +45,20 @@ struct serial_device uart0 =
};
struct rt_device uart0_device;
#define UART2 ((struct uartport *)&U2BASE)
struct serial_int_rx uart2_int_rx;
struct serial_device uart2 =
{
UART2,
&uart2_int_rx,
RT_NULL
};
struct rt_device uart2_device;
/**
* This function will handle rtos timer
*/
void rt_timer_handler(int vector)
static void rt_timer_handler(int vector)
{
rt_tick_increase();
}
......@@ -60,7 +66,7 @@ void rt_timer_handler(int vector)
/**
* This function will handle serial
*/
void rt_serial_handler(int vector)
static void rt_serial0_handler(int vector)
{
INTSUBMSK |= (BIT_SUB_RXD0);
......@@ -72,10 +78,25 @@ void rt_serial_handler(int vector)
INTSUBMSK &=~(BIT_SUB_RXD0);
}
/**
* This function will handle serial
*/
static void rt_serial2_handler(int vector)
{
INTSUBMSK |= (BIT_SUB_RXD2);
rt_hw_serial_isr(&uart2_device);
SUBSRCPND |= BIT_SUB_RXD2;
/* Unmask sub interrupt (RXD0) */
INTSUBMSK &=~(BIT_SUB_RXD2);
}
/**
* This function will handle init uart
*/
void rt_hw_uart_init(void)
static void rt_hw_uart_init(void)
{
int i;
/* UART0 port configure */
......@@ -99,19 +120,39 @@ void rt_hw_uart_init(void)
/* output PCLK to UART0/1, PWMTIMER */
CLKCON |= 0x0D00;
/* FIFO enable, Tx/Rx FIFO clear */
uart2.uart_device->ufcon = 0x0;
/* disable the flow control */
uart2.uart_device->umcon = 0x0;
/* Normal,No parity,1 stop,8 bit */
uart2.uart_device->ulcon = 0x3;
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
uart2.uart_device->ucon = 0x245;
/* Set uart0 bps */
uart2.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1;
for (i = 0; i < 100; i++);
/* install uart isr */
/* install uart0 isr */
INTSUBMSK &= ~(BIT_SUB_RXD0);
rt_hw_interrupt_install(INTUART0, rt_serial_handler, RT_NULL);
/* install uart2 isr */
INTSUBMSK &= ~(BIT_SUB_RXD2);
rt_hw_interrupt_install(INTUART0, rt_serial0_handler, RT_NULL);
rt_hw_interrupt_umask(INTUART0);
rt_hw_interrupt_install(INTUART2, rt_serial2_handler, RT_NULL);
rt_hw_interrupt_umask(INTUART2);
}
/**
* This function will init timer4 for system ticks
*/
void rt_hw_timer_init()
static void rt_hw_timer_init()
{
/* timer4, pre = 15+1 */
TCFG0 &= 0xffff00ff;
......@@ -148,11 +189,6 @@ void rt_hw_board_init()
/* initialize uart */
rt_hw_uart_init();
#ifdef RT_USING_RTGUI
/* init virtual keypad */
rt_hw_key_init();
#endif
/* initialize mmu */
rt_hw_mmu_init();
......
bsp/mini2440/dm9000.c
浏览文件 @ 7c83c7da
......@@ -23,38 +23,38 @@
*/
//--------------------------------------------------------
#define DM9000_PHY 0x40 /* PHY address 0x01 */
#define DM9000_PHY 0x40 /* PHY address 0x01 */
#define MAX_ADDR_LEN 6
enum DM9000_PHY_mode
{
DM9000_10MHD = 0, DM9000_100MHD = 1,
DM9000_10MFD = 4, DM9000_100MFD = 5,
DM9000_AUTO = 8, DM9000_1M_HPNA = 0x10
DM9000_10MHD = 0, DM9000_100MHD = 1,
DM9000_10MFD = 4, DM9000_100MFD = 5,
DM9000_AUTO = 8, DM9000_1M_HPNA = 0x10
};
enum DM9000_TYPE
{
TYPE_DM9000E,
TYPE_DM9000A,
TYPE_DM9000B
TYPE_DM9000E,
TYPE_DM9000A,
TYPE_DM9000B
};
struct rt_dm9000_eth
{
/* inherit from ethernet device */
struct eth_device parent;
/* inherit from ethernet device */
struct eth_device parent;
enum DM9000_TYPE type;
enum DM9000_TYPE type;
enum DM9000_PHY_mode mode;
rt_uint8_t imr_all;
rt_uint8_t imr_all;
rt_uint8_t packet_cnt; /* packet I or II */
rt_uint16_t queue_packet_len; /* queued packet (packet II) */
rt_uint8_t packet_cnt; /* packet I or II */
rt_uint16_t queue_packet_len; /* queued packet (packet II) */
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
};
static struct rt_dm9000_eth dm9000_device;
static struct rt_semaphore sem_ack, sem_lock;
......@@ -63,111 +63,111 @@ void rt_dm9000_isr(int irqno);
static void delay_ms(rt_uint32_t ms)
{
rt_uint32_t len;
for (;ms > 0; ms --)
for (len = 0; len < 100; len++ );
rt_uint32_t len;
for (;ms > 0; ms --)
for (len = 0; len < 100; len++ );
}
/* Read a byte from I/O port */
rt_inline rt_uint8_t dm9000_io_read(rt_uint16_t reg)
{
DM9000_IO = reg;
return (rt_uint8_t) DM9000_DATA;
DM9000_IO = reg;
return (rt_uint8_t) DM9000_DATA;
}
/* Write a byte to I/O port */
rt_inline void dm9000_io_write(rt_uint16_t reg, rt_uint16_t value)
{
DM9000_IO = reg;
DM9000_DATA = value;
DM9000_IO = reg;
DM9000_DATA = value;
}
/* Read a word from phyxcer */
rt_inline rt_uint16_t phy_read(rt_uint16_t reg)
{
rt_uint16_t val;
rt_uint16_t val;
/* Fill the phyxcer register into REG_0C */
dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
dm9000_io_write(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
/* Fill the phyxcer register into REG_0C */
dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
dm9000_io_write(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
delay_ms(100); /* Wait read complete */
delay_ms(100); /* Wait read complete */
dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
val = (dm9000_io_read(DM9000_EPDRH) << 8) | dm9000_io_read(DM9000_EPDRL);
dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
val = (dm9000_io_read(DM9000_EPDRH) << 8) | dm9000_io_read(DM9000_EPDRL);
return val;
return val;
}
/* Write a word to phyxcer */
rt_inline void phy_write(rt_uint16_t reg, rt_uint16_t value)
{
/* Fill the phyxcer register into REG_0C */
dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
/* Fill the phyxcer register into REG_0C */
dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
/* Fill the written data into REG_0D & REG_0E */
dm9000_io_write(DM9000_EPDRL, (value & 0xff));
dm9000_io_write(DM9000_EPDRH, ((value >> 8) & 0xff));
dm9000_io_write(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
/* Fill the written data into REG_0D & REG_0E */
dm9000_io_write(DM9000_EPDRL, (value & 0xff));
dm9000_io_write(DM9000_EPDRH, ((value >> 8) & 0xff));
dm9000_io_write(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
delay_ms(500); /* Wait write complete */
delay_ms(500); /* Wait write complete */
dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
}
/* Set PHY operationg mode */
rt_inline void phy_mode_set(rt_uint32_t media_mode)
{
rt_uint16_t phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
if (!(media_mode & DM9000_AUTO))
{
switch (media_mode)
{
case DM9000_10MHD:
phy_reg4 = 0x21;
phy_reg0 = 0x0000;
break;
case DM9000_10MFD:
phy_reg4 = 0x41;
phy_reg0 = 0x1100;
break;
case DM9000_100MHD:
phy_reg4 = 0x81;
phy_reg0 = 0x2000;
break;
case DM9000_100MFD:
phy_reg4 = 0x101;
phy_reg0 = 0x3100;
break;
}
phy_write(4, phy_reg4); /* Set PHY media mode */
phy_write(0, phy_reg0); /* Tmp */
}
dm9000_io_write(DM9000_GPCR, 0x01); /* Let GPIO0 output */
dm9000_io_write(DM9000_GPR, 0x00); /* Enable PHY */
rt_uint16_t phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
if (!(media_mode & DM9000_AUTO))
{
switch (media_mode)
{
case DM9000_10MHD:
phy_reg4 = 0x21;
phy_reg0 = 0x0000;
break;
case DM9000_10MFD:
phy_reg4 = 0x41;
phy_reg0 = 0x1100;
break;
case DM9000_100MHD:
phy_reg4 = 0x81;
phy_reg0 = 0x2000;
break;
case DM9000_100MFD:
phy_reg4 = 0x101;
phy_reg0 = 0x3100;
break;
}
phy_write(4, phy_reg4); /* Set PHY media mode */
phy_write(0, phy_reg0); /* Tmp */
}
dm9000_io_write(DM9000_GPCR, 0x01); /* Let GPIO0 output */
dm9000_io_write(DM9000_GPR, 0x00); /* Enable PHY */
}
/* interrupt service routine */
void rt_dm9000_isr(int irqno)
{
rt_uint16_t int_status;
rt_uint16_t last_io;
rt_uint32_t eint_pend;
rt_uint16_t int_status;
rt_uint16_t last_io;
rt_uint32_t eint_pend;
eint_pend = EINTPEND;
/* EINT7 for DM9000 */
if((eint_pend & 0x80) == 0x80)
{
eint_pend = EINTPEND;
/* EINT7 for DM9000 */
if((eint_pend & 0x80) == 0x80)
{
last_io = DM9000_IO;
/* Disable all interrupts */
// dm9000_io_write(DM9000_IMR, IMR_PAR);
/* Disable all interrupts */
// dm9000_io_write(DM9000_IMR, IMR_PAR);
/* Got DM9000 interrupt status */
int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
......@@ -182,13 +182,13 @@ void rt_dm9000_isr(int irqno)
rt_kprintf("overflow counter overflow\n");
}
/* Received the coming packet */
if (int_status & ISR_PRS)
{
/* disable receive interrupt */
dm9000_io_write(DM9000_IMR, IMR_PAR);
dm9000_device.imr_all = IMR_PAR | IMR_PTM;
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
/* Received the coming packet */
if (int_status & ISR_PRS)
{
/* disable receive interrupt */
dm9000_io_write(DM9000_IMR, IMR_PAR);
dm9000_device.imr_all = IMR_PAR | IMR_PTM;
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
/* a frame has been received */
eth_device_ready(&(dm9000_device.parent));
......@@ -198,7 +198,7 @@ void rt_dm9000_isr(int irqno)
if (int_status & ISR_PTS)
{
/* transmit done */
int tx_status = dm9000_io_read(DM9000_NSR); /* Got TX status */
int tx_status = dm9000_io_read(DM9000_NSR); /* Got TX status */
if (tx_status & (NSR_TX2END | NSR_TX1END))
{
......@@ -221,158 +221,158 @@ void rt_dm9000_isr(int irqno)
}
}
/* Re-enable interrupt mask */
// dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
/* Re-enable interrupt mask */
// dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
DM9000_IO = last_io;
}
}
/* clear EINT pending bit */
EINTPEND = eint_pend;
/* clear EINT pending bit */
EINTPEND = eint_pend;
}
/* RT-Thread Device Interface */
/* initialize the interface */
static rt_err_t rt_dm9000_init(rt_device_t dev)
{
int i, oft, lnk;
rt_uint32_t value;
/* RESET device */
dm9000_io_write(DM9000_NCR, NCR_RST);
delay_ms(1000); /* delay 1ms */
/* identfy DM9000 */
value = dm9000_io_read(DM9000_VIDL);
value |= dm9000_io_read(DM9000_VIDH) << 8;
value |= dm9000_io_read(DM9000_PIDL) << 16;
value |= dm9000_io_read(DM9000_PIDH) << 24;
if (value == DM9000_ID)
{
rt_kprintf("dm9000 id: 0x%x\n", value);
}
else
{
rt_kprintf("dm9000 id: 0x%x\n", value);
return -RT_ERROR;
}
/* GPIO0 on pre-activate PHY */
dm9000_io_write(DM9000_GPR, 0x00); /* REG_1F bit0 activate phyxcer */
dm9000_io_write(DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
dm9000_io_write(DM9000_GPR, 0x00); /* Enable PHY */
/* Set PHY */
phy_mode_set(dm9000_device.mode);
/* Program operating register */
dm9000_io_write(DM9000_NCR, 0x0); /* only intern phy supported by now */
dm9000_io_write(DM9000_TCR, 0); /* TX Polling clear */
dm9000_io_write(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
dm9000_io_write(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
dm9000_io_write(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
dm9000_io_write(DM9000_SMCR, 0); /* Special Mode */
dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
dm9000_io_write(DM9000_ISR, 0x0f); /* Clear interrupt status */
dm9000_io_write(DM9000_TCR2, 0x80); /* Switch LED to mode 1 */
/* set mac address */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
dm9000_io_write(oft, dm9000_device.dev_addr[i]);
/* set multicast address */
for (i = 0, oft = 0x16; i < 8; i++, oft++)
dm9000_io_write(oft, 0xff);
/* Activate DM9000 */
dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
dm9000_io_write(DM9000_IMR, IMR_PAR);
if (dm9000_device.mode == DM9000_AUTO)
{
while (!(phy_read(1) & 0x20))
{
/* autonegation complete bit */
rt_thread_delay( 10 );
i++;
if (i > 20)
{
rt_kprintf("could not establish link\n");
return 0;
}
}
}
/* see what we've got */
lnk = phy_read(17) >> 12;
rt_kprintf("operating at ");
switch (lnk)
{
case 1:
rt_kprintf("10M half duplex ");
break;
case 2:
rt_kprintf("10M full duplex ");
break;
case 4:
rt_kprintf("100M half duplex ");
break;
case 8:
rt_kprintf("100M full duplex ");
break;
default:
rt_kprintf("unknown: %d ", lnk);
break;
}
rt_kprintf("mode\n");
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all); /* Enable TX/RX interrupt mask */
return RT_EOK;
int i, oft, lnk;
rt_uint32_t value;
/* RESET device */
dm9000_io_write(DM9000_NCR, NCR_RST);
delay_ms(1000); /* delay 1ms */
/* identfy DM9000 */
value = dm9000_io_read(DM9000_VIDL);
value |= dm9000_io_read(DM9000_VIDH) << 8;
value |= dm9000_io_read(DM9000_PIDL) << 16;
value |= dm9000_io_read(DM9000_PIDH) << 24;
if (value == DM9000_ID)
{
rt_kprintf("dm9000 id: 0x%x\n", value);
}
else
{
rt_kprintf("dm9000 id: 0x%x\n", value);
return -RT_ERROR;
}
/* GPIO0 on pre-activate PHY */
dm9000_io_write(DM9000_GPR, 0x00); /* REG_1F bit0 activate phyxcer */
dm9000_io_write(DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
dm9000_io_write(DM9000_GPR, 0x00); /* Enable PHY */
/* Set PHY */
phy_mode_set(dm9000_device.mode);
/* Program operating register */
dm9000_io_write(DM9000_NCR, 0x0); /* only intern phy supported by now */
dm9000_io_write(DM9000_TCR, 0); /* TX Polling clear */
dm9000_io_write(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
dm9000_io_write(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
dm9000_io_write(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
dm9000_io_write(DM9000_SMCR, 0); /* Special Mode */
dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
dm9000_io_write(DM9000_ISR, 0x0f); /* Clear interrupt status */
dm9000_io_write(DM9000_TCR2, 0x80); /* Switch LED to mode 1 */
/* set mac address */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
dm9000_io_write(oft, dm9000_device.dev_addr[i]);
/* set multicast address */
for (i = 0, oft = 0x16; i < 8; i++, oft++)
dm9000_io_write(oft, 0xff);
/* Activate DM9000 */
dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
dm9000_io_write(DM9000_IMR, IMR_PAR);
if (dm9000_device.mode == DM9000_AUTO)
{
while (!(phy_read(1) & 0x20))
{
/* autonegation complete bit */
rt_thread_delay( 10 );
i++;
if (i > 20)
{
rt_kprintf("could not establish link\n");
return 0;
}
}
}
/* see what we've got */
lnk = phy_read(17) >> 12;
rt_kprintf("operating at ");
switch (lnk)
{
case 1:
rt_kprintf("10M half duplex ");
break;
case 2:
rt_kprintf("10M full duplex ");
break;
case 4:
rt_kprintf("100M half duplex ");
break;
case 8:
rt_kprintf("100M full duplex ");
break;
default:
rt_kprintf("unknown: %d ", lnk);
break;
}
rt_kprintf("mode\n");
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all); /* Enable TX/RX interrupt mask */
return RT_EOK;
}
static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_dm9000_close(rt_device_t dev)
{
/* RESET devie */
phy_write(0, 0x8000); /* PHY RESET */
dm9000_io_write(DM9000_GPR, 0x01); /* Power-Down PHY */
dm9000_io_write(DM9000_IMR, 0x80); /* Disable all interrupt */
dm9000_io_write(DM9000_RCR, 0x00); /* Disable RX */
/* RESET devie */
phy_write(0, 0x8000); /* PHY RESET */
dm9000_io_write(DM9000_GPR, 0x01); /* Power-Down PHY */
dm9000_io_write(DM9000_IMR, 0x80); /* Disable all interrupt */
dm9000_io_write(DM9000_RCR, 0x00); /* Disable RX */
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_dm9000_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, dm9000_device.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
return RT_EOK;
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, dm9000_device.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
return RT_EOK;
}
/* ethernet device interface */
......@@ -381,16 +381,16 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
{
DM9000_TRACE("dm9000 tx: %d\n", p->tot_len);
/* lock DM9000 device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
/* lock DM9000 device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
/* disable dm9000a interrupt */
dm9000_io_write(DM9000_IMR, IMR_PAR);
/* disable dm9000a interrupt */
dm9000_io_write(DM9000_IMR, IMR_PAR);
/* Move data to DM9000 TX RAM */
DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
/* Move data to DM9000 TX RAM */
DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
{
{
/* q traverses through linked list of pbuf's
* This list MUST consist of a single packet ONLY */
struct pbuf *q;
......@@ -408,7 +408,7 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
word[word_index++] = ((u8_t*)q->payload)[pbuf_index++];
if (word_index == 2)
{
DM9000_outw(DM9000_DATA_BASE, (word[1] << 8) | word[0]);
DM9000_outw(DM9000_DATA_BASE, (word[1] << 8) | word[0]);
word_index = 0;
}
}
......@@ -421,178 +421,178 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
/* One byte could still be unsent */
if (word_index == 1)
{
DM9000_outw(DM9000_DATA_BASE, word[0]);
DM9000_outw(DM9000_DATA_BASE, word[0]);
}
}
}
if (dm9000_device.packet_cnt == 0)
{
DM9000_TRACE("dm9000 tx: first packet\n");
if (dm9000_device.packet_cnt == 0)
{
DM9000_TRACE("dm9000 tx: first packet\n");
dm9000_device.packet_cnt ++;
/* Set TX length to DM9000 */
dm9000_io_write(DM9000_TXPLL, p->tot_len & 0xff);
dm9000_io_write(DM9000_TXPLH, (p->tot_len >> 8) & 0xff);
dm9000_device.packet_cnt ++;
/* Set TX length to DM9000 */
dm9000_io_write(DM9000_TXPLL, p->tot_len & 0xff);
dm9000_io_write(DM9000_TXPLH, (p->tot_len >> 8) & 0xff);
/* Issue TX polling command */
dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
}
else
{
DM9000_TRACE("dm9000 tx: second packet\n");
/* Issue TX polling command */
dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
}
else
{
DM9000_TRACE("dm9000 tx: second packet\n");
dm9000_device.packet_cnt ++;
dm9000_device.queue_packet_len = p->tot_len;
}
dm9000_device.packet_cnt ++;
dm9000_device.queue_packet_len = p->tot_len;
}
/* enable dm9000a interrupt */
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
/* enable dm9000a interrupt */
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
/* unlock DM9000 device */
rt_sem_release(&sem_lock);
/* unlock DM9000 device */
rt_sem_release(&sem_lock);
/* wait ack */
rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
/* wait ack */
rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
DM9000_TRACE("dm9000 tx done\n");
return RT_EOK;
return RT_EOK;
}
/* reception packet. */
struct pbuf *rt_dm9000_rx(rt_device_t dev)
{
struct pbuf* p;
rt_uint32_t rxbyte;
rt_uint16_t rx_status, rx_len;
rt_uint16_t* data;
struct pbuf* p;
rt_uint32_t rxbyte;
rt_uint16_t rx_status, rx_len;
rt_uint16_t* data;
/* init p pointer */
p = RT_NULL;
/* init p pointer */
p = RT_NULL;
/* lock DM9000 device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
/* lock DM9000 device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
__error_retry:
/* Check packet ready or not */
dm9000_io_read(DM9000_MRCMDX); /* Dummy read */
rxbyte = DM9000_inb(DM9000_DATA_BASE); /* Got most updated data */
if (rxbyte)
{
if (rxbyte > 1)
{
/* Check packet ready or not */
dm9000_io_read(DM9000_MRCMDX); /* Dummy read */
rxbyte = DM9000_inb(DM9000_DATA_BASE); /* Got most updated data */
if (rxbyte)
{
if (rxbyte > 1)
{
DM9000_TRACE("dm9000 rx: rx error, stop device\n");
dm9000_io_write(DM9000_RCR, 0x00); /* Stop Device */
dm9000_io_write(DM9000_ISR, 0x80); /* Stop INT request */
}
dm9000_io_write(DM9000_RCR, 0x00); /* Stop Device */
dm9000_io_write(DM9000_ISR, 0x80); /* Stop INT request */
}
/* A packet ready now & Get status/length */
DM9000_outb(DM9000_IO_BASE, DM9000_MRCMD);
/* A packet ready now & Get status/length */
DM9000_outb(DM9000_IO_BASE, DM9000_MRCMD);
rx_status = DM9000_inw(DM9000_DATA_BASE);
rx_len = DM9000_inw(DM9000_DATA_BASE);
rx_status = DM9000_inw(DM9000_DATA_BASE);
rx_len = DM9000_inw(DM9000_DATA_BASE);
DM9000_TRACE("dm9000 rx: status %04x len %d\n", rx_status, rx_len);
/* allocate buffer */
p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM);
if (p != RT_NULL)
{
struct pbuf* q;
rt_int32_t len;
for (q = p; q != RT_NULL; q= q->next)
{
data = (rt_uint16_t*)q->payload;
len = q->len;
while (len > 0)
{
*data = DM9000_inw(DM9000_DATA_BASE);
data ++;
len -= 2;
}
}
}
else
{
rt_uint16_t dummy;
rt_kprintf("dm9000 rx: no pbuf\n");
/* no pbuf, discard data from DM9000 */
data = &dummy;
while (rx_len)
{
*data = DM9000_inw(DM9000_DATA_BASE);
rx_len -= 2;
}
}
if ((rx_status & 0xbf00) || (rx_len < 0x40)
|| (rx_len > DM9000_PKT_MAX))
{
rt_kprintf("rx error: status %04x, rx_len: %d\n", rx_status, rx_len);
if (rx_status & 0x100)
{
rt_kprintf("rx fifo error\n");
}
if (rx_status & 0x200)
{
rt_kprintf("rx crc error\n");
}
if (rx_status & 0x8000)
{
rt_kprintf("rx length error\n");
}
if (rx_len > DM9000_PKT_MAX)
{
rt_kprintf("rx length too big\n");
/* RESET device */
dm9000_io_write(DM9000_NCR, NCR_RST);
rt_thread_delay(1); /* delay 5ms */
}
/* it issues an error, release pbuf */
if (p != RT_NULL) pbuf_free(p);
p = RT_NULL;
/* allocate buffer */
p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM);
if (p != RT_NULL)
{
struct pbuf* q;
rt_int32_t len;
for (q = p; q != RT_NULL; q= q->next)
{
data = (rt_uint16_t*)q->payload;
len = q->len;
while (len > 0)
{
*data = DM9000_inw(DM9000_DATA_BASE);
data ++;
len -= 2;
}
}
}
else
{
rt_uint16_t dummy;
rt_kprintf("dm9000 rx: no pbuf\n");
/* no pbuf, discard data from DM9000 */
data = &dummy;
while (rx_len)
{
*data = DM9000_inw(DM9000_DATA_BASE);
rx_len -= 2;
}
}
if ((rx_status & 0xbf00) || (rx_len < 0x40)
|| (rx_len > DM9000_PKT_MAX))
{
rt_kprintf("rx error: status %04x, rx_len: %d\n", rx_status, rx_len);
if (rx_status & 0x100)
{
rt_kprintf("rx fifo error\n");
}
if (rx_status & 0x200)
{
rt_kprintf("rx crc error\n");
}
if (rx_status & 0x8000)
{
rt_kprintf("rx length error\n");
}
if (rx_len > DM9000_PKT_MAX)
{
rt_kprintf("rx length too big\n");
/* RESET device */
dm9000_io_write(DM9000_NCR, NCR_RST);
rt_thread_delay(1); /* delay 5ms */
}
/* it issues an error, release pbuf */
if (p != RT_NULL) pbuf_free(p);
p = RT_NULL;
goto __error_retry;
}
}
else
{
}
}
else
{
/* clear packet received latch status */
dm9000_io_write(DM9000_ISR, ISR_PTS);
dm9000_io_write(DM9000_ISR, ISR_PTS);
/* restore receive interrupt */
dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
}
/* restore receive interrupt */
dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
}
/* unlock DM9000 device */
rt_sem_release(&sem_lock);
/* unlock DM9000 device */
rt_sem_release(&sem_lock);
return p;
return p;
}
#define B4_Tacs 0x0
#define B4_Tcos 0x0
#define B4_Tacc 0x7
#define B4_Tcoh 0x0
#define B4_Tah 0x0
#define B4_Tacp 0x0
#define B4_PMC 0x0
#define B4_Tacs 0x0
#define B4_Tcos 0x0
#define B4_Tacc 0x7
#define B4_Tcoh 0x0
#define B4_Tah 0x0
#define B4_Tacp 0x0
#define B4_PMC 0x0
void rt_hw_dm9000_init()
{
/* Set GPF7 as EINT7 */
GPFCON = GPFCON & (~(3 << 14)) | (2 << 14);
GPFUP = GPFUP | (1 << 7);
/* EINT7 High level interrupt */
GPFCON = GPFCON & (~(3 << 14)) | (2 << 14);
GPFUP = GPFUP | (1 << 7);
/* EINT7 High level interrupt */
EXTINT0 = (EXTINT0 & (~(0x7 << 28))) | (0x1 << 28);
/* Enable EINT7 */
EINTMASK = EINTMASK & (~(1<<7));
......@@ -602,62 +602,62 @@ void rt_hw_dm9000_init()
BWSCON = BWSCON & (~(0x7<<16)) | (0x5<<16);
BANKCON4 = (1<<13) | (1<<11) | (0x6<<8) | (1<<6) | (1<<4) | (0<<2) | (0);
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
dm9000_device.type = TYPE_DM9000A;
dm9000_device.type = TYPE_DM9000A;
dm9000_device.mode = DM9000_AUTO;
dm9000_device.packet_cnt = 0;
dm9000_device.queue_packet_len = 0;
/*
* SRAM Tx/Rx pointer automatically return to start address,
* Packet Transmitted, Packet Received
*/
dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
dm9000_device.dev_addr[0] = 0x01;
dm9000_device.dev_addr[1] = 0x60;
dm9000_device.dev_addr[2] = 0x6E;
dm9000_device.dev_addr[3] = 0x11;
dm9000_device.dev_addr[4] = 0x02;
dm9000_device.dev_addr[5] = 0x0F;
dm9000_device.parent.parent.init = rt_dm9000_init;
dm9000_device.parent.parent.open = rt_dm9000_open;
dm9000_device.parent.parent.close = rt_dm9000_close;
dm9000_device.parent.parent.read = rt_dm9000_read;
dm9000_device.parent.parent.write = rt_dm9000_write;
dm9000_device.parent.parent.control = rt_dm9000_control;
dm9000_device.parent.parent.user_data = RT_NULL;
dm9000_device.parent.eth_rx = rt_dm9000_rx;
dm9000_device.parent.eth_tx = rt_dm9000_tx;
eth_device_init(&(dm9000_device.parent), "e0");
/* instal interrupt */
/*
* SRAM Tx/Rx pointer automatically return to start address,
* Packet Transmitted, Packet Received
*/
dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
dm9000_device.dev_addr[0] = 0x01;
dm9000_device.dev_addr[1] = 0x60;
dm9000_device.dev_addr[2] = 0x6E;
dm9000_device.dev_addr[3] = 0x11;
dm9000_device.dev_addr[4] = 0x02;
dm9000_device.dev_addr[5] = 0x0F;
dm9000_device.parent.parent.init = rt_dm9000_init;
dm9000_device.parent.parent.open = rt_dm9000_open;
dm9000_device.parent.parent.close = rt_dm9000_close;
dm9000_device.parent.parent.read = rt_dm9000_read;
dm9000_device.parent.parent.write = rt_dm9000_write;
dm9000_device.parent.parent.control = rt_dm9000_control;
dm9000_device.parent.parent.user_data = RT_NULL;
dm9000_device.parent.eth_rx = rt_dm9000_rx;
dm9000_device.parent.eth_tx = rt_dm9000_tx;
eth_device_init(&(dm9000_device.parent), "e0");
/* instal interrupt */
rt_hw_interrupt_install(INTEINT4_7, rt_dm9000_isr, RT_NULL);
rt_hw_interrupt_umask(INTEINT4_7);
}
void dm9000a(void)
{
rt_kprintf("\n");
rt_kprintf("NCR (0x00): %02x\n", dm9000_io_read(DM9000_NCR));
rt_kprintf("NSR (0x01): %02x\n", dm9000_io_read(DM9000_NSR));
rt_kprintf("TCR (0x02): %02x\n", dm9000_io_read(DM9000_TCR));
rt_kprintf("TSRI (0x03): %02x\n", dm9000_io_read(DM9000_TSR1));
rt_kprintf("TSRII (0x04): %02x\n", dm9000_io_read(DM9000_TSR2));
rt_kprintf("RCR (0x05): %02x\n", dm9000_io_read(DM9000_RCR));
rt_kprintf("RSR (0x06): %02x\n", dm9000_io_read(DM9000_RSR));
rt_kprintf("ORCR (0x07): %02x\n", dm9000_io_read(DM9000_ROCR));
rt_kprintf("CRR (0x2C): %02x\n", dm9000_io_read(DM9000_CHIPR));
rt_kprintf("CSCR (0x31): %02x\n", dm9000_io_read(DM9000_CSCR));
rt_kprintf("RCSSR (0x32): %02x\n", dm9000_io_read(DM9000_RCSSR));
rt_kprintf("ISR (0xFE): %02x\n", dm9000_io_read(DM9000_ISR));
rt_kprintf("IMR (0xFF): %02x\n", dm9000_io_read(DM9000_IMR));
rt_kprintf("\n");
rt_kprintf("\n");
rt_kprintf("NCR (0x00): %02x\n", dm9000_io_read(DM9000_NCR));
rt_kprintf("NSR (0x01): %02x\n", dm9000_io_read(DM9000_NSR));
rt_kprintf("TCR (0x02): %02x\n", dm9000_io_read(DM9000_TCR));
rt_kprintf("TSRI (0x03): %02x\n", dm9000_io_read(DM9000_TSR1));
rt_kprintf("TSRII (0x04): %02x\n", dm9000_io_read(DM9000_TSR2));
rt_kprintf("RCR (0x05): %02x\n", dm9000_io_read(DM9000_RCR));
rt_kprintf("RSR (0x06): %02x\n", dm9000_io_read(DM9000_RSR));
rt_kprintf("ORCR (0x07): %02x\n", dm9000_io_read(DM9000_ROCR));
rt_kprintf("CRR (0x2C): %02x\n", dm9000_io_read(DM9000_CHIPR));
rt_kprintf("CSCR (0x31): %02x\n", dm9000_io_read(DM9000_CSCR));
rt_kprintf("RCSSR (0x32): %02x\n", dm9000_io_read(DM9000_RCSSR));
rt_kprintf("ISR (0xFE): %02x\n", dm9000_io_read(DM9000_ISR));
rt_kprintf("IMR (0xFF): %02x\n", dm9000_io_read(DM9000_IMR));
rt_kprintf("\n");
}
#ifdef RT_USING_FINSH
......
bsp/mini2440/key.c
浏览文件 @ 7c83c7da
/*
* File : touch.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-01 Yi.Qiu first version
*/
/*
* Warning, this keypad driver can only work on QEMU emulator
*/
#include <rtthread.h>
#include <s3c24x0.h>
#include <rthw.h>
#ifdef RT_USING_RTGUI
#include <rtgui/event.h>
#include <rtgui/rtgui_server.h>
#endif
#define KEY_RX_BUFFER_SIZE 32
static void key_handle(int key_value)
struct rt_key_device
{
#ifdef RT_USING_RTGUI
struct rtgui_event_kbd kbd_event;
struct rt_device parent;
rt_uint32_t rx_buffer[KEY_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
static struct rt_key_device *key_device = RT_NULL;
/* save a char to serial buffer */
static void rt_key_savechar(char ch)
{
rt_base_t level;
/* init keyboard event */
RTGUI_EVENT_KBD_INIT(&kbd_event);
kbd_event.mod = RTGUI_KMOD_NONE;
kbd_event.unicode = 0;
kbd_event.key = RTGUIK_UNKNOWN;
if(key_value & 0x80)
{
kbd_event.type = RTGUI_KEYUP;
}
else
{
kbd_event.type = RTGUI_KEYDOWN;
}
/* disable interrupt */
level = rt_hw_interrupt_disable();
key_device->rx_buffer[key_device->save_index] = ch;
key_device->save_index ++;
if (key_device->save_index >= KEY_RX_BUFFER_SIZE)
key_device->save_index = 0;
key_value &= 0x7F;
switch(key_value)
/* if the next position is read index, discard this 'read char' */
if (key_device->save_index == key_device->read_index)
{
case 80:
kbd_event.key = RTGUIK_DOWN;
break;
case 72:
kbd_event.key = RTGUIK_UP;
break;
case 77:
kbd_event.key = RTGUIK_RIGHT;
break;
case 75:
kbd_event.key = RTGUIK_LEFT;
break;
case 31:
kbd_event.key = 's';
break;
case 30:
kbd_event.key = 'a';
break;
case 44:
kbd_event.key = 'z';
break;
case 45:
kbd_event.key = 'x';
break;
case 46:
kbd_event.key = 'c';
break;
case 16:
kbd_event.key = 'q';
break;
case 33:
kbd_event.key = 'r';
break;
case 23:
kbd_event.key = 'i';
break;
case 50:
kbd_event.key = 'm';
break;
case 38:
kbd_event.key = 'l';
break;
case 47:
kbd_event.key = 'v';
break;
default:
break;
key_device->read_index ++;
if (key_device->read_index >= KEY_RX_BUFFER_SIZE)
key_device->read_index = 0;
}
if (kbd_event.key != RTGUIK_UNKNOWN)
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
/* ISR for serial interrupt */
static void rt_hw_key_isr(void)
{
/* save on rx buffer */
rt_key_savechar(URXH1 & 0xff);
/* invoke callback */
if (key_device->parent.rx_indicate != RT_NULL)
{
/* post down event */
rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event));
}
#endif
rt_size_t rx_length;
/* get rx length */
rx_length = key_device->read_index > key_device->save_index ?
KEY_RX_BUFFER_SIZE - key_device->read_index + key_device->save_index :
key_device->save_index - key_device->read_index;
key_device->parent.rx_indicate(&key_device->parent, rx_length);
}
}
/**
* This function is only for QEMU emulation
*/
void rt_virtual_key_isr(int vector)
static void rt_key_handler(int vector)
{
INTSUBMSK |= (BIT_SUB_RXD1);
key_handle(URXH1);
rt_hw_key_isr();
SUBSRCPND |= BIT_SUB_RXD1;
......@@ -105,9 +94,9 @@ void rt_virtual_key_isr(int vector)
/**
* This function is only for QEMU emulation
*/
void rt_hw_key_init(void)
static void key_init(void)
{
unsigned long i;
int i = 0;
GPHCON |= 0xa0;
/*PULLUP is enable */
......@@ -137,10 +126,219 @@ void rt_hw_key_init(void)
for (i = 0; i < 100; i++);
/* install keypad isr */
/* install key isr */
INTSUBMSK &= ~(BIT_SUB_RXD1);
rt_hw_interrupt_install(INTUART1, rt_virtual_key_isr, RT_NULL);
rt_hw_interrupt_install(INTUART1, rt_key_handler, RT_NULL);
rt_hw_interrupt_umask(INTUART1);
}
static rt_err_t rt_key_init(rt_device_t dev)
{
if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
{
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
rt_memset(key_device->rx_buffer, 0,
sizeof(key_device->rx_buffer));
key_device->read_index = key_device->save_index = 0;
}
dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
}
return RT_EOK;
}
static rt_err_t rt_key_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t rt_key_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_key_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
rt_err_t err_code;
rt_base_t level;
ptr = buffer;
err_code = RT_EOK;
/* interrupt mode Rx */
while (size)
{
if (key_device->read_index != key_device->save_index)
{
*ptr++ = key_device->rx_buffer[key_device->read_index];
size --;
/* disable interrupt */
level = rt_hw_interrupt_disable();
key_device->read_index ++;
if (key_device->read_index >= KEY_RX_BUFFER_SIZE)
key_device->read_index = 0;
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
else
{
/* set error code */
err_code = -RT_EEMPTY;
break;
}
}
/* set error code */
rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static rt_err_t rt_key_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
return RT_EOK;
}
#ifdef RT_USING_RTGUI
#include <rtgui/event.h>
#include <rtgui/rtgui_server.h>
#include <rtgui/kbddef.h>
static int s_key_map[0xff] = {0};
static void rt_keymap_init(void)
{
s_key_map[0x1] = RTGUIK_ESCAPE;
s_key_map[0xc] = RTGUIK_MINUS;
s_key_map[0x39] = RTGUIK_SPACE;
s_key_map[0xd] = RTGUIK_KP_EQUALS;
s_key_map[0xe] = RTGUIK_BACKSPACE;
s_key_map[0xf] = RTGUIK_TAB;
s_key_map[0x1c] = RTGUIK_KP_ENTER;
s_key_map[0xb] = RTGUIK_0;
s_key_map[0x2] = RTGUIK_1;
s_key_map[0x3] = RTGUIK_2;
s_key_map[0x4] = RTGUIK_3;
s_key_map[0x5] = RTGUIK_4;
s_key_map[0x6] = RTGUIK_5;
s_key_map[0x7] = RTGUIK_6;
s_key_map[0x8] = RTGUIK_7;
s_key_map[0x9] = RTGUIK_8;
s_key_map[0xa] = RTGUIK_9;
s_key_map[0x3b] = RTGUIK_F1;
s_key_map[0x3c] = RTGUIK_F2;
s_key_map[0x3d] = RTGUIK_F3;
s_key_map[0x3e] = RTGUIK_F4;
s_key_map[0xef] = RTGUIK_F5;
s_key_map[0x40] = RTGUIK_F6;
s_key_map[0x41] = RTGUIK_F7;
s_key_map[0x42] = RTGUIK_F8;
s_key_map[0x43] = RTGUIK_F9;
s_key_map[0x1e] = RTGUIK_a;
s_key_map[0x30] = RTGUIK_b;
s_key_map[0x2c] = RTGUIK_c;
s_key_map[0x20] = RTGUIK_d;
s_key_map[0x12] = RTGUIK_e;
s_key_map[0x21] = RTGUIK_f;
s_key_map[0x22] = RTGUIK_g;
s_key_map[0x23] = RTGUIK_h;
s_key_map[0x17] = RTGUIK_i;
s_key_map[0x24] = RTGUIK_j;
s_key_map[0x25] = RTGUIK_k;
s_key_map[0x26] = RTGUIK_l;
s_key_map[0x32] = RTGUIK_m;
s_key_map[0x31] = RTGUIK_n;
s_key_map[0x18] = RTGUIK_o;
s_key_map[0x19] = RTGUIK_p;
s_key_map[0x10] = RTGUIK_q;
s_key_map[0x13] = RTGUIK_r;
s_key_map[0x1f] = RTGUIK_s;
s_key_map[0x14] = RTGUIK_t;
s_key_map[0x16] = RTGUIK_u;
s_key_map[0x2f] = RTGUIK_v;
s_key_map[0x11] = RTGUIK_w;
s_key_map[0x2d] = RTGUIK_x;
s_key_map[0x15] = RTGUIK_y;
s_key_map[0x2c] = RTGUIK_z;
s_key_map[0x4b] = RTGUIK_LEFT;
s_key_map[0x4d] = RTGUIK_RIGHT;
s_key_map[0x50] = RTGUIK_DOWN;
s_key_map[0x2e] = RTGUIK_DELETE;
s_key_map[0x48] = RTGUIK_UP;
}
static void rtgui_key_rx(rt_device_t dev, rt_size_t size)
{
struct rtgui_event_kbd kbd_event;
char key_value;
while(rt_device_read(dev, 0, &key_value, 1) == 1)
{
/* init keyboard event */
RTGUI_EVENT_KBD_INIT(&kbd_event);
kbd_event.mod = RTGUI_KMOD_NONE;
kbd_event.unicode = 0;
kbd_event.key = RTGUIK_UNKNOWN;
if(key_value & 0x80)
{
kbd_event.type = RTGUI_KEYUP;
}
else
{
kbd_event.type = RTGUI_KEYDOWN;
}
kbd_event.key = s_key_map[key_value & 0x7F];
}
if (kbd_event.key != RTGUIK_UNKNOWN)
{
/* post down event */
rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event));
}
}
#endif
/*
* key driver register
*/
void rt_hw_key_init(void)
{
/* hardware init */
key_init();
key_device = (struct rt_key_device*)rt_malloc (sizeof(struct rt_key_device));
if (key_device == RT_NULL) return; /* no memory yet */
/* clear device structure */
rt_memset(&(key_device->parent), 0, sizeof(struct rt_device));
key_device->parent.type = RT_Device_Class_Char;
key_device->parent.tx_complete = RT_NULL;
key_device->parent.init = rt_key_init;
key_device->parent.open = rt_key_open;
key_device->parent.close = rt_key_close;
key_device->parent.read = rt_key_read;
key_device->parent.write = RT_NULL;
key_device->parent.control = rt_key_control;
key_device->parent.user_data = RT_NULL;
#ifdef RT_USING_RTGUI
key_device->parent.rx_indicate = rtgui_key_rx;
/* init keymap */
rt_keymap_init();
#endif
/* register key device to RT-Thread */
rt_device_register(&(key_device->parent), "key", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX);
}
bsp/mini2440/lcd_t35.c
浏览文件 @ 7c83c7da
......@@ -113,8 +113,8 @@
#define S3C2410_LCDINT_FRSYNC (1<<1)
static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
struct rtgui_lcd_device
{
......@@ -307,7 +307,7 @@ static rt_err_t rt_lcd_init (rt_device_t dev)
GPDCON = 0xaaaaaaaa;
#define M5D(n) ((n)&0x1fffff)
#define LCD_ADDR ((rt_uint32_t)_rt_hw_framebuffer)
#define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
......@@ -357,6 +357,20 @@ static rt_err_t rt_lcd_control (rt_device_t dev, rt_uint8_t cmd, void *args)
return RT_EOK;
}
static rt_err_t rt_lcd_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_lcd_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
void rt_hw_lcd_init(void)
{
lcd = (struct rtgui_lcd_device*)rt_malloc(sizeof(struct rtgui_lcd_device));
......@@ -365,12 +379,14 @@ void rt_hw_lcd_init(void)
/* init device structure */
lcd->parent.type = RT_Device_Class_Unknown;
lcd->parent.init = rt_lcd_init;
lcd->parent.open = rt_lcd_open;
lcd->parent.open = rt_lcd_close;
lcd->parent.control = rt_lcd_control;
lcd->parent.user_data = RT_NULL;
lcd->byte_per_pixel = 2;
lcd->width = LCD_WIDTH;
lcd->height = LCD_HEIGHT;
lcd->hw_framebuffer = (void*)_rt_hw_framebuffer;
lcd->hw_framebuffer = (void*)_rt_framebuffer;
/* register touch device to RT-Thread */
rt_device_register(&(lcd->parent), "lcd", RT_DEVICE_FLAG_RDWR);
......
bsp/mini2440/sdcard.c
浏览文件 @ 7c83c7da
......@@ -340,22 +340,22 @@ struct dfs_partition part[4];
static rt_err_t rt_sdcard_init(rt_device_t dev)
{
return 0;
return RT_EOK;
}
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{
return 0;
return RT_EOK;
}
static rt_err_t rt_sdcard_close(rt_device_t dev)
{
return 0;
return RT_EOK;
}
static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
return 0;
return RT_EOK;
}
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
......@@ -406,7 +406,7 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
return size;
}
void rt_hw_sdcard_init()
void rt_hw_sdcard_init(void)
{
rt_uint8_t i, status;
rt_uint8_t *sector;
......
bsp/mini2440/startup.c
浏览文件 @ 7c83c7da
......@@ -38,6 +38,8 @@ extern void rt_application_init(void);
extern struct serial_device uart0;
extern struct rt_device uart0_device;
extern struct serial_device uart2;
extern struct rt_device uart2_device;
/**
* @addtogroup mini2440
......@@ -105,11 +107,16 @@ void rtthread_startup(void)
rt_system_scheduler_init();
#ifdef RT_USING_DEVICE
/* register uart1 */
/* register uart0 */
rt_hw_serial_register(&uart0_device, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart0);
/* register uart2, used for RTI debug */
rt_hw_serial_register(&uart2_device, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart2);
#ifdef RT_USING_DFS
rt_hw_sdcard_init();
#endif
......
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