diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S
index 89ac0292825726d0735d9c441fa970656165c8ec..bf68592e63e653b1d5919343966feb61daddb8db 100644
--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@@ -183,13 +183,11 @@ rt_hw_context_switch_to    PROC
     LDR     r0, =NVIC_INT_CTRL
     LDR     r1, =NVIC_PENDSVSET
     STR     r1, [r0]
-    NOP
 
     ; restore MSP
     LDR     r0, =SCB_VTOR
     LDR     r0, [r0]
     LDR     r0, [r0]
-    NOP
     MSR     msp, r0
 
     ; enable interrupts at processor level
@@ -216,4 +214,6 @@ HardFault_Handler    PROC
     POP     {pc}
     ENDP
 
+    ALIGN   4
+
     END
diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S
index 33fcd124d9e846a8acfe719a9dce56fe858bbec6..ebfd5c8da8c39aadbe784e6463f40af363c194cb 100644
--- a/libcpu/arm/cortex-m3/context_rvds.S
+++ b/libcpu/arm/cortex-m3/context_rvds.S
@@ -177,7 +177,6 @@ rt_hw_context_switch_to    PROC
 rt_hw_interrupt_thread_switch PROC
     EXPORT rt_hw_interrupt_thread_switch
     BX      lr
-    NOP
     ENDP
 
     IMPORT rt_hw_hard_fault_exception
@@ -203,5 +202,6 @@ HardFault_Handler    PROC
     BX      lr
     ENDP
 
-    NOP
-    END
\ No newline at end of file
+    ALIGN   4
+
+    END
diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S
index af7461fd498774a476afd943edff53df6a13a0ea..d7cb34d5c33dd6de3c11dd049d656fe1bcf5b5b5 100644
--- a/libcpu/arm/cortex-m4/context_rvds.S
+++ b/libcpu/arm/cortex-m4/context_rvds.S
@@ -218,7 +218,6 @@ rt_hw_context_switch_to    PROC
 rt_hw_interrupt_thread_switch PROC
     EXPORT rt_hw_interrupt_thread_switch
     BX      lr
-    NOP
     ENDP
 
     IMPORT rt_hw_hard_fault_exception
@@ -235,4 +234,6 @@ HardFault_Handler    PROC
     BX      lr
     ENDP
 
+    ALIGN   4
+
     END