diff --git a/bsp/rx/RPDL/Interrupt_INTC.c b/bsp/rx/RPDL/Interrupt_INTC.c new file mode 100644 index 0000000000000000000000000000000000000000..1460196348f009439bd291ef26b794d7e6b3d5de --- /dev/null +++ b/bsp/rx/RPDL/Interrupt_INTC.c @@ -0,0 +1,475 @@ +/* Adapted for use with IAR Embedded Workbench */ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_INTC.c +* Version : 1.02 +* Contents : Interrupt handlers for the external interrupts +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_intc.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/* External functions */ +extern void PowerON_Reset_PC(void); +extern void rpdl_ADC_10_Start(void); + +/* CMT control register definition */ +#define CMSTR_ADDRESS(a) ( (volatile uint16_t *)&CMT.CMSTR0 + ( (0x10u * (a >> 1)) / sizeof(uint16_t)) ) + +/*""FUNC COMMENT""*************************************************** +* Module outline: External interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_XXXX(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for External interrupts +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------ +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_INTC_callback_func[n]() +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ0 +__fast_interrupt void Interrupt_IRQ0(void) +#else +#pragma vector = VECT_ICU_IRQ0 +__interrupt void Interrupt_IRQ0(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ0] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ0](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ1 +__fast_interrupt void Interrupt_IRQ1(void) +#else +#pragma vector = VECT_ICU_IRQ1 +__interrupt void Interrupt_IRQ1(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ1] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ1](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ2 +__fast_interrupt void Interrupt_IRQ2(void) +#else +#pragma vector = VECT_ICU_IRQ2 +__interrupt void Interrupt_IRQ2(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ2] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ2](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ3 +__fast_interrupt void Interrupt_IRQ3(void) +#else +#pragma vector = VECT_ICU_IRQ3 +__interrupt void Interrupt_IRQ3(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ3] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ3](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ4 +__fast_interrupt void Interrupt_IRQ4(void) +#else +#pragma vector = VECT_ICU_IRQ4 +__interrupt void Interrupt_IRQ4(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ4] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ4](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ5 +__fast_interrupt void Interrupt_IRQ5(void) +#else +#pragma vector = VECT_ICU_IRQ5 +__interrupt void Interrupt_IRQ5(void) +#endif +{ +#ifdef DEVICE_PACKAGE_TFLGA_85 + /* This pin is not available on the 85-pin package */ + nop(); +#else + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ5] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ5](); + } +#endif +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ6 +__fast_interrupt void Interrupt_IRQ6(void) +#else +#pragma vector = VECT_ICU_IRQ6 +__interrupt void Interrupt_IRQ6(void) +#endif +{ +#ifdef DEVICE_PACKAGE_TFLGA_85 + /* This pin is not available on the 85-pin package */ + nop(); +#else + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ6] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ6](); + } +#endif +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ7 +__fast_interrupt void Interrupt_IRQ7(void) +#else +#pragma vector = VECT_ICU_IRQ7 +__interrupt void Interrupt_IRQ7(void) +#endif +{ +#ifdef DEVICE_PACKAGE_TFLGA_85 + /* This pin is not available on the 85-pin package */ + nop(); +#else + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ7] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ7](); + } +#endif +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ8 +__fast_interrupt void Interrupt_IRQ8(void) +#else +#pragma vector = VECT_ICU_IRQ8 +__interrupt void Interrupt_IRQ8(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ8] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ8](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ9 +__fast_interrupt void Interrupt_IRQ9(void) +#else +#pragma vector = VECT_ICU_IRQ9 +__interrupt void Interrupt_IRQ9(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ9] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ9](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ10 +__fast_interrupt void Interrupt_IRQ10(void) +#else +#pragma vector = VECT_ICU_IRQ10 +__interrupt void Interrupt_IRQ10(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ10] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ10](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ11 +__fast_interrupt void Interrupt_IRQ11(void) +#else +#pragma vector = VECT_ICU_IRQ11 +__interrupt void Interrupt_IRQ11(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ11] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ11](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ12 +__fast_interrupt void Interrupt_IRQ12(void) +#else +#pragma vector = VECT_ICU_IRQ12 +__interrupt void Interrupt_IRQ12(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ12] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ12](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ13 +__fast_interrupt void Interrupt_IRQ13(void) +#else +#pragma vector = VECT_ICU_IRQ13 +__interrupt void Interrupt_IRQ13(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ13] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ13](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ14 +__fast_interrupt void Interrupt_IRQ14(void) +#else +#pragma vector = VECT_ICU_IRQ14 +__interrupt void Interrupt_IRQ14(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ14] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ14](); + } +} + +#if FAST_INTC_VECTOR == VECT_ICU_IRQ15 +__fast_interrupt void Interrupt_IRQ15(void) +#else +#pragma vector = VECT_ICU_IRQ15 +__interrupt void Interrupt_IRQ15(void) +#endif +{ + /* Call the user function */ + if (rpdl_INTC_callback_func[PDL_INTC_IRQ15] != PDL_NO_FUNC) + { + rpdl_INTC_callback_func[PDL_INTC_IRQ15](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Software interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_SWINT(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for the software interrupt +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------ +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_INTC_callback_func[PDL_INTC_SWINT]() +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +/*""FUNC COMMENT""*************************************************** +* Module outline: Break interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_BRK(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for the break interrupt +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------ +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ +#if 0 +#pragma vector = 0 +__interrupt void Interrupt_BRK(void) +{ + uint32_t * vector_location; + volatile uint32_t * stacked_psw_ptr; + uint32_t psw_copy; + switch (rpdl_INTC_brk_command) + { + case BRK_START_ADC_10: + rpdl_ADC_10_Start(); + break; + case BRK_START_ADC_10_AND_SLEEP: + rpdl_ADC_10_Start(); + /* Prevent all-module clock stop */ + SYSTEM.MSTPCRA.BIT.ACSE = 0; + /* Select sleep or all-module clock stop */ + SYSTEM.SBYCR.BIT.SSBY = 0; + /* Prevent out-of-order execution */ + while (SYSTEM.SBYCR.BIT.SSBY != 0); + wait(); + break; + case BRK_SLEEP: + /* Prevent all-module clock stop */ + SYSTEM.MSTPCRA.BIT.ACSE = 0; + /* Select sleep or all-module clock stop */ + SYSTEM.SBYCR.BIT.SSBY = 0; + /* Prevent out-of-order execution */ + while (SYSTEM.SBYCR.BIT.SSBY != 0); + wait(); + break; + case BRK_ALL_MODULE_CLOCK_STOP: + /* Select sleep or all-module clock stop */ + SYSTEM.SBYCR.BIT.SSBY = 0; + /* Prevent out-of-order execution */ + while (SYSTEM.SBYCR.BIT.SSBY != 0); + wait(); + break; + case BRK_STANDBY: + /* Prevent deep standby mode */ + SYSTEM.DPSBYCR.BIT.DPSBY = 0; + /* Select standby mode */ + SYSTEM.SBYCR.BIT.SSBY = 1; + /* Prevent out-of-order execution */ + while (SYSTEM.SBYCR.BIT.SSBY != 1); + wait(); + break; + case BRK_DEEP_STANDBY: + /* Stop the RAM clock */ + SYSTEM.MSTPCRC.BIT.MSTPC0 = 1; + SYSTEM.MSTPCRC.BIT.MSTPC1 = 1; + /* Select deep standby mode */ + SYSTEM.DPSBYCR.BIT.DPSBY = 1; + /* Select standby mode */ + SYSTEM.SBYCR.BIT.SSBY = 1; + /* Prevent out-of-order execution */ + while (SYSTEM.SBYCR.BIT.SSBY != 1); + wait(); + break; + case BRK_LOAD_FINTV_REGISTER: + /* Find the start of the maskable interrupt vector table */ + vector_location = (uint32_t *)get_intb(); + /* Move to the location of the address of the selected interrupt */ + vector_location += ICU.FIR.BIT.FVCT; + /* Store the address of this vector in the FINTV register */ + set_fintv((__fast_int_f)*vector_location); + break; + case BRK_WRITE_IPL: + /* Find the stacked PSW */ + stacked_psw_ptr = (uint32_t *)(rpdl_INTC_saved_isp) - 1; + /* Read the stacked PSW */ + psw_copy = *stacked_psw_ptr; + /* Clear the IPL bits */ + psw_copy &= (uint32_t)(INV_BIT_27 & INV_BIT_26 & INV_BIT_25 & INV_BIT_24); + /* Modify the IPL bits */ + psw_copy |= (uint32_t)(rpdl_INTC_brk_data8 << 24); + /* Modify the saved IPL */ + *stacked_psw_ptr = psw_copy; + break; + case BRK_CMT_START: + /* Set STRn to 1 */ + *(CMSTR_ADDRESS(rpdl_INTC_brk_data8)) |= (uint16_t)((rpdl_INTC_brk_data8 & 0x01u) + 1); + break; + case BRK_CMT_STOP: + /* Set STRn to 0 */ + *(CMSTR_ADDRESS(rpdl_INTC_brk_data8)) &= (uint16_t)(0x2u >> (rpdl_INTC_brk_data8 & 0x01u)); + break; + default: + /* This must never occur */ + break; + } + rpdl_INTC_brk_command = BRK_NO_COMMAND; +} + #endif +/* Exception (Privileged Instruction) */ +__interrupt void __privileged_handler(void) +{ + if (rpdl_INTC_callback_func[PDL_INTC_PRIVILEGED] != PDL_NO_FUNC) + { + /* Call the user function */ + rpdl_INTC_callback_func[PDL_INTC_PRIVILEGED](); + } +} + +/* Exception (Undefined Instruction) */ +__interrupt void __undefined_handler(void) +{ + if (rpdl_INTC_callback_func[PDL_INTC_UNDEFINED] != PDL_NO_FUNC) + { + /* Call the user function */ + rpdl_INTC_callback_func[PDL_INTC_UNDEFINED](); + } +} + +/* Exception(Floating Point) */ +__interrupt void __floating_point_handler(void) +{ + if (rpdl_INTC_callback_func[PDL_INTC_FLOATING_POINT] != PDL_NO_FUNC) + { + /* Call the user function */ + rpdl_INTC_callback_func[PDL_INTC_FLOATING_POINT](); + } +} + +__interrupt void __NMI_handler(void) +{ + if (rpdl_INTC_callback_func[PDL_INTC_NMI] != PDL_NO_FUNC) + { + /* Call the user function */ + rpdl_INTC_callback_func[PDL_INTC_NMI](); + } +} + +/* End of file */ diff --git a/bsp/rx/RPDL/Interrupt_RTC.c b/bsp/rx/RPDL/Interrupt_RTC.c new file mode 100644 index 0000000000000000000000000000000000000000..c195cd7992bc8b0d7dd6c688a76a0d2aeb972fe2 --- /dev/null +++ b/bsp/rx/RPDL/Interrupt_RTC.c @@ -0,0 +1,132 @@ +/*""FILE COMMENT""******************************************************* +* System Name : RTC Interrupt program for RX62Nxx +* File Name : Interrupt_RTC.c +* Version : 1.02 +* Contents : Interrupt handler for RTC +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_rtc.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline: RTC periodic interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_RTC_PRD(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for RTC +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_RTC_Periodic_callback_func() +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ +#if FAST_INTC_VECTOR == VECT_RTC_PRD +__fast_interrupt void Interrupt_RTC_PRD(void) +#else +#pragma vector = VECT_RTC_PRD +__interrupt void Interrupt_RTC_PRD(void) +#endif +{ + /* Call the user function */ + if (rpdl_RTC_Periodic_callback_func != PDL_NO_FUNC) + { + rpdl_RTC_Periodic_callback_func(); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: RTC alarm interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_RTC_ALM(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for RTC +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_RTC_Alarm_callback_func() +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ +#if FAST_INTC_VECTOR == VECT_RTC_ALM +__fast_interrupt void Interrupt_RTC_ALM(void) +#else +#pragma vector = VECT_RTC_ALM +__interrupt void Interrupt_RTC_ALM(void) +#endif +{ + /* Call the user function */ + if (rpdl_RTC_Alarm_callback_func != PDL_NO_FUNC) + { + rpdl_RTC_Alarm_callback_func(); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: RTC Carry interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_RTC_CUP(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for RTC +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : +*------------------------------------------------------------------- +* Notes : This interrupt is not used. +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ +#if FAST_INTC_VECTOR == VECT_RTC_CUP +__fast_interrupt void Interrupt_RTC_CUP(void) +#else +#pragma vector = VECT_RTC_CUP +__interrupt void Interrupt_RTC_CUP(void) +#endif +{ + /* Disable further requests */ + ICU.IER[IER_RTC_CUP].BIT.IEN_RTC_CUP = 0; +} + +/* End of file */ diff --git a/bsp/rx/RPDL/Interrupt_SPI.c b/bsp/rx/RPDL/Interrupt_SPI.c new file mode 100644 index 0000000000000000000000000000000000000000..61df961f4ed5dbcaaf4cec03be75c835a37291e1 --- /dev/null +++ b/bsp/rx/RPDL/Interrupt_SPI.c @@ -0,0 +1,568 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_SPI.c +* Version : 1.02 +* Contents : Interrupt handlers for all SPI channels +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_spi.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline: SPIn receive data error interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_RSPIn_SPEIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : None +*------------------------------------------------------------------- +* Use function : rpdl_SPI_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_RSPI0_SPEI0 +__fast_interrupt void Interrupt_RSPI0_SPEI0(void) +#else +#pragma vector = VECT_RSPI0_SPEI0 +__interrupt void Interrupt_RSPI0_SPEI0(void) +#endif +{ + /* Will the user handle the errors? */ + if (rpdl_SPI_callback_func[0] != PDL_NO_FUNC) + { + /* Notify the user */ + rpdl_SPI_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_RSPI1_SPEI1 +__fast_interrupt void Interrupt_RSPI1_SPEI1(void) +#else +#pragma vector = VECT_RSPI1_SPEI1 +__interrupt void Interrupt_RSPI1_SPEI1(void) +#endif +{ + /* Will the user handle the errors? */ + if (rpdl_SPI_callback_func[1] != PDL_NO_FUNC) + { + /* Notify the user */ + rpdl_SPI_callback_func[1](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: SPIn receive data interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_RSPIn_SPRIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : (I/ ) : SPDCR, SBDR +* Output : (I/O) : SPCR, SPCR2 +*------------------------------------------------------------------- +* Use function : None +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_RSPI0_SPRI0 +__fast_interrupt void Interrupt_RSPI0_SPRI0(void) +#else +#pragma vector = VECT_RSPI0_SPRI0 +__interrupt void Interrupt_RSPI0_SPRI0(void) +#endif +{ + uint8_t frame_count; + uint32_t received_frame; + uint8_t spdcr_copy; + uint8_t splw; + uint8_t spfc; + volatile uint32_t * rx_data_ptr; + + /* Ok to process the data? */ + if (rpdl_SPI_method[0] == SPI_USING_IRQ) + { + spdcr_copy = RSPI0.SPDCR.BYTE; + splw = (uint8_t)(spdcr_copy & BIT_5); + spfc = (uint8_t)(spdcr_copy & 0x03u); + rx_data_ptr = rpdl_SPI_rx_ptr[0]; + + /* Load the data register */ + for (frame_count = 0; frame_count <= spfc; frame_count++) + { + if (splw == 0) + { + /* Read the data */ + received_frame = (uint32_t)RSPI0.SPDR.WORD.H; + } + else + { + /* Read the data */ + received_frame = RSPI0.SPDR.LONG; + } + + /* Store the data? */ + if (rx_data_ptr != PDL_NO_PTR) + { + *rx_data_ptr = received_frame; + + /* Increment the address pointer */ + rx_data_ptr ++; + } + + /* Increment the frame counter */ + rpdl_SPI_rx_frame_counter[0] ++; + } + + /* Store the updated pointer */ + rpdl_SPI_rx_ptr[0] = rx_data_ptr; + + /* All data read? */ + if (rpdl_SPI_rx_frame_counter[0] == rpdl_SPI_frame_total[0]) + { + /* Increment the loop counter */ + rpdl_SPI_rx_sequence_counter[0]++; + + /* All loops completed? */ + if (rpdl_SPI_rx_sequence_counter[0] == rpdl_SPI_sequence_count[0]) + { + /* Disable receive interrupts */ + RSPI0.SPCR.BIT.SPRIE = 0; + + /* Master mode? */ + if (RSPI0.SPCR.BIT.MSTR == 1) + { + /* Enable idle interrupts */ + RSPI0.SPCR2.BIT.SPIIE = 1; + } + else + { + /* Notify the user */ + if (rpdl_SPI_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[0](); + } + } + } + else + { + /* Reset the frame counter */ + rpdl_SPI_rx_frame_counter[0] = 0; + } + } + } + else + { + /* Notify the user */ + if (rpdl_SPI_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[0](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_RSPI1_SPRI1 +__fast_interrupt void Interrupt_RSPI1_SPRI1(void) +#else +#pragma vector = VECT_RSPI1_SPRI1 +__interrupt void Interrupt_RSPI1_SPRI1(void) +#endif +{ + uint8_t frame_count; + uint32_t received_frame; + uint8_t spdcr_copy; + uint8_t splw; + uint8_t spfc; + volatile uint32_t * rx_data_ptr; + + /* Ok to process the data? */ + if (rpdl_SPI_method[1] == SPI_USING_IRQ) + { + spdcr_copy = RSPI1.SPDCR.BYTE; + splw = (uint8_t)(spdcr_copy & BIT_5); + spfc = (uint8_t)(spdcr_copy & 0x03u); + rx_data_ptr = rpdl_SPI_rx_ptr[1]; + + /* Load the data register */ + for (frame_count = 0; frame_count <= spfc; frame_count++) + { + if (splw == 0) + { + /* Read the data */ + received_frame = (uint32_t)RSPI1.SPDR.WORD.H; + } + else + { + /* Read the data */ + received_frame = RSPI1.SPDR.LONG; + } + + /* Store the data? */ + if (rx_data_ptr != PDL_NO_PTR) + { + *rx_data_ptr = received_frame; + + /* Increment the address pointer */ + rx_data_ptr ++; + } + + /* Increment the frame counter */ + rpdl_SPI_rx_frame_counter[1] ++; + } + + /* Store the updated pointer */ + rpdl_SPI_rx_ptr[1] = rx_data_ptr; + + /* All data read? */ + if (rpdl_SPI_rx_frame_counter[1] == rpdl_SPI_frame_total[1]) + { + /* Increment the loop counter */ + rpdl_SPI_rx_sequence_counter[1]++; + + /* All loops completed? */ + if (rpdl_SPI_rx_sequence_counter[1] == rpdl_SPI_sequence_count[1]) + { + /* Disable receive interrupts */ + RSPI1.SPCR.BIT.SPRIE = 0; + + /* Master mode? */ + if (RSPI1.SPCR.BIT.MSTR == 1) + { + /* Enable idle interrupts */ + RSPI1.SPCR2.BIT.SPIIE = 1; + } + else + { + /* Notify the user */ + if (rpdl_SPI_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[1](); + } + } + } + else + { + /* Reset the frame counter */ + rpdl_SPI_rx_frame_counter[1] = 0; + } + } + } + else + { + /* Notify the user */ + if (rpdl_SPI_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[1](); + } + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: SPIn transmit data interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_RSPIn_SPTIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : (I/ ) : SPDCR +* Output : ( /O) : SBDR +* : (I/O) : SPCR, SPCR2 +*------------------------------------------------------------------- +* Use function : +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_RSPI0_SPTI0 +__fast_interrupt void Interrupt_RSPI0_SPTI0(void) +#else +#pragma vector = VECT_RSPI0_SPTI0 +__interrupt void Interrupt_RSPI0_SPTI0(void) +#endif +{ + uint8_t frame_count; + uint8_t spdcr_copy; + uint8_t splw; + uint8_t spfc; + volatile const uint32_t * tx_data_ptr; + + /* Ok to process the string? */ + if (rpdl_SPI_method[0] == SPI_USING_IRQ) + { + spdcr_copy = RSPI0.SPDCR.BYTE; + splw = (uint8_t)(spdcr_copy & BIT_5); + spfc = (uint8_t)(spdcr_copy & 0x03u); + tx_data_ptr = rpdl_SPI_tx_ptr[0]; + + /* Load the data register */ + for (frame_count = 0; frame_count <= spfc; frame_count++) + { + if (splw == 0) + { + RSPI0.SPDR.WORD.H = (uint16_t)*tx_data_ptr; + } + else + { + RSPI0.SPDR.LONG = *tx_data_ptr; + } + + /* Increment the address pointer? */ + if (tx_data_ptr != PDL_NO_PTR) + { + tx_data_ptr ++; + } + + /* Increment the frame counter */ + rpdl_SPI_tx_frame_counter[0] ++; + } + + /* Store the updated pointer */ + rpdl_SPI_tx_ptr[0] = tx_data_ptr; + + /* All data written? */ + if (rpdl_SPI_tx_frame_counter[0] == rpdl_SPI_frame_total[0]) + { + /* Increment the loop counter */ + rpdl_SPI_tx_sequence_counter[0]++; + + /* All loops completed? */ + if (rpdl_SPI_tx_sequence_counter[0] == rpdl_SPI_sequence_count[0]) + { + /* Disable transmit interrupts */ + RSPI0.SPCR.BIT.SPTIE = 0; + + /* Transmit only? */ + if (RSPI0.SPCR.BIT.TXMD == 1) + { + /* Master mode? */ + if (RSPI0.SPCR.BIT.MSTR == 1) + { + /* Enable idle interrupts */ + RSPI0.SPCR2.BIT.SPIIE = 1; + } + else + { + /* Notify the user */ + if (rpdl_SPI_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[0](); + } + } + } + } + else + { + /* Reset the frame counter */ + rpdl_SPI_tx_frame_counter[0] = 0; + } + } + } + else + { + /* Notify the user */ + if (rpdl_SPI_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[0](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_RSPI1_SPTI1 +__fast_interrupt void Interrupt_RSPI1_SPTI1(void) +#else +#pragma vector = VECT_RSPI1_SPTI1 +__interrupt void Interrupt_RSPI1_SPTI1(void) +#endif +{ + uint8_t frame_count; + uint8_t spdcr_copy; + uint8_t splw; + uint8_t spfc; + volatile const uint32_t * tx_data_ptr; + + /* Ok to process the string? */ + if (rpdl_SPI_method[1] == SPI_USING_IRQ) + { + spdcr_copy = RSPI1.SPDCR.BYTE; + splw = (uint8_t)(spdcr_copy & BIT_5); + spfc = (uint8_t)(spdcr_copy & 0x03u); + tx_data_ptr = rpdl_SPI_tx_ptr[1]; + + /* Load the data register */ + for (frame_count = 0; frame_count <= spfc; frame_count++) + { + if (splw == 0) + { + RSPI1.SPDR.WORD.H = (uint16_t)*tx_data_ptr; + } + else + { + RSPI1.SPDR.LONG = *tx_data_ptr; + } + + /* Increment the address pointer? */ + if (tx_data_ptr != PDL_NO_PTR) + { + tx_data_ptr ++; + } + + /* Increment the frame counter */ + rpdl_SPI_tx_frame_counter[1] ++; + } + + /* Store the updated pointer */ + rpdl_SPI_tx_ptr[1] = tx_data_ptr; + + /* All data written? */ + if (rpdl_SPI_tx_frame_counter[1] == rpdl_SPI_frame_total[1]) + { + /* Increment the loop counter */ + rpdl_SPI_tx_sequence_counter[1]++; + + /* All loops completed? */ + if (rpdl_SPI_tx_sequence_counter[1] == rpdl_SPI_sequence_count[1]) + { + /* Disable transmit interrupts */ + RSPI1.SPCR.BIT.SPTIE = 0; + + /* Transmit only? */ + if (RSPI1.SPCR.BIT.TXMD == 1) + { + /* Master mode? */ + if (RSPI1.SPCR.BIT.MSTR == 1) + { + /* Enable idle interrupts */ + RSPI1.SPCR2.BIT.SPIIE = 1; + } + else + { + /* Notify the user */ + if (rpdl_SPI_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[1](); + } + } + } + } + else + { + /* Reset the frame counter */ + rpdl_SPI_tx_frame_counter[1] = 0; + } + } + } + else + { + /* Notify the user */ + if (rpdl_SPI_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[1](); + } + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: SPIn idle interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_RSPIn_SPIIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : SPCR, SPCR2 +*------------------------------------------------------------------- +* Use function : rpdl_SPI_callback_func() +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_RSPI0_SPII0 +__fast_interrupt void Interrupt_RSPI0_SPII0(void) +#else +#pragma vector = VECT_RSPI0_SPII0 +__interrupt void Interrupt_RSPI0_SPII0(void) +#endif +{ + /* Disable the channel */ + RSPI0.SPCR.BIT.SPE = 0; + + /* Disable idle interrupts */ + RSPI0.SPCR2.BIT.SPIIE = 0; + + /* Call the callback function */ + if (rpdl_SPI_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_RSPI1_SPII1 +__fast_interrupt void Interrupt_RSPI1_SPII1(void) +#else +#pragma vector = VECT_RSPI1_SPII1 +__interrupt void Interrupt_RSPI1_SPII1(void) +#endif +{ + /* Disable the channel */ + RSPI1.SPCR.BIT.SPE = 0; + + /* Disable idle interrupts */ + RSPI1.SPCR2.BIT.SPIIE = 0; + + /* Call the callback function */ + if (rpdl_SPI_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SPI_callback_func[1](); + } +} + +/* End of file */ diff --git a/bsp/rx/RPDL/Interrupt_TMR.c b/bsp/rx/RPDL/Interrupt_TMR.c new file mode 100644 index 0000000000000000000000000000000000000000..e8a8652b33a5cfabe45caa6c483a85ba226dca68 --- /dev/null +++ b/bsp/rx/RPDL/Interrupt_TMR.c @@ -0,0 +1,286 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_TMR.c +* Version : 1.02 +* Contents : Interrupt handlers for the Timer units +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_tmr.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline : Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_TMRn_XXX(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for Timer TMR channel n +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : R_TmrOverflowFunc[n](), R_TmrCMAFunc[n]() or +* : R_TmrCMBFunc[n]() as appropriate. +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_TMR0_CMIA0 +__fast_interrupt void Interrupt_TMR0_CMA(void) +#else +#pragma vector = VECT_TMR0_CMIA0 +__interrupt void Interrupt_TMR0_CMA(void) +#endif +{ + /* Call the user function? */ + if (rpdl_TMR_CMA_callback_func[0] != PDL_NO_FUNC) + { + /* Call the user function */ + rpdl_TMR_CMA_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR0_CMIB0 +__fast_interrupt void Interrupt_TMR0_CMB(void) +#else +#pragma vector = VECT_TMR0_CMIB0 +__interrupt void Interrupt_TMR0_CMB(void) +#endif +{ + if (rpdl_TMR_one_shot[0] != false) + { + /* Channel mode? */ + if (rpdl_TMR_one_shot[0] == CHANNEL_MODE) + { + /* Stop the channel 0 clock input */ + TMR0.TCCR.BYTE = 0x00u; + } + /* Unit mode? */ + else + { + /* Stop the channel 1 clock input */ + TMR1.TCCR.BYTE = 0x00u; + } + + rpdl_TMR_one_shot[0] = false; + + /* Clear the interrupt request flag (the timer may have set it again) */ + ICU.IR[VECT_TMR0_CMIB0].BIT.IR = 0; + } + + /* Call the user function? */ + if (rpdl_TMR_CMB_callback_func[0] != PDL_NO_FUNC) + { + rpdl_TMR_CMB_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR0_OVI0 +__fast_interrupt void Interrupt_TMR0_OV(void) +#else +#pragma vector = VECT_TMR0_OVI0 +__interrupt void Interrupt_TMR0_OV(void) +#endif +{ + /* Call the user function */ + if (rpdl_TMR_Overflow_callback_func[0] != PDL_NO_FUNC) + { + rpdl_TMR_Overflow_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR1_CMIA1 +__fast_interrupt void Interrupt_TMR1_CMA(void) +#else +#pragma vector = VECT_TMR1_CMIA1 +__interrupt void Interrupt_TMR1_CMA(void) +#endif +{ + /* Call the user function? */ + if (rpdl_TMR_CMA_callback_func[1] != PDL_NO_FUNC) + { + /* Call the user function */ + rpdl_TMR_CMA_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR1_CMIB1 +__fast_interrupt void Interrupt_TMR1_CMB(void) +#else +#pragma vector = VECT_TMR1_CMIB1 +__interrupt void Interrupt_TMR1_CMB(void) +#endif +{ + if (rpdl_TMR_one_shot[1] != false) + { + /* Stop the channel 1 clock input */ + TMR1.TCCR.BYTE = 0x00u; + + rpdl_TMR_one_shot[1] = false; + + /* Clear the interrupt request flag (the timer may have set it again) */ + ICU.IR[VECT_TMR1_CMIB1].BIT.IR = 0u; + } + + /* Call the user function? */ + if (rpdl_TMR_CMB_callback_func[1] != PDL_NO_FUNC) + { + rpdl_TMR_CMB_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR1_OVI1 +__fast_interrupt void Interrupt_TMR1_OV(void) +#else +#pragma vector = VECT_TMR1_OVI1 +__interrupt void Interrupt_TMR1_OV(void) +#endif +{ + /* Call the user function */ + if (rpdl_TMR_Overflow_callback_func[1] != PDL_NO_FUNC) + { + rpdl_TMR_Overflow_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR2_CMIA2 +__fast_interrupt void Interrupt_TMR2_CMA(void) +#else +#pragma vector = VECT_TMR2_CMIA2 +__interrupt void Interrupt_TMR2_CMA(void) +#endif +{ + /* Call the user function? */ + if (rpdl_TMR_CMA_callback_func[2] != PDL_NO_FUNC) + { + /* Call the user function */ + rpdl_TMR_CMA_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR2_CMIB2 +__fast_interrupt void Interrupt_TMR2_CMB(void) +#else +#pragma vector = VECT_TMR2_CMIB2 +__interrupt void Interrupt_TMR2_CMB(void) +#endif +{ + if (rpdl_TMR_one_shot[2] != false) + { + /* Channel mode? */ + if (rpdl_TMR_one_shot[2] == CHANNEL_MODE) + { + /* Stop the channel 2 clock input */ + TMR2.TCCR.BYTE = 0x00u; + } + /* Unit mode? */ + else + { + /* Stop the channel 3 clock input */ + TMR3.TCCR.BYTE = 0x00u; + } + + rpdl_TMR_one_shot[2] = false; + + /* Clear the interrupt request flag (the timer may have set it again) */ + ICU.IR[VECT_TMR2_CMIB2].BIT.IR = 0; + } + + /* Call the user function? */ + if (rpdl_TMR_CMB_callback_func[2] != PDL_NO_FUNC) + { + rpdl_TMR_CMB_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR2_OVI2 +__fast_interrupt void Interrupt_TMR2_OV(void) +#else +#pragma vector = VECT_TMR2_OVI2 +__interrupt void Interrupt_TMR2_OV(void) +#endif +{ + /* Call the user function */ + if (rpdl_TMR_Overflow_callback_func[2] != PDL_NO_FUNC) + { + rpdl_TMR_Overflow_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR3_CMIA3 +__fast_interrupt void Interrupt_TMR3_CMA(void) +#else +#pragma vector = VECT_TMR3_CMIA3 +__interrupt void Interrupt_TMR3_CMA(void) +#endif +{ + /* Call the user function? */ + if (rpdl_TMR_CMA_callback_func[3] != PDL_NO_FUNC) + { + /* Call the user function */ + rpdl_TMR_CMA_callback_func[3](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR3_CMIB3 +__fast_interrupt void Interrupt_TMR3_CMB(void) +#else +#pragma vector = VECT_TMR3_CMIB3 +__interrupt void Interrupt_TMR3_CMB(void) +#endif +{ + if (rpdl_TMR_one_shot[3] != false) + { + /* Stop the channel 3 clock input */ + TMR3.TCCR.BYTE = 0x00u; + + rpdl_TMR_one_shot[3] = false; + + /* Clear the interrupt request flag (the timer may have set it again) */ + ICU.IR[VECT_TMR3_CMIB3].BIT.IR = 0; + } + + /* Call the user function? */ + if (rpdl_TMR_CMB_callback_func[3] != PDL_NO_FUNC) + { + rpdl_TMR_CMB_callback_func[3](); + } +} + +#if FAST_INTC_VECTOR == VECT_TMR3_OVI3 +__fast_interrupt void Interrupt_TMR3_OV(void) +#else +#pragma vector = VECT_TMR3_OVI3 +__interrupt void Interrupt_TMR3_OV(void) +#endif +{ + /* Call the user function */ + if (rpdl_TMR_Overflow_callback_func[3] != PDL_NO_FUNC) + { + rpdl_TMR_Overflow_callback_func[3](); + } +} +/* End of file */ diff --git a/bsp/rx/RPDL/RX62N_library_LQFP_100.a b/bsp/rx/RPDL/RX62N_library_LQFP_100.a new file mode 100644 index 0000000000000000000000000000000000000000..8871f462e94cb53d9106798e439ee1d7dbfeda75 Binary files /dev/null and b/bsp/rx/RPDL/RX62N_library_LQFP_100.a differ diff --git a/bsp/rx/RPDL/interrupt_adc_10.c b/bsp/rx/RPDL/interrupt_adc_10.c new file mode 100644 index 0000000000000000000000000000000000000000..2dd08444e2c2e9d2b9d113841487a382f9250b82 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_adc_10.c @@ -0,0 +1,78 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_ADC_10.c +* Version : 1.02 +* Contents : Interrupt handlers for the ADC units +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_adc_10.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline: ADC interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_ADCn(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for ADC unit n +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : ADC_callback_func[n]() +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_AD0_ADI0 +__fast_interrupt void Interrupt_ADC0(void) +#else +#pragma vector = VECT_AD0_ADI0 +__interrupt void Interrupt_ADC0(void) +#endif +{ + /* Call the user function */ + if (rpdl_ADC_10_callback_func[0] != PDL_NO_FUNC) + { + rpdl_ADC_10_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_AD1_ADI1 +__fast_interrupt void Interrupt_ADC1(void) +#else +#pragma vector = VECT_AD1_ADI1 +__interrupt void Interrupt_ADC1(void) +#endif +{ + /* Call the user function */ + if (rpdl_ADC_10_callback_func[1] != PDL_NO_FUNC) + { + rpdl_ADC_10_callback_func[1](); + } +} + +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_adc_12.c b/bsp/rx/RPDL/interrupt_adc_12.c new file mode 100644 index 0000000000000000000000000000000000000000..e60c440ea39843a982d74d4e396b21e8076de524 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_adc_12.c @@ -0,0 +1,64 @@ +/*""FILE COMMENT""******************************************************* +* System Name : 12-bit ADC Interrupt program for RX62Nxx +* File Name : Interrupt_ADC_12.c +* Version : 1.02 +* Contents : Interrupt handler for ADC_12 +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_adc_12.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline: ADC interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_ADCn(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for ADC unit n +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_ADC_12_callback_func[n]() +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_S12AD_ADI +__fast_interrupt void Interrupt_ADC_12_0(void) +#else +#pragma vector = VECT_S12AD_ADI +__interrupt void Interrupt_ADC_12_0(void) +#endif +{ + /* Call the user function */ + if (rpdl_ADC_12_callback_func[0] != PDL_NO_FUNC) + { + rpdl_ADC_12_callback_func[0](); + } +} + +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_bsc.c b/bsp/rx/RPDL/interrupt_bsc.c new file mode 100644 index 0000000000000000000000000000000000000000..c12a05a214af191fa60eed4a58685d00a896eae8 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_bsc.c @@ -0,0 +1,63 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_BSC.c +* Version : 1.02 +* Contents : Interrupt handler for the BSC +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_bsc.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline : BSC interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_BSC(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for the BSC +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_BSC_callback_func +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_BSC_BUSERR +__fast_interrupt void Interrupt_BSC(void) +#else +#pragma vector = VECT_BSC_BUSERR +__interrupt void Interrupt_BSC(void) +#endif +{ + /* Call the user function */ + if (rpdl_BSC_callback_func != PDL_NO_FUNC) + { + rpdl_BSC_callback_func(); + } +} +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_cmt.c b/bsp/rx/RPDL/interrupt_cmt.c new file mode 100644 index 0000000000000000000000000000000000000000..700ebf301a6ccbb62b8aa61bce83c3ebb5e5b865 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_cmt.c @@ -0,0 +1,141 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_CMT.c +* Version : 1.02 +* Contents : Interrupt handlers for the CMT channels +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_cmt.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline : Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_CMTn(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for CMT channel n +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : CMT_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ +#if 0 +#if FAST_INTC_VECTOR == VECT_CMT0_CMI0 +__fast_interrupt void Interrupt_CMT0(void) +#else +#pragma vector = VECT_CMT0_CMI0 +__interrupt void Interrupt_CMT0(void) +#endif +{ + if (rpdl_CMT_one_shot[0] != false) + { + /* Stop the channel 0 clock input */ + CMT.CMSTR0.BIT.STR0 = 0; + + /* Clear the interrupt request flag (the timer may have set it again) */ + ICU.IR[IR_CMT0_CMI0].BIT.IR = 0; + } + + /* Call the user function */ + if (rpdl_CMT_callback_func[0] != PDL_NO_FUNC) + { + rpdl_CMT_callback_func[0](); + } +} +#endif +#if FAST_INTC_VECTOR == VECT_CMT1_CMI1 +__fast_interrupt void Interrupt_CMT1(void) +#else +#pragma vector = VECT_CMT1_CMI1 +__interrupt void Interrupt_CMT1(void) +#endif +{ + if (rpdl_CMT_one_shot[1] != false) + { + /* Stop the channel 0 clock input */ + CMT.CMSTR0.BIT.STR1 = 0; + + /* Clear the interrupt request flag (the timer may have set it again) */ + ICU.IR[IR_CMT1_CMI1].BIT.IR = 0; + } + + /* Call the user function */ + if (rpdl_CMT_callback_func[1] != PDL_NO_FUNC) + { + rpdl_CMT_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_CMT2_CMI2 +__fast_interrupt void Interrupt_CMT2(void) +#else +#pragma vector = VECT_CMT2_CMI2 +__interrupt void Interrupt_CMT2(void) +#endif +{ + if (rpdl_CMT_one_shot[2] != false) + { + /* Stop the channel 0 clock input */ + CMT.CMSTR1.BIT.STR2 = 0; + + /* Clear the interrupt request flag (the timer may have set it again) */ + ICU.IR[IR_CMT2_CMI2].BIT.IR = 0; + } + + /* Call the user function */ + if (rpdl_CMT_callback_func[2] != PDL_NO_FUNC) + { + rpdl_CMT_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_CMT3_CMI3 +__fast_interrupt void Interrupt_CMT3(void) +#else +#pragma vector = VECT_CMT3_CMI3 +__interrupt void Interrupt_CMT3(void) +#endif +{ + if (rpdl_CMT_one_shot[3] != false) + { + /* Stop the channel 0 clock input */ + CMT.CMSTR1.BIT.STR3 = 0; + + /* Clear the interrupt request flag (the timer may have set it again) */ + ICU.IR[IR_CMT3_CMI3].BIT.IR = 0; + } + + /* Call the user function */ + if (rpdl_CMT_callback_func[3] != PDL_NO_FUNC) + { + rpdl_CMT_callback_func[3](); + } +} +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_dmac.c b/bsp/rx/RPDL/interrupt_dmac.c new file mode 100644 index 0000000000000000000000000000000000000000..cd830ecff05a64ef8d05de9b07123b5f50320661 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_dmac.c @@ -0,0 +1,105 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62N +* File Name : Interrupt_DMAC.c +* Version : 1.02 +* Contents : Interrupt handlers for the DMAC channels +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_dmac.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline : DMAC interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_DMACn(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for DMAC channel n +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : DMAC_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_DMAC_DMAC0I +__fast_interrupt void Interrupt_DMAC0(void) +#else +#pragma vector = VECT_DMAC_DMAC0I +__interrupt void Interrupt_DMAC0(void) +#endif +{ + /* Call the user function */ + if (rpdl_DMAC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_DMAC_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_DMAC_DMAC1I +__fast_interrupt void Interrupt_DMAC1(void) +#else +#pragma vector = VECT_DMAC_DMAC1I +__interrupt void Interrupt_DMAC1(void) +#endif +{ + /* Call the user function */ + if (rpdl_DMAC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_DMAC_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_DMAC_DMAC2I +__fast_interrupt void Interrupt_DMAC2(void) +#else +#pragma vector = VECT_DMAC_DMAC2I +__interrupt void Interrupt_DMAC2(void) +#endif +{ + /* Call the user function */ + if (rpdl_DMAC_callback_func[2] != PDL_NO_FUNC) + { + rpdl_DMAC_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_DMAC_DMAC3I +__fast_interrupt void Interrupt_DMAC3(void) +#else +#pragma vector = VECT_DMAC_DMAC3I +__interrupt void Interrupt_DMAC3(void) +#endif +{ + /* Call the user function */ + if (rpdl_DMAC_callback_func[3] != PDL_NO_FUNC) + { + rpdl_DMAC_callback_func[3](); + } +} +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_exdmac.c b/bsp/rx/RPDL/interrupt_exdmac.c new file mode 100644 index 0000000000000000000000000000000000000000..2a98f8cef43138dcf0e42a4369e2f65931db049e --- /dev/null +++ b/bsp/rx/RPDL/interrupt_exdmac.c @@ -0,0 +1,88 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62N +* File Name : Interrupt_EXDMAC.c +* Version : 1.02 +* Contents : Interrupt handlers for the EXDMAC channels +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_exdmac.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline : EXDMAC interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_EXDMACn(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for EXDMAC channel n +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : EXDMAC_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_EXDMAC_EXDMAC0I +__fast_interrupt void Interrupt_EXDMAC0(void) +#else +#pragma vector = VECT_EXDMAC_EXDMAC0I +__interrupt void Interrupt_EXDMAC0(void) +#endif +{ +#if defined(DEVICE_PACKAGE_LQFP_100) || defined(DEVICE_PACKAGE_TFLGA_85) + /* This peripheral is not available on the 100-pin or 85-pin packages */ + nop(); +#else + /* Call the user function */ + if (rpdl_EXDMAC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_EXDMAC_callback_func[0](); + } +#endif +} + +#if FAST_INTC_VECTOR == VECT_EXDMAC_EXDMAC1I +__fast_interrupt void Interrupt_EXDMAC1(void) +#else +#pragma vector = VECT_EXDMAC_EXDMAC1I +__interrupt void Interrupt_EXDMAC1(void) +#endif +{ +#if defined(DEVICE_PACKAGE_LQFP_100) || defined(DEVICE_PACKAGE_TFLGA_85) + /* This peripheral is not available on the 100-pin or 85-pin packages */ + nop(); +#else + /* Call the user function */ + if (rpdl_EXDMAC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_EXDMAC_callback_func[1](); + } +#endif +} + +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_iic.c b/bsp/rx/RPDL/interrupt_iic.c new file mode 100644 index 0000000000000000000000000000000000000000..d5d71c224a47b56f0c357d78c576abf8df1edb28 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_iic.c @@ -0,0 +1,901 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nx +* File Name : Interrupt_IIC.c +* Version : 1.02 +* Contents : Interrupt handlers for all IIC channels +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_iic.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/* For DMAC support */ +#define DMCNT_ADDRESS(a) ((volatile uint8_t *)&DMAC0.DMCNT + ((0x40u * a) / sizeof( uint8_t)) ) + +/* External functions */ +extern void Store_detected_address(const uint8_t); + +/*""FUNC COMMENT""*************************************************** +* Module outline: IICn event interrupt processing +*------------------------------------------------------------------- +* Declaration : void InterruptIIC_ICEEIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : +*------------------------------------------------------------------- +* Use function : +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_RIIC0_ICEEI0 +__fast_interrupt void Interrupt_IIC_ICEEI0(void) +#else +#pragma vector = VECT_RIIC0_ICEEI0 +__interrupt void Interrupt_IIC_ICEEI0(void) +#endif +{ + uint8_t valid_flags; + volatile uint8_t unwanted_byte; + + /* Read the status register */ + valid_flags = RIIC0.ICSR2.BYTE; + + /* Remove any that are not enabled */ + valid_flags &= RIIC0.ICIER.BYTE; + + /* Remove the transmit and receive flags */ + valid_flags &= 0x1Fu; + + /* Start or Repeated Start detected? */ + if ((valid_flags & BIT_2) != 0x0u) + { + /* Decide what to send */ + switch(rpdl_IIC_next_state[0]) + { + case IIC_MASTER_SEND_SLAVE_ADDRESS_7: + /* Send the slave address */ + RIIC0.ICDRT = rpdl_IIC_slave_address_lower[0]; + + /* Transmit mode? */ + if ((rpdl_IIC_slave_address_lower[0] & BIT_0) == 0) + { + rpdl_IIC_current_state[0] = IIC_MASTER_SEND_DATA; + } + else + { + rpdl_IIC_current_state[0] = IIC_MASTER_START_READ; + } + break; + case IIC_MASTER_SEND_SLAVE_ADDRESS_10a: + rpdl_IIC_current_state[0] = IIC_MASTER_SEND_SLAVE_ADDRESS_10b; + + /* Send the first part of the slave address */ + RIIC0.ICDRT = rpdl_IIC_slave_address_upper[0]; + break; + default: + break; + } + + /* Were we expecting data? */ + if (rpdl_IIC_current_state[0] == IIC_SLAVE_READ_DATA) + { + /* Go back to checking for a device address */ + rpdl_IIC_current_state[0] = IIC_SLAVE_MONITOR; + + /* Disable Start detection */ + RIIC0.ICIER.BIT.STIE = 0; + } + + /* Clear the flag */ + RIIC0.ICSR2.BIT.START = 0; + } + /* NACK detected? */ + else if ((valid_flags & BIT_4) != 0x0u) + { + /* Disable NACK interrupt request generation */ + RIIC0.ICIER.BIT.NAKIE = 0; + + /* Failed transmission of data? */ + if (rpdl_IIC_current_state[0] == IIC_MASTER_SEND_DATA) + { + /* Decrement the counter */ + rpdl_IIC_tx_counter[0]--; + + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + } + /* NACK received from the master? */ + else + { + /* Do a dummy read to release SCL */ + unwanted_byte = RIIC0.ICDRR; + } + } + else + { + /* Disable all interrupt request generation */ + RIIC0.ICIER.BYTE = 0x00u; + + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_RIIC1_ICEEI1 +__fast_interrupt void Interrupt_IIC_ICEEI1(void) +#else +#pragma vector = VECT_RIIC1_ICEEI1 +__interrupt void Interrupt_IIC_ICEEI1(void) +#endif +{ +#ifdef DEVICE_PACKAGE_LQFP_100 + /* This channel is not available on the 100-pin package */ + nop(); +#else + uint8_t valid_flags; + volatile uint8_t unwanted_byte; + + /* Read the status register */ + valid_flags = RIIC1.ICSR2.BYTE; + /* Remove any that are not enabled */ + valid_flags &= RIIC1.ICIER.BYTE; + /* Remove the transmit and receive flags */ + valid_flags &= 0x1Fu; + + /* Start or Repeated Start detected? */ + if ((valid_flags & BIT_2) != 0x0u) + { + /* Decide what to send */ + switch(rpdl_IIC_next_state[1]) + { + case IIC_MASTER_SEND_SLAVE_ADDRESS_7: + /* Send the slave address */ + RIIC1.ICDRT = rpdl_IIC_slave_address_lower[1]; + + /* Transmit mode? */ + if ((rpdl_IIC_slave_address_lower[1] & BIT_0) == 0) + { + rpdl_IIC_current_state[1] = IIC_MASTER_SEND_DATA; + } + else + { + rpdl_IIC_current_state[1] = IIC_MASTER_START_READ; + } + break; + case IIC_MASTER_SEND_SLAVE_ADDRESS_10a: + rpdl_IIC_current_state[1] = IIC_MASTER_SEND_SLAVE_ADDRESS_10b; + + /* Send the first part of the slave address */ + RIIC1.ICDRT = rpdl_IIC_slave_address_upper[1]; + break; + default: + break; + } + + /* Were we expecting data? */ + if (rpdl_IIC_current_state[1] == IIC_SLAVE_READ_DATA) + { + /* Go back to checking for a device address */ + rpdl_IIC_current_state[1] = IIC_SLAVE_MONITOR; + + /* Disable Start detection */ + RIIC1.ICIER.BIT.STIE = 0; + } + + /* Clear the flag */ + RIIC1.ICSR2.BIT.START = 0; + } + /* NACK detected? */ + else if ((valid_flags & BIT_4) != 0x0u) + { + /* Disable NACK interrupt request generation */ + RIIC1.ICIER.BIT.NAKIE = 0; + + /* Failed transmission of data? */ + if (rpdl_IIC_current_state[1] == IIC_MASTER_SEND_DATA) + { + /* Decrement the counter */ + rpdl_IIC_tx_counter[1]--; + + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + } + /* NACK received from the master? */ + else + { + /* Do a dummy read to release SCL */ + unwanted_byte = RIIC1.ICDRR; + } + } + else + { + /* Disable all interrupt request generation */ + RIIC1.ICIER.BYTE = 0x00u; + + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + } +#endif +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: IICn receive data interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_IIC_ICRXIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : ICDRR, ICIER +*------------------------------------------------------------------- +* Use function : +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ +#if FAST_INTC_VECTOR == VECT_RIIC0_ICRXI0 +__fast_interrupt void Interrupt_IIC_ICRXI0(void) +#else +#pragma vector = VECT_RIIC0_ICRXI0 +__interrupt void Interrupt_IIC_ICRXI0(void) +#endif +{ + volatile uint8_t unwanted_byte; + + switch (rpdl_IIC_current_state[0]) + { + case IIC_MASTER_START_READ: + /* Only one byte to be read? */ + if (rpdl_IIC_rx_threshold[0] == 1) + { + /* Prepare to signal a NACK to the slave (ACKBT = 1) */ + RIIC0.ICMR3.BIT.ACKBT = 1; + } + rpdl_IIC_current_state[0] = IIC_MASTER_READ_DATA; + + /* Do a dummy read */ + unwanted_byte = RIIC0.ICDRR; + break; + case IIC_MASTER_READ_DATA: + /* Is the last byte about to be read from the slave? */ + if (rpdl_IIC_rx_counter[0] == (rpdl_IIC_rx_threshold[0] - 2)) + { + /* Prepare to signal a NACK to the slave (ACKBT = 1) */ + RIIC0.ICMR3.BIT.ACKBT = 1; + } + /* All data read from the slave? */ + else if (rpdl_IIC_rx_counter[0] == (rpdl_IIC_rx_threshold[0] - 1)) + { + rpdl_IIC_current_state[0] = IIC_MASTER_WAIT_FOR_STOP; + + /* Enable Stop detection */ + RIIC0.ICIER.BIT.SPIE = 1; + + /* Issue a stop condition */ + RIIC0.ICCR2.BIT.SP = 1; + } + + /* Store the data byte */ + *rpdl_IIC_rx_data_pointer[0] = RIIC0.ICDRR; + + /* Increment the pointer */ + rpdl_IIC_rx_data_pointer[0]++; + + /* Increment the counter */ + rpdl_IIC_rx_counter[0]++; + break; + case IIC_SLAVE_MONITOR: + /* Note the detected address */ + Store_detected_address(0); + + /* Clear the Start flag */ + RIIC0.ICSR2.BIT.START = 0; + + /* Enable Start detection (in case a Repeated Start arrives) */ + RIIC0.ICIER.BIT.STIE = 1; + + /* Will interrupts be used for the transfers? */ + if (rpdl_IIC_rx_transfer_method[0] == IIC_TRANSFER_CPU) + { + rpdl_IIC_current_state[0] = IIC_SLAVE_READ_DATA; + } + else + { + /* Disable ACK / NACK decisions (RDRFS = 0) */ + RIIC0.ICMR3.BIT.RDRFS = 0; + /* Select DMAC or DTC transfers */ + if (rpdl_IIC_rx_transfer_method[0] == IIC_TRANSFER_DTC) + { + ICU.DTCER[DTCE_RIIC0_ICRXI0].BIT.DTCE = 1; + } + else /* DMAC */ + { + /* Set DTE = 1 */ + *DMCNT_ADDRESS(rpdl_IIC_rx_dmac_channel[0]) = 0x01u; + } + /* Prevent further RX-based interrupts */ + ICU.IPR[IPR_RIIC0_ICRXI0].BIT.IPR = 0; + rpdl_IIC_current_state[0] = IIC_EXIT_LOOP; + } + + /* Do a dummy read */ + unwanted_byte = RIIC0.ICDRR; + break; + case IIC_SLAVE_READ_DATA: + /* All data received? */ + if (rpdl_IIC_rx_counter[0] == rpdl_IIC_rx_threshold[0]) + { + /* Do a dummy read */ + unwanted_byte = RIIC0.ICDRR; + + /* Signal a NACK to the master */ + RIIC0.ICMR3.BIT.ACKBT = 1; + } + else + { + /* Store the data byte */ + *rpdl_IIC_rx_data_pointer[0] = RIIC0.ICDRR; + + /* Increment the pointer */ + rpdl_IIC_rx_data_pointer[0]++; + + /* Increment the counter */ + rpdl_IIC_rx_counter[0]++; + + /* Signal an ACK to the master */ + RIIC0.ICMR3.BIT.ACKBT = 0; + } + break; + case IIC_SLAVE_SEND_DATA: + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + break; + case IIC_EXIT_LOOP: + /* This will occur if the DMAC/DTC is being used with a callback */ + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + break; + default: + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + break; + } +} + +#if FAST_INTC_VECTOR == VECT_RIIC1_ICRXI1 +__fast_interrupt void Interrupt_IIC_ICRXI1(void) +#else +#pragma vector = VECT_RIIC1_ICRXI1 +__interrupt void Interrupt_IIC_ICRXI1(void) +#endif +{ +#ifdef DEVICE_PACKAGE_LQFP_100 + /* This channel is not available on the 100-pin package */ + nop(); +#else + volatile uint8_t unwanted_byte; + + switch (rpdl_IIC_current_state[1]) + { + case IIC_MASTER_START_READ: + /* Only one byte to be read? */ + if (rpdl_IIC_rx_threshold[1] == 1) + { + /* Prepare to signal a NACK to the slave (ACKBT = 1) */ + RIIC1.ICMR3.BIT.ACKBT = 1; + } + rpdl_IIC_current_state[1] = IIC_MASTER_READ_DATA; + + /* Do a dummy read */ + unwanted_byte = RIIC1.ICDRR; + break; + case IIC_MASTER_READ_DATA: + /* Is the last byte about to be read from the slave? */ + if (rpdl_IIC_rx_counter[1] == (rpdl_IIC_rx_threshold[1] - 2)) + { + /* Prepare to signal a NACK to the slave (ACKBT = 1) */ + RIIC1.ICMR3.BIT.ACKBT = 1; + } + /* All data read from the slave? */ + else if (rpdl_IIC_rx_counter[1] == (rpdl_IIC_rx_threshold[1] - 1)) + { + rpdl_IIC_current_state[1] = IIC_MASTER_WAIT_FOR_STOP; + + /* Enable Stop detection */ + RIIC1.ICIER.BIT.SPIE = 1; + + /* Issue a stop condition */ + RIIC1.ICCR2.BIT.SP = 1; + } + + /* Store the data byte */ + *rpdl_IIC_rx_data_pointer[1] = RIIC1.ICDRR; + + /* Increment the pointer */ + rpdl_IIC_rx_data_pointer[1]++; + + /* Increment the counter */ + rpdl_IIC_rx_counter[1]++; + break; + case IIC_SLAVE_MONITOR: + /* Note the detected address */ + Store_detected_address(1); + + /* Clear the Start flag */ + RIIC1.ICSR2.BIT.START = 0; + + /* Enable Start detection (in case a Repeated Start arrives) */ + RIIC1.ICIER.BIT.STIE = 1; + + /* Will interrupts be used for the transfers? */ + if (rpdl_IIC_rx_transfer_method[1] == IIC_TRANSFER_CPU) + { + rpdl_IIC_current_state[1] = IIC_SLAVE_READ_DATA; + } + else + { + /* Disable ACK / NACK decisions (RDRFS = 0) */ + RIIC1.ICMR3.BIT.RDRFS = 0; + /* Select DMAC or DTC transfers */ + if (rpdl_IIC_rx_transfer_method[1] == IIC_TRANSFER_DTC) + { + ICU.DTCER[DTCE_RIIC1_ICRXI1].BIT.DTCE = 1; + } + else /* DMAC */ + { + /* Set DTE = 1 */ + *DMCNT_ADDRESS(rpdl_IIC_rx_dmac_channel[1]) = 0x01u; + } + /* Prevent further RX-based interrupts */ + ICU.IPR[IPR_RIIC1_ICRXI1].BIT.IPR = 0; + rpdl_IIC_current_state[1] = IIC_EXIT_LOOP; + } + + /* Do a dummy read */ + unwanted_byte = RIIC1.ICDRR; + break; + + case IIC_SLAVE_READ_DATA: + /* All data received? */ + if (rpdl_IIC_rx_counter[1] == rpdl_IIC_rx_threshold[1]) + { + /* Do a dummy read */ + unwanted_byte = RIIC1.ICDRR; + + /* Signal a NACK to the master */ + RIIC1.ICMR3.BIT.ACKBT = 1; + } + else + { + /* Store the data byte */ + *rpdl_IIC_rx_data_pointer[1] = RIIC1.ICDRR; + + /* Increment the pointer */ + rpdl_IIC_rx_data_pointer[1]++; + + /* Increment the counter */ + rpdl_IIC_rx_counter[1]++; + + /* Signal an ACK to the master */ + RIIC1.ICMR3.BIT.ACKBT = 0; + } + break; + case IIC_SLAVE_SEND_DATA: + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + break; + case IIC_EXIT_LOOP: + /* This will occur if the DMAC/DTC is being used with a callback */ + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + break; + default: + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + break; + } +#endif +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: IICn transmit data interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_IIC_ICTXIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : ICDRT, ICIER +*------------------------------------------------------------------- +* Use function : +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ +#if FAST_INTC_VECTOR == VECT_RIIC0_ICTXI0 +__fast_interrupt void Interrupt_IIC_ICTXI0(void) +#else +#pragma vector = VECT_RIIC0_ICTXI0 +__interrupt void Interrupt_IIC_ICTXI0(void) +#endif +{ + switch (rpdl_IIC_current_state[0]) + { + case IIC_MASTER_SEND_SLAVE_ADDRESS_10b: + /* Send the second part of the slave address */ + RIIC0.ICDRT = rpdl_IIC_slave_address_lower[0]; + + /* Transmit mode? */ + if ((rpdl_IIC_slave_address_upper[0] & BIT_0) == 0) + { + rpdl_IIC_current_state[0] = IIC_MASTER_SEND_DATA; + } + else + { + rpdl_IIC_current_state[0] = IIC_MASTER_START_READ; + + /* Enable receive interrupt request generation */ + RIIC0.ICIER.BIT.RIE = 1; + } + break; + case IIC_MASTER_SEND_DATA: + /* All data sent? */ + if (rpdl_IIC_tx_counter[0] == rpdl_IIC_tx_threshold[0]) + { + rpdl_IIC_current_state[0] = IIC_MASTER_WAIT_FOR_TX_COMPLETE; + + /* Disable ICTXI interrupt request generation */ + RIIC0.ICIER.BIT.TIE = 0; + + /* Ensure the ICTEI IR flag is clear */ + ICU.IR[IR_RIIC0_ICTEI0].BIT.IR = 0; + + /* Enable Transmit End interrupt generation */ + RIIC0.ICIER.BIT.TEIE = 1; + } + else + { + /* Load the data to be sent */ + RIIC0.ICDRT = *rpdl_IIC_tx_data_pointer[0]; + + /* Increment the pointer */ + rpdl_IIC_tx_data_pointer[0]++; + + /* Increment the counter */ + rpdl_IIC_tx_counter[0]++; + } + break; + case IIC_SLAVE_MONITOR: + /* Note the detected address */ + Store_detected_address(0); + + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + break; + case IIC_SLAVE_SEND_DATA: + /* All data sent? */ + if (rpdl_IIC_tx_counter[0] == rpdl_IIC_tx_threshold[0]) + { + /* Clear the counter */ + rpdl_IIC_tx_counter[0] = 0; + + /* Loop back to the start */ + rpdl_IIC_tx_data_pointer[0] = rpdl_IIC_tx_data_start[0]; + } + + /* Load the data to be sent */ + RIIC0.ICDRT = *rpdl_IIC_tx_data_pointer[0]; + + /* Increment the pointer */ + rpdl_IIC_tx_data_pointer[0]++; + + /* Increment the counter */ + rpdl_IIC_tx_counter[0]++; + break; + case IIC_SLAVE_READ_DATA: + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + break; + case IIC_EXIT_LOOP: + /* This will occur if the DMAC/DTC is being used with a callback */ + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + break; + default: + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + break; + } +} + +#if FAST_INTC_VECTOR == VECT_RIIC1_ICTXI1 +__fast_interrupt void Interrupt_IIC_ICTXI1(void) +#else +#pragma vector = VECT_RIIC1_ICTXI1 +__interrupt void Interrupt_IIC_ICTXI1(void) +#endif +{ +#ifdef DEVICE_PACKAGE_LQFP_100 + /* This channel is not available on the 100-pin package */ + nop(); +#else + switch (rpdl_IIC_current_state[1]) + { + case IIC_MASTER_SEND_SLAVE_ADDRESS_10b: + /* Send the second part of the slave address */ + RIIC1.ICDRT = rpdl_IIC_slave_address_lower[1]; + + /* Transmit mode? */ + if ((rpdl_IIC_slave_address_upper[1] & BIT_0) == 0) + { + rpdl_IIC_current_state[1] = IIC_MASTER_SEND_DATA; + } + else + { + rpdl_IIC_current_state[1] = IIC_MASTER_START_READ; + + /* Enable receive interrupt request generation */ + RIIC1.ICIER.BIT.RIE = 1; + } + break; + case IIC_MASTER_SEND_DATA: + /* All data sent? */ + if (rpdl_IIC_tx_counter[1] == rpdl_IIC_tx_threshold[1]) + { + rpdl_IIC_current_state[1] = IIC_MASTER_WAIT_FOR_TX_COMPLETE; + + /* Disable ICTXI interrupt request generation */ + RIIC1.ICIER.BIT.TIE = 0; + + /* Ensure the ICTEI IR flag is clear */ + ICU.IR[IR_RIIC1_ICTEI1].BIT.IR = 0; + + /* Enable Transmit End interrupt generation */ + RIIC1.ICIER.BIT.TEIE = 1; + } + else + { + /* Load the data to be sent */ + RIIC1.ICDRT = *rpdl_IIC_tx_data_pointer[1]; + + /* Increment the pointer */ + rpdl_IIC_tx_data_pointer[1]++; + + /* Increment the counter */ + rpdl_IIC_tx_counter[1]++; + } + break; + case IIC_SLAVE_MONITOR: + /* Note the detected address */ + Store_detected_address(1); + + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + break; + case IIC_SLAVE_SEND_DATA: + /* All data sent? */ + if (rpdl_IIC_tx_counter[1] == rpdl_IIC_tx_threshold[1]) + { + /* Clear the counter */ + rpdl_IIC_tx_counter[1] = 0; + + /* Loop back to the start */ + rpdl_IIC_tx_data_pointer[1] = rpdl_IIC_tx_data_start[1]; + } + + /* Load the data to be sent */ + RIIC1.ICDRT = *rpdl_IIC_tx_data_pointer[1]; + + /* Increment the pointer */ + rpdl_IIC_tx_data_pointer[1]++; + + /* Increment the counter */ + rpdl_IIC_tx_counter[1]++; + break; + case IIC_SLAVE_READ_DATA: + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + break; + case IIC_EXIT_LOOP: + /* This will occur if the DMAC/DTC is being used with a callback */ + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + break; + default: + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + break; + } +#endif +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: IICn transmit end interrupt processing +*------------------------------------------------------------------- +* Declaration : void InterruptIIC_ICTEIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : ICIER, ICSR2 +*------------------------------------------------------------------- +* Use function : +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_RIIC0_ICTEI0 +__fast_interrupt void Interrupt_IIC_ICTEI0(void) +#else +#pragma vector = VECT_RIIC0_ICTEI0 +__interrupt void Interrupt_IIC_ICTEI0(void) +#endif +{ + /* Disable Transmit End interrupt request generation */ + RIIC0.ICIER.BIT.TEIE = 0; + /* Clear the flag */ + RIIC0.ICSR2.BIT.TEND = 0; + + /* Stop condition required? */ + if (rpdl_IIC_stop[0] == true) + { + rpdl_IIC_current_state[0] = IIC_MASTER_WAIT_FOR_STOP; + + /* Enable Stop detection */ + RIIC0.ICIER.BIT.SPIE = 1; + + /* Issue a stop condition */ + RIIC0.ICCR2.BIT.SP = 1; + } + else + { + /* Disable all interrupt request generation */ + RIIC0.ICIER.BYTE = 0x00u; + + /* Call the callback function */ + if (rpdl_IIC_callback_func[0] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[0](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_RIIC1_ICTEI1 +__fast_interrupt void Interrupt_IIC_ICTEI1(void) +#else +#pragma vector = VECT_RIIC1_ICTEI1 +__interrupt void Interrupt_IIC_ICTEI1(void) +#endif +{ +#ifdef DEVICE_PACKAGE_LQFP_100 + /* This channel is not available on the 100-pin package */ + nop(); +#else + /* Disable Transmit End interrupt request generation */ + RIIC1.ICIER.BIT.TEIE = 0; + /* Clear the flag */ + RIIC1.ICSR2.BIT.TEND = 0; + + /* Stop condition required? */ + if (rpdl_IIC_stop[1] == true) + { + rpdl_IIC_current_state[1] = IIC_MASTER_WAIT_FOR_STOP; + + /* Enable Stop detection */ + RIIC1.ICIER.BIT.SPIE = 1; + + /* Issue a stop condition */ + RIIC1.ICCR2.BIT.SP = 1; + } + else + { + /* Disable all interrupt request generation */ + RIIC1.ICIER.BYTE = 0x00u; + + /* Call the callback function */ + if (rpdl_IIC_callback_func[1] != PDL_NO_FUNC) + { + rpdl_IIC_callback_func[1](); + } + } +#endif +} +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_mtu2.c b/bsp/rx/RPDL/interrupt_mtu2.c new file mode 100644 index 0000000000000000000000000000000000000000..27e80ab07b45ff7a803bfd31d9483c6b894df5bb --- /dev/null +++ b/bsp/rx/RPDL/interrupt_mtu2.c @@ -0,0 +1,1064 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_MTU2.c +* Version : 1.02 +* Contents : Interrupt handlers for the MTU channels +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_mtu2.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGIA0(void) +*------------------------------------------------------------------- +* Function : TGIAn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_func1_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU0_TGIA0 +__fast_interrupt void Interrupt_MTU0_TGIA0(void) +#else +#pragma vector = VECT_MTU0_TGIA0 +__interrupt void Interrupt_MTU0_TGIA0(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[0] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU1_TGIA1 +__fast_interrupt void Interrupt_MTU1_TGIA1(void) +#else +#pragma vector = VECT_MTU1_TGIA1 +__interrupt void Interrupt_MTU1_TGIA1(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[1] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU2_TGIA2 +__fast_interrupt void Interrupt_MTU2_TGIA2(void) +#else +#pragma vector = VECT_MTU2_TGIA2 +__interrupt void Interrupt_MTU2_TGIA2(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[2] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU3_TGIA3 +__fast_interrupt void Interrupt_MTU3_TGIA3(void) +#else +#pragma vector = VECT_MTU3_TGIA3 +__interrupt void Interrupt_MTU3_TGIA3(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[3] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[3](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU4_TGIA4 +__fast_interrupt void Interrupt_MTU4_TGIA4(void) +#else +#pragma vector = VECT_MTU4_TGIA4 +__interrupt void Interrupt_MTU4_TGIA4(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[4] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[4](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU6_TGIA6 +__fast_interrupt void Interrupt_MTU6_TGIA6(void) +#else +#pragma vector = VECT_MTU6_TGIA6 +__interrupt void Interrupt_MTU6_TGIA6(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[6] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[6](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU7_TGIA7 +__fast_interrupt void Interrupt_MTU7_TGIA7(void) +#else +#pragma vector = VECT_MTU7_TGIA7 +__interrupt void Interrupt_MTU7_TGIA7(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[7] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[7](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU8_TGIA8 +__fast_interrupt void Interrupt_MTU8_TGIA8(void) +#else +#pragma vector = VECT_MTU8_TGIA8 +__interrupt void Interrupt_MTU8_TGIA8(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[8] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[8](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU9_TGIA9 +__fast_interrupt void Interrupt_MTU9_TGIA9(void) +#else +#pragma vector = VECT_MTU9_TGIA9 +__interrupt void Interrupt_MTU9_TGIA9(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[9] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[9](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU10_TGIA10 +__fast_interrupt void Interrupt_MTU10_TGIA10(void) +#else +#pragma vector = VECT_MTU10_TGIA10 +__interrupt void Interrupt_MTU10_TGIA10(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[10] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[10](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGIBn(void) +*------------------------------------------------------------------- +* Function : TGIBn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_func2_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU0_TGIB0 +__fast_interrupt void Interrupt_MTU0_TGIB0(void) +#else +#pragma vector = VECT_MTU0_TGIB0 +__interrupt void Interrupt_MTU0_TGIB0(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[0] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU1_TGIB1 +__fast_interrupt void Interrupt_MTU1_TGIB1(void) +#else +#pragma vector = VECT_MTU1_TGIB1 +__interrupt void Interrupt_MTU1_TGIB1(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[1] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU2_TGIB2 +__fast_interrupt void Interrupt_MTU2_TGIB2(void) +#else +#pragma vector = VECT_MTU2_TGIB2 +__interrupt void Interrupt_MTU2_TGIB2(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[2] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU3_TGIB3 +__fast_interrupt void Interrupt_MTU3_TGIB3(void) +#else +#pragma vector = VECT_MTU3_TGIB3 +__interrupt void Interrupt_MTU3_TGIB3(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[3] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[3](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU4_TGIB4 +__fast_interrupt void Interrupt_MTU4_TGIB4(void) +#else +#pragma vector = VECT_MTU4_TGIB4 +__interrupt void Interrupt_MTU4_TGIB4(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[4] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[4](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU6_TGIB6 +__fast_interrupt void Interrupt_MTU6_TGIB6(void) +#else +#pragma vector = VECT_MTU6_TGIB6 +__interrupt void Interrupt_MTU6_TGIB6(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[6] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[6](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU7_TGIB7 +__fast_interrupt void Interrupt_MTU7_TGIB7(void) +#else +#pragma vector = VECT_MTU7_TGIB7 +__interrupt void Interrupt_MTU7_TGIB7(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[7] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[7](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU8_TGIB8 +__fast_interrupt void Interrupt_MTU8_TGIB8(void) +#else +#pragma vector = VECT_MTU8_TGIB8 +__interrupt void Interrupt_MTU8_TGIB8(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[8] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[8](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU9_TGIB9 +__fast_interrupt void Interrupt_MTU9_TGIB9(void) +#else +#pragma vector = VECT_MTU9_TGIB9 +__interrupt void Interrupt_MTU9_TGIB9(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[9] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[9](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU10_TGIB10 +__fast_interrupt void Interrupt_MTU10_TGIB10(void) +#else +#pragma vector = VECT_MTU10_TGIB10 +__interrupt void Interrupt_MTU10_TGIB10(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[10] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[10](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGICn(void) +*------------------------------------------------------------------- +* Function : TGICn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_func3_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU0_TGIC0 +__fast_interrupt void Interrupt_MTU0_TGIC0(void) +#else +#pragma vector = VECT_MTU0_TGIC0 +__interrupt void Interrupt_MTU0_TGIC0(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func3_callback_func[0] != PDL_NO_FUNC) + { + rpdl_MTU2_func3_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU3_TGIC3 +__fast_interrupt void Interrupt_MTU3_TGIC3(void) +#else +#pragma vector = VECT_MTU3_TGIC3 +__interrupt void Interrupt_MTU3_TGIC3(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func3_callback_func[3] != PDL_NO_FUNC) + { + rpdl_MTU2_func3_callback_func[3](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU4_TGIC4 +__fast_interrupt void Interrupt_MTU4_TGIC4(void) +#else +#pragma vector = VECT_MTU4_TGIC4 +__interrupt void Interrupt_MTU4_TGIC4(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func3_callback_func[4] != PDL_NO_FUNC) + { + rpdl_MTU2_func3_callback_func[4](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU6_TGIC6 +__fast_interrupt void Interrupt_MTU6_TGIC6(void) +#else +#pragma vector = VECT_MTU6_TGIC6 +__interrupt void Interrupt_MTU6_TGIC6(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func3_callback_func[6] != PDL_NO_FUNC) + { + rpdl_MTU2_func3_callback_func[6](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU9_TGIC9 +__fast_interrupt void Interrupt_MTU9_TGIC9(void) +#else +#pragma vector = VECT_MTU9_TGIC9 +__interrupt void Interrupt_MTU9_TGIC9(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func3_callback_func[9] != PDL_NO_FUNC) + { + rpdl_MTU2_func3_callback_func[9](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU10_TGIC10 +__fast_interrupt void Interrupt_MTU10_TGIC10(void) +#else +#pragma vector = VECT_MTU10_TGIC10 +__interrupt void Interrupt_MTU10_TGIC10(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func3_callback_func[10] != PDL_NO_FUNC) + { + rpdl_MTU2_func3_callback_func[10](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGIDn(void) +*------------------------------------------------------------------- +* Function : TGIDn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_func4_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU0_TGID0 +__fast_interrupt void Interrupt_MTU0_TGID0(void) +#else +#pragma vector = VECT_MTU0_TGID0 +__interrupt void Interrupt_MTU0_TGID0(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func4_callback_func[0] != PDL_NO_FUNC) + { + rpdl_MTU2_func4_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU3_TGID3 +__fast_interrupt void Interrupt_MTU3_TGID3(void) +#else +#pragma vector = VECT_MTU3_TGID3 +__interrupt void Interrupt_MTU3_TGID3(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func4_callback_func[3] != PDL_NO_FUNC) + { + rpdl_MTU2_func4_callback_func[3](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU4_TGID4 +__fast_interrupt void Interrupt_MTU4_TGID4(void) +#else +#pragma vector = VECT_MTU4_TGID4 +__interrupt void Interrupt_MTU4_TGID4(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func4_callback_func[4] != PDL_NO_FUNC) + { + rpdl_MTU2_func4_callback_func[4](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU6_TGID6 +__fast_interrupt void Interrupt_MTU6_TGID6(void) +#else +#pragma vector = VECT_MTU6_TGID6 +__interrupt void Interrupt_MTU6_TGID6(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func4_callback_func[6] != PDL_NO_FUNC) + { + rpdl_MTU2_func4_callback_func[6](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU9_TGID9 +__fast_interrupt void Interrupt_MTU9_TGID9(void) +#else +#pragma vector = VECT_MTU9_TGID9 +__interrupt void Interrupt_MTU9_TGID9(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func4_callback_func[9] != PDL_NO_FUNC) + { + rpdl_MTU2_func4_callback_func[9](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU10_TGID10 +__fast_interrupt void Interrupt_MTU10_TGID10(void) +#else +#pragma vector = VECT_MTU10_TGID10 +__interrupt void Interrupt_MTU10_TGID10(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func4_callback_func[10] != PDL_NO_FUNC) + { + rpdl_MTU2_func4_callback_func[10](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGIEn(void) +*------------------------------------------------------------------- +* Function : TGIEn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_TGRE_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU0_TGIE0 +__fast_interrupt void Interrupt_MTU0_TGIE0(void) +#else +#pragma vector = VECT_MTU0_TGIE0 +__interrupt void Interrupt_MTU0_TGIE0(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_TGRE_callback_func[0] != PDL_NO_FUNC) + { + rpdl_MTU2_TGRE_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU6_TGIE6 +__fast_interrupt void Interrupt_MTU6_TGIE6(void) +#else +#pragma vector = VECT_MTU6_TGIE6 +__interrupt void Interrupt_MTU6_TGIE6(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_TGRE_callback_func[6] != PDL_NO_FUNC) + { + rpdl_MTU2_TGRE_callback_func[6](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGIFn(void) +*------------------------------------------------------------------- +* Function : TGIFn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_TGRF_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU0_TGIF0 +__fast_interrupt void Interrupt_MTU0_TGIF0(void) +#else +#pragma vector = VECT_MTU0_TGIF0 +__interrupt void Interrupt_MTU0_TGIF0(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_TGRF_callback_func[0] != PDL_NO_FUNC) + { + rpdl_MTU2_TGRF_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU6_TGIF6 +__fast_interrupt void Interrupt_MTU6_TGIF6(void) +#else +#pragma vector = VECT_MTU6_TGIF6 +__interrupt void Interrupt_MTU6_TGIF6(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_TGRF_callback_func[6] != PDL_NO_FUNC) + { + rpdl_MTU2_TGRF_callback_func[6](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TCIVn(void) +*------------------------------------------------------------------- +* Function : TCIVn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_Overflow_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU0_TCIV0 +__fast_interrupt void Interrupt_MTU0_TCIV0(void) +#else +#pragma vector = VECT_MTU0_TCIV0 +__interrupt void Interrupt_MTU0_TCIV0(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[0] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU1_TCIV1 +__fast_interrupt void Interrupt_MTU1_TCIV1(void) +#else +#pragma vector = VECT_MTU1_TCIV1 +__interrupt void Interrupt_MTU1_TCIV1(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[1] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU2_TCIV2 +__fast_interrupt void Interrupt_MTU2_TCIV2(void) +#else +#pragma vector = VECT_MTU2_TCIV2 +__interrupt void Interrupt_MTU2_TCIV2(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[2] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU3_TCIV3 +__fast_interrupt void Interrupt_MTU3_TCIV3(void) +#else +#pragma vector = VECT_MTU3_TCIV3 +__interrupt void Interrupt_MTU3_TCIV3(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[3] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[3](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU4_TCIV4 +__fast_interrupt void Interrupt_MTU4_TCIV4(void) +#else +#pragma vector = VECT_MTU4_TCIV4 +__interrupt void Interrupt_MTU4_TCIV4(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[4] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[4](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU6_TCIV6 +__fast_interrupt void Interrupt_MTU6_TCIV6(void) +#else +#pragma vector = VECT_MTU6_TCIV6 +__interrupt void Interrupt_MTU6_TCIV6(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[6] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[6](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU7_TCIV7 +__fast_interrupt void Interrupt_MTU7_TCIV7(void) +#else +#pragma vector = VECT_MTU7_TCIV7 +__interrupt void Interrupt_MTU7_TCIV7(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[7] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[7](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU8_TCIV8 +__fast_interrupt void Interrupt_MTU8_TCIV8(void) +#else +#pragma vector = VECT_MTU8_TCIV8 +__interrupt void Interrupt_MTU8_TCIV8(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[8] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[8](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU9_TCIV9 +__fast_interrupt void Interrupt_MTU9_TCIV9(void) +#else +#pragma vector = VECT_MTU9_TCIV9 +__interrupt void Interrupt_MTU9_TCIV9(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[9] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[9](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU10_TCIV10 +__fast_interrupt void Interrupt_MTU10_TCIV10(void) +#else +#pragma vector = VECT_MTU10_TCIV10 +__interrupt void Interrupt_MTU10_TCIV10(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Overflow_callback_func[10] != PDL_NO_FUNC) + { + rpdl_MTU2_Overflow_callback_func[10](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TCIUn(void) +*------------------------------------------------------------------- +* Function : TCIUn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_Underflow_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU1_TCIU1 +__fast_interrupt void Interrupt_MTU1_TCIU1(void) +#else +#pragma vector = VECT_MTU1_TCIU1 +__interrupt void Interrupt_MTU1_TCIU1(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Underflow_callback_func[1] != PDL_NO_FUNC) + { + rpdl_MTU2_Underflow_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU2_TCIU2 +__fast_interrupt void Interrupt_MTU2_TCIU2(void) +#else +#pragma vector = VECT_MTU2_TCIU2 +__interrupt void Interrupt_MTU2_TCIU2(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Underflow_callback_func[2] != PDL_NO_FUNC) + { + rpdl_MTU2_Underflow_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU7_TCIU7 +__fast_interrupt void Interrupt_MTU7_TCIU7(void) +#else +#pragma vector = VECT_MTU7_TCIU7 +__interrupt void Interrupt_MTU7_TCIU7(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Underflow_callback_func[7] != PDL_NO_FUNC) + { + rpdl_MTU2_Underflow_callback_func[7](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU8_TCIU8 +__fast_interrupt void Interrupt_MTU8_TCIU8(void) +#else +#pragma vector = VECT_MTU8_TCIU8 +__interrupt void Interrupt_MTU8_TCIU8(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_Underflow_callback_func[8] != PDL_NO_FUNC) + { + rpdl_MTU2_Underflow_callback_func[8](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGIUn(void) +*------------------------------------------------------------------- +* Function : TGIUn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_func1_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU5_TGIU5 +__fast_interrupt void Interrupt_MTU5_TGIU5(void) +#else +#pragma vector = VECT_MTU5_TGIU5 +__interrupt void Interrupt_MTU5_TGIU5(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[5] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[5](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU11_TGIU11 +__fast_interrupt void Interrupt_MTU11_TGIU11(void) +#else +#pragma vector = VECT_MTU11_TGIU11 +__interrupt void Interrupt_MTU11_TGIU11(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func1_callback_func[11] != PDL_NO_FUNC) + { + rpdl_MTU2_func1_callback_func[11](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGIVn(void) +*------------------------------------------------------------------- +* Function : TGIVn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_func2_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU5_TGIV5 +__fast_interrupt void Interrupt_MTU5_TGIV5(void) +#else +#pragma vector = VECT_MTU5_TGIV5 +__interrupt void Interrupt_MTU5_TGIV5(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[5] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[5](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU11_TGIV11 +__fast_interrupt void Interrupt_MTU11_TGIV11(void) +#else +#pragma vector = VECT_MTU11_TGIV11 +__interrupt void Interrupt_MTU11_TGIV11(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func2_callback_func[11] != PDL_NO_FUNC) + { + rpdl_MTU2_func2_callback_func[11](); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_MTUn_TGIWn(void) +*------------------------------------------------------------------- +* Function : TGIWn interrupt processing +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_MTU2_func3_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_MTU5_TGIW5 +__fast_interrupt void Interrupt_MTU5_TGIW5(void) +#else +#pragma vector = VECT_MTU5_TGIW5 +__interrupt void Interrupt_MTU5_TGIW5(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func3_callback_func[5] != PDL_NO_FUNC) + { + rpdl_MTU2_func3_callback_func[5](); + } +} + +#if FAST_INTC_VECTOR == VECT_MTU11_TGIW11 +__fast_interrupt void Interrupt_MTU11_TGIW11(void) +#else +#pragma vector = VECT_MTU11_TGIW11 +__interrupt void Interrupt_MTU11_TGIW11(void) +#endif +{ + /* Call the user function */ + if (rpdl_MTU2_func3_callback_func[11] != PDL_NO_FUNC) + { + rpdl_MTU2_func3_callback_func[11](); + } +} + +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_not_rpdl.c b/bsp/rx/RPDL/interrupt_not_rpdl.c new file mode 100644 index 0000000000000000000000000000000000000000..470aba7c1cf5334a38931d1b0d5f8609be0c8c91 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_not_rpdl.c @@ -0,0 +1,203 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_not_RPDL.c +* Version : 1.02 +* Contents : Interrupt handlers for peripherals outside the scope +* : of RPDL +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_common_defs_RX62Nxx.h" +#include "r_pdl_user_definitions.h" + +#if FAST_INTC_VECTOR == VECT_FCU_FIFERR +__fast_interrupt void Interrupt_FIFERR(void) +#else +#pragma vector = VECT_FCU_FIFERR +__interrupt void Interrupt_FIFERR(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_FCU_FRDYI +__fast_interrupt void Interrupt_FRDYI(void) +#else +#pragma vector = VECT_FCU_FRDYI +__interrupt void Interrupt_FRDYI(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_ETHER_EINT +__fast_interrupt void Interrupt_EINT(void) +#else +#pragma vector = VECT_ETHER_EINT +__interrupt void Interrupt_EINT(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_USB0_D0FIFO0 +__fast_interrupt void Interrupt_D0FIFO0(void) +#else +#pragma vector = VECT_USB0_D0FIFO0 +__interrupt void Interrupt_D0FIFO0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_USB0_D1FIFO0 +__fast_interrupt void Interrupt_D1FIFO0(void) +#else +#pragma vector = VECT_USB0_D1FIFO0 +__interrupt void Interrupt_D1FIFO0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_USB0_USBI0 +__fast_interrupt void Interrupt_USBI0(void) +#else +#pragma vector = VECT_USB0_USBI0 +__interrupt void Interrupt_USBI0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_USB_USBR0 +__fast_interrupt void Interrupt_USBR0(void) +#else +#pragma vector = VECT_USB_USBR0 +__interrupt void Interrupt_USBR0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_USB1_D0FIFO1 +__fast_interrupt void Interrupt_D0FIFO1(void) +#else +#pragma vector = VECT_USB1_D0FIFO1 +__interrupt void Interrupt_D0FIFO1(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_USB1_D1FIFO1 +__fast_interrupt void Interrupt_D1FIFO1(void) +#else +#pragma vector = VECT_USB1_D1FIFO1 +__interrupt void Interrupt_D1FIFO1(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_USB1_USBI1 +__fast_interrupt void Interrupt_USBI1(void) +#else +#pragma vector = VECT_USB1_USBI1 +__interrupt void Interrupt_USBI1(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_USB_USBR1 +__fast_interrupt void Interrupt_USBR1(void) +#else +#pragma vector = VECT_USB_USBR1 +__interrupt void Interrupt_USBR1(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_CAN0_ERS0 +__fast_interrupt void Interrupt_ERS0(void) +#else +#pragma vector = VECT_CAN0_ERS0 +__interrupt void Interrupt_ERS0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_CAN0_RXF0 +__fast_interrupt void Interrupt_RXF0(void) +#else +#pragma vector = VECT_CAN0_RXF0 +__interrupt void Interrupt_RXF0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_CAN0_TXF0 +__fast_interrupt void Interrupt_TXF0(void) +#else +#pragma vector = VECT_CAN0_TXF0 +__interrupt void Interrupt_TXF0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_CAN0_RXM0 +__fast_interrupt void Interrupt_RXM0(void) +#else +#pragma vector = VECT_CAN0_RXM0 +__interrupt void Interrupt_RXM0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +#if FAST_INTC_VECTOR == VECT_CAN0_TXM0 +__fast_interrupt void Interrupt_TXM0(void) +#else +#pragma vector = VECT_CAN0_TXM0 +__interrupt void Interrupt_TXM0(void) +#endif +{ + /* The user can put their own code here */ + nop(); +} + +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_poe.c b/bsp/rx/RPDL/interrupt_poe.c new file mode 100644 index 0000000000000000000000000000000000000000..3dd275704c60abb03dbe8093f023ac00de5e1333 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_poe.c @@ -0,0 +1,126 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62N +* File Name : Interrupt_POE.c +* Version : 1.02 +* Contents : Interrupt handlers for the Port Output Enable module +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_poe.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline : POE interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_OEIn(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for POE interrupt n +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : POE_callback_func[n] +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_POE_OEI1 +__fast_interrupt void Interrupt_OEI1(void) +#else +#pragma vector = VECT_POE_OEI1 +__interrupt void Interrupt_OEI1(void) +#endif +{ +#ifdef DEVICE_PACKAGE_TFLGA_85 + /* This peripheral is not available on the 85-pin package */ + nop(); +#else + /* Call the user function */ + if (rpdl_POE_callback_func[0] != PDL_NO_FUNC) + { + rpdl_POE_callback_func[0](); + } +#endif +} + +#if FAST_INTC_VECTOR == VECT_POE_OEI2 +__fast_interrupt void Interrupt_OEI2(void) +#else +#pragma vector = VECT_POE_OEI2 +__interrupt void Interrupt_OEI2(void) +#endif +{ +#ifdef DEVICE_PACKAGE_TFLGA_85 + /* This peripheral is not available on the 85-pin package */ + nop(); +#else + /* Call the user function */ + if (rpdl_POE_callback_func[2] != PDL_NO_FUNC) + { + rpdl_POE_callback_func[2](); + } +#endif +} + +#if FAST_INTC_VECTOR == VECT_POE_OEI3 +__fast_interrupt void Interrupt_OEI3(void) +#else +#pragma vector = VECT_POE_OEI3 +__interrupt void Interrupt_OEI3(void) +#endif +{ +#ifdef DEVICE_PACKAGE_TFLGA_85 + /* This peripheral is not available on the 85-pin package */ + nop(); +#else + /* Call the user function */ + if (rpdl_POE_callback_func[1] != PDL_NO_FUNC) + { + rpdl_POE_callback_func[1](); + } +#endif +} + +#if FAST_INTC_VECTOR == VECT_POE_OEI4 +__fast_interrupt void Interrupt_OEI4(void) +#else +#pragma vector = VECT_POE_OEI4 +__interrupt void Interrupt_OEI4(void) +#endif +{ +#ifdef DEVICE_PACKAGE_TFLGA_85 + /* This peripheral is not available on the 85-pin package */ + nop(); +#else + /* Call the user function */ + if (rpdl_POE_callback_func[3] != PDL_NO_FUNC) + { + rpdl_POE_callback_func[3](); + } +#endif +} + +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_sci.c b/bsp/rx/RPDL/interrupt_sci.c new file mode 100644 index 0000000000000000000000000000000000000000..b06fa2411e6fee5773786533d0beef6513d3d9f9 --- /dev/null +++ b/bsp/rx/RPDL/interrupt_sci.c @@ -0,0 +1,1219 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_SCI.c +* Version : 1.02 +* Contents : Interrupt handlers for all SCI channels +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_sci.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline: SCIn receive data error interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_SCIn_ERIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : SSR for that SCI channel +*------------------------------------------------------------------- +* Use function : rpdl_SCI_RX_Error_callback_func +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_SCI0_ERI0 +__fast_interrupt void Interrupt_SCI0_ERI0(void) +#else +#pragma vector = VECT_SCI0_ERI0 +__interrupt void Interrupt_SCI0_ERI0(void) +#endif +{ + /* Will the user handle the errors? */ + if (rpdl_SCI_RX_Error_callback_func[0] != PDL_NO_FUNC) + { + /* Call the error handler */ + rpdl_SCI_RX_Error_callback_func[0](); + } + else + { + /* Clear the error flags */ + SCI0.SSR.BYTE = (uint8_t)(BIT_7 | BIT_6); + } +} + +#if FAST_INTC_VECTOR == VECT_SCI1_ERI1 +__fast_interrupt void Interrupt_SCI1_ERI1(void) +#else +#pragma vector = VECT_SCI1_ERI1 +__interrupt void Interrupt_SCI1_ERI1(void) +#endif +{ + /* Will the user handle the errors? */ + if (rpdl_SCI_RX_Error_callback_func[1] != PDL_NO_FUNC) + { + /* Call the error handler */ + rpdl_SCI_RX_Error_callback_func[1](); + } + else + { + /* Clear the error flags */ + SCI1.SSR.BYTE = (uint8_t)(BIT_7 | BIT_6); + } +} +#if 0 +#if FAST_INTC_VECTOR == VECT_SCI2_ERI2 +__fast_interrupt void Interrupt_SCI2_ERI2(void) +#else +#pragma vector = VECT_SCI2_ERI2 +__interrupt void Interrupt_SCI2_ERI2(void) +#endif +{ + /* Will the user handle the errors? */ + if (rpdl_SCI_RX_Error_callback_func[2] != PDL_NO_FUNC) + { + /* Call the error handler */ + rpdl_SCI_RX_Error_callback_func[2](); + } + else + { + /* Clear the error flags */ + SCI2.SSR.BYTE = (uint8_t)(BIT_7 | BIT_6); + } +} +#endif + +#if FAST_INTC_VECTOR == VECT_SCI3_ERI3 +__fast_interrupt void Interrupt_SCI3_ERI3(void) +#else +#pragma vector = VECT_SCI3_ERI3 +__interrupt void Interrupt_SCI3_ERI3(void) +#endif +{ + /* Will the user handle the errors? */ + if (rpdl_SCI_RX_Error_callback_func[3] != PDL_NO_FUNC) + { + /* Call the error handler */ + rpdl_SCI_RX_Error_callback_func[3](); + } + else + { + /* Clear the error flags */ + SCI3.SSR.BYTE = (uint8_t)(BIT_7 | BIT_6); + } +} + + +#if FAST_INTC_VECTOR == VECT_SCI5_ERI5 +__fast_interrupt void Interrupt_SCI5_ERI5(void) +#else +#pragma vector = VECT_SCI5_ERI5 +__interrupt void Interrupt_SCI5_ERI5(void) +#endif +{ + /* Will the user handle the errors? */ + if (rpdl_SCI_RX_Error_callback_func[5] != PDL_NO_FUNC) + { + /* Call the error handler */ + rpdl_SCI_RX_Error_callback_func[5](); + } + else + { + /* Clear the error flags */ + SCI5.SSR.BYTE = (uint8_t)(BIT_7 | BIT_6); + } +} + +#if FAST_INTC_VECTOR == VECT_SCI6_ERI6 +__fast_interrupt void Interrupt_SCI6_ERI6(void) +#else +#pragma vector = VECT_SCI6_ERI6 +__interrupt void Interrupt_SCI6_ERI6(void) +#endif +{ + /* Will the user handle the errors? */ + if (rpdl_SCI_RX_Error_callback_func[6] != PDL_NO_FUNC) + { + /* Call the error handler */ + rpdl_SCI_RX_Error_callback_func[6](); + } + else + { + /* Clear the error flags */ + SCI6.SSR.BYTE = (uint8_t)(BIT_7 | BIT_6); + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: SCIn receive data interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_SCIn_RXIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : +*------------------------------------------------------------------- +* Use function : rpdl_SCI_RX_End_callback_func +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_SCI0_RXI0 +__fast_interrupt void Interrupt_SCI0_RXI0(void) +#else +#pragma vector = VECT_SCI0_RXI0 +__interrupt void Interrupt_SCI0_RXI0(void) +#endif +{ + /* Ok to process the data? */ + if (rpdl_SCI_rx_using_irq[0] == true) + { + /* check if ID reception in Multiprocessor mode */ + if (rpdl_SCI_MP_mode[0] == 2) + { + /* check if ID cycle ? */ + if (SCI0.SSR.BIT.MPB == 1) + { + uint8_t id; + + /* Read the ID */ + id = SCI0.RDR; + + /* ID matching ? */ + if (id != rpdl_SCI_MP_rx_stationID[0]) + { + /* ID does not match */ + /* MPIE = 1 */ + SCI0.SCR.BIT.MPIE = 1; + } + else + { + /* ID matches */ + /* Disable interrupt request generation, and try to disable reception */ + SCI0.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[0](); + } + } + + /* Exit ISR */ + return; + } + } + + /* Read and store the character */ + *rpdl_SCI_rx_string_pointer[0] = SCI0.RDR; + + /* Increment the character counter */ + rpdl_SCI_rx_counter[0]++; + + /* More characters expected? */ + if (rpdl_SCI_rx_counter[0] < rpdl_SCI_rx_threshold[0]) + { + /* Move to the next location in the buffer */ + rpdl_SCI_rx_string_pointer[0]++; + } + else + { + /* Disable interrupt request generation, and try to disable reception */ + SCI0.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Async MP mode ? */ + if (((SCI0.SMR.BIT.MP) != 0) && ((rpdl_SCI_MP_mode[0]) != 0)) + { + /* Set MPIE = 1 (multiprocessor mode reception) */ + SCI0.SCR.BIT.MPIE = 1; + } + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[0](); + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_RX_End_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[0](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_SCI1_RXI1 +__fast_interrupt void Interrupt_SCI1_RXI1(void) +#else +#pragma vector = VECT_SCI1_RXI1 +__interrupt void Interrupt_SCI1_RXI1(void) +#endif +{ + /* Ok to process the data? */ + if (rpdl_SCI_rx_using_irq[1] == true) + { + /* check if ID reception in Multiprocessor mode */ + if (rpdl_SCI_MP_mode[1] == 2) + { + /* check if ID cycle ? */ + if (SCI1.SSR.BIT.MPB == 1) + { + uint8_t id; + + /* Read the ID */ + id = SCI1.RDR; + + /* ID matching ? */ + if (id != rpdl_SCI_MP_rx_stationID[1]) + { + /* ID does not match */ + /* MPIE = 1 */ + SCI1.SCR.BIT.MPIE = 1; + } + else + { + /* ID matches */ + /* Disable interrupt request generation, and try to disable reception */ + SCI1.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[1](); + } + } + + /* Exit ISR */ + return; + } + } + + /* Read and store the character */ + *rpdl_SCI_rx_string_pointer[1] = SCI1.RDR; + + /* Increment the character counter */ + rpdl_SCI_rx_counter[1]++; + + /* More characters expected? */ + if (rpdl_SCI_rx_counter[1] < rpdl_SCI_rx_threshold[1]) + { + /* Move to the next location in the buffer */ + rpdl_SCI_rx_string_pointer[1]++; + } + else + { + /* Disable interrupt request generation, and try to disable reception */ + SCI1.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Async MP mode ? */ + if (((SCI1.SMR.BIT.MP) != 0) && ((rpdl_SCI_MP_mode[1]) != 0)) + { + /* Set MPIE = 1 (multiprocessor mode reception) */ + SCI1.SCR.BIT.MPIE = 1; + } + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[1](); + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_RX_End_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[1](); + } + } +} + +#if 0 +#if FAST_INTC_VECTOR == VECT_SCI2_RXI2 +__fast_interrupt void Interrupt_SCI2_RXI2(void) +#else +#pragma vector = VECT_SCI2_RXI2 +__interrupt void Interrupt_SCI2_RXI2(void) +#endif +{ + /* Ok to process the data? */ + if (rpdl_SCI_rx_using_irq[2] == true) + { + /* check if ID reception in Multiprocessor mode */ + if (rpdl_SCI_MP_mode[2] == 2) + { + /* check if ID cycle ? */ + if (SCI2.SSR.BIT.MPB == 1) + { + uint8_t id; + + /* Read the ID */ + id = SCI2.RDR; + + /* ID matching ? */ + if (id != rpdl_SCI_MP_rx_stationID[2]) + { + /* ID does not match */ + /* MPIE = 1 */ + SCI2.SCR.BIT.MPIE = 1; + } + else + { + /* ID matches */ + /* Disable interrupt request generation, and try to disable reception */ + SCI2.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[2] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[2](); + } + } + + /* Exit ISR */ + return; + } + } + + + /* Read and store the character */ + *rpdl_SCI_rx_string_pointer[2] = SCI2.RDR; + + /* Increment the character counter */ + rpdl_SCI_rx_counter[2]++; + + /* More characters expected? */ + if (rpdl_SCI_rx_counter[2] < rpdl_SCI_rx_threshold[2]) + { + /* Move to the next location in the buffer */ + rpdl_SCI_rx_string_pointer[2]++; + } + else + { + /* Disable interrupt request generation, and try to disable reception */ + SCI2.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Async MP mode ? */ + if (((SCI2.SMR.BIT.MP) != 0) && ((rpdl_SCI_MP_mode[2]) != 0)) + { + /* Set MPIE = 1 (multiprocessor mode reception) */ + SCI2.SCR.BIT.MPIE = 1; + } + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[2] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[2](); + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_RX_End_callback_func[2] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[2](); + } + } +} + #endif +#if FAST_INTC_VECTOR == VECT_SCI3_RXI3 +__fast_interrupt void Interrupt_SCI3_RXI3(void) +#else +#pragma vector = VECT_SCI3_RXI3 +__interrupt void Interrupt_SCI3_RXI3(void) +#endif +{ + /* Ok to process the data? */ + if (rpdl_SCI_rx_using_irq[3] == true) + { + /* check if ID reception in Multiprocessor mode */ + if (rpdl_SCI_MP_mode[3] == 2) + { + /* check if ID cycle ? */ + if (SCI3.SSR.BIT.MPB == 1) + { + uint8_t id; + + /* Read the ID */ + id = SCI3.RDR; + + /* ID matching ? */ + if (id != rpdl_SCI_MP_rx_stationID[3]) + { + /* ID does not match */ + /* MPIE = 1 */ + SCI3.SCR.BIT.MPIE = 1; + } + else + { + /* ID matches */ + /* Disable interrupt request generation, and try to disable reception */ + SCI3.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[3] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[3](); + } + } + + /* Exit ISR */ + return; + } + } + + /* Read and store the character */ + *rpdl_SCI_rx_string_pointer[3] = SCI3.RDR; + + /* Increment the character counter */ + rpdl_SCI_rx_counter[3]++; + + /* More characters expected? */ + if (rpdl_SCI_rx_counter[3] < rpdl_SCI_rx_threshold[3]) + { + /* Move to the next location in the buffer */ + rpdl_SCI_rx_string_pointer[3]++; + } + else + { + /* Disable interrupt request generation, and try to disable reception */ + SCI3.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Async MP mode ? */ + if (((SCI3.SMR.BIT.MP) != 0) && ((rpdl_SCI_MP_mode[3]) != 0)) + { + /* Set MPIE = 1 (multiprocessor mode reception) */ + SCI3.SCR.BIT.MPIE = 1; + } + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[3] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[3](); + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_RX_End_callback_func[3] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[3](); + } + } +} + + +#if FAST_INTC_VECTOR == VECT_SCI5_RXI5 +__fast_interrupt void Interrupt_SCI5_RXI5(void) +#else +#pragma vector = VECT_SCI5_RXI5 +__interrupt void Interrupt_SCI5_RXI5(void) +#endif +{ + /* Ok to process the data? */ + if (rpdl_SCI_rx_using_irq[5] == true) + { + /* check if ID reception in Multiprocessor mode */ + if (rpdl_SCI_MP_mode[5] == 2) + { + /* check if ID cycle ? */ + if (SCI5.SSR.BIT.MPB == 1) + { + uint8_t id; + + /* Read the ID */ + id = SCI5.RDR; + + /* ID matching ? */ + if (id != rpdl_SCI_MP_rx_stationID[5]) + { + /* ID does not match */ + /* MPIE = 1 */ + SCI5.SCR.BIT.MPIE = 1; + } + else + { + /* ID matches */ + /* Disable interrupt request generation, and try to disable reception */ + SCI5.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[5] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[5](); + } + } + + /* Exit ISR */ + return; + } + } + + /* Read and store the character */ + *rpdl_SCI_rx_string_pointer[5] = SCI5.RDR; + + /* Increment the character counter */ + rpdl_SCI_rx_counter[5]++; + + /* More characters expected? */ + if (rpdl_SCI_rx_counter[5] < rpdl_SCI_rx_threshold[5]) + { + /* Move to the next location in the buffer */ + rpdl_SCI_rx_string_pointer[5]++; + } + else + { + /* Disable interrupt request generation, and try to disable reception */ + SCI5.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Async MP mode ? */ + if (((SCI5.SMR.BIT.MP) != 0) && ((rpdl_SCI_MP_mode[5]) != 0)) + { + /* Set MPIE = 1 (multiprocessor mode reception) */ + SCI5.SCR.BIT.MPIE = 1; + } + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[5] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[5](); + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_RX_End_callback_func[5] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[5](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_SCI6_RXI6 +__fast_interrupt void Interrupt_SCI6_RXI6(void) +#else +#pragma vector = VECT_SCI6_RXI6 +__interrupt void Interrupt_SCI6_RXI6(void) +#endif +{ + /* Ok to process the data? */ + if (rpdl_SCI_rx_using_irq[6] == true) + { + /* check if ID reception in Multiprocessor mode */ + if (rpdl_SCI_MP_mode[6] == 2) + { + /* check if ID cycle ? */ + if (SCI6.SSR.BIT.MPB == 1) + { + uint8_t id; + + /* Read the ID */ + id = SCI6.RDR; + + /* ID matching ? */ + if (id != rpdl_SCI_MP_rx_stationID[6]) + { + /* ID does not match */ + /* MPIE = 1 */ + SCI6.SCR.BIT.MPIE = 1; + } + else + { + /* ID matches */ + /* Disable interrupt request generation, and try to disable reception */ + SCI6.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[6] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[6](); + } + } + + /* Exit ISR */ + return; + } + } + + /* Read and store the character */ + *rpdl_SCI_rx_string_pointer[6] = SCI6.RDR; + + /* Increment the character counter */ + rpdl_SCI_rx_counter[6]++; + + /* More characters expected? */ + if (rpdl_SCI_rx_counter[6] < rpdl_SCI_rx_threshold[6]) + { + /* Move to the next location in the buffer */ + rpdl_SCI_rx_string_pointer[6]++; + } + else + { + /* Disable interrupt request generation, and try to disable reception */ + SCI6.SCR.BYTE &= (uint8_t)(INV_BIT_6 & INV_BIT_4); + + /* Async MP mode ? */ + if (((SCI6.SMR.BIT.MP) != 0) && ((rpdl_SCI_MP_mode[6]) != 0)) + { + /* Set MPIE = 1 (multiprocessor mode reception) */ + SCI6.SCR.BIT.MPIE = 1; + } + + /* Notify the user */ + if (rpdl_SCI_RX_End_callback_func[6] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[6](); + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_RX_End_callback_func[6] != PDL_NO_FUNC) + { + rpdl_SCI_RX_End_callback_func[6](); + } + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: SCIn transmit data interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_SCIn_TXIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : TDR for that SCI channel +*------------------------------------------------------------------- +* Use function : +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_SCI0_TXI0 +__fast_interrupt void Interrupt_SCI0_TXI0(void) +#else +#pragma vector = VECT_SCI0_TXI0 +__interrupt void Interrupt_SCI0_TXI0(void) +#endif +{ + /* Ok to process the string? */ + if (rpdl_SCI_tx_using_irq[0] == true) + { + /* Another character to be sent? */ + if ( + /* Sending a string and next character is not a Null? */ + ((rpdl_SCI_tx_threshold[0] == 0) && (*rpdl_SCI_tx_string_pointer[0] != NULL)) + || + /* Not reached the byte total? */ + (rpdl_SCI_tx_counter[0] < rpdl_SCI_tx_threshold[0]) + ) + { + /* Send the character */ + SCI0.TDR = *rpdl_SCI_tx_string_pointer[0]; + + /* Increment the pointer */ + rpdl_SCI_tx_string_pointer[0]++; + + /* Increment the counter */ + rpdl_SCI_tx_counter[0]++; + } + else + { + /* Disable interrupt request generation */ + SCI0.SCR.BIT.TIE = 0; + + /* Smart card mode? */ + if (SCI0.SCMR.BIT.SMIF == 1) + { + /* Disable transmission and interrupt request generation */ + SCI0.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[0](); + } + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[0](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_SCI1_TXI1 +__fast_interrupt void Interrupt_SCI1_TXI1(void) +#else +#pragma vector = VECT_SCI1_TXI1 +__interrupt void Interrupt_SCI1_TXI1(void) +#endif +{ + /* Ok to process the string? */ + if (rpdl_SCI_tx_using_irq[1] == true) + { + /* Another character to be sent? */ + if ( + /* Sending a string and next character is not a Null? */ + ((rpdl_SCI_tx_threshold[1] == 0) && (*rpdl_SCI_tx_string_pointer[1] != NULL)) + || + /* Not reached the byte total? */ + (rpdl_SCI_tx_counter[1] < rpdl_SCI_tx_threshold[1]) + ) + { + /* Send the character */ + SCI1.TDR = *rpdl_SCI_tx_string_pointer[1]; + + /* Increment the pointer */ + rpdl_SCI_tx_string_pointer[1]++; + + /* Increment the counter */ + rpdl_SCI_tx_counter[1]++; + } + else + { + /* Disable interrupt request generation */ + SCI1.SCR.BIT.TIE = 0; + + /* Smart card mode? */ + if (SCI1.SCMR.BIT.SMIF == 1) + { + /* Disable transmission and interrupt request generation */ + SCI1.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[1](); + } + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[1](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_SCI2_TXI2 +__fast_interrupt void Interrupt_SCI2_TXI2(void) +#else +#pragma vector = VECT_SCI2_TXI2 +__interrupt void Interrupt_SCI2_TXI2(void) +#endif +{ + /* Ok to process the string? */ + if (rpdl_SCI_tx_using_irq[2] == true) + { + /* Another character to be sent? */ + if ( + /* Sending a string and next character is not a Null? */ + ((rpdl_SCI_tx_threshold[2] == 0) && (*rpdl_SCI_tx_string_pointer[2] != NULL)) + || + /* Not reached the byte total? */ + (rpdl_SCI_tx_counter[2] < rpdl_SCI_tx_threshold[2]) + ) + { + /* Send the character */ + SCI2.TDR = *rpdl_SCI_tx_string_pointer[2]; + + /* Increment the pointer */ + rpdl_SCI_tx_string_pointer[2]++; + + /* Increment the counter */ + rpdl_SCI_tx_counter[2]++; + } + else + { + /* Disable interrupt request generation */ + SCI2.SCR.BIT.TIE = 0; + + /* Smart card mode? */ + if (SCI2.SCMR.BIT.SMIF == 1) + { + /* Disable transmission and interrupt request generation */ + SCI2.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[2] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[2](); + } + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[2] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[2](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_SCI3_TXI3 +__fast_interrupt void Interrupt_SCI3_TXI3(void) +#else +#pragma vector = VECT_SCI3_TXI3 +__interrupt void Interrupt_SCI3_TXI3(void) +#endif +{ + /* Ok to process the string? */ + if (rpdl_SCI_tx_using_irq[3] == true) + { + /* Another character to be sent? */ + if ( + /* Sending a string and next character is not a Null? */ + ((rpdl_SCI_tx_threshold[3] == 0) && (*rpdl_SCI_tx_string_pointer[3] != NULL)) + || + /* Not reached the byte total? */ + (rpdl_SCI_tx_counter[3] < rpdl_SCI_tx_threshold[3]) + ) + { + /* Send the character */ + SCI3.TDR = *rpdl_SCI_tx_string_pointer[3]; + + /* Increment the pointer */ + rpdl_SCI_tx_string_pointer[3]++; + + /* Increment the counter */ + rpdl_SCI_tx_counter[3]++; + } + else + { + /* Disable interrupt request generation */ + SCI3.SCR.BIT.TIE = 0; + + /* Smart card mode? */ + if (SCI3.SCMR.BIT.SMIF == 1) + { + /* Disable transmission and interrupt request generation */ + SCI3.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[3] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[3](); + } + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[3] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[3](); + } + } +} + + +#if FAST_INTC_VECTOR == VECT_SCI5_TXI5 +__fast_interrupt void Interrupt_SCI5_TXI5(void) +#else +#pragma vector = VECT_SCI5_TXI5 +__interrupt void Interrupt_SCI5_TXI5(void) +#endif +{ + /* Ok to process the string? */ + if (rpdl_SCI_tx_using_irq[5] == true) + { + /* Another character to be sent? */ + if ( + /* Sending a string and next character is not a Null? */ + ((rpdl_SCI_tx_threshold[5] == 0) && (*rpdl_SCI_tx_string_pointer[5] != NULL)) + || + /* Not reached the byte total? */ + (rpdl_SCI_tx_counter[5] < rpdl_SCI_tx_threshold[5]) + ) + { + /* Send the character */ + SCI5.TDR = *rpdl_SCI_tx_string_pointer[5]; + + /* Increment the pointer */ + rpdl_SCI_tx_string_pointer[5]++; + + /* Increment the counter */ + rpdl_SCI_tx_counter[5]++; + } + else + { + /* Disable interrupt request generation */ + SCI5.SCR.BIT.TIE = 0; + + /* Smart card mode? */ + if (SCI5.SCMR.BIT.SMIF == 1) + { + /* Disable transmission and interrupt request generation */ + SCI5.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[5] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[5](); + } + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[5] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[5](); + } + } +} + +#if FAST_INTC_VECTOR == VECT_SCI6_TXI6 +__fast_interrupt void Interrupt_SCI6_TXI6(void) +#else +#pragma vector = VECT_SCI6_TXI6 +__interrupt void Interrupt_SCI6_TXI6(void) +#endif +{ + /* Ok to process the string? */ + if (rpdl_SCI_tx_using_irq[6] == true) + { + /* Another character to be sent? */ + if ( + /* Sending a string and next character is not a Null? */ + ((rpdl_SCI_tx_threshold[6] == 0) && (*rpdl_SCI_tx_string_pointer[6] != NULL)) + || + /* Not reached the byte total? */ + (rpdl_SCI_tx_counter[6] < rpdl_SCI_tx_threshold[6]) + ) + { + /* Send the character */ + SCI6.TDR = *rpdl_SCI_tx_string_pointer[6]; + + /* Increment the pointer */ + rpdl_SCI_tx_string_pointer[6]++; + + /* Increment the counter */ + rpdl_SCI_tx_counter[6]++; + } + else + { + /* Disable interrupt request generation */ + SCI6.SCR.BIT.TIE = 0; + + /* Smart card mode? */ + if (SCI6.SCMR.BIT.SMIF == 1) + { + /* Disable transmission and interrupt request generation */ + SCI6.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[6] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[6](); + } + } + } + } + /* Either the DMAC or DTC has passed on the interrupt */ + else + { + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[6] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[6](); + } + } +} + +/*""FUNC COMMENT""*************************************************** +* Module outline: SCIn transmit end interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_SCIn_TEIn(void) +*------------------------------------------------------------------- +* Function : +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Output : SCR for that channel +*------------------------------------------------------------------- +* Use function : rpdl_SCI_TX_End_callback_func() +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_SCI0_TEI0 +__fast_interrupt void Interrupt_SCI0_TEI0(void) +#else +#pragma vector = VECT_SCI0_TEI0 +__interrupt void Interrupt_SCI0_TEI0(void) +#endif +{ + /* Disable interrupt request generation, and try to disable transmission */ + SCI0.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5 & INV_BIT_2); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[0] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[0](); + } +} + +#if FAST_INTC_VECTOR == VECT_SCI1_TEI1 +__fast_interrupt void Interrupt_SCI1_TEI1(void) +#else +#pragma vector = VECT_SCI1_TEI1 +__interrupt void Interrupt_SCI1_TEI1(void) +#endif +{ + /* Disable interrupt request generation, and try to disable transmission */ + SCI1.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5 & INV_BIT_2); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[1] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[1](); + } +} + +#if FAST_INTC_VECTOR == VECT_SCI2_TEI2 +__fast_interrupt void Interrupt_SCI2_TEI2(void) +#else +#pragma vector = VECT_SCI2_TEI2 +__interrupt void Interrupt_SCI2_TEI2(void) +#endif +{ + /* Disable interrupt request generation, and try to disable transmission */ + SCI2.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5 & INV_BIT_2); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[2] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[2](); + } +} + +#if FAST_INTC_VECTOR == VECT_SCI3_TEI3 +__fast_interrupt void Interrupt_SCI3_TEI3(void) +#else +#pragma vector = VECT_SCI3_TEI3 +__interrupt void Interrupt_SCI3_TEI3(void) +#endif +{ + /* Disable interrupt request generation, and try to disable transmission */ + SCI3.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5 & INV_BIT_2); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[3] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[3](); + } +} + + +#if FAST_INTC_VECTOR == VECT_SCI5_TEI5 +__fast_interrupt void Interrupt_SCI5_TEI5(void) +#else +#pragma vector = VECT_SCI5_TEI5 +__interrupt void Interrupt_SCI5_TEI5(void) +#endif +{ + /* Disable interrupt request generation, and try to disable transmission */ + SCI5.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5 & INV_BIT_2); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[5] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[5](); + } +} + +#if FAST_INTC_VECTOR == VECT_SCI6_TEI6 +__fast_interrupt void Interrupt_SCI6_TEI6(void) +#else +#pragma vector = VECT_SCI6_TEI6 +__interrupt void Interrupt_SCI6_TEI6(void) +#endif +{ + /* Disable interrupt request generation, and try to disable transmission */ + SCI6.SCR.BYTE &= (uint8_t)(INV_BIT_7 & INV_BIT_5 & INV_BIT_2); + + /* Call the callback function */ + if (rpdl_SCI_TX_End_callback_func[6] != PDL_NO_FUNC) + { + rpdl_SCI_TX_End_callback_func[6](); + } +} +/* End of file */ diff --git a/bsp/rx/RPDL/interrupt_wdt.c b/bsp/rx/RPDL/interrupt_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..a93e366955d70731fb905d6567566438a3bac15c --- /dev/null +++ b/bsp/rx/RPDL/interrupt_wdt.c @@ -0,0 +1,63 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Interrupt program for RX62Nxx +* File Name : Interrupt_WDT.c +* Version : 1.02 +* Contents : Interrupt handler for the Watchdog timer +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#include "r_pdl_wdt.h" +#include "r_pdl_definitions.h" +#include "r_pdl_user_definitions.h" + +/*""FUNC COMMENT""*************************************************** +* Module outline : Timer interrupt processing +*------------------------------------------------------------------- +* Declaration : void Interrupt_WDT(void) +*------------------------------------------------------------------- +* Function : Interrupt processing function for the WDT +*------------------------------------------------------------------- +* Argument : Nothing +*------------------------------------------------------------------- +* Return value : Nothing +*------------------------------------------------------------------- +* Input : +* Output : +*------------------------------------------------------------------- +* Use function : WDT_callback_func +*------------------------------------------------------------------- +* Notes : +*------------------------------------------------------------------- +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FUNC COMMENT END""**********************************************/ + +#if FAST_INTC_VECTOR == VECT_WDT_WOVI +__fast_interrupt void Interrupt_WDT(void) +#else +#pragma vector = VECT_WDT_WOVI +__interrupt void Interrupt_WDT(void) +#endif +{ + /* Call the user function */ + if (rpdl_WDT_callback_func != PDL_NO_FUNC) + { + rpdl_WDT_callback_func(); + } +} +/* End of file */ diff --git a/bsp/rx/RPDL/macro.h b/bsp/rx/RPDL/macro.h new file mode 100644 index 0000000000000000000000000000000000000000..ddd830db5426103ed573d340c58aea661d037197 --- /dev/null +++ b/bsp/rx/RPDL/macro.h @@ -0,0 +1,72 @@ +/********************************************************************************/ +/* RX FAMILY C/C++ Compiler */ +/* Copyright (C) 2007 Renesas Technology Corp. and Renesas Solutions Corp. */ +/* All Rights Reserved. */ +/********************************************************************************/ + +#ifndef _MACRO +#define _MACRO + +#ifdef __RX + +#ifndef _NO_MT +#define _NO_MT +#endif /* !_NO_MT */ + +#ifdef __STDC_VERSION__ +#if 199901L <= __STDC_VERSION__ +#define _C99 +#endif /* 199901L <= __STDC_VERSION__ */ +#endif /* __STDC_VERSION__ */ + +#ifndef _HAS_TR1 +#define _HAS_TR1 0 +#endif /* !_HAS_TR1 */ + +#ifndef __STDC_WANT_LIB_EXT1__ +#define __STDC_WANT_LIB_EXT1__ 0 +#endif /* !__STDC_WANT_LIB_EXT1 */ + +#ifndef _ADDED_C_LIB +#define _ADDED_C_LIB 0 +#endif /* !_ADDED_C_LIB */ + +#ifndef __STDC_WANT_SAFER_LIB__ +#define __STDC_WANT_SAFER_LIB__ 0 +#endif /* !__STDC_WANT_SAFER_LIB__ */ + +#ifndef _ALT_NS +#define _ALT_NS 0 +#endif /* !_ALT_NS */ + +#ifdef __cplusplus + +#ifndef _C99 +#define _C99 +#endif /* !_C99*/ + +#endif /* __cplusplus */ + +#ifdef __embedded_cplusplus + +#ifndef _NO_NS +#define _NO_NS +#endif /* !_NO_NS */ + +#ifndef _ECPP +#define _ECPP +#endif /* !_ECPP */ + +#endif /* __embedded_cplusplus */ + +#ifdef _REENTRANT + +#ifndef _R_REENT +#define _R_REENT +#endif /* !_R_REENT */ + +#endif /* _REENTRANT */ + +#endif /* __RX */ + +#endif /* _MACRO */ diff --git a/bsp/rx/RPDL/r_pdl_adc_10.h b/bsp/rx/RPDL/r_pdl_adc_10.h new file mode 100644 index 0000000000000000000000000000000000000000..7590f11cb0939084d4808f1e90ee16f174be60d6 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_adc_10.h @@ -0,0 +1,111 @@ +/*""FILE COMMENT""******************************************************* +* System Name : ADC converter API for RX62Nxx +* File Name : r_pdl_adc_10.h +* Version : 1.02 +* Contents : ADC function prototypes +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_ADC_10_H +#define R_PDL_ADC_10_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_ADC_10_Create( + uint8_t, + uint32_t, + uint32_t, + float, + void *, + uint8_t +); +bool R_ADC_10_Destroy( + uint8_t +); +bool R_ADC_10_Control( + uint16_t +); +bool R_ADC_10_Read( + uint8_t, + uint16_t * +); + +/* Scan mode */ +#define PDL_ADC_10_MODE_SINGLE 0x00000001u +#define PDL_ADC_10_MODE_CONTINUOUS_SCAN 0x00000002u +#define PDL_ADC_10_MODE_ONE_CYCLE_SCAN 0x00000004u + +/* Channel selection */ +#define PDL_ADC_10_CHANNELS_OPTION_1 0x00000008u +#define PDL_ADC_10_CHANNELS_OPTION_2 0x00000010u +#define PDL_ADC_10_CHANNELS_OPTION_3 0x00000020u +#define PDL_ADC_10_CHANNELS_OPTION_4 0x00000040u + +/* Trigger selection */ +#define PDL_ADC_10_TRIGGER_SOFTWARE 0x00000080u +#define PDL_ADC_10_TRIGGER_MTU0_MTU4_CMIC_A 0x00000100u +#define PDL_ADC_10_TRIGGER_TMR0_CM_A 0x00000200u +#define PDL_ADC_10_TRIGGER_ADTRG0 0x00000400u +#define PDL_ADC_10_TRIGGER_ADTRG1 0x00000800u +#define PDL_ADC_10_TRIGGER_MTU0_CMIC 0x00001000u +#define PDL_ADC_10_TRIGGER_MTU6_MTU10_CMIC_A 0x00002000u +#define PDL_ADC_10_TRIGGER_MTU4_CM 0x00004000u +#define PDL_ADC_10_TRIGGER_MTU10_CM 0x00008000u + +/* Data alignment */ +#define PDL_ADC_10_DATA_ALIGNMENT_LEFT 0x00010000u +#define PDL_ADC_10_DATA_ALIGNMENT_RIGHT 0x00020000u + +/* DMAC / DTC trigger control */ +#define PDL_ADC_10_DMAC_DTC_TRIGGER_DISABLE 0x00040000u +#define PDL_ADC_10_DMAC_TRIGGER_ENABLE 0x00080000u +#define PDL_ADC_10_DTC_TRIGGER_ENABLE 0x00100000u + +/* Sampling time calcuation control */ +#define PDL_ADC_10_ADSSTR_CALCULATE 0x00200000u +#define PDL_ADC_10_ADSSTR_SPECIFY 0x00400000u + +/* Pin selection */ +#define PDL_ADC_10_PIN_ADTRG0_A 0x00800000u +#define PDL_ADC_10_PIN_ADTRG0_B 0x01000000u + +/* Self-Diagnostic */ +#define PDL_ADC_10_SINGLE_AN0_SW (PDL_ADC_10_MODE_SINGLE | \ + PDL_ADC_10_CHANNELS_OPTION_1 | \ + PDL_ADC_10_TRIGGER_SOFTWARE) +#define PDL_ADC_10_ADDIAGR_DISABLE 0x02000000u +#define PDL_ADC_10_ADDIAGR_VREF_0 0x04000000u +#define PDL_ADC_10_ADDIAGR_VREF_0_5 0x08000000u +#define PDL_ADC_10_ADDIAGR_VREF_1 0x10000000u +#define PDL_ADC_10_SELF_DIAGNOSTIC_DISABLE (PDL_ADC_10_ADDIAGR_DISABLE) +#define PDL_ADC_10_SELF_DIAGNOSTIC_VREF_0 (PDL_ADC_10_SINGLE_AN0_SW | PDL_ADC_10_ADDIAGR_VREF_0) +#define PDL_ADC_10_SELF_DIAGNOSTIC_VREF_0_5 (PDL_ADC_10_SINGLE_AN0_SW | PDL_ADC_10_ADDIAGR_VREF_0_5) +#define PDL_ADC_10_SELF_DIAGNOSTIC_VREF_1 (PDL_ADC_10_SINGLE_AN0_SW | PDL_ADC_10_ADDIAGR_VREF_1) + +/* On / off control */ +#define PDL_ADC_10_0_ON 0x0001u +#define PDL_ADC_10_0_OFF 0x0002u +#define PDL_ADC_10_1_ON 0x0004u +#define PDL_ADC_10_1_OFF 0x0008u + +/* CPU control */ +#define PDL_ADC_10_CPU_ON 0x0100u +#define PDL_ADC_10_CPU_OFF 0x0200u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_adc_10_RX62Nxx.h b/bsp/rx/RPDL/r_pdl_adc_10_RX62Nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..263f2a2e155daee230ba20530987e917f55ba649 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_adc_10_RX62Nxx.h @@ -0,0 +1,82 @@ +/*""FILE COMMENT""******************************************************* +* System Name : A/D converter API for RX62Nxx +* File Name : r_pdl_adc_10_RX62Nxx.h +* Version : 1.02 +* Contents : ADC header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_ADC_10_RX62Nxx_H +#define R_PDL_ADC_10_RX62Nxx_H + +#define ADC_10_UNITS 2 + +extern VoidCallBackFunc rpdl_ADC_10_callback_func[]; + +/* Library prototypes */ +bool R_ADC_10_CreateAll( + const uint8_t, + const uint32_t, + const uint32_t, + const float, + VoidCallBackFunc const, + const uint8_t +); +bool R_ADC_10_DestroyAll( + const uint8_t +); +bool R_ADC_10_ControlAll( + const uint16_t +); +bool R_ADC_10_ReadAll( + const uint8_t, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_ADC_10_Create(a, b, c, d, e, f) \ +( \ +( ( ((a) < ADC_10_UNITS) && ((f) <= IPL_MAX) ) ) ? \ +R_ADC_10_CreateAll( (a), (b), (c), (d), (e), (f)): \ +ReturnFalse() \ +) + +#define R_ADC_10_Destroy(a) \ +( \ +( (a) < ADC_10_UNITS ) ? \ +R_ADC_10_DestroyAll( (a) ): \ +ReturnFalse() \ +) + +#define R_ADC_10_Control(a) \ +( \ +( ((a) & 0xFFu) != 0x00u ) ? \ +R_ADC_10_ControlAll( (a) ): \ +ReturnFalse() \ +) + +#define R_ADC_10_Read(a, b) \ +( \ +( (a) < ADC_10_UNITS ) ? \ +R_ADC_10_ReadAll( (a), (b) ): \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_adc_12.h b/bsp/rx/RPDL/r_pdl_adc_12.h new file mode 100644 index 0000000000000000000000000000000000000000..e0c49b289ed898291dda69def781c51977b1d258 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_adc_12.h @@ -0,0 +1,123 @@ +/*""FILE COMMENT""******************************************************* +* System Name : 12-bit ADC converter API for RX62Nxx +* File Name : r_pdl_adc_12.h +* Version : 1.02 +* Contents : ADC_12 function prototypes +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_ADC_12_H +#define R_PDL_ADC_12_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_ADC_12_Create( + uint8_t, + uint32_t, + uint16_t, + uint16_t, + void *, + uint8_t +); +bool R_ADC_12_Destroy( + uint8_t +); +bool R_ADC_12_Control( + uint8_t +); +bool R_ADC_12_Read( + uint8_t, + uint16_t * +); + +/* Scan mode */ +#define PDL_ADC_12_SCAN_SINGLE 0x00000001ul +#define PDL_ADC_12_SCAN_CONTINUOUS 0x00000002ul + +// Input channel selection +#define PDL_ADC_12_CHANNEL_0 0x00000004ul +#define PDL_ADC_12_CHANNEL_1 0x00000008ul +#define PDL_ADC_12_CHANNEL_2 0x00000010ul +#define PDL_ADC_12_CHANNEL_3 0x00000020ul +#define PDL_ADC_12_CHANNEL_4 0x00000040ul +#define PDL_ADC_12_CHANNEL_5 0x00000080ul +#define PDL_ADC_12_CHANNEL_6 0x00000100ul +#define PDL_ADC_12_CHANNEL_7 0x00000200ul + +/* Clock division */ +#define PDL_ADC_12_DIV_1 0x00000400ul +#define PDL_ADC_12_DIV_2 0x00000800ul +#define PDL_ADC_12_DIV_4 0x00001000ul +#define PDL_ADC_12_DIV_8 0x00002000ul + +/* Data alignment */ +#define PDL_ADC_12_DATA_ALIGNMENT_LEFT 0x00004000ul +#define PDL_ADC_12_DATA_ALIGNMENT_RIGHT 0x00008000ul + +/* Result register clearing */ +#define PDL_ADC_12_RETAIN_RESULT 0x00010000ul +#define PDL_ADC_12_CLEAR_RESULT 0x00020000ul + +/* DMAC / DTC trigger control */ +#define PDL_ADC_12_DMAC_DTC_TRIGGER_DISABLE 0x00040000ul +#define PDL_ADC_12_DMAC_TRIGGER_ENABLE 0x00080000ul +#define PDL_ADC_12_DTC_TRIGGER_ENABLE 0x00100000ul + +/* Trigger selection */ +#define PDL_ADC_12_TRIGGER_SOFTWARE 0x0001u +#define PDL_ADC_12_TRIGGER_ADTRG0 0x0002u +#define PDL_ADC_12_TRIGGER_MTU0_ICCM_A 0x0004u +#define PDL_ADC_12_TRIGGER_MTU0_ICCM_B 0x0008u +#define PDL_ADC_12_TRIGGER_MTU0_MTU4_ICCM 0x0010u +#define PDL_ADC_12_TRIGGER_MTU6_MTU10_ICCM 0x0020u +#define PDL_ADC_12_TRIGGER_MTU0_CM_E 0x0040u +#define PDL_ADC_12_TRIGGER_MTU0_CM_F 0x0080u +#define PDL_ADC_12_TRIGGER_MTU4_CM 0x0100u +#define PDL_ADC_12_TRIGGER_MTU10_CM 0x0200u +#define PDL_ADC_12_TRIGGER_TMR0 0x0400u +#define PDL_ADC_12_TRIGGER_TMR2 0x0800u + +/* Pin selection */ +#define PDL_ADC_12_PIN_ADTRG0_A 0x1000u +#define PDL_ADC_12_PIN_ADTRG0_B 0x2000u + +/* Value addition mode selection */ +#define PDL_ADC_12_VALUE_ADD_CHANNEL_0 0x0001u +#define PDL_ADC_12_VALUE_ADD_CHANNEL_1 0x0002u +#define PDL_ADC_12_VALUE_ADD_CHANNEL_2 0x0004u +#define PDL_ADC_12_VALUE_ADD_CHANNEL_3 0x0008u +#define PDL_ADC_12_VALUE_ADD_CHANNEL_4 0x0010u +#define PDL_ADC_12_VALUE_ADD_CHANNEL_5 0x0020u +#define PDL_ADC_12_VALUE_ADD_CHANNEL_6 0x0040u +#define PDL_ADC_12_VALUE_ADD_CHANNEL_7 0x0080u + +/* Value addition count selection */ +#define PDL_ADC_12_VALUE_ADD_TIME_1 0x0100u +#define PDL_ADC_12_VALUE_ADD_TIME_2 0x0200u +#define PDL_ADC_12_VALUE_ADD_TIME_3 0x0400u +#define PDL_ADC_12_VALUE_ADD_TIME_4 0x0800u + +/* On / off control */ +#define PDL_ADC_12_0_ON 0x01u +#define PDL_ADC_12_0_OFF 0x02u + +/* CPU control */ +#define PDL_ADC_12_CPU_OFF 0x04u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_adc_12_RX62Nxx.h b/bsp/rx/RPDL/r_pdl_adc_12_RX62Nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..574c5328c39d0525331c7a4e3e418c67342931fc --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_adc_12_RX62Nxx.h @@ -0,0 +1,80 @@ +/*""FILE COMMENT""******************************************************* +* System Name : 12-bit A/D converter API for RX62Nxx +* File Name : r_pdl_adc_12_RX62Nxx.h +* Version : 1.02 +* Contents : ADC_12 header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_ADC_12_RX62Nxx_H +#define R_PDL_ADC_12_RX62Nxx_H + +extern VoidCallBackFunc rpdl_ADC_12_callback_func[]; + +#define ADC_12_UNITS 1 + +/* Library prototypes */ +bool R_ADC_12_CreateAll( + const uint8_t, + const uint32_t, + const uint16_t, + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_ADC_12_DestroyAll( + const uint8_t +); +bool R_ADC_12_ControlAll( + const uint8_t +); +bool R_ADC_12_ReadAll( + const uint8_t, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_ADC_12_Create(a, b, c, d, e, f) \ +( \ +( ( ((a) < ADC_12_UNITS) && ((f) <= IPL_MAX) ) ) ? \ +R_ADC_12_CreateAll( (a), (b), (c), (d), (e), (f)): \ +ReturnFalse() \ +) + +#define R_ADC_12_Destroy(a) \ +( \ +( (a) < ADC_12_UNITS ) ? \ +R_ADC_12_DestroyAll( (a) ): \ +ReturnFalse() \ +) + +#define R_ADC_12_Control(a) \ +( \ +R_ADC_12_ControlAll( (a) ) \ +) + +#define R_ADC_12_Read(a, b) \ +( \ +( (a) < ADC_12_UNITS ) ? \ +R_ADC_12_ReadAll( (a), (b) ): \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_bsc.h b/bsp/rx/RPDL/r_pdl_bsc.h new file mode 100644 index 0000000000000000000000000000000000000000..1a3f8a31e97eb1d44e6975b345aad65ed68c354a --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_bsc.h @@ -0,0 +1,210 @@ +/*""FILE COMMENT""******************************************************* +* System Name : BSC API for RX62Nxx +* File Name : r_pdl_bsc.h +* Version : 1.02 +* Contents : BSC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_BSC_H +#define R_PDL_BSC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_BSC_Create( + uint32_t, + uint32_t, + uint8_t, + void *, + uint8_t +); +bool R_BSC_CreateArea( + uint8_t, + uint16_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t +); +bool R_BSC_SDRAM_CreateArea( + uint16_t, + uint16_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + uint16_t +); +bool R_BSC_Destroy( + uint8_t +); +bool R_BSC_Control( + uint16_t +); +bool R_BSC_GetStatus( + uint8_t *, + uint16_t *, + uint8_t * +); + +/* R_BSC_Create parameter options */ +/* Configuration1 (pin select control) */ +/* Chip select pin selection */ +#define PDL_BSC_CS0_A 0x00000001ul +#define PDL_BSC_CS0_B 0x00000002ul +#define PDL_BSC_CS1_A 0x00000004ul +#define PDL_BSC_CS1_B 0x00000008ul +#define PDL_BSC_CS1_C 0x00000010ul +#define PDL_BSC_CS2_A 0x00000020ul +#define PDL_BSC_CS2_B 0x00000040ul +#define PDL_BSC_CS2_C 0x00000080ul +#define PDL_BSC_CS3_A 0x00000100ul +#define PDL_BSC_CS3_B 0x00000200ul +#define PDL_BSC_CS3_C 0x00000400ul +#define PDL_BSC_CS4_A 0x00000800ul +#define PDL_BSC_CS4_B 0x00001000ul +#define PDL_BSC_CS4_C 0x00002000ul +#define PDL_BSC_CS5_A 0x00004000ul +#define PDL_BSC_CS5_B 0x00008000ul +#define PDL_BSC_CS5_C 0x00010000ul +#define PDL_BSC_CS6_A 0x00020000ul +#define PDL_BSC_CS6_B 0x00040000ul +#define PDL_BSC_CS6_C 0x00080000ul +#define PDL_BSC_CS7_A 0x00100000ul +#define PDL_BSC_CS7_B 0x00200000ul +#define PDL_BSC_CS7_C 0x00400000ul + +/* Address (A23-A16) pin selection */ +#define PDL_BSC_A23_A16_A 0x00800000ul +#define PDL_BSC_A23_A16_B 0x01000000ul + +/* WAIT pin selection */ +#define PDL_BSC_WAIT_NOT_USED 0x02000000ul +#define PDL_BSC_WAIT_A 0x04000000ul +#define PDL_BSC_WAIT_B 0x08000000ul +#define PDL_BSC_WAIT_C 0x10000000ul +#define PDL_BSC_WAIT_D 0x20000000ul + +/* Configuration2 (output enable control) */ +/* Address output control */ +#define PDL_BSC_A9_A0_DISABLE 0x00000001ul +#define PDL_BSC_A9_A4_DISABLE 0x00000002ul +#define PDL_BSC_A9_A8_DISABLE 0x00000004ul +#define PDL_BSC_A10_DISABLE 0x00000008ul +#define PDL_BSC_A11_DISABLE 0x00000010ul +#define PDL_BSC_A12_DISABLE 0x00000020ul +#define PDL_BSC_A13_DISABLE 0x00000040ul +#define PDL_BSC_A14_DISABLE 0x00000080ul +#define PDL_BSC_A15_DISABLE 0x00000100ul +#define PDL_BSC_A16_DISABLE 0x00000200ul +#define PDL_BSC_A17_DISABLE 0x00000400ul +#define PDL_BSC_A18_DISABLE 0x00000800ul +#define PDL_BSC_A19_DISABLE 0x00001000ul +#define PDL_BSC_A20_DISABLE 0x00002000ul +#define PDL_BSC_A21_DISABLE 0x00004000ul +#define PDL_BSC_A22_DISABLE 0x00008000ul +#define PDL_BSC_A23_DISABLE 0x00010000ul + +/* SDRAM output control */ +#define PDL_BSC_SDRAM_PINS_DISABLE 0x00020000ul +#define PDL_BSC_SDRAM_PINS_ENABLE 0x00040000ul +#define PDL_BSC_SDRAM_DQM1_DISABLE 0x00080000ul +#define PDL_BSC_SDRAM_DQM1_ENABLE 0x00100000ul + + +/* Configuration3 (error control) */ +/* Error monitoring */ +#define PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE 0x01u +#define PDL_BSC_ERROR_ILLEGAL_ADDRESS_DISABLE 0x02u +#define PDL_BSC_ERROR_TIME_OUT_ENABLE 0x04u +#define PDL_BSC_ERROR_TIME_OUT_DISABLE 0x08u + +/* R_BSC_CreateArea parameter options */ +/* Configuration selection */ +/* Bus width */ +#define PDL_BSC_WIDTH_16 0x0001u +#define PDL_BSC_WIDTH_8 0x0002u +#define PDL_BSC_WIDTH_32 0x0004u + +/* Endian mode */ +#define PDL_BSC_ENDIAN_SAME 0x0008u +#define PDL_BSC_ENDIAN_OPPOSITE 0x0010u + +/* Write access mode */ +#define PDL_BSC_WRITE_BYTE 0x0020u +#define PDL_BSC_WRITE_SINGLE 0x0040u + +/* External wait control */ +#define PDL_BSC_WAIT_DISABLE 0x0080u +#define PDL_BSC_WAIT_ENABLE 0x0100u + +/* Page access control */ +#define PDL_BSC_PAGE_READ_DISABLE 0x0200u +#define PDL_BSC_PAGE_READ_NORMAL 0x0400u +#define PDL_BSC_PAGE_READ_CONTINUOUS 0x0800u +#define PDL_BSC_PAGE_WRITE_DISABLE 0x1000u +#define PDL_BSC_PAGE_WRITE_ENABLE 0x2000u + +/* R_BSC_Control parameter options */ +#define PDL_BSC_ERROR_CLEAR 0x0001u +#define PDL_BSC_SDRAM_INITIALIZATION 0x0002u +#define PDL_BSC_SDRAM_AUTO_REFRESH_ENABLE 0x0004u +#define PDL_BSC_SDRAM_AUTO_REFRESH_DISABLE 0x0008u +#define PDL_BSC_SDRAM_SELF_REFRESH_ENABLE 0x0010u +#define PDL_BSC_SDRAM_SELF_REFRESH_DISABLE 0x0020u +#define PDL_BSC_SDRAM_ENABLE 0x0040u +#define PDL_BSC_SDRAM_DISABLE 0x0080u +#define PDL_BSC_DISABLE_BUSERR_IRQ 0x0100u + +/* R_BSC_SDRAM_CreateArea parameter options */ +/* Configuration selection */ +/* Bus width */ +#define PDL_BSC_SDRAM_WIDTH_16 0x0001u +#define PDL_BSC_SDRAM_WIDTH_8 0x0002u +#define PDL_BSC_SDRAM_WIDTH_32 0x0004u + +/* Endian mode */ +#define PDL_BSC_SDRAM_ENDIAN_SAME 0x0008u +#define PDL_BSC_SDRAM_ENDIAN_OPPOSITE 0x0010u + +/* Continuous access mode */ +#define PDL_BSC_SDRAM_CONT_ACCESS_ENABLE 0x0020u +#define PDL_BSC_SDRAM_CONT_ACCESS_DISABLE 0x0040u + +/* Address multiplex selection */ +#define PDL_BSC_SDRAM_8_BIT_SHIFT 0x0080u +#define PDL_BSC_SDRAM_9_BIT_SHIFT 0x0100u +#define PDL_BSC_SDRAM_10_BIT_SHIFT 0x0200u +#define PDL_BSC_SDRAM_11_BIT_SHIFT 0x0400u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_bsc_rx62nxx.h b/bsp/rx/RPDL/r_pdl_bsc_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..178d2bbdea02d0313b03e1d13aefc2a31c248902 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_bsc_rx62nxx.h @@ -0,0 +1,129 @@ +/*""FILE COMMENT""******************************************************* +* System Name : BSC API for RX62N +* File Name : r_pdl_bsc_RX62Nxx.h +* Version : 1.02 +* Contents : BSC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_BSC_RX62Nxx_H +#define R_PDL_BSC_RX62Nxx_H + +#define BSC_AREAS 8 + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_BSC_callback_func; + +/* Library prototypes */ +bool R_BSC_CreateAll( + const uint32_t, + const uint32_t, + const uint8_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_BSC_CreateAreaAll( + const uint8_t, + const uint16_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_BSC_SDRAM_CreateAreaAll( + const uint16_t, + const uint16_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint16_t +); +bool R_BSC_DestroyAll( + const uint8_t +); +bool R_BSC_ControlAll( + const uint16_t +); +bool R_BSC_GetStatusAll( + volatile uint8_t * const, + volatile uint16_t * const, + volatile uint8_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_BSC_Create(a, b, c, d, e) \ +( \ +( (e) <= IPL_MAX ) ? \ +R_BSC_CreateAll( (a), (b), (c), (d), (e) ) : \ +ReturnFalse() \ +) + +#define R_BSC_CreateArea(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o) \ +( \ +( (a) < BSC_AREAS ) ? \ +R_BSC_CreateAreaAll( (a), (b), (c), (d), (e), (f), (g), (h), (i), (j), (k), (l), (m), (n), (o) ) : \ +ReturnFalse() \ +) + +#if defined (DEVICE_PACKAGE_LQFP_100) || defined (DEVICE_PACKAGE_TFLGA_85) +#define R_BSC_SDRAM_CreateArea(a, b, c, d, e, f, g, h, i, j, k, l) \ +( \ +ReturnFalse() \ +) +#else +#define R_BSC_SDRAM_CreateArea(a, b, c, d, e, f, g, h, i, j, k, l) \ +( \ +R_BSC_SDRAM_CreateAreaAll( (a), (b), (c), (d), (e), (f), (g), (h), (i), (j), (k), (l) ) \ +) +#endif + +#define R_BSC_Destroy(a) \ +( \ +( (a) < BSC_AREAS ) ? \ +R_BSC_DestroyAll( (a) ) : \ +ReturnFalse() \ +) + +#define R_BSC_Control(a) \ +( \ +R_BSC_ControlAll( (a) ) \ +) + +#define R_BSC_GetStatus(a, b, c) \ +( \ +R_BSC_GetStatusAll( (a), (b), (c) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_cgc.h b/bsp/rx/RPDL/r_pdl_cgc.h new file mode 100644 index 0000000000000000000000000000000000000000..e7869422978a7fc232f225ba0ad88a0bccda8e70 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_cgc.h @@ -0,0 +1,64 @@ +/*""FILE COMMENT""******************************************************* +* System Name : CGC API +* File Name : r_pdl_cgc.h +* Version : 1.02 +* Contents : CGC header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_CGC_H +#define R_PDL_CGC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_CGC_Set( + uint32_t, + uint32_t, + uint32_t, + uint32_t, + uint16_t +); + +bool R_CGC_Control( + uint16_t +); + +bool R_CGC_GetStatus( + uint8_t * +); + +/* BCLK pin putput control */ +#define PDL_CGC_BCLK_DISABLE 0x0001u +#define PDL_CGC_BCLK_DIV_1 0x0002u +#define PDL_CGC_BCLK_DIV_2 0x0004u +#define PDL_CGC_BCLK_HIGH 0x0008u + +/* SDCLK pin putput control */ +#define PDL_CGC_SDCLK_DISABLE 0x0010u +#define PDL_CGC_SDCLK_ENABLE 0x0020u + +/* Oscillation Stop Detection control */ +#define PDL_CGC_OSC_STOP_ENABLE 0x0040u +#define PDL_CGC_OSC_STOP_DISABLE 0x0080u + +/* Sub-clock oscillator control */ +#define PDL_CGC_SUB_CLOCK_ENABLE 0x0100u +#define PDL_CGC_SUB_CLOCK_DISABLE 0x0200u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_cgc_rx62nxx.h b/bsp/rx/RPDL/r_pdl_cgc_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..33d85f2f55ff8a67ce05335d3fe4c4d51dfd7565 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_cgc_rx62nxx.h @@ -0,0 +1,55 @@ +/*""FILE COMMENT""******************************************************* +* System Name : CGC API for RX62Nxx +* File Name : r_pdl_cgc_RX62Nxx.h +* Version : 1.02 +* Contents : CGC header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_CGC_RX62Nxx_H +#define R_PDL_CGC_RX62Nxx_H + +/* Library prototypes */ +bool R_CGC_SetAll( + const uint32_t, + const uint32_t, + const uint32_t, + const uint32_t, + const uint16_t +); + +bool R_CGC_ControlAll( + const uint16_t +); + +bool R_CGC_GetStatusAll( + volatile uint8_t * const +); + +/* Macro definitions */ + +#define R_CGC_Set(a, b, c, d, e) \ +R_CGC_SetAll( (a), (b), (c), (d), (e) ) + +#define R_CGC_Control(a) \ +R_CGC_ControlAll( (a) ) + +#define R_CGC_GetStatus(a) \ +R_CGC_GetStatusAll( (a) ) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_cmt.h b/bsp/rx/RPDL/r_pdl_cmt.h new file mode 100644 index 0000000000000000000000000000000000000000..6cf9ef1be951435c905cd912d66bb8f44440bf2e --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_cmt.h @@ -0,0 +1,83 @@ +/*""FILE COMMENT""******************************************************* +* System Name : CMT API for RX62Nxx +* File Name : r_pdl_cmt.h +* Version : 1.02 +* Contents : CMT API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_CMT_H +#define R_PDL_CMT_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_CMT_Create( + uint8_t, + uint16_t, + float, + void *, + uint8_t +); +bool R_CMT_CreateOneShot( + uint8_t, + uint16_t, + float, + void *, + uint8_t +); +bool R_CMT_Destroy( + uint8_t +); +bool R_CMT_Control( + uint8_t, + uint16_t, + float +); +bool R_CMT_Read( + uint8_t, + uint8_t *, + uint16_t * +); + +/* Timer counter control */ +#define PDL_CMT_STOP 0x0001u +#define PDL_CMT_START 0x0002u + +/* Calculation selection */ +#define PDL_CMT_PERIOD 0x0004u +#define PDL_CMT_FREQUENCY 0x0008u + +/* CPU control */ +#define PDL_CMT_CPU_ON 0x0010u +#define PDL_CMT_CPU_OFF 0x0020u + +/* DMAC / DTC trigger control */ +#define PDL_CMT_DMAC_DTC_TRIGGER_DISABLE 0x0040u +#define PDL_CMT_DMAC_TRIGGER_ENABLE 0x0080u +#define PDL_CMT_DTC_TRIGGER_ENABLE 0x0100u + +/* Direct register control */ +#define PDL_CMT_CONSTANT 0x0200u +#define PDL_CMT_COUNTER 0x0400u +#define PDL_CMT_PCLK_DIV_8 0x0800u +#define PDL_CMT_PCLK_DIV_32 0x1000u +#define PDL_CMT_PCLK_DIV_128 0x2000u +#define PDL_CMT_PCLK_DIV_512 0x4000u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_cmt_rx62nxx.h b/bsp/rx/RPDL/r_pdl_cmt_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..ae425dca0c505923a738098b902393072685b3eb --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_cmt_rx62nxx.h @@ -0,0 +1,104 @@ +/*""FILE COMMENT""******************************************************* +* System Name : CMT API for RX62Nxx +* File Name : r_pdl_cmt_RX62Nxx.h +* Version : 1.02 +* Contents : CMT API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_CMT_RX62Nxx_H +#define R_PDL_CMT_RX62Nxx_H + +#define CMT_UNITS 2 +#define CMT_CHANNELS_PER_UNIT 2 +#define CMT_CHANNELS (uint8_t)(CMT_UNITS * CMT_CHANNELS_PER_UNIT) + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_CMT_callback_func[CMT_CHANNELS]; + +/* Global variables */ +extern volatile uint8_t rpdl_CMT_one_shot[CMT_CHANNELS]; + +/* Library prototypes */ +bool R_CMT_CreateAll( + const uint8_t, + const uint16_t, + const float, + VoidCallBackFunc const, + const uint8_t +); +bool R_CMT_CreateOneShotAll( + const uint8_t, + const uint16_t, + const float, + VoidCallBackFunc const, + const uint8_t +); +bool R_CMT_DestroyAll( + const uint8_t +); +bool R_CMT_ControlAll( + const uint8_t, + const uint16_t, + const float +); +bool R_CMT_ReadAll( + const uint8_t, + volatile uint8_t * const, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_CMT_Create(a, b, c, d, e) \ +( \ +( ( ((a) < CMT_CHANNELS ) && ((e) <= IPL_MAX) ) ) ? \ +R_CMT_CreateAll( (a), (b), (c), (d), (e) ) : \ +ReturnFalse() \ +) + +#define R_CMT_CreateOneShot(a, b, c, d, e) \ +( \ +( ( ((a) < CMT_CHANNELS ) && ((e) <= IPL_MAX) ) ) ? \ +R_CMT_CreateOneShotAll( (a), (b), (c), (d), (e) ) : \ +ReturnFalse() \ +) + +#define R_CMT_Destroy(a) \ +( \ +( (a) < CMT_UNITS ) ? \ +R_CMT_DestroyAll( (a) ) : \ +ReturnFalse() \ +) + +#define R_CMT_Control(a, b, c) \ +( \ +( (a) < CMT_CHANNELS ) ? \ +R_CMT_ControlAll( (a), (b), (c) ) : \ +ReturnFalse() \ +) + +#define R_CMT_Read(a, b, c) \ +( \ +( (a) < CMT_CHANNELS ) ? \ +R_CMT_ReadAll( (a), (b), (c) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_common_defs_rx62nxx.h b/bsp/rx/RPDL/r_pdl_common_defs_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..13fcd8296e1c51f6ca6d6ee4062fca02eb27f870 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_common_defs_rx62nxx.h @@ -0,0 +1,315 @@ +/*""FILE COMMENT""******************************************************* +* System Name : API for RX62Nxx +* File Name : r_pdl_common_defs_RX62Nxx.h +* Version : 1.02 +* Contents : API common definitions +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_COMMON_DEFS_RX62Nxx_H +#define R_PDL_COMMON_DEFS_RX62Nxx_H + +#include +#include +#include +#include +#include + +/* Callback function type */ +typedef void (* VoidCallBackFunc)(void); + +/* The supported MCU group */ +#define PDL_MCU_GROUP RX62N + +/* The highest interrupt priority level */ +#define IPL_MAX 15 + +/* Use the I/O register area to indicate that a callback function pointer is not to be used */ +#define PDL_NO_FUNC (VoidCallBackFunc)0x00080000ul +/* Use the ROM area to indicate that a data pointer is not to be used */ +#define PDL_NO_PTR (void *)0xFFFFFFFCul +/* When no parameters options are required */ +#define PDL_NO_DATA 0 + +/* Shared global variables */ +extern volatile uint32_t rpdl_CGC_f_pclk; +extern volatile uint32_t rpdl_CGC_f_iclk; +extern volatile uint32_t rpdl_CGC_f_bclk; +extern volatile uint8_t rpdl_INTC_brk_command; +extern volatile uint8_t rpdl_INTC_brk_data8; +extern volatile uint32_t rpdl_INTC_saved_isp; + +/* Shared functions */ +uint8_t rpdl_DMAC_get_channel(const uint8_t); + +/* Utility functions */ +uint8_t rpdl_BCD8_to_dec(const uint8_t); +uint16_t rpdl_BCD16_to_dec(const uint16_t); +bool rpdl_common_BCD8_check(const uint8_t); +bool rpdl_common_BCD16_check(const uint16_t); +bool rpdl_common_BCD32_check(const uint32_t); + +/* BRK handler command options */ +typedef enum { + BRK_NO_COMMAND, + BRK_START_ADC_10, + BRK_START_ADC_10_AND_SLEEP, + BRK_SLEEP, + BRK_ALL_MODULE_CLOCK_STOP, + BRK_STANDBY, + BRK_DEEP_STANDBY, + BRK_LOAD_FINTV_REGISTER, + BRK_WRITE_IPL, + BRK_CMT_START, + BRK_CMT_STOP +} brk_commands; + +/* Bit definitions */ +#define BIT_0 0x00000001ul +#define BIT_1 0x00000002ul +#define BIT_2 0x00000004ul +#define BIT_3 0x00000008ul +#define BIT_4 0x00000010ul +#define BIT_5 0x00000020ul +#define BIT_6 0x00000040ul +#define BIT_7 0x00000080ul +#define BIT_8 0x00000100ul +#define BIT_9 0x00000200ul +#define BIT_10 0x00000400ul +#define BIT_11 0x00000800ul +#define BIT_12 0x00001000ul +#define BIT_13 0x00002000ul +#define BIT_14 0x00004000ul +#define BIT_15 0x00008000ul +#define BIT_16 0x00010000ul +#define BIT_17 0x00020000ul +#define BIT_18 0x00040000ul +#define BIT_19 0x00080000ul +#define BIT_20 0x00100000ul +#define BIT_21 0x00200000ul +#define BIT_22 0x00400000ul +#define BIT_23 0x00800000ul +#define BIT_24 0x01000000ul +#define BIT_25 0x02000000ul +#define BIT_26 0x04000000ul +#define BIT_27 0x08000000ul +#define BIT_28 0x10000000ul +#define BIT_29 0x20000000ul +#define BIT_30 0x40000000ul +#define BIT_31 0x80000000ul + +#define INV_BIT_0 0xFFFFFFFEul +#define INV_BIT_1 0xFFFFFFFDul +#define INV_BIT_2 0xFFFFFFFBul +#define INV_BIT_3 0xFFFFFFF7ul +#define INV_BIT_4 0xFFFFFFEFul +#define INV_BIT_5 0xFFFFFFDFul +#define INV_BIT_6 0xFFFFFFBFul +#define INV_BIT_7 0xFFFFFF7Ful +#define INV_BIT_8 0xFFFFFEFFul +#define INV_BIT_9 0xFFFFFDFFul +#define INV_BIT_10 0xFFFFFBFFul +#define INV_BIT_11 0xFFFFF7FFul +#define INV_BIT_12 0xFFFFEFFFul +#define INV_BIT_13 0xFFFFDFFFul +#define INV_BIT_14 0xFFFFBFFFul +#define INV_BIT_15 0xFFFF7FFFul +#define INV_BIT_16 0xFFFEFFFFul +#define INV_BIT_17 0xFFFDFFFFul +#define INV_BIT_18 0xFFFBFFFFul +#define INV_BIT_19 0xFFF7FFFFul +#define INV_BIT_20 0xFFEFFFFFul +#define INV_BIT_21 0xFFDFFFFFul +#define INV_BIT_22 0xFFBFFFFFul +#define INV_BIT_23 0xFF7FFFFFul +#define INV_BIT_24 0xFEFFFFFFul +#define INV_BIT_25 0xFDFFFFFFul +#define INV_BIT_26 0xFBFFFFFFul +#define INV_BIT_27 0xF7FFFFFFul +#define INV_BIT_28 0xEFFFFFFFul +#define INV_BIT_29 0xDFFFFFFFul +#define INV_BIT_30 0xBFFFFFFFul +#define INV_BIT_31 0x7FFFFFFFul + +/* Interrupt vector numbers */ +#define PDL_INTC_VECTOR_BUSERR VECT_BSC_BUSERR +#define PDL_INTC_VECTOR_FIFERR VECT_FCU_FIFERR +#define PDL_INTC_VECTOR_FRDYI VECT_FCU_FRDYI +#define PDL_INTC_VECTOR_SWINT VECT_ICU_SWINT +#define PDL_INTC_VECTOR_CMT0 VECT_CMT0_CMI0 +#define PDL_INTC_VECTOR_CMT1 VECT_CMT1_CMI1 +#define PDL_INTC_VECTOR_CMT2 VECT_CMT2_CMI2 +#define PDL_INTC_VECTOR_CMT3 VECT_CMT3_CMI3 +#define PDL_INTC_VECTOR_EINT VECT_ETHER_EINT +#define PDL_INTC_VECTOR_D0FIFO0 VECT_USB0_D0FIFO0 +#define PDL_INTC_VECTOR_D1FIFO0 VECT_USB0_D1FIFO0 +#define PDL_INTC_VECTOR_USBI0 VECT_USB0_USBI0 +#define PDL_INTC_VECTOR_USBR0 VECT_USB_USBR0 +#define PDL_INTC_VECTOR_D0FIFO1 VECT_USB1_D0FIFO1 +#define PDL_INTC_VECTOR_D1FIFO1 VECT_USB1_D1FIFO1 +#define PDL_INTC_VECTOR_USBI1 VECT_USB1_USBI1 +#define PDL_INTC_VECTOR_USBR1 VECT_USB_USBR1 +#define PDL_INTC_VECTOR_SPEI0 VECT_RSPI0_SPEI0 +#define PDL_INTC_VECTOR_SPRI0 VECT_RSPI0_SPRI0 +#define PDL_INTC_VECTOR_SPTI0 VECT_RSPI0_SPTI0 +#define PDL_INTC_VECTOR_SPII0 VECT_RSPI0_SPII0 +#define PDL_INTC_VECTOR_SPEI1 VECT_RSPI1_SPEI1 +#define PDL_INTC_VECTOR_SPRI1 VECT_RSPI1_SPRI1 +#define PDL_INTC_VECTOR_SPTI1 VECT_RSPI1_SPTI1 +#define PDL_INTC_VECTOR_SPII1 VECT_RSPI1_SPII1 +#define PDL_INTC_VECTOR_ERS0 VECT_CAN0_ERS0 +#define PDL_INTC_VECTOR_RXF0 VECT_CAN0_RXF0 +#define PDL_INTC_VECTOR_TXF0 VECT_CAN0_TXF0 +#define PDL_INTC_VECTOR_RXM0 VECT_CAN0_RXM0 +#define PDL_INTC_VECTOR_TXM0 VECT_CAN0_TXM0 +#define PDL_INTC_VECTOR_PRD VECT_RTC_PRD +#define PDL_INTC_VECTOR_CUP VECT_RTC_CUP +#define PDL_INTC_VECTOR_ALM VECT_RTC_ALM +#define PDL_INTC_VECTOR_IRQ0 VECT_ICU_IRQ0 +#define PDL_INTC_VECTOR_IRQ1 VECT_ICU_IRQ1 +#define PDL_INTC_VECTOR_IRQ2 VECT_ICU_IRQ2 +#define PDL_INTC_VECTOR_IRQ3 VECT_ICU_IRQ3 +#define PDL_INTC_VECTOR_IRQ4 VECT_ICU_IRQ4 +#define PDL_INTC_VECTOR_IRQ5 VECT_ICU_IRQ5 +#define PDL_INTC_VECTOR_IRQ6 VECT_ICU_IRQ6 +#define PDL_INTC_VECTOR_IRQ7 VECT_ICU_IRQ7 +#define PDL_INTC_VECTOR_IRQ8 VECT_ICU_IRQ8 +#define PDL_INTC_VECTOR_IRQ9 VECT_ICU_IRQ9 +#define PDL_INTC_VECTOR_IRQ10 VECT_ICU_IRQ10 +#define PDL_INTC_VECTOR_IRQ11 VECT_ICU_IRQ11 +#define PDL_INTC_VECTOR_IRQ12 VECT_ICU_IRQ12 +#define PDL_INTC_VECTOR_IRQ13 VECT_ICU_IRQ13 +#define PDL_INTC_VECTOR_IRQ14 VECT_ICU_IRQ14 +#define PDL_INTC_VECTOR_IRQ15 VECT_ICU_IRQ15 +#define PDL_INTC_VECTOR_WOVI VECT_WDT_WOVI +#define PDL_INTC_VECTOR_ADI0 VECT_AD0_ADI0 +#define PDL_INTC_VECTOR_ADI1 VECT_AD1_ADI1 +#define PDL_INTC_VECTOR_ADI12_0 VECT_S12AD_ADI +#define PDL_INTC_VECTOR_TGIA0 VECT_MTU0_TGIA0 +#define PDL_INTC_VECTOR_TGIB0 VECT_MTU0_TGIB0 +#define PDL_INTC_VECTOR_TGIC0 VECT_MTU0_TGIC0 +#define PDL_INTC_VECTOR_TGID0 VECT_MTU0_TGID0 +#define PDL_INTC_VECTOR_TCIV0 VECT_MTU0_TCIV0 +#define PDL_INTC_VECTOR_TGIE0 VECT_MTU0_TGIE0 +#define PDL_INTC_VECTOR_TGIF0 VECT_MTU0_TGIF0 +#define PDL_INTC_VECTOR_TGIA1 VECT_MTU1_TGIA1 +#define PDL_INTC_VECTOR_TGIB1 VECT_MTU1_TGIB1 +#define PDL_INTC_VECTOR_TCIV1 VECT_MTU1_TCIV1 +#define PDL_INTC_VECTOR_TCIU1 VECT_MTU1_TCIU1 +#define PDL_INTC_VECTOR_TGIA2 VECT_MTU2_TGIA2 +#define PDL_INTC_VECTOR_TGIB2 VECT_MTU2_TGIB2 +#define PDL_INTC_VECTOR_TCIV2 VECT_MTU2_TCIV2 +#define PDL_INTC_VECTOR_TCIU2 VECT_MTU2_TCIU2 +#define PDL_INTC_VECTOR_TGIA3 VECT_MTU3_TGIA3 +#define PDL_INTC_VECTOR_TGIB3 VECT_MTU3_TGIB3 +#define PDL_INTC_VECTOR_TGIC3 VECT_MTU3_TGIC3 +#define PDL_INTC_VECTOR_TGID3 VECT_MTU3_TGID3 +#define PDL_INTC_VECTOR_TCIV3 VECT_MTU3_TCIV3 +#define PDL_INTC_VECTOR_TGIA4 VECT_MTU4_TGIA4 +#define PDL_INTC_VECTOR_TGIB4 VECT_MTU4_TGIB4 +#define PDL_INTC_VECTOR_TGIC4 VECT_MTU4_TGIC4 +#define PDL_INTC_VECTOR_TGID4 VECT_MTU4_TGID4 +#define PDL_INTC_VECTOR_TCIV4 VECT_MTU4_TCIV4 +#define PDL_INTC_VECTOR_TGIU5 VECT_MTU5_TGIU5 +#define PDL_INTC_VECTOR_TGIV5 VECT_MTU5_TGIV5 +#define PDL_INTC_VECTOR_TGIW5 VECT_MTU5_TGIW5 +#define PDL_INTC_VECTOR_TGIA6 VECT_MTU6_TGIA6 +#define PDL_INTC_VECTOR_TGIB6 VECT_MTU6_TGIB6 +#define PDL_INTC_VECTOR_TGIC6 VECT_MTU6_TGIC6 +#define PDL_INTC_VECTOR_TGID6 VECT_MTU6_TGID6 +#define PDL_INTC_VECTOR_TCIV6 VECT_MTU6_TCIV6 +#define PDL_INTC_VECTOR_TGIE6 VECT_MTU6_TGIE6 +#define PDL_INTC_VECTOR_TGIF6 VECT_MTU6_TGIF6 +#define PDL_INTC_VECTOR_TGIA7 VECT_MTU7_TGIA7 +#define PDL_INTC_VECTOR_TGIB7 VECT_MTU7_TGIB7 +#define PDL_INTC_VECTOR_TCIV7 VECT_MTU7_TCIV7 +#define PDL_INTC_VECTOR_TCIU7 VECT_MTU7_TCIU7 +#define PDL_INTC_VECTOR_TGIA8 VECT_MTU8_TGIA8 +#define PDL_INTC_VECTOR_TGIB8 VECT_MTU8_TGIB8 +#define PDL_INTC_VECTOR_TCIV8 VECT_MTU8_TCIV8 +#define PDL_INTC_VECTOR_TCIU8 VECT_MTU8_TCIU8 +#define PDL_INTC_VECTOR_TGIA9 VECT_MTU9_TGIA9 +#define PDL_INTC_VECTOR_TGIB9 VECT_MTU9_TGIB9 +#define PDL_INTC_VECTOR_TGIC9 VECT_MTU9_TGIC9 +#define PDL_INTC_VECTOR_TGID9 VECT_MTU9_TGID9 +#define PDL_INTC_VECTOR_TCIV9 VECT_MTU9_TCIV9 +#define PDL_INTC_VECTOR_TGIA10 VECT_MTU10_TGIA10 +#define PDL_INTC_VECTOR_TGIB10 VECT_MTU10_TGIB10 +#define PDL_INTC_VECTOR_TGIC10 VECT_MTU10_TGIC10 +#define PDL_INTC_VECTOR_TGID10 VECT_MTU10_TGID10 +#define PDL_INTC_VECTOR_TCIV10 VECT_MTU10_TCIV10 +#define PDL_INTC_VECTOR_TGIU11 VECT_MTU11_TGIU11 +#define PDL_INTC_VECTOR_TGIV11 VECT_MTU11_TGIV11 +#define PDL_INTC_VECTOR_TGIW11 VECT_MTU11_TGIW11 +#define PDL_INTC_VECTOR_OEI1 VECT_POE_OEI1 +#define PDL_INTC_VECTOR_OEI2 VECT_POE_OEI2 +#define PDL_INTC_VECTOR_OEI3 VECT_POE_OEI3 +#define PDL_INTC_VECTOR_OEI4 VECT_POE_OEI4 +#define PDL_INTC_VECTOR_CMIA0 VECT_TMR0_CMIA0 +#define PDL_INTC_VECTOR_CMIB0 VECT_TMR0_CMIB0 +#define PDL_INTC_VECTOR_OVI0 VECT_TMR0_OVI0 +#define PDL_INTC_VECTOR_CMIA1 VECT_TMR1_CMIA1 +#define PDL_INTC_VECTOR_CMIB1 VECT_TMR1_CMIB1 +#define PDL_INTC_VECTOR_OVI1 VECT_TMR1_OVI1 +#define PDL_INTC_VECTOR_CMIA2 VECT_TMR2_CMIA2 +#define PDL_INTC_VECTOR_CMIB2 VECT_TMR2_CMIB2 +#define PDL_INTC_VECTOR_OVI2 VECT_TMR2_OVI2 +#define PDL_INTC_VECTOR_CMIA3 VECT_TMR3_CMIA3 +#define PDL_INTC_VECTOR_CMIB3 VECT_TMR3_CMIB3 +#define PDL_INTC_VECTOR_OVI3 VECT_TMR3_OVI3 +#define PDL_INTC_VECTOR_DMAC0I VECT_DMAC_DMAC0I +#define PDL_INTC_VECTOR_DMAC1I VECT_DMAC_DMAC1I +#define PDL_INTC_VECTOR_DMAC2I VECT_DMAC_DMAC2I +#define PDL_INTC_VECTOR_DMAC3I VECT_DMAC_DMAC3I +#define PDL_INTC_VECTOR_EXDMAC0I VECT_EXDMAC_EXDMAC0I +#define PDL_INTC_VECTOR_EXDMAC1I VECT_EXDMAC_EXDMAC1I +#define PDL_INTC_VECTOR_ERI0 VECT_SCI0_ERI0 +#define PDL_INTC_VECTOR_RXI0 VECT_SCI0_RXI0 +#define PDL_INTC_VECTOR_TXI0 VECT_SCI0_TXI0 +#define PDL_INTC_VECTOR_TEI0 VECT_SCI0_TEI0 +#define PDL_INTC_VECTOR_ERI1 VECT_SCI1_ERI1 +#define PDL_INTC_VECTOR_RXI1 VECT_SCI1_RXI1 +#define PDL_INTC_VECTOR_TXI1 VECT_SCI1_TXI1 +#define PDL_INTC_VECTOR_TEI1 VECT_SCI1_TEI1 +#define PDL_INTC_VECTOR_ERI2 VECT_SCI2_ERI2 +#define PDL_INTC_VECTOR_RXI2 VECT_SCI2_RXI2 +#define PDL_INTC_VECTOR_TXI2 VECT_SCI2_TXI2 +#define PDL_INTC_VECTOR_TEI2 VECT_SCI2_TEI2 +#define PDL_INTC_VECTOR_ERI3 VECT_SCI3_ERI3 +#define PDL_INTC_VECTOR_RXI3 VECT_SCI3_RXI3 +#define PDL_INTC_VECTOR_TXI3 VECT_SCI3_TXI3 +#define PDL_INTC_VECTOR_TEI3 VECT_SCI3_TEI3 +#define PDL_INTC_VECTOR_ERI5 VECT_SCI5_ERI5 +#define PDL_INTC_VECTOR_RXI5 VECT_SCI5_RXI5 +#define PDL_INTC_VECTOR_TXI5 VECT_SCI5_TXI5 +#define PDL_INTC_VECTOR_TEI5 VECT_SCI5_TEI5 +#define PDL_INTC_VECTOR_ERI6 VECT_SCI6_ERI6 +#define PDL_INTC_VECTOR_RXI6 VECT_SCI6_RXI6 +#define PDL_INTC_VECTOR_TXI6 VECT_SCI6_TXI6 +#define PDL_INTC_VECTOR_TEI6 VECT_SCI6_TEI6 +#define PDL_INTC_VECTOR_ICEEI0 VECT_RIIC0_ICEEI0 +#define PDL_INTC_VECTOR_ICRXI0 VECT_RIIC0_ICRXI0 +#define PDL_INTC_VECTOR_ICTXI0 VECT_RIIC0_ICTXI0 +#define PDL_INTC_VECTOR_ICTEI0 VECT_RIIC0_ICTEI0 +#define PDL_INTC_VECTOR_ICEEI1 VECT_RIIC1_ICEEI1 +#define PDL_INTC_VECTOR_ICRXI1 VECT_RIIC1_ICRXI1 +#define PDL_INTC_VECTOR_ICTXI1 VECT_RIIC1_ICTXI1 +#define PDL_INTC_VECTOR_ICTEI1 VECT_RIIC1_ICTEI1 + +#endif + +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_crc.h b/bsp/rx/RPDL/r_pdl_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..2df13298122c36ab70edc63f0f7c25f3e1962964 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_crc.h @@ -0,0 +1,57 @@ +/*""FILE COMMENT""******************************************************* +* System Name : CRC calculator API for RX62Nxx +* File Name : r_pdl_crc.h +* Version : 1.02 +* Contents : CRC function prototypes +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_CRC_H +#define R_PDL_CRC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_CRC_Create( + uint8_t +); +bool R_CRC_Destroy( + void +); +bool R_CRC_Write( + uint8_t +); +bool R_CRC_Read( + uint8_t, + uint16_t * +); + +/* Polynomial selection */ +#define PDL_CRC_POLY_CRC_8 0x01u +#define PDL_CRC_POLY_CRC_16 0x02u +#define PDL_CRC_POLY_CRC_CCITT 0x04u + +/* Bit order */ +#define PDL_CRC_LSB_FIRST 0x08u +#define PDL_CRC_MSB_FIRST 0x10u + +/* Result register clearing */ +#define PDL_CRC_CLEAR_RESULT 0x01u +#define PDL_CRC_RETAIN_RESULT 0x02u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_crc_rx62nxx.h b/bsp/rx/RPDL/r_pdl_crc_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..183c489acd09beeb072a6668b0f2078737a6dd28 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_crc_rx62nxx.h @@ -0,0 +1,64 @@ +/*""FILE COMMENT""******************************************************* +* System Name : CRC calculator API for RX62Nxx +* File Name : r_pdl_crc_RX62Nxx.h +* Version : 1.02 +* Contents : CRC header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_CRC_RX62Nxx_H +#define R_PDL_CRC_RX62Nxx_H + +/* Library prototypes */ +bool R_CRC_CreateAll( + const uint8_t +); +bool R_CRC_DestroyAll( + void +); +bool R_CRC_WriteAll( + const uint8_t +); +bool R_CRC_ReadAll( + const uint8_t, + volatile uint16_t * const +); + +/* Macro definitions */ + +#define R_CRC_Create(a) \ +( \ +R_CRC_CreateAll( (a) ) \ +) + +#define R_CRC_Destroy() \ +( \ +R_CRC_DestroyAll() \ +) + +#define R_CRC_Write(a) \ +( \ +R_CRC_WriteAll( (a) ) \ +) + +#define R_CRC_Read(a, b) \ +( \ +R_CRC_ReadAll( (a), (b) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_dac_10.h b/bsp/rx/RPDL/r_pdl_dac_10.h new file mode 100644 index 0000000000000000000000000000000000000000..3c281bd4dd8761200e0e72ff5f31dd8b01b091f7 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_dac_10.h @@ -0,0 +1,52 @@ +/*""FILE COMMENT""******************************************************* +* System Name : DAC API for RX62Nxx +* File Name : r_pdl_dac_10.h +* Version : 1.02 +* Contents : CRC function prototypes +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_DAC_H +#define R_PDL_DAC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_DAC_10_Create( + uint8_t, + uint16_t, + uint16_t +); +bool R_DAC_10_Destroy( + uint8_t +); +bool R_DAC_10_Write( + uint8_t, + uint16_t, + uint16_t +); + +/* Channel selection */ +#define PDL_DAC_10_CHANNEL_0 0x01u +#define PDL_DAC_10_CHANNEL_1 0x02u + +/* Data alignment */ +#define PDL_DAC_10_ALIGN_LEFT 0x04u +#define PDL_DAC_10_ALIGN_RIGHT 0x08u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_dac_10_rx62nxx.h b/bsp/rx/RPDL/r_pdl_dac_10_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..968392e60a4a9c3dd13e46bd1f11ddb3400af937 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_dac_10_rx62nxx.h @@ -0,0 +1,59 @@ +/*""FILE COMMENT""******************************************************* +* System Name : DAC API for RX62Nxx +* File Name : r_pdl_dac_10_RX62Nxx.h +* Version : 1.02 +* Contents : DAC header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_DAC_RX62Nxx_H +#define R_PDL_DAC_RX62Nxx_H + +/* Library prototypes */ +bool R_DAC_10_CreateAll( + const uint8_t, + const uint16_t, + const uint16_t +); +bool R_DAC_10_DestroyAll( + const uint8_t +); +bool R_DAC_10_WriteAll( + const uint8_t, + const uint16_t, + const uint16_t +); + +/* Macro definitions */ + +#define R_DAC_10_Create(a, b, c) \ +( \ +R_DAC_10_CreateAll( (a), (b), (c) ) \ +) + +#define R_DAC_10_Destroy(a) \ +( \ +R_DAC_10_DestroyAll( (a) ) \ +) + +#define R_DAC_10_Write(a, b, c) \ +( \ +R_DAC_10_WriteAll( (a), (b), (c) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_definitions.h b/bsp/rx/RPDL/r_pdl_definitions.h new file mode 100644 index 0000000000000000000000000000000000000000..cc138721080361a38b14f8736d59bc28a7cac25d --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_definitions.h @@ -0,0 +1,59 @@ +/*""FILE COMMENT""******************************************************* +* System Name : PDL driver API +* File Name : r_pdl_definitions.h +* Version : 1.02 +* Contents : API headers for RX62N (100-pin package) +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_DEFS_H +#define R_PDL_DEFS_H + +#define PDL_VERSION 0x0102u /* v01.02 in BCD format */ +#define DEVICE_PACKAGE_LQFP_100 + +/* Peripiherals that are common to all device packages */ +#include "r_pdl_adc_10_RX62Nxx.h" +#include "r_pdl_adc_12_RX62Nxx.h" +#include "r_pdl_bsc_RX62Nxx.h" +#include "r_pdl_cgc_RX62Nxx.h" +#include "r_pdl_cmt_RX62Nxx.h" +#include "r_pdl_crc_RX62Nxx.h" +#include "r_pdl_dac_10_RX62Nxx.h" +#include "r_pdl_dmac_RX62Nxx.h" +#include "r_pdl_dtc_RX62Nxx.h" +#include "r_pdl_intc_RX62Nxx.h" +#include "r_pdl_iwdt_RX62Nxx.h" +#include "r_pdl_lpc_RX62Nxx.h" +#include "r_pdl_lvd_RX62Nxx.h" +#include "r_pdl_mcu_RX62Nxx.h" +#include "r_pdl_mtu2_RX62Nxx.h" +#include "r_pdl_pfc_RX62Nxx.h" +#include "r_pdl_poe_RX62Nxx.h" +#include "r_pdl_ppg_RX62Nxx.h" +#include "r_pdl_rtc_RX62Nxx.h" +#include "r_pdl_sci_RX62Nxx.h" +#include "r_pdl_spi_RX62Nxx.h" +#include "r_pdl_tmr_RX62Nxx.h" +#include "r_pdl_wdt_RX62Nxx.h" + +/* Peripiherals that are device package-dependent */ +#include "r_pdl_iic_RX62NxFP.h" +#include "r_pdl_io_port_RX62NxFP.h" + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_dmac.h b/bsp/rx/RPDL/r_pdl_dmac.h new file mode 100644 index 0000000000000000000000000000000000000000..818f0b8d84edf0038ac816b356456a744ae47dd5 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_dmac.h @@ -0,0 +1,174 @@ +/*""FILE COMMENT""******************************************************* +* System Name : DMAC API for RX62Nxx +* File Name : r_pdl_dmac.h +* Version : 1.02 +* Contents : DMAC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_DMAC_H +#define R_PDL_DMAC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_DMAC_Create( + uint8_t, + uint32_t, + uint8_t, + void *, + void *, + uint16_t, + uint16_t, + int32_t, + uint32_t, + uint32_t, + void *, + uint8_t +); +bool R_DMAC_Destroy( + uint8_t +); +bool R_DMAC_Control( + uint8_t, + uint16_t, + void *, + void *, + uint16_t, + uint16_t, + int32_t, + uint32_t, + uint32_t +); +bool R_DMAC_GetStatus( + uint8_t, + uint8_t *, + uint32_t *, + uint32_t *, + uint16_t *, + uint16_t * +); + +/* Transfer mode selection */ +#define PDL_DMAC_NORMAL 0x00000001ul +#define PDL_DMAC_REPEAT 0x00000002ul +#define PDL_DMAC_BLOCK 0x00000004ul +#define PDL_DMAC_SOURCE 0x00000008ul +#define PDL_DMAC_DESTINATION 0x00000010ul + +/* Address addition direction selection */ +#define PDL_DMAC_SOURCE_ADDRESS_FIXED 0x00000020ul +#define PDL_DMAC_SOURCE_ADDRESS_PLUS 0x00000040ul +#define PDL_DMAC_SOURCE_ADDRESS_MINUS 0x00000080ul +#define PDL_DMAC_SOURCE_ADDRESS_OFFSET 0x00000100ul +#define PDL_DMAC_DESTINATION_ADDRESS_FIXED 0x00000200ul +#define PDL_DMAC_DESTINATION_ADDRESS_PLUS 0x00000400ul +#define PDL_DMAC_DESTINATION_ADDRESS_MINUS 0x00000800ul +#define PDL_DMAC_DESTINATION_ADDRESS_OFFSET 0x00001000ul + +/* Transfer data size */ +#define PDL_DMAC_SIZE_8 0x00002000ul +#define PDL_DMAC_SIZE_16 0x00004000ul +#define PDL_DMAC_SIZE_32 0x00008000ul + +/* Interrupt generation */ +#define PDL_DMAC_IRQ_END 0x00010000ul +#define PDL_DMAC_IRQ_ESCAPE_END 0x00020000ul +#define PDL_DMAC_IRQ_REPEAT_SIZE_END 0x00040000ul +#define PDL_DMAC_IRQ_EXT_SOURCE 0x00080000ul +#define PDL_DMAC_IRQ_EXT_DESTINATION 0x00100000ul + +/* Start trigger forwarding */ +#define PDL_DMAC_TRIGGER_CLEAR 0x00200000ul +#define PDL_DMAC_TRIGGER_FORWARD 0x00400000ul + +/* DTC trigger control */ +#define PDL_DMAC_DTC_TRIGGER_DISABLE 0x00800000ul +#define PDL_DMAC_DTC_TRIGGER_ENABLE 0x01000000ul + +/* DMAC activation source */ +#define PDL_DMAC_TRIGGER_SW 0x00u +#define PDL_DMAC_TRIGGER_CMT0 VECT_CMT0_CMI0 +#define PDL_DMAC_TRIGGER_CMT1 VECT_CMT1_CMI1 +#define PDL_DMAC_TRIGGER_CMT2 VECT_CMT2_CMI2 +#define PDL_DMAC_TRIGGER_CMT3 VECT_CMT3_CMI3 +#define PDL_DMAC_TRIGGER_USB0_D0 VECT_USB0_D0FIFO0 +#define PDL_DMAC_TRIGGER_USB0_D1 VECT_USB0_D1FIFO0 +#define PDL_DMAC_TRIGGER_USB1_D0 VECT_USB1_D0FIFO1 +#define PDL_DMAC_TRIGGER_USB1_D1 VECT_USB1_D1FIFO1 +#define PDL_DMAC_TRIGGER_SPI0_RX VECT_RSPI0_SPRI0 +#define PDL_DMAC_TRIGGER_SPI0_TX VECT_RSPI0_SPTI0 +#define PDL_DMAC_TRIGGER_SPI1_RX VECT_RSPI1_SPRI1 +#define PDL_DMAC_TRIGGER_SPI1_TX VECT_RSPI1_SPTI1 +#define PDL_DMAC_TRIGGER_IRQ0 VECT_ICU_IRQ0 +#define PDL_DMAC_TRIGGER_IRQ1 VECT_ICU_IRQ1 +#define PDL_DMAC_TRIGGER_IRQ2 VECT_ICU_IRQ2 +#define PDL_DMAC_TRIGGER_IRQ3 VECT_ICU_IRQ3 +#define PDL_DMAC_TRIGGER_ADC10_0 VECT_AD0_ADI0 +#define PDL_DMAC_TRIGGER_ADC10_1 VECT_AD1_ADI1 +#define PDL_DMAC_TRIGGER_ADC12 VECT_S12AD_ADI +#define PDL_DMAC_TRIGGER_MTU0 VECT_MTU0_TGIA0 +#define PDL_DMAC_TRIGGER_MTU1 VECT_MTU1_TGIA1 +#define PDL_DMAC_TRIGGER_MTU2 VECT_MTU2_TGIA2 +#define PDL_DMAC_TRIGGER_MTU3 VECT_MTU3_TGIA3 +#define PDL_DMAC_TRIGGER_MTU4 VECT_MTU4_TGIA4 +#define PDL_DMAC_TRIGGER_MTU6 VECT_MTU6_TGIA6 +#define PDL_DMAC_TRIGGER_MTU7 VECT_MTU7_TGIA7 +#define PDL_DMAC_TRIGGER_MTU8 VECT_MTU8_TGIA8 +#define PDL_DMAC_TRIGGER_MTU9 VECT_MTU9_TGIA9 +#define PDL_DMAC_TRIGGER_MTU10 VECT_MTU10_TGIA10 +#define PDL_DMAC_TRIGGER_SCI0_RX VECT_SCI0_RXI0 +#define PDL_DMAC_TRIGGER_SCI0_TX VECT_SCI0_TXI0 +#define PDL_DMAC_TRIGGER_SCI1_RX VECT_SCI1_RXI1 +#define PDL_DMAC_TRIGGER_SCI1_TX VECT_SCI1_TXI1 +#define PDL_DMAC_TRIGGER_SCI2_RX VECT_SCI2_RXI2 +#define PDL_DMAC_TRIGGER_SCI2_TX VECT_SCI2_TXI2 +#define PDL_DMAC_TRIGGER_SCI3_RX VECT_SCI3_RXI3 +#define PDL_DMAC_TRIGGER_SCI3_TX VECT_SCI3_TXI3 +#define PDL_DMAC_TRIGGER_SCI5_RX VECT_SCI5_RXI5 +#define PDL_DMAC_TRIGGER_SCI5_TX VECT_SCI5_TXI5 +#define PDL_DMAC_TRIGGER_SCI6_RX VECT_SCI6_RXI6 +#define PDL_DMAC_TRIGGER_SCI6_TX VECT_SCI6_TXI6 +#define PDL_DMAC_TRIGGER_IIC0_RX VECT_RIIC0_ICRXI0 +#define PDL_DMAC_TRIGGER_IIC0_TX VECT_RIIC0_ICTXI0 +#define PDL_DMAC_TRIGGER_IIC1_RX VECT_RIIC1_ICRXI1 +#define PDL_DMAC_TRIGGER_IIC1_TX VECT_RIIC1_ICTXI1 + +/* Enable / suspend control */ +#define PDL_DMAC_ENABLE 0x0001u +#define PDL_DMAC_SUSPEND 0x0002u + +/* Software trigger control */ +#define PDL_DMAC_START 0x0004u +#define PDL_DMAC_START_RUN 0x0008u +#define PDL_DMAC_STOP 0x0010u + +/* Transfer end interrupt flag control */ +#define PDL_DMAC_CLEAR_DTIF 0x0020u +#define PDL_DMAC_CLEAR_ESIF 0x0040u + +/* Modify registers selection */ +#define PDL_DMAC_UPDATE_SOURCE 0x0080u +#define PDL_DMAC_UPDATE_DESTINATION 0x0100u +#define PDL_DMAC_UPDATE_COUNT 0x0200u +#define PDL_DMAC_UPDATE_SIZE 0x0400u +#define PDL_DMAC_UPDATE_OFFSET 0x0800u +#define PDL_DMAC_UPDATE_REPEAT_SOURCE 0x1000u +#define PDL_DMAC_UPDATE_REPEAT_DESTINATION 0x2000u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_dmac_rx62nxx.h b/bsp/rx/RPDL/r_pdl_dmac_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..3b631ebdaee48c45f3574260bbc790a28ca65a2c --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_dmac_rx62nxx.h @@ -0,0 +1,101 @@ +/*""FILE COMMENT""******************************************************* +* System Name : DMAC API for RX62Nxx +* File Name : r_pdl_dmac_RX62Nxx.h +* Version : 1.02 +* Contents : DMAC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_DMAC_RX62Nxx_H +#define R_PDL_DMAC_RX62Nxx_H + +#define DMAC_CHANNELS 4 + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_DMAC_callback_func[]; + +/* Library prototypes */ +bool R_DMAC_CreateAll( + const uint8_t, + const uint32_t, + const uint8_t, + volatile const void * const, + volatile const void * const, + const uint16_t, + const uint16_t, + const int32_t, + const uint32_t, + const uint32_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_DMAC_DestroyAll( + const uint8_t +); +bool R_DMAC_ControlAll( + const uint8_t, + const uint16_t, + volatile const void * const, + volatile const void * const, + const uint16_t, + const uint16_t, + const int32_t, + const uint32_t, + const uint32_t +); +bool R_DMAC_GetStatusAll( + const uint8_t, + volatile uint8_t * const, + volatile uint32_t * const, + volatile uint32_t * const, + volatile uint16_t * const, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_DMAC_Create(a, b, c, d, e, f, g, h, i, j, k, l) \ +( \ +( ( ((a) < DMAC_CHANNELS ) && ((l) <= IPL_MAX) ) ) ? \ +R_DMAC_CreateAll( (a), (b), (c), (d), (e), (f), (g), (h), (i), (j), (k), (l) ) : \ +ReturnFalse() \ +) + +#define R_DMAC_Control(a, b, c, d, e, f, g, h, i) \ +( \ +( ((a) < DMAC_CHANNELS) ) ? \ +R_DMAC_ControlAll( (a), (b), (c), (d), (e), (f), (g), (h), (i) ) : \ +ReturnFalse() \ +) + +#define R_DMAC_GetStatus(a, b, c, d, e, f) \ +( \ +( ((a) < DMAC_CHANNELS) ) ? \ +R_DMAC_GetStatusAll( (a), (b), (c), (d), (e), (f) ) : \ +ReturnFalse() \ +) + +#define R_DMAC_Destroy(a) \ +( \ +( ((a) < DMAC_CHANNELS) ) ? \ +R_DMAC_DestroyAll( (a) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_dtc.h b/bsp/rx/RPDL/r_pdl_dtc.h new file mode 100644 index 0000000000000000000000000000000000000000..810caa0381d0423e970eb9baef3845769fb70dd8 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_dtc.h @@ -0,0 +1,214 @@ +/*""FILE COMMENT""******************************************************* +* System Name : DTC API for RX62N +* File Name : r_pdl_dtc.h +* Version : 1.02 +* Contents : DTC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_DTC_H +#define R_PDL_DTC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_DTC_Set( + uint8_t, + uint32_t * +); +bool R_DTC_Create( + uint32_t, + uint32_t *, + void *, + void *, + uint16_t, + uint8_t +); +bool R_DTC_Destroy( + void +); +bool R_DTC_Control( + uint32_t, + uint32_t *, + void *, + void *, + uint16_t, + uint8_t +); +bool R_DTC_GetStatus( + uint32_t *, + uint16_t *, + uint32_t *, + uint32_t *, + uint16_t *, + uint8_t * +); + +/* Read skip control */ +#define PDL_DTC_READ_SKIP_DISABLE 0x01u +#define PDL_DTC_READ_SKIP_ENABLE 0x02u + +/* Address size control */ +#define PDL_DTC_ADDRESS_FULL 0x04u +#define PDL_DTC_ADDRESS_SHORT 0x08u + +/* Transfer mode selection */ +#define PDL_DTC_NORMAL 0x00000001ul +#define PDL_DTC_REPEAT 0x00000002ul +#define PDL_DTC_BLOCK 0x00000004ul +#define PDL_DTC_SOURCE 0x00000008ul +#define PDL_DTC_DESTINATION 0x00000010ul + +/* Address direction selection */ +#define PDL_DTC_SOURCE_ADDRESS_FIXED 0x00000020ul +#define PDL_DTC_SOURCE_ADDRESS_PLUS 0x00000040ul +#define PDL_DTC_SOURCE_ADDRESS_MINUS 0x00000080ul +#define PDL_DTC_DESTINATION_ADDRESS_FIXED 0x00000100ul +#define PDL_DTC_DESTINATION_ADDRESS_PLUS 0x00000200ul +#define PDL_DTC_DESTINATION_ADDRESS_MINUS 0x00000400ul + +/* Transfer data size */ +#define PDL_DTC_SIZE_8 0x00000800ul +#define PDL_DTC_SIZE_16 0x00001000ul +#define PDL_DTC_SIZE_32 0x00002000ul + +/* Chain transfer control */ +#define PDL_DTC_CHAIN_DISABLE 0x00004000ul +#define PDL_DTC_CHAIN_CONTINUOUS 0x00008000ul +#define PDL_DTC_CHAIN_0 0x00010000ul + +/* Interrupt generation */ +#define PDL_DTC_IRQ_COMPLETE 0x00020000ul +#define PDL_DTC_IRQ_TRANSFER 0x00040000ul + +/* Trigger selection */ +#define PDL_DTC_TRIGGER_CHAIN (uint32_t)(0x00u << 24) +#define PDL_DTC_TRIGGER_SW (uint32_t)(VECT_ICU_SWINT << 24) +#define PDL_DTC_TRIGGER_CMT0 (uint32_t)(VECT_CMT0_CMI0 << 24) +#define PDL_DTC_TRIGGER_CMT1 (uint32_t)(VECT_CMT1_CMI1 << 24) +#define PDL_DTC_TRIGGER_CMT2 (uint32_t)(VECT_CMT2_CMI2 << 24) +#define PDL_DTC_TRIGGER_CMT3 (uint32_t)(VECT_CMT3_CMI3 << 24) +#define PDL_DTC_TRIGGER_USB0_D0 (uint32_t)(VECT_USB0_D0FIFO0 << 24) +#define PDL_DTC_TRIGGER_USB1_D0 (uint32_t)(VECT_USB1_D0FIFO1 << 24) +#define PDL_DTC_TRIGGER_USB0_D1 (uint32_t)(VECT_USB0_D1FIFO0 << 24) +#define PDL_DTC_TRIGGER_USB1_D1 (uint32_t)(VECT_USB1_D1FIFO1 << 24) +#define PDL_DTC_TRIGGER_SPI0_RX (uint32_t)(VECT_RSPI0_SPRI0 << 24) +#define PDL_DTC_TRIGGER_SPI1_RX (uint32_t)(VECT_RSPI1_SPRI1 << 24) +#define PDL_DTC_TRIGGER_SPI0_TX (uint32_t)(VECT_RSPI0_SPTI0 << 24) +#define PDL_DTC_TRIGGER_SPI1_TX (uint32_t)(VECT_RSPI1_SPTI1 << 24) +#define PDL_DTC_TRIGGER_IRQ0 (uint32_t)(VECT_ICU_IRQ0 << 24) +#define PDL_DTC_TRIGGER_IRQ1 (uint32_t)(VECT_ICU_IRQ1 << 24) +#define PDL_DTC_TRIGGER_IRQ2 (uint32_t)(VECT_ICU_IRQ2 << 24) +#define PDL_DTC_TRIGGER_IRQ3 (uint32_t)(VECT_ICU_IRQ3 << 24) +#define PDL_DTC_TRIGGER_IRQ4 (uint32_t)(VECT_ICU_IRQ4 << 24) +#define PDL_DTC_TRIGGER_IRQ5 (uint32_t)(VECT_ICU_IRQ5 << 24) +#define PDL_DTC_TRIGGER_IRQ6 (uint32_t)(VECT_ICU_IRQ6 << 24) +#define PDL_DTC_TRIGGER_IRQ7 (uint32_t)(VECT_ICU_IRQ7 << 24) +#define PDL_DTC_TRIGGER_IRQ8 (uint32_t)(VECT_ICU_IRQ8 << 24) +#define PDL_DTC_TRIGGER_IRQ9 (uint32_t)(VECT_ICU_IRQ9 << 24) +#define PDL_DTC_TRIGGER_IRQ10 (uint32_t)(VECT_ICU_IRQ10 << 24) +#define PDL_DTC_TRIGGER_IRQ11 (uint32_t)(VECT_ICU_IRQ11 << 24) +#define PDL_DTC_TRIGGER_IRQ12 (uint32_t)(VECT_ICU_IRQ12 << 24) +#define PDL_DTC_TRIGGER_IRQ13 (uint32_t)(VECT_ICU_IRQ13 << 24) +#define PDL_DTC_TRIGGER_IRQ14 (uint32_t)(VECT_ICU_IRQ14 << 24) +#define PDL_DTC_TRIGGER_IRQ15 (uint32_t)(VECT_ICU_IRQ15 << 24) +#define PDL_DTC_TRIGGER_ADI0 (uint32_t)(VECT_AD0_ADI0 << 24) +#define PDL_DTC_TRIGGER_ADI1 (uint32_t)(VECT_AD1_ADI1 << 24) +#define PDL_DTC_TRIGGER_ADC12 (uint32_t)(VECT_S12AD_ADI << 24) +#define PDL_DTC_TRIGGER_TGIA0 (uint32_t)(VECT_MTU0_TGIA0 << 24) +#define PDL_DTC_TRIGGER_TGIA1 (uint32_t)(VECT_MTU1_TGIA1 << 24) +#define PDL_DTC_TRIGGER_TGIA2 (uint32_t)(VECT_MTU2_TGIA2 << 24) +#define PDL_DTC_TRIGGER_TGIA3 (uint32_t)(VECT_MTU3_TGIA3 << 24) +#define PDL_DTC_TRIGGER_TGIA4 (uint32_t)(VECT_MTU4_TGIA4 << 24) +#define PDL_DTC_TRIGGER_TGIA6 (uint32_t)(VECT_MTU6_TGIA6 << 24) +#define PDL_DTC_TRIGGER_TGIA7 (uint32_t)(VECT_MTU7_TGIA7 << 24) +#define PDL_DTC_TRIGGER_TGIA8 (uint32_t)(VECT_MTU8_TGIA8 << 24) +#define PDL_DTC_TRIGGER_TGIA9 (uint32_t)(VECT_MTU9_TGIA9 << 24) +#define PDL_DTC_TRIGGER_TGIA10 (uint32_t)(VECT_MTU10_TGIA10 << 24) +#define PDL_DTC_TRIGGER_TGIB0 (uint32_t)(VECT_MTU0_TGIB0 << 24) +#define PDL_DTC_TRIGGER_TGIB1 (uint32_t)(VECT_MTU1_TGIB1 << 24) +#define PDL_DTC_TRIGGER_TGIB2 (uint32_t)(VECT_MTU2_TGIB2 << 24) +#define PDL_DTC_TRIGGER_TGIB3 (uint32_t)(VECT_MTU3_TGIB3 << 24) +#define PDL_DTC_TRIGGER_TGIB4 (uint32_t)(VECT_MTU4_TGIB4 << 24) +#define PDL_DTC_TRIGGER_TGIB6 (uint32_t)(VECT_MTU6_TGIB6 << 24) +#define PDL_DTC_TRIGGER_TGIB7 (uint32_t)(VECT_MTU7_TGIB7 << 24) +#define PDL_DTC_TRIGGER_TGIB8 (uint32_t)(VECT_MTU8_TGIB8 << 24) +#define PDL_DTC_TRIGGER_TGIB9 (uint32_t)(VECT_MTU9_TGIB9 << 24) +#define PDL_DTC_TRIGGER_TGIB10 (uint32_t)(VECT_MTU10_TGIB10 << 24) +#define PDL_DTC_TRIGGER_TGIC0 (uint32_t)(VECT_MTU0_TGIC0 << 24) +#define PDL_DTC_TRIGGER_TGIC3 (uint32_t)(VECT_MTU3_TGIC3 << 24) +#define PDL_DTC_TRIGGER_TGIC4 (uint32_t)(VECT_MTU4_TGIC4 << 24) +#define PDL_DTC_TRIGGER_TGIC6 (uint32_t)(VECT_MTU6_TGIC6 << 24) +#define PDL_DTC_TRIGGER_TGIC9 (uint32_t)(VECT_MTU9_TGIC9 << 24) +#define PDL_DTC_TRIGGER_TGIC10 (uint32_t)(VECT_MTU10_TGIC10 << 24) +#define PDL_DTC_TRIGGER_TGID0 (uint32_t)(VECT_MTU0_TGID0 << 24) +#define PDL_DTC_TRIGGER_TGID3 (uint32_t)(VECT_MTU3_TGID3 << 24) +#define PDL_DTC_TRIGGER_TGID4 (uint32_t)(VECT_MTU4_TGID4 << 24) +#define PDL_DTC_TRIGGER_TGID6 (uint32_t)(VECT_MTU6_TGID6 << 24) +#define PDL_DTC_TRIGGER_TGID9 (uint32_t)(VECT_MTU9_TGID9 << 24) +#define PDL_DTC_TRIGGER_TGID10 (uint32_t)(VECT_MTU10_TGID10 << 24) +#define PDL_DTC_TRIGGER_TGIU5 (uint32_t)(VECT_MTU5_TGIU5 << 24) +#define PDL_DTC_TRIGGER_TGIU11 (uint32_t)(VECT_MTU11_TGIU11 << 24) +#define PDL_DTC_TRIGGER_TGIV5 (uint32_t)(VECT_MTU5_TGIV5 << 24) +#define PDL_DTC_TRIGGER_TGIV11 (uint32_t)(VECT_MTU11_TGIV11 << 24) +#define PDL_DTC_TRIGGER_TGIW5 (uint32_t)(VECT_MTU5_TGIW5 << 24) +#define PDL_DTC_TRIGGER_TGIW11 (uint32_t)(VECT_MTU11_TGIW11 << 24) +#define PDL_DTC_TRIGGER_TCIV4 (uint32_t)(VECT_MTU4_TCIV4 << 24) +#define PDL_DTC_TRIGGER_TCIV10 (uint32_t)(VECT_MTU10_TCIV10 << 24) +#define PDL_DTC_TRIGGER_CMIA0 (uint32_t)(VECT_TMR0_CMIA0 << 24) +#define PDL_DTC_TRIGGER_CMIA1 (uint32_t)(VECT_TMR1_CMIA1 << 24) +#define PDL_DTC_TRIGGER_CMIA2 (uint32_t)(VECT_TMR2_CMIA2 << 24) +#define PDL_DTC_TRIGGER_CMIA3 (uint32_t)(VECT_TMR3_CMIA3 << 24) +#define PDL_DTC_TRIGGER_CMIB0 (uint32_t)(VECT_TMR0_CMIB0 << 24) +#define PDL_DTC_TRIGGER_CMIB1 (uint32_t)(VECT_TMR1_CMIB1 << 24) +#define PDL_DTC_TRIGGER_CMIB2 (uint32_t)(VECT_TMR2_CMIB2 << 24) +#define PDL_DTC_TRIGGER_CMIB3 (uint32_t)(VECT_TMR3_CMIB3 << 24) +#define PDL_DTC_TRIGGER_DMACI0 (uint32_t)(VECT_DMAC_DMAC0I << 24) +#define PDL_DTC_TRIGGER_DMACI1 (uint32_t)(VECT_DMAC_DMAC1I << 24) +#define PDL_DTC_TRIGGER_DMACI2 (uint32_t)(VECT_DMAC_DMAC2I << 24) +#define PDL_DTC_TRIGGER_DMACI3 (uint32_t)(VECT_DMAC_DMAC3I << 24) +#define PDL_DTC_TRIGGER_EXDMACI0 (uint32_t)(VECT_EXDMAC_EXDMAC0I << 24) +#define PDL_DTC_TRIGGER_EXDMACI1 (uint32_t)(VECT_EXDMAC_EXDMAC1I << 24) +#define PDL_DTC_TRIGGER_RXI0 (uint32_t)(VECT_SCI0_RXI0 << 24) +#define PDL_DTC_TRIGGER_RXI1 (uint32_t)(VECT_SCI1_RXI1 << 24) +#define PDL_DTC_TRIGGER_RXI2 (uint32_t)(VECT_SCI2_RXI2 << 24) +#define PDL_DTC_TRIGGER_RXI3 (uint32_t)(VECT_SCI3_RXI3 << 24) +#define PDL_DTC_TRIGGER_RXI5 (uint32_t)(VECT_SCI5_RXI5 << 24) +#define PDL_DTC_TRIGGER_RXI6 (uint32_t)(VECT_SCI6_RXI6 << 24) +#define PDL_DTC_TRIGGER_TXI0 (uint32_t)(VECT_SCI0_TXI0 << 24) +#define PDL_DTC_TRIGGER_TXI1 (uint32_t)(VECT_SCI1_TXI1 << 24) +#define PDL_DTC_TRIGGER_TXI2 (uint32_t)(VECT_SCI2_TXI2 << 24) +#define PDL_DTC_TRIGGER_TXI3 (uint32_t)(VECT_SCI3_TXI3 << 24) +#define PDL_DTC_TRIGGER_TXI5 (uint32_t)(VECT_SCI5_TXI5 << 24) +#define PDL_DTC_TRIGGER_TXI6 (uint32_t)(VECT_SCI6_TXI6 << 24) +#define PDL_DTC_TRIGGER_ICRXI0 (uint32_t)(VECT_RIIC0_ICRXI0 << 24) +#define PDL_DTC_TRIGGER_ICRXI1 (uint32_t)(VECT_RIIC1_ICRXI1 << 24) +#define PDL_DTC_TRIGGER_ICTXI0 (uint32_t)(VECT_RIIC0_ICTXI0 << 24) +#define PDL_DTC_TRIGGER_ICTXI1 (uint32_t)(VECT_RIIC1_ICTXI1 << 24) + +/* Stop / Start control */ +#define PDL_DTC_STOP 0x01u +#define PDL_DTC_START 0x02u + +/* Register modification control */ +#define PDL_DTC_UPDATE_SOURCE 0x04ul +#define PDL_DTC_UPDATE_DESTINATION 0x08ul +#define PDL_DTC_UPDATE_COUNT 0x10ul +#define PDL_DTC_UPDATE_BLOCK_SIZE 0x20ul + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_dtc_rx62nxx.h b/bsp/rx/RPDL/r_pdl_dtc_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..3f42d21bf0ecc987733ef8740da03c8c82f3d2eb --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_dtc_rx62nxx.h @@ -0,0 +1,90 @@ +/*""FILE COMMENT""******************************************************* +* System Name : DTC API for RX62N +* File Name : r_pdl_dtc_RX62Nxx.h +* Version : 1.02 +* Contents : DTC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_DTC_RX62Nxx_H +#define R_PDL_DTC_RX62Nxx_H + +/* Library prototypes */ +bool R_DTC_SetAll( + const uint8_t, + uint32_t * const +); +bool R_DTC_CreateAll( + const uint32_t, + const uint8_t, + uint32_t * const, + volatile const void * const, + volatile const void * const, + const uint16_t, + const uint8_t +); +bool R_DTC_DestroyAll( + void +); +bool R_DTC_ControlAll( + const uint32_t, + const uint8_t, + uint32_t * const, + volatile const void * const, + volatile const void * const, + const uint16_t, + const uint8_t +); +bool R_DTC_GetStatusAll( + const uint32_t * const, + volatile uint16_t * const, + volatile uint32_t * const, + volatile uint32_t * const, + volatile uint16_t * const, + volatile uint8_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_DTC_Set(a, b) \ +( \ +R_DTC_SetAll( (a), (b) ) \ +) + +#define R_DTC_Create(a, b, c, d, e, f) \ +( \ +R_DTC_CreateAll( (a), (uint8_t)((a) >> 24), (b), (c), (d), (e), (f) ) \ +) + +#define R_DTC_Destroy() \ +( \ +R_DTC_DestroyAll() \ +) + +#define R_DTC_Control(a, b, c, d, e, f) \ +( \ +R_DTC_ControlAll( (a), (uint8_t)((a) >> 24), (b), (c), (d), (e), (f) ) \ +) + +#define R_DTC_GetStatus(a, b, c, d, e, f) \ +( \ +R_DTC_GetStatusAll( (a), (b), (c), (d), (e), (f) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_exdmac.h b/bsp/rx/RPDL/r_pdl_exdmac.h new file mode 100644 index 0000000000000000000000000000000000000000..04d1f5409b5e786613ac79ab6ac5fff134ff377e --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_exdmac.h @@ -0,0 +1,148 @@ +/*""FILE COMMENT""******************************************************* +* System Name : EXDMAC API for RX62Nxx +* File Name : r_pdl_exdmac.h +* Version : 1.02 +* Contents : EXDMAC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_EXDMAC_H +#define R_PDL_EXDMAC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_EXDMAC_Create( + uint8_t, + uint32_t, + uint16_t, + uint8_t, + void *, + void *, + uint16_t, + uint16_t, + int32_t, + uint32_t, + uint32_t, + void *, + uint8_t +); +bool R_EXDMAC_Destroy( + uint8_t +); +bool R_EXDMAC_Control( + uint8_t, + uint16_t, + void *, + void *, + uint16_t, + uint16_t, + int32_t, + uint32_t, + uint32_t +); +bool R_EXDMAC_GetStatus( + uint8_t, + uint8_t *, + uint32_t *, + uint32_t *, + uint16_t *, + uint16_t * +); + +/* Transfer mode selection */ +#define PDL_EXDMAC_NORMAL 0x00000001ul +#define PDL_EXDMAC_REPEAT 0x00000002ul +#define PDL_EXDMAC_BLOCK 0x00000004ul +#define PDL_EXDMAC_CLUSTER 0x00000008ul +#define PDL_EXDMAC_SOURCE 0x00000010ul +#define PDL_EXDMAC_DESTINATION 0x00000020ul + +/* Address addition direction selection */ +#define PDL_EXDMAC_SOURCE_ADDRESS_FIXED 0x00000040ul +#define PDL_EXDMAC_SOURCE_ADDRESS_PLUS 0x00000080ul +#define PDL_EXDMAC_SOURCE_ADDRESS_MINUS 0x00000100ul +#define PDL_EXDMAC_SOURCE_ADDRESS_OFFSET 0x00000200ul +#define PDL_EXDMAC_DESTINATION_ADDRESS_FIXED 0x00000400ul +#define PDL_EXDMAC_DESTINATION_ADDRESS_PLUS 0x00000800ul +#define PDL_EXDMAC_DESTINATION_ADDRESS_MINUS 0x00001000ul +#define PDL_EXDMAC_DESTINATION_ADDRESS_OFFSET 0x00002000ul + +/* Address mode selection */ +#define PDL_EXDMAC_ADDRESS_MODE_READ 0x00004000ul +#define PDL_EXDMAC_ADDRESS_MODE_WRITE 0x00008000ul +#define PDL_EXDMAC_ADDRESS_MODE_DUAL 0x00010000ul + +/* Transfer data size */ +#define PDL_EXDMAC_SIZE_8 0x00020000ul +#define PDL_EXDMAC_SIZE_16 0x00040000ul +#define PDL_EXDMAC_SIZE_32 0x00080000ul + +/* Pin selection */ +#define PDL_EXDMAC_PIN_A 0x0001u +#define PDL_EXDMAC_PIN_B 0x0002u +#define PDL_EXDMAC_PIN_C 0x0004u + +/* EDACKn pin output control */ +#define PDL_EXDMAC_EDACK_DISABLE 0x0008u +#define PDL_EXDMAC_EDACK_LOW 0x0010u +#define PDL_EXDMAC_EDACK_HIGH 0x0020u +#define PDL_EXDMAC_EDACK_SYNC 0x0040u +#define PDL_EXDMAC_EDACK_WAIT 0x0080u + +/* Trigger selection */ +#define PDL_EXDMAC_TRIGGER_SW 0x0100u +#define PDL_EXDMAC_TRIGGER_RISING 0x0200u +#define PDL_EXDMAC_TRIGGER_FALLING 0x0400u +#define PDL_EXDMAC_TRIGGER_LOW 0x0800u +#define PDL_EXDMAC_TRIGGER_MTU1 0x1000u + +/* Interrupt generation */ +#define PDL_EXDMAC_IRQ_END 0x01u +#define PDL_EXDMAC_IRQ_ESCAPE_END 0x02u +#define PDL_EXDMAC_IRQ_REPEAT_SIZE_END 0x04u +#define PDL_EXDMAC_IRQ_EXT_SOURCE 0x08u +#define PDL_EXDMAC_IRQ_EXT_DESTINATION 0x10u + +/* DTC trigger control */ +#define PDL_EXDMAC_DTC_TRIGGER_DISABLE 0x20u +#define PDL_EXDMAC_DTC_TRIGGER_ENABLE 0x40u + +/* Enable / suspend control */ +#define PDL_EXDMAC_ENABLE 0x0001u +#define PDL_EXDMAC_SUSPEND 0x0002u + +/* Software trigger control */ +#define PDL_EXDMAC_START 0x0004u +#define PDL_EXDMAC_START_RUN 0x0008u +#define PDL_EXDMAC_STOP 0x0010u + +/* Transfer end interrupt flag control */ +#define PDL_EXDMAC_CLEAR_DTIF 0x0020u +#define PDL_EXDMAC_CLEAR_ESIF 0x0040u + +/* Modify registers selection */ +#define PDL_EXDMAC_UPDATE_SOURCE 0x0080u +#define PDL_EXDMAC_UPDATE_DESTINATION 0x0100u +#define PDL_EXDMAC_UPDATE_COUNT 0x0200u +#define PDL_EXDMAC_UPDATE_SIZE 0x0400u +#define PDL_EXDMAC_UPDATE_OFFSET 0x0800u +#define PDL_EXDMAC_UPDATE_REPEAT_SOURCE 0x1000u +#define PDL_EXDMAC_UPDATE_REPEAT_DESTINATION 0x2000u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_exdmac_rx62nxx.h b/bsp/rx/RPDL/r_pdl_exdmac_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..0a7cb0f50a5a091ee05e7ed87befc634ca2a32b4 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_exdmac_rx62nxx.h @@ -0,0 +1,102 @@ +/*""FILE COMMENT""******************************************************* +* System Name : EXDMAC API for RX62Nxx +* File Name : r_pdl_exdmac_RX62Nxx.h +* Version : 1.02 +* Contents : EXDMAC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_EXDMAC_RX62Nxx_H +#define R_PDL_EXDMAC_RX62Nxx_H + +#define EXDMAC_CHANNELS 2 + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_EXDMAC_callback_func[]; + +/* Library prototypes */ +bool R_EXDMAC_CreateAll( + const uint8_t, + const uint32_t, + const uint16_t, + const uint8_t, + volatile const void * const, + volatile const void * const, + const uint16_t, + const uint16_t, + const int32_t, + const uint32_t, + const uint32_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_EXDMAC_DestroyAll( + const uint8_t +); +bool R_EXDMAC_ControlAll( + const uint8_t, + const uint16_t, + volatile const void * const, + volatile const void * const, + const uint16_t, + const uint16_t, + const int32_t, + const uint32_t, + const uint32_t +); +bool R_EXDMAC_GetStatusAll( + const uint8_t, + volatile uint8_t * const, + volatile uint32_t * const, + volatile uint32_t * const, + volatile uint16_t * const, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_EXDMAC_Create(a, b, c, d, e, f, g, h, i, j, k, l, m) \ +( \ +( ( ((a) < EXDMAC_CHANNELS ) && ((m) <= IPL_MAX) ) ) ? \ +R_EXDMAC_CreateAll( (a), (b), (c), (d), (e), (f), (g), (h), (i), (j), (k), (l), (m) ) : \ +ReturnFalse() \ +) + +#define R_EXDMAC_Control(a, b, c, d, e, f, g, h, i) \ +( \ +( ((a) < EXDMAC_CHANNELS) ) ? \ +R_EXDMAC_ControlAll( (a), (b), (c), (d), (e), (f), (g), (h), (i) ) : \ +ReturnFalse() \ +) + +#define R_EXDMAC_GetStatus(a, b, c, d, e, f) \ +( \ +( ((a) < EXDMAC_CHANNELS) ) ? \ +R_EXDMAC_GetStatusAll( (a), (b), (c), (d), (e), (f) ) : \ +ReturnFalse() \ +) + +#define R_EXDMAC_Destroy(a) \ +( \ +( ((a) < EXDMAC_CHANNELS) ) ? \ +R_EXDMAC_DestroyAll( (a) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_iic.h b/bsp/rx/RPDL/r_pdl_iic.h new file mode 100644 index 0000000000000000000000000000000000000000..116a3fbb3a5c48f25a2f90b7252119b00ab7a87b --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_iic.h @@ -0,0 +1,203 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I²C API for RX62Nxx +* File Name : r_pdl_iic.h +* Version : 1.02 +* Contents : I²C API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IIC_H +#define R_PDL_IIC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_IIC_Create( + uint8_t, + uint32_t, + uint32_t, + uint16_t, + uint16_t, + uint16_t, + uint32_t, + uint32_t +); +bool R_IIC_Destroy( + uint8_t +); +bool R_IIC_MasterSend( + uint8_t, + uint16_t, + uint16_t, + uint8_t *, + uint16_t, + void *, + uint8_t +); +bool R_IIC_MasterReceive( + uint8_t, + uint16_t, + uint16_t, + uint8_t *, + uint16_t, + void *, + uint8_t +); +bool R_IIC_MasterReceiveLast( + uint8_t, + uint8_t * +); +bool R_IIC_SlaveMonitor( + uint8_t, + uint16_t, + uint8_t *, + uint16_t, + void *, + uint8_t +); +bool R_IIC_SlaveSend( + uint8_t, + uint8_t *, + uint16_t +); +bool R_IIC_Control( + uint8_t, + uint8_t +); +bool R_IIC_GetStatus( + uint8_t, + uint32_t *, + uint16_t *, + uint16_t * +); + +/* Bus mode */ +#define PDL_IIC_MODE_IIC 0x00000001ul +#define PDL_IIC_MODE_IIC_FMP 0x00000002ul +#define PDL_IIC_MODE_SMBUS 0x00000004ul + +/* Internal reference clock */ +#define PDL_IIC_INT_PCLK_DIV_1 0x00000008ul +#define PDL_IIC_INT_PCLK_DIV_2 0x00000010ul +#define PDL_IIC_INT_PCLK_DIV_4 0x00000020ul +#define PDL_IIC_INT_PCLK_DIV_8 0x00000040ul +#define PDL_IIC_INT_PCLK_DIV_16 0x00000080ul +#define PDL_IIC_INT_PCLK_DIV_32 0x00000100ul +#define PDL_IIC_INT_PCLK_DIV_64 0x00000200ul +#define PDL_IIC_INT_PCLK_DIV_128 0x00000400ul + +/* Timeout detection */ +#define PDL_IIC_TIMEOUT_DISABLE 0x00000800ul +#define PDL_IIC_TIMEOUT_LOW 0x00001000ul +#define PDL_IIC_TIMEOUT_HIGH 0x00002000ul +#define PDL_IIC_TIMEOUT_BOTH 0x00004000ul + +/* Timeout mode */ +#define PDL_IIC_TIMEOUT_LONG 0x00008000ul +#define PDL_IIC_TIMEOUT_SHORT 0x00010000ul + +/* SDA output delay count */ +#define PDL_IIC_SDA_DELAY_0 0x00020000ul +#define PDL_IIC_SDA_DELAY_1 0x00040000ul +#define PDL_IIC_SDA_DELAY_2 0x00080000ul +#define PDL_IIC_SDA_DELAY_3 0x00100000ul +#define PDL_IIC_SDA_DELAY_4 0x00200000ul +#define PDL_IIC_SDA_DELAY_5 0x00400000ul +#define PDL_IIC_SDA_DELAY_6 0x00800000ul +#define PDL_IIC_SDA_DELAY_7 0x01000000ul + +/* SDA output delay clock source */ +#define PDL_IIC_SDA_DELAY_DIV_1 0x02000000ul +#define PDL_IIC_SDA_DELAY_DIV_2 0x04000000ul + +/* Noise filter control */ +#define PDL_IIC_NF_DISABLE 0x08000000ul +#define PDL_IIC_NF_1 0x10000000ul +#define PDL_IIC_NF_2 0x20000000ul +#define PDL_IIC_NF_3 0x40000000ul +#define PDL_IIC_NF_4 0x80000000ul + +/* NACK Transmission Arbitration Lost Detection control */ +#define PDL_IIC_NTALD_DISABLE 0x00000001ul +#define PDL_IIC_NTALD_ENABLE 0x00000002ul + +/* Slave Arbitration Lost Detection control */ +#define PDL_IIC_SALD_DISABLE 0x00000004ul +#define PDL_IIC_SALD_ENABLE 0x00000008ul + +/* Slave address detection control */ +#define PDL_IIC_SLAVE_0_DISABLE 0x00000010ul +#define PDL_IIC_SLAVE_0_ENABLE_7 0x00000020ul +#define PDL_IIC_SLAVE_0_ENABLE_10 0x00000040ul +#define PDL_IIC_SLAVE_1_DISABLE 0x00000080ul +#define PDL_IIC_SLAVE_1_ENABLE_7 0x00000100ul +#define PDL_IIC_SLAVE_1_ENABLE_10 0x00000200ul +#define PDL_IIC_SLAVE_2_DISABLE 0x00000400ul +#define PDL_IIC_SLAVE_2_ENABLE_7 0x00000800ul +#define PDL_IIC_SLAVE_2_ENABLE_10 0x00001000ul +#define PDL_IIC_SLAVE_GCA_DISABLE 0x00002000ul +#define PDL_IIC_SLAVE_GCA_ENABLE 0x00004000ul + +/* Device-ID detection control */ +#define PDL_IIC_DEVICE_ID_DISABLE 0x00008000ul +#define PDL_IIC_DEVICE_ID_ENABLE 0x00010000ul + +/* Host Address detection control */ +#define PDL_IIC_HOST_ADDRESS_DISABLE 0x00020000ul +#define PDL_IIC_HOST_ADDRESS_ENABLE 0x00040000ul + +/* Start / Repeated Start condition control */ +#define PDL_IIC_START_ENABLE 0x0001u +#define PDL_IIC_START_DISABLE 0x0002u + +/* Stop condition control */ +#define PDL_IIC_STOP_ENABLE 0x0004u +#define PDL_IIC_STOP_DISABLE 0x0008u + +/* Master DMAC / DTC trigger control */ +#define PDL_IIC_DMAC_DTC_TRIGGER_DISABLE 0x0010u +#define PDL_IIC_DMAC_TRIGGER_ENABLE 0x0020u +#define PDL_IIC_DTC_TRIGGER_ENABLE 0x0040u + +/* Slave DMAC / DTC trigger control */ +#define PDL_IIC_RX_DMAC_DTC_TRIGGER_DISABLE 0x0080u +#define PDL_IIC_RX_DMAC_TRIGGER_ENABLE 0x0100u +#define PDL_IIC_RX_DTC_TRIGGER_ENABLE 0x0200u +#define PDL_IIC_TX_DMAC_DTC_TRIGGER_DISABLE 0x0400u +#define PDL_IIC_TX_DMAC_TRIGGER_ENABLE 0x0800u +#define PDL_IIC_TX_DTC_TRIGGER_ENABLE 0x1000u + +/* Stop generation */ +#define PDL_IIC_STOP 0x01u + +/* NACK generation */ +#define PDL_IIC_NACK 0x02u + +/* Pin control */ +#define PDL_IIC_SDA_LOW 0x04u +#define PDL_IIC_SDA_HI_Z 0x08u +#define PDL_IIC_SCL_LOW 0x10u +#define PDL_IIC_SCL_HI_Z 0x20u + +/* Extra clock cycle generation */ +#define PDL_IIC_CYCLE_SCL 0x40u + +/* Reset control */ +#define PDL_IIC_RESET 0x80u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_iic_rx62nxfp.h b/bsp/rx/RPDL/r_pdl_iic_rx62nxfp.h new file mode 100644 index 0000000000000000000000000000000000000000..876690e2cc6153639377b59114ab2c18543b4b3f --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_iic_rx62nxfp.h @@ -0,0 +1,203 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I²C API for RX62Nxx (FP suffix) +* File Name : r_pdl_iic_RX62NxFP.h +* Version : 1.02 +* Contents : I²C API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IIC_RX62NxFP_H +#define R_PDL_IIC_RX62NxFP_H + +#define IIC_CHANNELS 1 + +/* Globals */ +extern volatile uint8_t rpdl_IIC_stop[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_current_state[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_next_state[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_slave_address_lower[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_slave_address_upper[IIC_CHANNELS]; +extern const volatile uint8_t * rpdl_IIC_tx_data_pointer[IIC_CHANNELS]; +extern const volatile uint8_t * rpdl_IIC_tx_data_start[IIC_CHANNELS]; +extern volatile uint8_t * rpdl_IIC_rx_data_pointer[IIC_CHANNELS]; +extern volatile uint8_t * rpdl_IIC_rx_data_start[IIC_CHANNELS]; +extern volatile uint16_t rpdl_IIC_rx_counter[IIC_CHANNELS]; +extern volatile uint16_t rpdl_IIC_tx_counter[IIC_CHANNELS]; +extern volatile uint16_t rpdl_IIC_rx_threshold[IIC_CHANNELS]; +extern volatile uint16_t rpdl_IIC_tx_threshold[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_detected_address[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_rx_transfer_method[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_rx_dmac_channel[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_tx_dmac_channel[IIC_CHANNELS]; + +/* IIC state machine states */ +typedef enum { + IIC_SEND_START, + IIC_MASTER_SEND_SLAVE_ADDRESS_7, + IIC_MASTER_SEND_SLAVE_ADDRESS_10a, + IIC_MASTER_SEND_SLAVE_ADDRESS_10b, + IIC_MASTER_SEND_SLAVE_ADDRESS_10c, + IIC_MASTER_SEND_SLAVE_ADDRESS_10d, + IIC_MASTER_SEND_DATA, + IIC_MASTER_WAIT_FOR_TX_COMPLETE, + IIC_MASTER_WAIT_FOR_STOP, + IIC_EXIT_LOOP, + IIC_MASTER_START_READ, + IIC_MASTER_READ_DATA, + IIC_SEND_STOP, + IIC_SLAVE_MONITOR, + IIC_SLAVE_SEND_DATA, + IIC_SLAVE_READ_SLAVE_ADDRESS, + IIC_SLAVE_READ_DATA +} iic_states; + +/* Transfer options */ +#define IIC_TRANSFER_CPU 0 +#define IIC_TRANSFER_DMAC 2 +#define IIC_TRANSFER_DTC 1 + +/* Callback function prototype */ +extern VoidCallBackFunc rpdl_IIC_callback_func[IIC_CHANNELS]; + +/* Library prototypes */ +bool R_IIC_CreateAll( + const uint8_t, + const uint32_t, + const uint32_t, + const uint16_t, + const uint16_t, + const uint16_t, + const uint32_t, + const uint32_t +); +bool R_IIC_DestroyAll( + const uint8_t +); +bool R_IIC_MasterSendAll( + const uint8_t, + const uint16_t, + const uint16_t, + const volatile uint8_t * const, + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_IIC_MasterReceiveAll( + const uint8_t, + const uint16_t, + const uint16_t, + volatile uint8_t * const, + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_IIC_MasterReceiveLastAll( + const uint8_t, + volatile uint8_t * const +); +bool R_IIC_SlaveMonitorAll( + const uint8_t, + const uint16_t, + volatile uint8_t * const, + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_IIC_SlaveSendAll( + const uint8_t, + const volatile uint8_t * const, + const uint16_t +); +bool R_IIC_ControlAll( + const uint8_t, + const uint8_t +); +bool R_IIC_GetStatusAll( + const uint8_t, + volatile uint32_t * const, + volatile uint16_t * const, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_IIC_Create(a, b, c, d, e, f, g, h) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_CreateAll( (a), (b), (c), (d), (e), (f), (g), (h) ) : \ +ReturnFalse() \ +) + +#define R_IIC_Destroy(a) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_DestroyAll( (a) ) : \ +ReturnFalse() \ +) + +#define R_IIC_MasterSend(a, b, c, d, e, f, g) \ +( \ +( ( (a) < IIC_CHANNELS ) && ((g) <= IPL_MAX) ) ? \ +R_IIC_MasterSendAll( (a), (b), (c), (d), (e), (f), (g) ) : \ +ReturnFalse() \ +) + +#define R_IIC_MasterReceive(a, b, c, d, e, f, g) \ +( \ +( ( (a) < IIC_CHANNELS ) && ((g) <= IPL_MAX) ) ? \ +R_IIC_MasterReceiveAll( (a), (b), (c), (d), (e), (f), (g) ) : \ +ReturnFalse() \ +) + +#define R_IIC_MasterReceiveLast(a, b) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_MasterReceiveLastAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_IIC_SlaveMonitor(a, b, c, d, e, f) \ +( \ +( ( (a) < IIC_CHANNELS ) && ((f) <= IPL_MAX) ) ? \ +R_IIC_SlaveMonitorAll( (a), (b), (c), (d), (e), (f) ) : \ +ReturnFalse() \ +) + +#define R_IIC_SlaveSend(a, b, c) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_SlaveSendAll( (a), (b), (c) ) : \ +ReturnFalse() \ +) + +#define R_IIC_Control(a, b) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_ControlAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_IIC_GetStatus(a, b, c, d) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_GetStatusAll( (a), (b), (c), (d) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_iic_rx62nxnfp.h b/bsp/rx/RPDL/r_pdl_iic_rx62nxnfp.h new file mode 100644 index 0000000000000000000000000000000000000000..eb32b20b3d9ecbce8866b4b6a905c515f140c12f --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_iic_rx62nxnfp.h @@ -0,0 +1,203 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I²C API for RX62N (not FP suffix) +* File Name : r_pdl_iic_RX62NxnFP.h +* Version : 1.02 +* Contents : I²C API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IIC_RX62NxnFP_H +#define R_PDL_IIC_RX62NxnFP_H + +#define IIC_CHANNELS 2 + +/* Globals */ +extern volatile uint8_t rpdl_IIC_stop[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_current_state[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_next_state[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_slave_address_lower[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_slave_address_upper[IIC_CHANNELS]; +extern const volatile uint8_t * rpdl_IIC_tx_data_pointer[IIC_CHANNELS]; +extern const volatile uint8_t * rpdl_IIC_tx_data_start[IIC_CHANNELS]; +extern volatile uint8_t * rpdl_IIC_rx_data_pointer[IIC_CHANNELS]; +extern volatile uint8_t * rpdl_IIC_rx_data_start[IIC_CHANNELS]; +extern volatile uint16_t rpdl_IIC_rx_counter[IIC_CHANNELS]; +extern volatile uint16_t rpdl_IIC_tx_counter[IIC_CHANNELS]; +extern volatile uint16_t rpdl_IIC_rx_threshold[IIC_CHANNELS]; +extern volatile uint16_t rpdl_IIC_tx_threshold[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_detected_address[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_rx_transfer_method[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_rx_dmac_channel[IIC_CHANNELS]; +extern volatile uint8_t rpdl_IIC_tx_dmac_channel[IIC_CHANNELS]; + +/* IIC state machine states */ +typedef enum { + IIC_SEND_START, + IIC_MASTER_SEND_SLAVE_ADDRESS_7, + IIC_MASTER_SEND_SLAVE_ADDRESS_10a, + IIC_MASTER_SEND_SLAVE_ADDRESS_10b, + IIC_MASTER_SEND_SLAVE_ADDRESS_10c, + IIC_MASTER_SEND_SLAVE_ADDRESS_10d, + IIC_MASTER_SEND_DATA, + IIC_MASTER_WAIT_FOR_TX_COMPLETE, + IIC_MASTER_WAIT_FOR_STOP, + IIC_EXIT_LOOP, + IIC_MASTER_START_READ, + IIC_MASTER_READ_DATA, + IIC_SEND_STOP, + IIC_SLAVE_MONITOR, + IIC_SLAVE_SEND_DATA, + IIC_SLAVE_READ_SLAVE_ADDRESS, + IIC_SLAVE_READ_DATA +} iic_states; + +/* Transfer options */ +#define IIC_TRANSFER_CPU 0 +#define IIC_TRANSFER_DMAC 2 +#define IIC_TRANSFER_DTC 1 + +/* Callback function prototype */ +extern VoidCallBackFunc rpdl_IIC_callback_func[IIC_CHANNELS]; + +/* Library prototypes */ +bool R_IIC_CreateAll( + const uint8_t, + const uint32_t, + const uint32_t, + const uint16_t, + const uint16_t, + const uint16_t, + const uint32_t, + const uint32_t +); +bool R_IIC_DestroyAll( + const uint8_t +); +bool R_IIC_MasterSendAll( + const uint8_t, + const uint16_t, + const uint16_t, + const volatile uint8_t * const, + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_IIC_MasterReceiveAll( + const uint8_t, + const uint16_t, + const uint16_t, + volatile uint8_t * const, + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_IIC_MasterReceiveLastAll( + const uint8_t, + volatile uint8_t * const +); +bool R_IIC_SlaveMonitorAll( + const uint8_t, + const uint16_t, + volatile uint8_t * const, + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_IIC_SlaveSendAll( + const uint8_t, + const volatile uint8_t * const, + const uint16_t +); +bool R_IIC_ControlAll( + const uint8_t, + const uint8_t +); +bool R_IIC_GetStatusAll( + const uint8_t, + volatile uint32_t * const, + volatile uint16_t * const, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_IIC_Create(a, b, c, d, e, f, g, h) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_CreateAll( (a), (b), (c), (d), (e), (f), (g), (h) ) : \ +ReturnFalse() \ +) + +#define R_IIC_Destroy(a) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_DestroyAll( (a) ) : \ +ReturnFalse() \ +) + +#define R_IIC_MasterSend(a, b, c, d, e, f, g) \ +( \ +( ( (a) < IIC_CHANNELS ) && ((g) <= IPL_MAX) ) ? \ +R_IIC_MasterSendAll( (a), (b), (c), (d), (e), (f), (g) ) : \ +ReturnFalse() \ +) + +#define R_IIC_MasterReceive(a, b, c, d, e, f, g) \ +( \ +( ( (a) < IIC_CHANNELS ) && ((g) <= IPL_MAX) ) ? \ +R_IIC_MasterReceiveAll( (a), (b), (c), (d), (e), (f), (g) ) : \ +ReturnFalse() \ +) + +#define R_IIC_MasterReceiveLast(a, b) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_MasterReceiveLastAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_IIC_SlaveMonitor(a, b, c, d, e, f) \ +( \ +( ( (a) < IIC_CHANNELS ) && ((f) <= IPL_MAX) ) ? \ +R_IIC_SlaveMonitorAll( (a), (b), (c), (d), (e), (f) ) : \ +ReturnFalse() \ +) + +#define R_IIC_SlaveSend(a, b, c) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_SlaveSendAll( (a), (b), (c) ) : \ +ReturnFalse() \ +) + +#define R_IIC_Control(a, b) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_ControlAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_IIC_GetStatus(a, b, c, d) \ +( \ +( (a) < IIC_CHANNELS ) ? \ +R_IIC_GetStatusAll( (a), (b), (c), (d) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_intc.h b/bsp/rx/RPDL/r_pdl_intc.h new file mode 100644 index 0000000000000000000000000000000000000000..6fea67b028f04f8433c1ba31e67399b2708d5327 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_intc.h @@ -0,0 +1,606 @@ +/*""FILE COMMENT""******************************************************* +* System Name : External interrupt API +* File Name : r_pdl_intc.h +* Version : 1.02 +* Contents : External interrupt API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_INTC_H +#define R_PDL_INTC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_INTC_CreateExtInterrupt( + uint8_t, + uint32_t, + void *, + uint8_t +); +bool R_INTC_CreateSoftwareInterrupt( + uint8_t, + void *, + uint8_t +); +bool R_INTC_CreateFastInterrupt( + uint8_t +); +bool R_INTC_CreateExceptionHandlers( + void *, + void *, + void * +); +bool R_INTC_ControlExtInterrupt( + uint8_t, + uint32_t +); +bool R_INTC_GetExtInterruptStatus( + uint8_t, + uint8_t * +); +bool R_INTC_Read( + uint16_t, + uint8_t * +); +bool R_INTC_Write( + uint16_t, + uint8_t +); +bool R_INTC_Modify( + uint16_t, + uint8_t, + uint8_t +); + +/* Interrupt pins */ +#define PDL_INTC_IRQ0 0 +#define PDL_INTC_IRQ1 1 +#define PDL_INTC_IRQ2 2 +#define PDL_INTC_IRQ3 3 +#define PDL_INTC_IRQ4 4 +#define PDL_INTC_IRQ5 5 +#define PDL_INTC_IRQ6 6 +#define PDL_INTC_IRQ7 7 +#define PDL_INTC_IRQ8 8 +#define PDL_INTC_IRQ9 9 +#define PDL_INTC_IRQ10 10 +#define PDL_INTC_IRQ11 11 +#define PDL_INTC_IRQ12 12 +#define PDL_INTC_IRQ13 13 +#define PDL_INTC_IRQ14 14 +#define PDL_INTC_IRQ15 15 +#define PDL_INTC_PRIVILEGED 16 +#define PDL_INTC_UNDEFINED 17 +#define PDL_INTC_FLOATING_POINT 18 +#define PDL_INTC_NMI 19 +#define PDL_INTC_SWINT 20 + +/* Detection sense selection */ +#define PDL_INTC_LOW 0x00000001ul +#define PDL_INTC_FALLING 0x00000002ul +#define PDL_INTC_RISING 0x00000004ul +#define PDL_INTC_BOTH 0x00000008ul + +/* IRQ alternate pin selection */ +#define PDL_INTC_A 0x00000010ul +#define PDL_INTC_B 0x00000020ul + +/* DMAC / DTC trigger control */ +#define PDL_INTC_DMAC_DTC_TRIGGER_DISABLE 0x00000040ul +#define PDL_INTC_DMAC_TRIGGER_ENABLE 0x00000080ul +#define PDL_INTC_DTC_TRIGGER_ENABLE 0x00000100ul + +/* LVD detection control */ +#define PDL_INTC_LVD_DISABLE 0x00000200ul +#define PDL_INTC_LVD_ENABLE 0x00000400ul + +/* Oscillation stop detection control */ +#define PDL_INTC_OSD_DISABLE 0x00000800ul +#define PDL_INTC_OSD_ENABLE 0x00001000ul + +/* Interrupt control */ +#define PDL_INTC_ENABLE 0x00002000ul +#define PDL_INTC_DISABLE 0x00004000ul + +/* Flag control */ +#define PDL_INTC_CLEAR_IR_FLAG 0x00008000ul +#define PDL_INTC_CLEAR_OSD_FLAG 0x00010000ul + +/* DTC software trigger control */ +#define PDL_INTC_DTC_SW_TRIGGER_DISABLE 0x01u +#define PDL_INTC_DTC_SW_TRIGGER_ENABLE 0x02u + +/* Interrupt registers */ +#define PDL_INTC_REG_IPL 0x0100u +#define PDL_INTC_REG_IR 0x0200u +#define PDL_INTC_REG_IER 0x0400u +#define PDL_INTC_REG_IPR 0x0800u +#define PDL_INTC_REG_DTCER 0x1000u +#define PDL_INTC_REG_SWINTR 0x2000u + +/* Logical operations */ +#define PDL_INTC_AND 0x01u +#define PDL_INTC_OR 0x02u +#define PDL_INTC_XOR 0x04u + +/* IR registers */ +#define PDL_INTC_REG_IR_BSC_BUSERR (PDL_INTC_REG_IR | IR_BSC_BUSERR) +#define PDL_INTC_REG_IR_FCU_FIFERR (PDL_INTC_REG_IR | IR_FCU_FIFERR) +#define PDL_INTC_REG_IR_FCU_FRDYI (PDL_INTC_REG_IR | IR_FCU_FRDYI) +#define PDL_INTC_REG_IR_ICU_SWINT (PDL_INTC_REG_IR | IR_ICU_SWINT) +#define PDL_INTC_REG_IR_CMT0_CMI (PDL_INTC_REG_IR | IR_CMT0_CMI0) +#define PDL_INTC_REG_IR_CMT1_CMI (PDL_INTC_REG_IR | IR_CMT1_CMI1) +#define PDL_INTC_REG_IR_CMT2_CMI (PDL_INTC_REG_IR | IR_CMT2_CMI2) +#define PDL_INTC_REG_IR_CMT3_CMI (PDL_INTC_REG_IR | IR_CMT3_CMI3) +#define PDL_INTC_REG_IR_ETHER_EINT (PDL_INTC_REG_IR | IR_ETHER_EINT) +#define PDL_INTC_REG_IR_USB0_D0FIFO (PDL_INTC_REG_IR | IR_USB0_D0FIFO0) +#define PDL_INTC_REG_IR_USB0_D1FIFO (PDL_INTC_REG_IR | IR_USB0_D1FIFO0) +#define PDL_INTC_REG_IR_USB0_USBI (PDL_INTC_REG_IR | IR_USB0_USBI0) +#define PDL_INTC_REG_IR_USB1_D0FIFO (PDL_INTC_REG_IR | IR_USB1_D0FIFO1) +#define PDL_INTC_REG_IR_USB1_D1FIFO (PDL_INTC_REG_IR | IR_USB1_D1FIFO1) +#define PDL_INTC_REG_IR_USB1_USBI (PDL_INTC_REG_IR | IR_USB1_USBI1) +#define PDL_INTC_REG_IR_SPI0_SPEI (PDL_INTC_REG_IR | IR_RSPI0_SPEI0) +#define PDL_INTC_REG_IR_SPI0_SPRI (PDL_INTC_REG_IR | IR_RSPI0_SPRI0) +#define PDL_INTC_REG_IR_SPI0_SPTI (PDL_INTC_REG_IR | IR_RSPI0_SPTI0) +#define PDL_INTC_REG_IR_SPI0_SPII (PDL_INTC_REG_IR | IR_RSPI0_SPII0) +#define PDL_INTC_REG_IR_SPI1_SPEI (PDL_INTC_REG_IR | IR_RSPI1_SPEI1) +#define PDL_INTC_REG_IR_SPI1_SPRI (PDL_INTC_REG_IR | IR_RSPI1_SPRI1) +#define PDL_INTC_REG_IR_SPI1_SPTI (PDL_INTC_REG_IR | IR_RSPI1_SPTI1) +#define PDL_INTC_REG_IR_SPI1_SPII (PDL_INTC_REG_IR | IR_RSPI1_SPII1) +#define PDL_INTC_REG_IR_CAN0_ERS (PDL_INTC_REG_IR | IR_CAN0_ERS0) +#define PDL_INTC_REG_IR_CAN0_RXF (PDL_INTC_REG_IR | IR_CAN0_RXF0) +#define PDL_INTC_REG_IR_CAN0_TXF (PDL_INTC_REG_IR | IR_CAN0_TXF0) +#define PDL_INTC_REG_IR_CAN0_RXM (PDL_INTC_REG_IR | IR_CAN0_RXM0) +#define PDL_INTC_REG_IR_CAN0_TXM (PDL_INTC_REG_IR | IR_CAN0_TXM0) +#define PDL_INTC_REG_IR_RTC_PRD (PDL_INTC_REG_IR | IR_RTC_PRD) +#define PDL_INTC_REG_IR_RTC_CUP (PDL_INTC_REG_IR | IR_RTC_CUP) +#define PDL_INTC_REG_IR_ICU_IRQ0 (PDL_INTC_REG_IR | IR_ICU_IRQ0) +#define PDL_INTC_REG_IR_ICU_IRQ1 (PDL_INTC_REG_IR | IR_ICU_IRQ1) +#define PDL_INTC_REG_IR_ICU_IRQ2 (PDL_INTC_REG_IR | IR_ICU_IRQ2) +#define PDL_INTC_REG_IR_ICU_IRQ3 (PDL_INTC_REG_IR | IR_ICU_IRQ3) +#define PDL_INTC_REG_IR_ICU_IRQ4 (PDL_INTC_REG_IR | IR_ICU_IRQ4) +#define PDL_INTC_REG_IR_ICU_IRQ5 (PDL_INTC_REG_IR | IR_ICU_IRQ5) +#define PDL_INTC_REG_IR_ICU_IRQ6 (PDL_INTC_REG_IR | IR_ICU_IRQ6) +#define PDL_INTC_REG_IR_ICU_IRQ7 (PDL_INTC_REG_IR | IR_ICU_IRQ7) +#define PDL_INTC_REG_IR_ICU_IRQ8 (PDL_INTC_REG_IR | IR_ICU_IRQ8) +#define PDL_INTC_REG_IR_ICU_IRQ9 (PDL_INTC_REG_IR | IR_ICU_IRQ9) +#define PDL_INTC_REG_IR_ICU_IRQ10 (PDL_INTC_REG_IR | IR_ICU_IRQ10) +#define PDL_INTC_REG_IR_ICU_IRQ11 (PDL_INTC_REG_IR | IR_ICU_IRQ11) +#define PDL_INTC_REG_IR_ICU_IRQ12 (PDL_INTC_REG_IR | IR_ICU_IRQ12) +#define PDL_INTC_REG_IR_ICU_IRQ13 (PDL_INTC_REG_IR | IR_ICU_IRQ13) +#define PDL_INTC_REG_IR_ICU_IRQ14 (PDL_INTC_REG_IR | IR_ICU_IRQ14) +#define PDL_INTC_REG_IR_ICU_IRQ15 (PDL_INTC_REG_IR | IR_ICU_IRQ15) +#define PDL_INTC_REG_IR_USB_USBR0 (PDL_INTC_REG_IR | IR_USB_USBR0) +#define PDL_INTC_REG_IR_USB_USBR1 (PDL_INTC_REG_IR | IR_USB_USBR1) +#define PDL_INTC_REG_IR_RTC_ALM (PDL_INTC_REG_IR | IR_RTC_ALM) +#define PDL_INTC_REG_IR_WDT_WOVI (PDL_INTC_REG_IR | IR_WDT_WOVI) +#define PDL_INTC_REG_IR_AD0_ADI (PDL_INTC_REG_IR | IR_AD0_ADI0) +#define PDL_INTC_REG_IR_AD1_ADI (PDL_INTC_REG_IR | IR_AD1_ADI1) +#define PDL_INTC_REG_IR_S12AD_ADI (PDL_INTC_REG_IR | IR_S12AD_ADI) +#define PDL_INTC_REG_IR_MTU0_TGIA (PDL_INTC_REG_IR | IR_MTU0_TGIA0) +#define PDL_INTC_REG_IR_MTU0_TGIB (PDL_INTC_REG_IR | IR_MTU0_TGIB0) +#define PDL_INTC_REG_IR_MTU0_TGIC (PDL_INTC_REG_IR | IR_MTU0_TGIC0) +#define PDL_INTC_REG_IR_MTU0_TGID (PDL_INTC_REG_IR | IR_MTU0_TGID0) +#define PDL_INTC_REG_IR_MTU0_TCIV (PDL_INTC_REG_IR | IR_MTU0_TCIV0) +#define PDL_INTC_REG_IR_MTU0_TGIE (PDL_INTC_REG_IR | IR_MTU0_TGIE0) +#define PDL_INTC_REG_IR_MTU0_TGIF (PDL_INTC_REG_IR | IR_MTU0_TGIF0) +#define PDL_INTC_REG_IR_MTU1_TGIA (PDL_INTC_REG_IR | IR_MTU1_TGIA1) +#define PDL_INTC_REG_IR_MTU1_TGIB (PDL_INTC_REG_IR | IR_MTU1_TGIB1) +#define PDL_INTC_REG_IR_MTU1_TCIV (PDL_INTC_REG_IR | IR_MTU1_TCIV1) +#define PDL_INTC_REG_IR_MTU1_TCIU (PDL_INTC_REG_IR | IR_MTU1_TCIU1) +#define PDL_INTC_REG_IR_MTU2_TGIA (PDL_INTC_REG_IR | IR_MTU2_TGIA2) +#define PDL_INTC_REG_IR_MTU2_TGIB (PDL_INTC_REG_IR | IR_MTU2_TGIB2) +#define PDL_INTC_REG_IR_MTU2_TCIV (PDL_INTC_REG_IR | IR_MTU2_TCIV2) +#define PDL_INTC_REG_IR_MTU2_TCIU (PDL_INTC_REG_IR | IR_MTU2_TCIU2) +#define PDL_INTC_REG_IR_MTU3_TGIA (PDL_INTC_REG_IR | IR_MTU3_TGIA3) +#define PDL_INTC_REG_IR_MTU3_TGIB (PDL_INTC_REG_IR | IR_MTU3_TGIB3) +#define PDL_INTC_REG_IR_MTU3_TGIC (PDL_INTC_REG_IR | IR_MTU3_TGIC3) +#define PDL_INTC_REG_IR_MTU3_TGID (PDL_INTC_REG_IR | IR_MTU3_TGID3) +#define PDL_INTC_REG_IR_MTU3_TCIV (PDL_INTC_REG_IR | IR_MTU3_TCIV3) +#define PDL_INTC_REG_IR_MTU4_TGIA (PDL_INTC_REG_IR | IR_MTU4_TGIA4) +#define PDL_INTC_REG_IR_MTU4_TGIB (PDL_INTC_REG_IR | IR_MTU4_TGIB4) +#define PDL_INTC_REG_IR_MTU4_TGIC (PDL_INTC_REG_IR | IR_MTU4_TGIC4) +#define PDL_INTC_REG_IR_MTU4_TGID (PDL_INTC_REG_IR | IR_MTU4_TGID4) +#define PDL_INTC_REG_IR_MTU4_TCIV (PDL_INTC_REG_IR | IR_MTU4_TCIV4) +#define PDL_INTC_REG_IR_MTU5_TGIU (PDL_INTC_REG_IR | IR_MTU5_TGIU5) +#define PDL_INTC_REG_IR_MTU5_TGIV (PDL_INTC_REG_IR | IR_MTU5_TGIV5) +#define PDL_INTC_REG_IR_MTU5_TGIW (PDL_INTC_REG_IR | IR_MTU5_TGIW5) +#define PDL_INTC_REG_IR_MTU6_TGIA (PDL_INTC_REG_IR | IR_MTU6_TGIA6) +#define PDL_INTC_REG_IR_MTU6_TGIB (PDL_INTC_REG_IR | IR_MTU6_TGIB6) +#define PDL_INTC_REG_IR_MTU6_TGIC (PDL_INTC_REG_IR | IR_MTU6_TGIC6) +#define PDL_INTC_REG_IR_MTU6_TGID (PDL_INTC_REG_IR | IR_MTU6_TGID6) +#define PDL_INTC_REG_IR_MTU6_TCIV (PDL_INTC_REG_IR | IR_MTU6_TCIV6) +#define PDL_INTC_REG_IR_MTU6_TGIE (PDL_INTC_REG_IR | IR_MTU6_TGIE6) +#define PDL_INTC_REG_IR_MTU6_TGIF (PDL_INTC_REG_IR | IR_MTU6_TGIF6) +#define PDL_INTC_REG_IR_MTU7_TGIA (PDL_INTC_REG_IR | IR_MTU7_TGIA7) +#define PDL_INTC_REG_IR_MTU7_TGIB (PDL_INTC_REG_IR | IR_MTU7_TGIB7) +#define PDL_INTC_REG_IR_MTU7_TCIV (PDL_INTC_REG_IR | IR_MTU7_TCIV7) +#define PDL_INTC_REG_IR_MTU7_TCIU (PDL_INTC_REG_IR | IR_MTU7_TCIU7) +#define PDL_INTC_REG_IR_MTU8_TGIA (PDL_INTC_REG_IR | IR_MTU8_TGIA8) +#define PDL_INTC_REG_IR_MTU8_TGIB (PDL_INTC_REG_IR | IR_MTU8_TGIB8) +#define PDL_INTC_REG_IR_MTU8_TCIV (PDL_INTC_REG_IR | IR_MTU8_TCIV8) +#define PDL_INTC_REG_IR_MTU8_TCIU (PDL_INTC_REG_IR | IR_MTU8_TCIU8) +#define PDL_INTC_REG_IR_MTU9_TGIA (PDL_INTC_REG_IR | IR_MTU9_TGIA9) +#define PDL_INTC_REG_IR_MTU9_TGIB (PDL_INTC_REG_IR | IR_MTU9_TGIB9) +#define PDL_INTC_REG_IR_MTU9_TGIC (PDL_INTC_REG_IR | IR_MTU9_TGIC9) +#define PDL_INTC_REG_IR_MTU9_TGID (PDL_INTC_REG_IR | IR_MTU9_TGID9) +#define PDL_INTC_REG_IR_MTU9_TCIV (PDL_INTC_REG_IR | IR_MTU9_TCIV9) +#define PDL_INTC_REG_IR_MTU10_TGIA (PDL_INTC_REG_IR | IR_MTU10_TGIA10) +#define PDL_INTC_REG_IR_MTU10_TGIB (PDL_INTC_REG_IR | IR_MTU10_TGIB10) +#define PDL_INTC_REG_IR_MTU10_TGIC (PDL_INTC_REG_IR | IR_MTU10_TGIC10) +#define PDL_INTC_REG_IR_MTU10_TGID (PDL_INTC_REG_IR | IR_MTU10_TGID10) +#define PDL_INTC_REG_IR_MTU10_TCIV (PDL_INTC_REG_IR | IR_MTU10_TCIV10) +#define PDL_INTC_REG_IR_MTU11_TGIU (PDL_INTC_REG_IR | IR_MTU11_TGIU11) +#define PDL_INTC_REG_IR_MTU11_TGIV (PDL_INTC_REG_IR | IR_MTU11_TGIV11) +#define PDL_INTC_REG_IR_MTU11_TGIW (PDL_INTC_REG_IR | IR_MTU11_TGIW11) +#define PDL_INTC_REG_IR_POE_OEI1 (PDL_INTC_REG_IR | IR_POE_OEI1) +#define PDL_INTC_REG_IR_POE_OEI2 (PDL_INTC_REG_IR | IR_POE_OEI2) +#define PDL_INTC_REG_IR_POE_OEI3 (PDL_INTC_REG_IR | IR_POE_OEI3) +#define PDL_INTC_REG_IR_POE_OEI4 (PDL_INTC_REG_IR | IR_POE_OEI4) +#define PDL_INTC_REG_IR_TMR0_CMIA (PDL_INTC_REG_IR | IR_TMR0_CMIA0) +#define PDL_INTC_REG_IR_TMR0_CMIB (PDL_INTC_REG_IR | IR_TMR0_CMIB0) +#define PDL_INTC_REG_IR_TMR0_OVI (PDL_INTC_REG_IR | IR_TMR0_OVI0) +#define PDL_INTC_REG_IR_TMR1_CMIA (PDL_INTC_REG_IR | IR_TMR1_CMIA1) +#define PDL_INTC_REG_IR_TMR1_CMIB (PDL_INTC_REG_IR | IR_TMR1_CMIB1) +#define PDL_INTC_REG_IR_TMR1_OVI (PDL_INTC_REG_IR | IR_TMR1_OVI1) +#define PDL_INTC_REG_IR_TMR2_CMIA (PDL_INTC_REG_IR | IR_TMR2_CMIA2) +#define PDL_INTC_REG_IR_TMR2_CMIB (PDL_INTC_REG_IR | IR_TMR2_CMIB2) +#define PDL_INTC_REG_IR_TMR2_OVI (PDL_INTC_REG_IR | IR_TMR2_OVI2) +#define PDL_INTC_REG_IR_TMR3_CMIA (PDL_INTC_REG_IR | IR_TMR3_CMIA3) +#define PDL_INTC_REG_IR_TMR3_CMIB (PDL_INTC_REG_IR | IR_TMR3_CMIB3) +#define PDL_INTC_REG_IR_TMR3_OVI (PDL_INTC_REG_IR | IR_TMR3_OVI3) +#define PDL_INTC_REG_IR_DMAC_DMAC0I (PDL_INTC_REG_IR | IR_DMAC_DMAC0I) +#define PDL_INTC_REG_IR_DMAC_DMAC1I (PDL_INTC_REG_IR | IR_DMAC_DMAC1I) +#define PDL_INTC_REG_IR_DMAC_DMAC2I (PDL_INTC_REG_IR | IR_DMAC_DMAC2I) +#define PDL_INTC_REG_IR_DMAC_DMAC3I (PDL_INTC_REG_IR | IR_DMAC_DMAC3I) +#define PDL_INTC_REG_IR_EXDMAC_EXDMAC0I (PDL_INTC_REG_IR | IR_EXDMAC_EXDMAC0I) +#define PDL_INTC_REG_IR_EXDMAC_EXDMAC1I (PDL_INTC_REG_IR | IR_EXDMAC_EXDMAC1I) +#define PDL_INTC_REG_IR_SCI0_ERI (PDL_INTC_REG_IR | IR_SCI0_ERI0) +#define PDL_INTC_REG_IR_SCI0_RXI (PDL_INTC_REG_IR | IR_SCI0_RXI0) +#define PDL_INTC_REG_IR_SCI0_TXI (PDL_INTC_REG_IR | IR_SCI0_TXI0) +#define PDL_INTC_REG_IR_SCI0_TEI (PDL_INTC_REG_IR | IR_SCI0_TEI0) +#define PDL_INTC_REG_IR_SCI1_ERI (PDL_INTC_REG_IR | IR_SCI1_ERI1) +#define PDL_INTC_REG_IR_SCI1_RXI (PDL_INTC_REG_IR | IR_SCI1_RXI1) +#define PDL_INTC_REG_IR_SCI1_TXI (PDL_INTC_REG_IR | IR_SCI1_TXI1) +#define PDL_INTC_REG_IR_SCI1_TEI (PDL_INTC_REG_IR | IR_SCI1_TEI1) +#define PDL_INTC_REG_IR_SCI2_ERI (PDL_INTC_REG_IR | IR_SCI2_ERI2) +#define PDL_INTC_REG_IR_SCI2_RXI (PDL_INTC_REG_IR | IR_SCI2_RXI2) +#define PDL_INTC_REG_IR_SCI2_TXI (PDL_INTC_REG_IR | IR_SCI2_TXI2) +#define PDL_INTC_REG_IR_SCI2_TEI (PDL_INTC_REG_IR | IR_SCI2_TEI2) +#define PDL_INTC_REG_IR_SCI3_ERI (PDL_INTC_REG_IR | IR_SCI3_ERI3) +#define PDL_INTC_REG_IR_SCI3_RXI (PDL_INTC_REG_IR | IR_SCI3_RXI3) +#define PDL_INTC_REG_IR_SCI3_TXI (PDL_INTC_REG_IR | IR_SCI3_TXI3) +#define PDL_INTC_REG_IR_SCI3_TEI (PDL_INTC_REG_IR | IR_SCI3_TEI3) +#define PDL_INTC_REG_IR_SCI5_ERI (PDL_INTC_REG_IR | IR_SCI5_ERI5) +#define PDL_INTC_REG_IR_SCI5_RXI (PDL_INTC_REG_IR | IR_SCI5_RXI5) +#define PDL_INTC_REG_IR_SCI5_TXI (PDL_INTC_REG_IR | IR_SCI5_TXI5) +#define PDL_INTC_REG_IR_SCI5_TEI (PDL_INTC_REG_IR | IR_SCI5_TEI5) +#define PDL_INTC_REG_IR_SCI6_ERI (PDL_INTC_REG_IR | IR_SCI6_ERI6) +#define PDL_INTC_REG_IR_SCI6_RXI (PDL_INTC_REG_IR | IR_SCI6_RXI6) +#define PDL_INTC_REG_IR_SCI6_TXI (PDL_INTC_REG_IR | IR_SCI6_TXI6) +#define PDL_INTC_REG_IR_SCI6_TEI (PDL_INTC_REG_IR | IR_SCI6_TEI6) +#define PDL_INTC_REG_IR_IIC0_EEI (PDL_INTC_REG_IR | IR_RIIC0_ICEEI0) +#define PDL_INTC_REG_IR_IIC0_RXI (PDL_INTC_REG_IR | IR_RIIC0_ICRXI0) +#define PDL_INTC_REG_IR_IIC0_TXI (PDL_INTC_REG_IR | IR_RIIC0_ICTXI0) +#define PDL_INTC_REG_IR_IIC0_TEI (PDL_INTC_REG_IR | IR_RIIC0_ICTEI0) +#define PDL_INTC_REG_IR_IIC1_EEI (PDL_INTC_REG_IR | IR_RIIC1_ICEEI1) +#define PDL_INTC_REG_IR_IIC1_RXI (PDL_INTC_REG_IR | IR_RIIC1_ICRXI1) +#define PDL_INTC_REG_IR_IIC1_TXI (PDL_INTC_REG_IR | IR_RIIC1_ICTXI1) +#define PDL_INTC_REG_IR_IIC1_TEI (PDL_INTC_REG_IR | IR_RIIC1_ICTEI1) + +/* IER registers */ +#define PDL_INTC_REG_IER02 (PDL_INTC_REG_IER | 0x02) +#define PDL_INTC_REG_IER03 (PDL_INTC_REG_IER | 0x03) +#define PDL_INTC_REG_IER04 (PDL_INTC_REG_IER | 0x04) +#define PDL_INTC_REG_IER05 (PDL_INTC_REG_IER | 0x05) +#define PDL_INTC_REG_IER06 (PDL_INTC_REG_IER | 0x06) +#define PDL_INTC_REG_IER07 (PDL_INTC_REG_IER | 0x07) +#define PDL_INTC_REG_IER08 (PDL_INTC_REG_IER | 0x08) +#define PDL_INTC_REG_IER09 (PDL_INTC_REG_IER | 0x09) +#define PDL_INTC_REG_IER0B (PDL_INTC_REG_IER | 0x0B) +#define PDL_INTC_REG_IER0C (PDL_INTC_REG_IER | 0x0C) +#define PDL_INTC_REG_IER0E (PDL_INTC_REG_IER | 0x0E) +#define PDL_INTC_REG_IER0F (PDL_INTC_REG_IER | 0x0F) +#define PDL_INTC_REG_IER10 (PDL_INTC_REG_IER | 0x10) +#define PDL_INTC_REG_IER11 (PDL_INTC_REG_IER | 0x11) +#define PDL_INTC_REG_IER12 (PDL_INTC_REG_IER | 0x12) +#define PDL_INTC_REG_IER13 (PDL_INTC_REG_IER | 0x13) +#define PDL_INTC_REG_IER14 (PDL_INTC_REG_IER | 0x14) +#define PDL_INTC_REG_IER15 (PDL_INTC_REG_IER | 0x15) +#define PDL_INTC_REG_IER16 (PDL_INTC_REG_IER | 0x16) +#define PDL_INTC_REG_IER17 (PDL_INTC_REG_IER | 0x17) +#define PDL_INTC_REG_IER18 (PDL_INTC_REG_IER | 0x18) +#define PDL_INTC_REG_IER19 (PDL_INTC_REG_IER | 0x19) +#define PDL_INTC_REG_IER1A (PDL_INTC_REG_IER | 0x1A) +#define PDL_INTC_REG_IER1B (PDL_INTC_REG_IER | 0x1B) +#define PDL_INTC_REG_IER1C (PDL_INTC_REG_IER | 0x1C) +#define PDL_INTC_REG_IER1D (PDL_INTC_REG_IER | 0x1D) +#define PDL_INTC_REG_IER1E (PDL_INTC_REG_IER | 0x1E) +#define PDL_INTC_REG_IER1F (PDL_INTC_REG_IER | 0x1F) + +/* IPR registers */ +#define PDL_INTC_REG_IPR_BSC_BUSERR (PDL_INTC_REG_IPR | IPR_BSC_BUSERR) +#define PDL_INTC_REG_IPR_FCU_FIFERR (PDL_INTC_REG_IPR | IPR_FCU_FIFERR) +#define PDL_INTC_REG_IPR_FCU_FRDYI (PDL_INTC_REG_IPR | IPR_FCU_FRDYI) +#define PDL_INTC_REG_IPR_ICU_SWINT (PDL_INTC_REG_IPR | IPR_ICU_SWINT) +#define PDL_INTC_REG_IPR_CMT0_CMI (PDL_INTC_REG_IPR | IPR_CMT0_CMI0) +#define PDL_INTC_REG_IPR_CMT1_CMI (PDL_INTC_REG_IPR | IPR_CMT1_CMI1) +#define PDL_INTC_REG_IPR_CMT2_CMI (PDL_INTC_REG_IPR | IPR_CMT2_CMI2) +#define PDL_INTC_REG_IPR_CMT3_CMI (PDL_INTC_REG_IPR | IPR_CMT3_CMI3) +#define PDL_INTC_REG_IPR_ETHER_EINT (PDL_INTC_REG_IPR | IPR_ETHER_EINT) +#define PDL_INTC_REG_IPR_USB0_D0FIFO (PDL_INTC_REG_IPR | IPR_USB0_D0FIFO0) +#define PDL_INTC_REG_IPR_USB0_D1FIFO (PDL_INTC_REG_IPR | IPR_USB0_D1FIFO0) +#define PDL_INTC_REG_IPR_USB0_USBI (PDL_INTC_REG_IPR | IPR_USB0_USBI0) +#define PDL_INTC_REG_IPR_USB1_D0FIFO (PDL_INTC_REG_IPR | IPR_USB1_D0FIFO1) +#define PDL_INTC_REG_IPR_USB1_D1FIFO (PDL_INTC_REG_IPR | IPR_USB1_D1FIFO1) +#define PDL_INTC_REG_IPR_USB1_USBI (PDL_INTC_REG_IPR | IPR_USB1_USBI1) +#define PDL_INTC_REG_IPR_SPI0_SPEI (PDL_INTC_REG_IPR | IPR_RSPI0_SPEI0) +#define PDL_INTC_REG_IPR_SPI0_SPRI (PDL_INTC_REG_IPR | IPR_RSPI0_SPRI0) +#define PDL_INTC_REG_IPR_SPI0_SPTI (PDL_INTC_REG_IPR | IPR_RSPI0_SPTI0) +#define PDL_INTC_REG_IPR_SPI0_SPII (PDL_INTC_REG_IPR | IPR_RSPI0_SPII0) +#define PDL_INTC_REG_IPR_SPI1_SPEI (PDL_INTC_REG_IPR | IPR_RSPI1_SPEI1) +#define PDL_INTC_REG_IPR_SPI1_SPRI (PDL_INTC_REG_IPR | IPR_RSPI1_SPRI1) +#define PDL_INTC_REG_IPR_SPI1_SPTI (PDL_INTC_REG_IPR | IPR_RSPI1_SPTI1) +#define PDL_INTC_REG_IPR_SPI1_SPII (PDL_INTC_REG_IPR | IPR_RSPI1_SPII1) +#define PDL_INTC_REG_IPR_CAN0_ERS (PDL_INTC_REG_IPR | IPR_CAN0_ERS0) +#define PDL_INTC_REG_IPR_CAN0_RXF (PDL_INTC_REG_IPR | IPR_CAN0_RXF0) +#define PDL_INTC_REG_IPR_CAN0_TXF (PDL_INTC_REG_IPR | IPR_CAN0_TXF0) +#define PDL_INTC_REG_IPR_CAN0_RXM (PDL_INTC_REG_IPR | IPR_CAN0_RXM0) +#define PDL_INTC_REG_IPR_CAN0_TXM (PDL_INTC_REG_IPR | IPR_CAN0_TXM0) +#define PDL_INTC_REG_IPR_RTC_PRD (PDL_INTC_REG_IPR | IPR_RTC_PRD) +#define PDL_INTC_REG_IPR_RTC_CUP (PDL_INTC_REG_IPR | IPR_RTC_CUP) +#define PDL_INTC_REG_IPR_ICU_IRQ0 (PDL_INTC_REG_IPR | IPR_ICU_IRQ0) +#define PDL_INTC_REG_IPR_ICU_IRQ1 (PDL_INTC_REG_IPR | IPR_ICU_IRQ1) +#define PDL_INTC_REG_IPR_ICU_IRQ2 (PDL_INTC_REG_IPR | IPR_ICU_IRQ2) +#define PDL_INTC_REG_IPR_ICU_IRQ3 (PDL_INTC_REG_IPR | IPR_ICU_IRQ3) +#define PDL_INTC_REG_IPR_ICU_IRQ4 (PDL_INTC_REG_IPR | IPR_ICU_IRQ4) +#define PDL_INTC_REG_IPR_ICU_IRQ5 (PDL_INTC_REG_IPR | IPR_ICU_IRQ5) +#define PDL_INTC_REG_IPR_ICU_IRQ6 (PDL_INTC_REG_IPR | IPR_ICU_IRQ6) +#define PDL_INTC_REG_IPR_ICU_IRQ7 (PDL_INTC_REG_IPR | IPR_ICU_IRQ7) +#define PDL_INTC_REG_IPR_ICU_IRQ8 (PDL_INTC_REG_IPR | IPR_ICU_IRQ8) +#define PDL_INTC_REG_IPR_ICU_IRQ9 (PDL_INTC_REG_IPR | IPR_ICU_IRQ9) +#define PDL_INTC_REG_IPR_ICU_IRQ10 (PDL_INTC_REG_IPR | IPR_ICU_IRQ10) +#define PDL_INTC_REG_IPR_ICU_IRQ11 (PDL_INTC_REG_IPR | IPR_ICU_IRQ11) +#define PDL_INTC_REG_IPR_ICU_IRQ12 (PDL_INTC_REG_IPR | IPR_ICU_IRQ12) +#define PDL_INTC_REG_IPR_ICU_IRQ13 (PDL_INTC_REG_IPR | IPR_ICU_IRQ13) +#define PDL_INTC_REG_IPR_ICU_IRQ14 (PDL_INTC_REG_IPR | IPR_ICU_IRQ14) +#define PDL_INTC_REG_IPR_ICU_IRQ15 (PDL_INTC_REG_IPR | IPR_ICU_IRQ15) +#define PDL_INTC_REG_IPR_USB_USBR0 (PDL_INTC_REG_IPR | IPR_USB_USBR0) +#define PDL_INTC_REG_IPR_USB_USBR1 (PDL_INTC_REG_IPR | IPR_USB_USBR1) +#define PDL_INTC_REG_IPR_RTC_ALM (PDL_INTC_REG_IPR | IPR_RTC_ALM) +#define PDL_INTC_REG_IPR_WDT_WOVI (PDL_INTC_REG_IPR | IPR_WDT_WOVI) +#define PDL_INTC_REG_IPR_AD0_ADI (PDL_INTC_REG_IPR | IPR_AD0_ADI0) +#define PDL_INTC_REG_IPR_AD1_ADI (PDL_INTC_REG_IPR | IPR_AD1_ADI1) +#define PDL_INTC_REG_IPR_S12AD_ADI (PDL_INTC_REG_IPR | IPR_S12AD_ADI) +#define PDL_INTC_REG_IPR_MTU0_TGIA (PDL_INTC_REG_IPR | IPR_MTU0_TGIA0) +#define PDL_INTC_REG_IPR_MTU0_TGIB (PDL_INTC_REG_IPR | IPR_MTU0_TGIB0) +#define PDL_INTC_REG_IPR_MTU0_TGIC (PDL_INTC_REG_IPR | IPR_MTU0_TGIC0) +#define PDL_INTC_REG_IPR_MTU0_TGID (PDL_INTC_REG_IPR | IPR_MTU0_TGID0) +#define PDL_INTC_REG_IPR_MTU0_TCIV (PDL_INTC_REG_IPR | IPR_MTU0_TCIV0) +#define PDL_INTC_REG_IPR_MTU0_TGIE (PDL_INTC_REG_IPR | IPR_MTU0_TGIE0) +#define PDL_INTC_REG_IPR_MTU0_TGIF (PDL_INTC_REG_IPR | IPR_MTU0_TGIF0) +#define PDL_INTC_REG_IPR_MTU1_TGIA (PDL_INTC_REG_IPR | IPR_MTU1_TGIA1) +#define PDL_INTC_REG_IPR_MTU1_TGIB (PDL_INTC_REG_IPR | IPR_MTU1_TGIB1) +#define PDL_INTC_REG_IPR_MTU1_TCIV (PDL_INTC_REG_IPR | IPR_MTU1_TCIV1) +#define PDL_INTC_REG_IPR_MTU1_TCIU (PDL_INTC_REG_IPR | IPR_MTU1_TCIU1) +#define PDL_INTC_REG_IPR_MTU2_TGIA (PDL_INTC_REG_IPR | IPR_MTU2_TGIA2) +#define PDL_INTC_REG_IPR_MTU2_TGIB (PDL_INTC_REG_IPR | IPR_MTU2_TGIB2) +#define PDL_INTC_REG_IPR_MTU2_TCIV (PDL_INTC_REG_IPR | IPR_MTU2_TCIV2) +#define PDL_INTC_REG_IPR_MTU2_TCIU (PDL_INTC_REG_IPR | IPR_MTU2_TCIU2) +#define PDL_INTC_REG_IPR_MTU3_TGIA (PDL_INTC_REG_IPR | IPR_MTU3_TGIA3) +#define PDL_INTC_REG_IPR_MTU3_TGIB (PDL_INTC_REG_IPR | IPR_MTU3_TGIB3) +#define PDL_INTC_REG_IPR_MTU3_TGIC (PDL_INTC_REG_IPR | IPR_MTU3_TGIC3) +#define PDL_INTC_REG_IPR_MTU3_TGID (PDL_INTC_REG_IPR | IPR_MTU3_TGID3) +#define PDL_INTC_REG_IPR_MTU3_TCIV (PDL_INTC_REG_IPR | IPR_MTU3_TCIV3) +#define PDL_INTC_REG_IPR_MTU4_TGIA (PDL_INTC_REG_IPR | IPR_MTU4_TGIA4) +#define PDL_INTC_REG_IPR_MTU4_TGIB (PDL_INTC_REG_IPR | IPR_MTU4_TGIB4) +#define PDL_INTC_REG_IPR_MTU4_TGIC (PDL_INTC_REG_IPR | IPR_MTU4_TGIC4) +#define PDL_INTC_REG_IPR_MTU4_TGID (PDL_INTC_REG_IPR | IPR_MTU4_TGID4) +#define PDL_INTC_REG_IPR_MTU4_TCIV (PDL_INTC_REG_IPR | IPR_MTU4_TCIV4) +#define PDL_INTC_REG_IPR_MTU5_TGIU (PDL_INTC_REG_IPR | IPR_MTU5_TGIU5) +#define PDL_INTC_REG_IPR_MTU5_TGIV (PDL_INTC_REG_IPR | IPR_MTU5_TGIV5) +#define PDL_INTC_REG_IPR_MTU5_TGIW (PDL_INTC_REG_IPR | IPR_MTU5_TGIW5) +#define PDL_INTC_REG_IPR_MTU6_TGIA (PDL_INTC_REG_IPR | IPR_MTU6_TGIA6) +#define PDL_INTC_REG_IPR_MTU6_TGIB (PDL_INTC_REG_IPR | IPR_MTU6_TGIB6) +#define PDL_INTC_REG_IPR_MTU6_TGIC (PDL_INTC_REG_IPR | IPR_MTU6_TGIC6) +#define PDL_INTC_REG_IPR_MTU6_TGID (PDL_INTC_REG_IPR | IPR_MTU6_TGID6) +#define PDL_INTC_REG_IPR_MTU6_TCIV (PDL_INTC_REG_IPR | IPR_MTU6_TCIV6) +#define PDL_INTC_REG_IPR_MTU6_TGIE (PDL_INTC_REG_IPR | IPR_MTU6_TGIE6) +#define PDL_INTC_REG_IPR_MTU6_TGIF (PDL_INTC_REG_IPR | IPR_MTU6_TGIF6) +#define PDL_INTC_REG_IPR_MTU7_TGIA (PDL_INTC_REG_IPR | IPR_MTU7_TGIA7) +#define PDL_INTC_REG_IPR_MTU7_TGIB (PDL_INTC_REG_IPR | IPR_MTU7_TGIB7) +#define PDL_INTC_REG_IPR_MTU7_TCIV (PDL_INTC_REG_IPR | IPR_MTU7_TCIV7) +#define PDL_INTC_REG_IPR_MTU7_TCIU (PDL_INTC_REG_IPR | IPR_MTU7_TCIU7) +#define PDL_INTC_REG_IPR_MTU8_TGIA (PDL_INTC_REG_IPR | IPR_MTU8_TGIA8) +#define PDL_INTC_REG_IPR_MTU8_TGIB (PDL_INTC_REG_IPR | IPR_MTU8_TGIB8) +#define PDL_INTC_REG_IPR_MTU8_TCIV (PDL_INTC_REG_IPR | IPR_MTU8_TCIV8) +#define PDL_INTC_REG_IPR_MTU8_TCIU (PDL_INTC_REG_IPR | IPR_MTU8_TCIU8) +#define PDL_INTC_REG_IPR_MTU9_TGIA (PDL_INTC_REG_IPR | IPR_MTU9_TGIA9) +#define PDL_INTC_REG_IPR_MTU9_TGIB (PDL_INTC_REG_IPR | IPR_MTU9_TGIB9) +#define PDL_INTC_REG_IPR_MTU9_TGIC (PDL_INTC_REG_IPR | IPR_MTU9_TGIC9) +#define PDL_INTC_REG_IPR_MTU9_TGID (PDL_INTC_REG_IPR | IPR_MTU9_TGID9) +#define PDL_INTC_REG_IPR_MTU9_TCIV (PDL_INTC_REG_IPR | IPR_MTU9_TCIV9) +#define PDL_INTC_REG_IPR_MTU10_TGIA (PDL_INTC_REG_IPR | IPR_MTU10_TGIA10) +#define PDL_INTC_REG_IPR_MTU10_TGIB (PDL_INTC_REG_IPR | IPR_MTU10_TGIB10) +#define PDL_INTC_REG_IPR_MTU10_TGIC (PDL_INTC_REG_IPR | IPR_MTU10_TGIC10) +#define PDL_INTC_REG_IPR_MTU10_TGID (PDL_INTC_REG_IPR | IPR_MTU10_TGID10) +#define PDL_INTC_REG_IPR_MTU10_TCIV (PDL_INTC_REG_IPR | IPR_MTU10_TCIV10) +#define PDL_INTC_REG_IPR_MTU11_TGIU (PDL_INTC_REG_IPR | IPR_MTU11_TGIU11) +#define PDL_INTC_REG_IPR_MTU11_TGIV (PDL_INTC_REG_IPR | IPR_MTU11_TGIV11) +#define PDL_INTC_REG_IPR_MTU11_TGIW (PDL_INTC_REG_IPR | IPR_MTU11_TGIW11) +#define PDL_INTC_REG_IPR_POE_OEI1 (PDL_INTC_REG_IPR | IPR_POE_OEI1) +#define PDL_INTC_REG_IPR_POE_OEI2 (PDL_INTC_REG_IPR | IPR_POE_OEI2) +#define PDL_INTC_REG_IPR_POE_OEI3 (PDL_INTC_REG_IPR | IPR_POE_OEI3) +#define PDL_INTC_REG_IPR_POE_OEI4 (PDL_INTC_REG_IPR | IPR_POE_OEI4) +#define PDL_INTC_REG_IPR_TMR0_CMIA (PDL_INTC_REG_IPR | IPR_TMR0_CMIA0) +#define PDL_INTC_REG_IPR_TMR0_CMIB (PDL_INTC_REG_IPR | IPR_TMR0_CMIB0) +#define PDL_INTC_REG_IPR_TMR0_OVI (PDL_INTC_REG_IPR | IPR_TMR0_OVI0) +#define PDL_INTC_REG_IPR_TMR1_CMIA (PDL_INTC_REG_IPR | IPR_TMR1_CMIA1) +#define PDL_INTC_REG_IPR_TMR1_CMIB (PDL_INTC_REG_IPR | IPR_TMR1_CMIB1) +#define PDL_INTC_REG_IPR_TMR1_OVI (PDL_INTC_REG_IPR | IPR_TMR1_OVI1) +#define PDL_INTC_REG_IPR_TMR2_CMIA (PDL_INTC_REG_IPR | IPR_TMR2_CMIA2) +#define PDL_INTC_REG_IPR_TMR2_CMIB (PDL_INTC_REG_IPR | IPR_TMR2_CMIB2) +#define PDL_INTC_REG_IPR_TMR2_OVI (PDL_INTC_REG_IPR | IPR_TMR2_OVI2) +#define PDL_INTC_REG_IPR_TMR3_CMIA (PDL_INTC_REG_IPR | IPR_TMR3_CMIA3) +#define PDL_INTC_REG_IPR_TMR3_CMIB (PDL_INTC_REG_IPR | IPR_TMR3_CMIB3) +#define PDL_INTC_REG_IPR_TMR3_OVI (PDL_INTC_REG_IPR | IPR_TMR3_OVI3) +#define PDL_INTC_REG_IPR_DMAC_DMAC0I (PDL_INTC_REG_IPR | IPR_DMAC_DMAC0I) +#define PDL_INTC_REG_IPR_DMAC_DMAC1I (PDL_INTC_REG_IPR | IPR_DMAC_DMAC1I) +#define PDL_INTC_REG_IPR_DMAC_DMAC2I (PDL_INTC_REG_IPR | IPR_DMAC_DMAC2I) +#define PDL_INTC_REG_IPR_DMAC_DMAC3I (PDL_INTC_REG_IPR | IPR_DMAC_DMAC3I) +#define PDL_INTC_REG_IPR_EXDMAC_EXDMAC0I (PDL_INTC_REG_IPR | IPR_EXDMAC_EXDMAC0I) +#define PDL_INTC_REG_IPR_EXDMAC_EXDMAC1I (PDL_INTC_REG_IPR | IPR_EXDMAC_EXDMAC1I) +#define PDL_INTC_REG_IPR_SCI0_ERI (PDL_INTC_REG_IPR | IPR_SCI0_ERI0) +#define PDL_INTC_REG_IPR_SCI0_RXI (PDL_INTC_REG_IPR | IPR_SCI0_RXI0) +#define PDL_INTC_REG_IPR_SCI0_TXI (PDL_INTC_REG_IPR | IPR_SCI0_TXI0) +#define PDL_INTC_REG_IPR_SCI0_TEI (PDL_INTC_REG_IPR | IPR_SCI0_TEI0) +#define PDL_INTC_REG_IPR_SCI1_ERI (PDL_INTC_REG_IPR | IPR_SCI1_ERI1) +#define PDL_INTC_REG_IPR_SCI1_RXI (PDL_INTC_REG_IPR | IPR_SCI1_RXI1) +#define PDL_INTC_REG_IPR_SCI1_TXI (PDL_INTC_REG_IPR | IPR_SCI1_TXI1) +#define PDL_INTC_REG_IPR_SCI1_TEI (PDL_INTC_REG_IPR | IPR_SCI1_TEI1) +#define PDL_INTC_REG_IPR_SCI2_ERI (PDL_INTC_REG_IPR | IPR_SCI2_ERI2) +#define PDL_INTC_REG_IPR_SCI2_RXI (PDL_INTC_REG_IPR | IPR_SCI2_RXI2) +#define PDL_INTC_REG_IPR_SCI2_TXI (PDL_INTC_REG_IPR | IPR_SCI2_TXI2) +#define PDL_INTC_REG_IPR_SCI2_TEI (PDL_INTC_REG_IPR | IPR_SCI2_TEI2) +#define PDL_INTC_REG_IPR_SCI3_ERI (PDL_INTC_REG_IPR | IPR_SCI3_ERI3) +#define PDL_INTC_REG_IPR_SCI3_RXI (PDL_INTC_REG_IPR | IPR_SCI3_RXI3) +#define PDL_INTC_REG_IPR_SCI3_TXI (PDL_INTC_REG_IPR | IPR_SCI3_TXI3) +#define PDL_INTC_REG_IPR_SCI3_TEI (PDL_INTC_REG_IPR | IPR_SCI3_TEI3) +#define PDL_INTC_REG_IPR_SCI5_ERI (PDL_INTC_REG_IPR | IPR_SCI5_ERI5) +#define PDL_INTC_REG_IPR_SCI5_RXI (PDL_INTC_REG_IPR | IPR_SCI5_RXI5) +#define PDL_INTC_REG_IPR_SCI5_TXI (PDL_INTC_REG_IPR | IPR_SCI5_TXI5) +#define PDL_INTC_REG_IPR_SCI5_TEI (PDL_INTC_REG_IPR | IPR_SCI5_TEI5) +#define PDL_INTC_REG_IPR_SCI6_ERI (PDL_INTC_REG_IPR | IPR_SCI6_ERI6) +#define PDL_INTC_REG_IPR_SCI6_RXI (PDL_INTC_REG_IPR | IPR_SCI6_RXI6) +#define PDL_INTC_REG_IPR_SCI6_TXI (PDL_INTC_REG_IPR | IPR_SCI6_TXI6) +#define PDL_INTC_REG_IPR_SCI6_TEI (PDL_INTC_REG_IPR | IPR_SCI6_TEI6) +#define PDL_INTC_REG_IPR_IIC0_EEI (PDL_INTC_REG_IPR | IPR_RIIC0_ICEEI0) +#define PDL_INTC_REG_IPR_IIC0_RXI (PDL_INTC_REG_IPR | IPR_RIIC0_ICRXI0) +#define PDL_INTC_REG_IPR_IIC0_TXI (PDL_INTC_REG_IPR | IPR_RIIC0_ICTXI0) +#define PDL_INTC_REG_IPR_IIC0_TEI (PDL_INTC_REG_IPR | IPR_RIIC0_ICTEI0) +#define PDL_INTC_REG_IPR_IIC1_EEI (PDL_INTC_REG_IPR | IPR_RIIC1_ICEEI1) +#define PDL_INTC_REG_IPR_IIC1_RXI (PDL_INTC_REG_IPR | IPR_RIIC1_ICRXI1) +#define PDL_INTC_REG_IPR_IIC1_TXI (PDL_INTC_REG_IPR | IPR_RIIC1_ICTXI1) +#define PDL_INTC_REG_IPR_IIC1_TEI (PDL_INTC_REG_IPR | IPR_RIIC1_ICTEI1) + +/* DTCER registers */ +#define PDL_INTC_REG_DTCER_ICU_SWINT (PDL_INTC_REG_DTCER | DTCE_ICU_SWINT) +#define PDL_INTC_REG_DTCER_CMT0_CMI (PDL_INTC_REG_DTCER | DTCE_CMT0_CMI0) +#define PDL_INTC_REG_DTCER_CMT1_CMI (PDL_INTC_REG_DTCER | DTCE_CMT1_CMI1) +#define PDL_INTC_REG_DTCER_CMT2_CMI (PDL_INTC_REG_DTCER | DTCE_CMT2_CMI2) +#define PDL_INTC_REG_DTCER_CMT3_CMI (PDL_INTC_REG_DTCER | DTCE_CMT3_CMI3) +#define PDL_INTC_REG_DTCER_USB0_D0FIFO (PDL_INTC_REG_DTCER | DTCE_USB0_D0FIFO0) +#define PDL_INTC_REG_DTCER_USB0_D1FIFO (PDL_INTC_REG_DTCER | DTCE_USB0_D1FIFO0) +#define PDL_INTC_REG_DTCER_USB1_D0FIFO (PDL_INTC_REG_DTCER | DTCE_USB1_D0FIFO1) +#define PDL_INTC_REG_DTCER_USB1_D1FIFO (PDL_INTC_REG_DTCER | DTCE_USB1_D1FIFO1) +#define PDL_INTC_REG_DTCER_SPI0_SPRI (PDL_INTC_REG_DTCER | DTCE_RSPI0_SPRI0) +#define PDL_INTC_REG_DTCER_SPI0_SPTI (PDL_INTC_REG_DTCER | DTCE_RSPI0_SPTI0) +#define PDL_INTC_REG_DTCER_SPI1_SPRI (PDL_INTC_REG_DTCER | DTCE_RSPI1_SPRI1) +#define PDL_INTC_REG_DTCER_SPI1_SPTI (PDL_INTC_REG_DTCER | DTCE_RSPI1_SPTI1) +#define PDL_INTC_REG_DTCER_ICU_IRQ0 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ0) +#define PDL_INTC_REG_DTCER_ICU_IRQ1 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ1) +#define PDL_INTC_REG_DTCER_ICU_IRQ2 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ2) +#define PDL_INTC_REG_DTCER_ICU_IRQ3 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ3) +#define PDL_INTC_REG_DTCER_ICU_IRQ4 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ4) +#define PDL_INTC_REG_DTCER_ICU_IRQ5 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ5) +#define PDL_INTC_REG_DTCER_ICU_IRQ6 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ6) +#define PDL_INTC_REG_DTCER_ICU_IRQ7 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ7) +#define PDL_INTC_REG_DTCER_ICU_IRQ8 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ8) +#define PDL_INTC_REG_DTCER_ICU_IRQ9 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ9) +#define PDL_INTC_REG_DTCER_ICU_IRQ10 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ10) +#define PDL_INTC_REG_DTCER_ICU_IRQ11 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ11) +#define PDL_INTC_REG_DTCER_ICU_IRQ12 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ12) +#define PDL_INTC_REG_DTCER_ICU_IRQ13 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ13) +#define PDL_INTC_REG_DTCER_ICU_IRQ14 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ14) +#define PDL_INTC_REG_DTCER_ICU_IRQ15 (PDL_INTC_REG_DTCER | DTCE_ICU_IRQ15) +#define PDL_INTC_REG_DTCER_AD0_ADI (PDL_INTC_REG_DTCER | DTCE_AD0_ADI0) +#define PDL_INTC_REG_DTCER_AD1_ADI (PDL_INTC_REG_DTCER | DTCE_AD1_ADI1) +#define PDL_INTC_REG_DTCER_S12AD_ADI (PDL_INTC_REG_DTCER | DTCE_S12AD_ADI) +#define PDL_INTC_REG_DTCER_MTU0_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU0_TGIA0) +#define PDL_INTC_REG_DTCER_MTU0_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU0_TGIB0) +#define PDL_INTC_REG_DTCER_MTU0_TGIC (PDL_INTC_REG_DTCER | DTCE_MTU0_TGIC0) +#define PDL_INTC_REG_DTCER_MTU0_TGID (PDL_INTC_REG_DTCER | DTCE_MTU0_TGID0) +#define PDL_INTC_REG_DTCER_MTU1_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU1_TGIA1) +#define PDL_INTC_REG_DTCER_MTU1_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU1_TGIB1) +#define PDL_INTC_REG_DTCER_MTU2_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU2_TGIA2) +#define PDL_INTC_REG_DTCER_MTU2_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU2_TGIB2) +#define PDL_INTC_REG_DTCER_MTU3_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU3_TGIA3) +#define PDL_INTC_REG_DTCER_MTU3_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU3_TGIB3) +#define PDL_INTC_REG_DTCER_MTU3_TGIC (PDL_INTC_REG_DTCER | DTCE_MTU3_TGIC3) +#define PDL_INTC_REG_DTCER_MTU3_TGID (PDL_INTC_REG_DTCER | DTCE_MTU3_TGID3) +#define PDL_INTC_REG_DTCER_MTU4_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU4_TGIA4) +#define PDL_INTC_REG_DTCER_MTU4_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU4_TGIB4) +#define PDL_INTC_REG_DTCER_MTU4_TGIC (PDL_INTC_REG_DTCER | DTCE_MTU4_TGIC4) +#define PDL_INTC_REG_DTCER_MTU4_TGID (PDL_INTC_REG_DTCER | DTCE_MTU4_TGID4) +#define PDL_INTC_REG_DTCER_MTU4_TCIV (PDL_INTC_REG_DTCER | DTCE_MTU4_TCIV4) +#define PDL_INTC_REG_DTCER_MTU5_TGIU (PDL_INTC_REG_DTCER | DTCE_MTU5_TGIU5) +#define PDL_INTC_REG_DTCER_MTU5_TGIV (PDL_INTC_REG_DTCER | DTCE_MTU5_TGIV5) +#define PDL_INTC_REG_DTCER_MTU5_TGIW (PDL_INTC_REG_DTCER | DTCE_MTU5_TGIW5) +#define PDL_INTC_REG_DTCER_MTU6_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU6_TGIA6) +#define PDL_INTC_REG_DTCER_MTU6_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU6_TGIB6) +#define PDL_INTC_REG_DTCER_MTU6_TGIC (PDL_INTC_REG_DTCER | DTCE_MTU6_TGIC6) +#define PDL_INTC_REG_DTCER_MTU6_TGID (PDL_INTC_REG_DTCER | DTCE_MTU6_TGID6) +#define PDL_INTC_REG_DTCER_MTU7_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU7_TGIA7) +#define PDL_INTC_REG_DTCER_MTU7_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU7_TGIB7) +#define PDL_INTC_REG_DTCER_MTU8_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU8_TGIA8) +#define PDL_INTC_REG_DTCER_MTU8_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU8_TGIB8) +#define PDL_INTC_REG_DTCER_MTU9_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU9_TGIA9) +#define PDL_INTC_REG_DTCER_MTU9_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU9_TGIB9) +#define PDL_INTC_REG_DTCER_MTU9_TGIC (PDL_INTC_REG_DTCER | DTCE_MTU9_TGIC9) +#define PDL_INTC_REG_DTCER_MTU9_TGID (PDL_INTC_REG_DTCER | DTCE_MTU9_TGID9) +#define PDL_INTC_REG_DTCER_MTU10_TGIA (PDL_INTC_REG_DTCER | DTCE_MTU10_TGIA10) +#define PDL_INTC_REG_DTCER_MTU10_TGIB (PDL_INTC_REG_DTCER | DTCE_MTU10_TGIB10) +#define PDL_INTC_REG_DTCER_MTU10_TGIC (PDL_INTC_REG_DTCER | DTCE_MTU10_TGIC10) +#define PDL_INTC_REG_DTCER_MTU10_TGID (PDL_INTC_REG_DTCER | DTCE_MTU10_TGID10) +#define PDL_INTC_REG_DTCER_MTU10_TCIV (PDL_INTC_REG_DTCER | DTCE_MTU10_TCIV10) +#define PDL_INTC_REG_DTCER_MTU11_TGIU (PDL_INTC_REG_DTCER | DTCE_MTU11_TGIU11) +#define PDL_INTC_REG_DTCER_MTU11_TGIV (PDL_INTC_REG_DTCER | DTCE_MTU11_TGIV11) +#define PDL_INTC_REG_DTCER_MTU11_TGIW (PDL_INTC_REG_DTCER | DTCE_MTU11_TGIW11) +#define PDL_INTC_REG_DTCER_TMR0_CMIA0 (PDL_INTC_REG_DTCER | DTCE_TMR0_CMIA0) +#define PDL_INTC_REG_DTCER_TMR0_CMIB0 (PDL_INTC_REG_DTCER | DTCE_TMR0_CMIB0) +#define PDL_INTC_REG_DTCER_TMR1_CMIA (PDL_INTC_REG_DTCER | DTCE_TMR1_CMIA1) +#define PDL_INTC_REG_DTCER_TMR1_CMIB (PDL_INTC_REG_DTCER | DTCE_TMR1_CMIB1) +#define PDL_INTC_REG_DTCER_TMR2_CMIA (PDL_INTC_REG_DTCER | DTCE_TMR2_CMIA2) +#define PDL_INTC_REG_DTCER_TMR2_CMIB (PDL_INTC_REG_DTCER | DTCE_TMR2_CMIB2) +#define PDL_INTC_REG_DTCER_TMR3_CMIA (PDL_INTC_REG_DTCER | DTCE_TMR3_CMIA3) +#define PDL_INTC_REG_DTCER_TMR3_CMIB (PDL_INTC_REG_DTCER | DTCE_TMR3_CMIB3) +#define PDL_INTC_REG_DTCER_DMAC_DMAC0I (PDL_INTC_REG_DTCER | DTCE_DMAC_DMAC0I) +#define PDL_INTC_REG_DTCER_DMAC_DMAC1I (PDL_INTC_REG_DTCER | DTCE_DMAC_DMAC1I) +#define PDL_INTC_REG_DTCER_DMAC_DMAC2I (PDL_INTC_REG_DTCER | DTCE_DMAC_DMAC2I) +#define PDL_INTC_REG_DTCER_DMAC_DMAC3I (PDL_INTC_REG_DTCER | DTCE_DMAC_DMAC3I) +#define PDL_INTC_REG_DTCER_EXDMAC_EXDMAC0I (PDL_INTC_REG_DTCER | DTCE_EXDMAC_EXDMAC0I) +#define PDL_INTC_REG_DTCER_EXDMAC_EXDMAC1I (PDL_INTC_REG_DTCER | DTCE_EXDMAC_EXDMAC1I) +#define PDL_INTC_REG_DTCER_SCI0_RXI (PDL_INTC_REG_DTCER | DTCE_SCI0_RXI0) +#define PDL_INTC_REG_DTCER_SCI0_TXI (PDL_INTC_REG_DTCER | DTCE_SCI0_TXI0) +#define PDL_INTC_REG_DTCER_SCI1_RXI (PDL_INTC_REG_DTCER | DTCE_SCI1_RXI1) +#define PDL_INTC_REG_DTCER_SCI1_TXI (PDL_INTC_REG_DTCER | DTCE_SCI1_TXI1) +#define PDL_INTC_REG_DTCER_SCI2_RXI (PDL_INTC_REG_DTCER | DTCE_SCI2_RXI2) +#define PDL_INTC_REG_DTCER_SCI2_TXI (PDL_INTC_REG_DTCER | DTCE_SCI2_TXI2) +#define PDL_INTC_REG_DTCER_SCI3_RXI (PDL_INTC_REG_DTCER | DTCE_SCI3_RXI3) +#define PDL_INTC_REG_DTCER_SCI3_TXI (PDL_INTC_REG_DTCER | DTCE_SCI3_TXI3) +#define PDL_INTC_REG_DTCER_SCI5_RXI (PDL_INTC_REG_DTCER | DTCE_SCI5_RXI5) +#define PDL_INTC_REG_DTCER_SCI5_TXI (PDL_INTC_REG_DTCER | DTCE_SCI5_TXI5) +#define PDL_INTC_REG_DTCER_SCI6_RXI (PDL_INTC_REG_DTCER | DTCE_SCI6_RXI6) +#define PDL_INTC_REG_DTCER_SCI6_TXI (PDL_INTC_REG_DTCER | DTCE_SCI6_TXI6) +#define PDL_INTC_REG_DTCER_IIC0_RXI (PDL_INTC_REG_DTCER | DTCE_RIIC0_ICRXI0) +#define PDL_INTC_REG_DTCER_IIC0_TXI (PDL_INTC_REG_DTCER | DTCE_RIIC0_ICTXI0) +#define PDL_INTC_REG_DTCER_IIC1_RXI (PDL_INTC_REG_DTCER | DTCE_RIIC1_ICRXI1) +#define PDL_INTC_REG_DTCER_IIC1_TXI (PDL_INTC_REG_DTCER | DTCE_RIIC1_ICTXI1) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_intc_rx62nxx.h b/bsp/rx/RPDL/r_pdl_intc_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..aad34d6a474a968a9ad93e9829b4ccf99adc6e6e --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_intc_rx62nxx.h @@ -0,0 +1,118 @@ +/*""FILE COMMENT""******************************************************* +* System Name : External interrupt API for RX62Nxx +* File Name : r_pdl_intc_RX62Nxx.h +* Version : 1.02 +* Contents : INTC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_INTC_RX62Nxx_H +#define R_PDL_INTC_RX62Nxx_H + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_INTC_callback_func[]; + +/* Library prototypes */ +bool R_INTC_CreateExtInterruptAll( + const uint8_t, + const uint32_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_INTC_CreateSoftwareInterruptAll( + const uint8_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_INTC_CreateFastInterruptAll( + const uint8_t +); +bool R_INTC_CreateExceptionHandlersAll( + VoidCallBackFunc const, + VoidCallBackFunc const, + VoidCallBackFunc const +); +bool R_INTC_ControlExtInterruptAll( + const uint8_t, + const uint32_t +); +bool R_INTC_GetExtInterruptStatusAll( + const uint8_t, + volatile uint8_t * const +); +bool R_INTC_ReadAll( + const uint16_t, + volatile uint8_t * const +); +bool R_INTC_WriteAll( + const uint16_t, + const uint8_t +); +bool R_INTC_ModifyAll( + const uint16_t, + const uint8_t, + const uint8_t +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_INTC_CreateExtInterrupt(a, b, c, d) \ +( \ +( ( (a) <= PDL_INTC_NMI ) && ((d) <= IPL_MAX) ) ? \ +R_INTC_CreateExtInterruptAll( (a), (b), (c), (d) ) : \ +ReturnFalse() \ +) + +#define R_INTC_CreateSoftwareInterrupt(a, b, c) \ +( \ +( (c) <= IPL_MAX ) ? \ +R_INTC_CreateSoftwareInterruptAll( (a), (b), (c) ) : \ +ReturnFalse() \ +) + +#define R_INTC_ControlExtInterrupt(a, b) \ +( \ +( (a) <= PDL_INTC_NMI ) ? \ +R_INTC_ControlExtInterruptAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_INTC_GetExtInterruptStatus(a, b) \ +( \ +( (a) <= PDL_INTC_NMI ) ? \ +R_INTC_GetExtInterruptStatusAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_INTC_CreateFastInterrupt(a) \ +( R_INTC_CreateFastInterruptAll( (a) ) ) + +#define R_INTC_CreateExceptionHandlers(a, b, c) \ +( R_INTC_CreateExceptionHandlersAll( (a), (b), (c) ) ) + +#define R_INTC_Read(a, b) \ +( R_INTC_ReadAll( (a), (b) ) ) + +#define R_INTC_Write(a, b) \ +( R_INTC_WriteAll( (a), (b) ) ) + +#define R_INTC_Modify(a, b, c) \ +( R_INTC_ModifyAll( (a), (b), (c) ) ) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_io_port.h b/bsp/rx/RPDL/r_pdl_io_port.h new file mode 100644 index 0000000000000000000000000000000000000000..04647f0c41fa9377d0c3579eed67dddee64d168c --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_io_port.h @@ -0,0 +1,252 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I/O Port API +* File Name : r_pdl_io_port.h +* Version : 1.02 +* Contents : I/O Port API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IO_PORT_H +#define R_PDL_IO_PORT_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_IO_PORT_Set( + uint16_t, + uint8_t +); +bool R_IO_PORT_ReadControl( + uint16_t, + uint8_t, + uint8_t * +); +bool R_IO_PORT_ModifyControl( + uint16_t, + uint8_t, + uint8_t +); +bool R_IO_PORT_Read( + uint16_t, + uint8_t * +); +bool R_IO_PORT_Write( + uint16_t, + uint8_t +); +bool R_IO_PORT_Compare( + uint16_t, + uint8_t, + void * +); +bool R_IO_PORT_Modify( + uint16_t, + uint8_t, + uint8_t +); +bool R_IO_PORT_Wait( + uint16_t, + uint8_t +); + +/* I/O Ports*/ +#define PDL_IO_PORT_0 0xF000u /* Port 0 */ +#define PDL_IO_PORT_1 0xF001u /* Port 1 */ +#define PDL_IO_PORT_2 0xF002u /* Port 2 */ +#define PDL_IO_PORT_3 0xF003u /* Port 3 */ +#define PDL_IO_PORT_4 0xF004u /* Port 4 */ +#define PDL_IO_PORT_5 0xF005u /* Port 5 */ +#define PDL_IO_PORT_6 0xF006u /* Port 6 */ +#define PDL_IO_PORT_7 0xF007u /* Port 7 */ +#define PDL_IO_PORT_8 0xF008u /* Port 8 */ +#define PDL_IO_PORT_9 0xF009u /* Port 9 */ +#define PDL_IO_PORT_A 0xF00Au /* Port A */ +#define PDL_IO_PORT_B 0xF00Bu /* Port B */ +#define PDL_IO_PORT_C 0xF00Cu /* Port C */ +#define PDL_IO_PORT_D 0xF00Du /* Port D */ +#define PDL_IO_PORT_E 0xF00Eu /* Port E */ +#define PDL_IO_PORT_F 0xF00Fu /* Port F */ +#define PDL_IO_PORT_G 0xF010u /* Port G */ + +/* I/O port pins */ +#define PDL_IO_PORT_0_0 0x0001u /* P00 */ +#define PDL_IO_PORT_0_1 0x0002u /* P01 */ +#define PDL_IO_PORT_0_2 0x0004u /* P02 */ +#define PDL_IO_PORT_0_3 0x0008u /* P03 */ +#define PDL_IO_PORT_0_5 0x0020u /* P05 */ +#define PDL_IO_PORT_0_7 0x0080u /* P07 */ + +#define PDL_IO_PORT_1_0 0x0101u /* P10 */ +#define PDL_IO_PORT_1_1 0x0102u /* P11 */ +#define PDL_IO_PORT_1_2 0x0104u /* P12 */ +#define PDL_IO_PORT_1_3 0x0108u /* P13 */ +#define PDL_IO_PORT_1_4 0x0110u /* P14 */ +#define PDL_IO_PORT_1_5 0x0120u /* P15 */ +#define PDL_IO_PORT_1_6 0x0140u /* P16 */ +#define PDL_IO_PORT_1_7 0x0180u /* P17 */ + +#define PDL_IO_PORT_2_0 0x0201u /* P20 */ +#define PDL_IO_PORT_2_1 0x0202u /* P21 */ +#define PDL_IO_PORT_2_2 0x0204u /* P22 */ +#define PDL_IO_PORT_2_3 0x0208u /* P23 */ +#define PDL_IO_PORT_2_4 0x0210u /* P24 */ +#define PDL_IO_PORT_2_5 0x0220u /* P25 */ +#define PDL_IO_PORT_2_6 0x0240u /* P26 */ +#define PDL_IO_PORT_2_7 0x0280u /* P27 */ + +#define PDL_IO_PORT_3_0 0x0301u /* P30 */ +#define PDL_IO_PORT_3_1 0x0302u /* P31 */ +#define PDL_IO_PORT_3_2 0x0304u /* P32 */ +#define PDL_IO_PORT_3_3 0x0308u /* P33 */ +#define PDL_IO_PORT_3_4 0x0310u /* P34 */ +#define PDL_IO_PORT_3_5 0x0320u /* P35 */ + +#define PDL_IO_PORT_4_0 0x0401u /* P40 */ +#define PDL_IO_PORT_4_1 0x0402u /* P41 */ +#define PDL_IO_PORT_4_2 0x0404u /* P42 */ +#define PDL_IO_PORT_4_3 0x0408u /* P43 */ +#define PDL_IO_PORT_4_4 0x0410u /* P44 */ +#define PDL_IO_PORT_4_5 0x0420u /* P45 */ +#define PDL_IO_PORT_4_6 0x0440u /* P46 */ +#define PDL_IO_PORT_4_7 0x0480u /* P47 */ + +#define PDL_IO_PORT_5_0 0x0501u /* P50 */ +#define PDL_IO_PORT_5_1 0x0502u /* P51 */ +#define PDL_IO_PORT_5_2 0x0504u /* P52 */ +#define PDL_IO_PORT_5_3 0x0508u /* P53 */ +#define PDL_IO_PORT_5_4 0x0510u /* P54 */ +#define PDL_IO_PORT_5_5 0x0520u /* P55 */ +#define PDL_IO_PORT_5_6 0x0540u /* P56 */ +#define PDL_IO_PORT_5_7 0x0580u /* P57 */ + +#define PDL_IO_PORT_6_0 0x0601u /* P60 */ +#define PDL_IO_PORT_6_1 0x0602u /* P61 */ +#define PDL_IO_PORT_6_2 0x0604u /* P62 */ +#define PDL_IO_PORT_6_3 0x0608u /* P63 */ +#define PDL_IO_PORT_6_4 0x0610u /* P64 */ +#define PDL_IO_PORT_6_5 0x0620u /* P65 */ +#define PDL_IO_PORT_6_6 0x0640u /* P66 */ +#define PDL_IO_PORT_6_7 0x0680u /* P67 */ + +#define PDL_IO_PORT_7_0 0x0701u /* P70 */ +#define PDL_IO_PORT_7_1 0x0702u /* P71 */ +#define PDL_IO_PORT_7_2 0x0704u /* P72 */ +#define PDL_IO_PORT_7_3 0x0708u /* P73 */ +#define PDL_IO_PORT_7_4 0x0710u /* P74 */ +#define PDL_IO_PORT_7_5 0x0720u /* P75 */ +#define PDL_IO_PORT_7_6 0x0740u /* P76 */ +#define PDL_IO_PORT_7_7 0x0780u /* P77 */ + +#define PDL_IO_PORT_8_0 0x0801u /* P80 */ +#define PDL_IO_PORT_8_1 0x0802u /* P81 */ +#define PDL_IO_PORT_8_2 0x0804u /* P82 */ +#define PDL_IO_PORT_8_3 0x0808u /* P83 */ +#define PDL_IO_PORT_8_4 0x0810u /* P84 */ +#define PDL_IO_PORT_8_5 0x0820u /* P85 */ + +#define PDL_IO_PORT_9_0 0x0901u /* P90 */ +#define PDL_IO_PORT_9_1 0x0902u /* P91 */ +#define PDL_IO_PORT_9_2 0x0904u /* P92 */ +#define PDL_IO_PORT_9_3 0x0908u /* P93 */ +#define PDL_IO_PORT_9_4 0x0910u /* P94 */ +#define PDL_IO_PORT_9_5 0x0920u /* P95 */ +#define PDL_IO_PORT_9_6 0x0940u /* P96 */ +#define PDL_IO_PORT_9_7 0x0980u /* P97 */ + +#define PDL_IO_PORT_A_0 0x0A01u /* PA0 */ +#define PDL_IO_PORT_A_1 0x0A02u /* PA1 */ +#define PDL_IO_PORT_A_2 0x0A04u /* PA2 */ +#define PDL_IO_PORT_A_3 0x0A08u /* PA3 */ +#define PDL_IO_PORT_A_4 0x0A10u /* PA4 */ +#define PDL_IO_PORT_A_5 0x0A20u /* PA5 */ +#define PDL_IO_PORT_A_6 0x0A40u /* PA6 */ +#define PDL_IO_PORT_A_7 0x0A80u /* PA7 */ + +#define PDL_IO_PORT_B_0 0x0B01u /* PB0 */ +#define PDL_IO_PORT_B_1 0x0B02u /* PB1 */ +#define PDL_IO_PORT_B_2 0x0B04u /* PB2 */ +#define PDL_IO_PORT_B_3 0x0B08u /* PB3 */ +#define PDL_IO_PORT_B_4 0x0B10u /* PB4 */ +#define PDL_IO_PORT_B_5 0x0B20u /* PB5 */ +#define PDL_IO_PORT_B_6 0x0B40u /* PB6 */ +#define PDL_IO_PORT_B_7 0x0B80u /* PB7 */ + +#define PDL_IO_PORT_C_0 0x0C01u /* PC0 */ +#define PDL_IO_PORT_C_1 0x0C02u /* PC1 */ +#define PDL_IO_PORT_C_2 0x0C04u /* PC2 */ +#define PDL_IO_PORT_C_3 0x0C08u /* PC3 */ +#define PDL_IO_PORT_C_4 0x0C10u /* PC4 */ +#define PDL_IO_PORT_C_5 0x0C20u /* PC5 */ +#define PDL_IO_PORT_C_6 0x0C40u /* PC6 */ +#define PDL_IO_PORT_C_7 0x0C80u /* PC7 */ + +#define PDL_IO_PORT_D_0 0x0D01u /* PD0 */ +#define PDL_IO_PORT_D_1 0x0D02u /* PD1 */ +#define PDL_IO_PORT_D_2 0x0D04u /* PD2 */ +#define PDL_IO_PORT_D_3 0x0D08u /* PD3 */ +#define PDL_IO_PORT_D_4 0x0D10u /* PD4 */ +#define PDL_IO_PORT_D_5 0x0D20u /* PD5 */ +#define PDL_IO_PORT_D_6 0x0D40u /* PD6 */ +#define PDL_IO_PORT_D_7 0x0D80u /* PD7 */ + +#define PDL_IO_PORT_E_0 0x0E01u /* PE0 */ +#define PDL_IO_PORT_E_1 0x0E02u /* PE1 */ +#define PDL_IO_PORT_E_2 0x0E04u /* PE2 */ +#define PDL_IO_PORT_E_3 0x0E08u /* PE3 */ +#define PDL_IO_PORT_E_4 0x0E10u /* PE4 */ +#define PDL_IO_PORT_E_5 0x0E20u /* PE5 */ +#define PDL_IO_PORT_E_6 0x0E40u /* PE6 */ +#define PDL_IO_PORT_E_7 0x0E80u /* PE7 */ + +#define PDL_IO_PORT_F_0 0x0F01u /* PF0 */ +#define PDL_IO_PORT_F_1 0x0F02u /* PF1 */ +#define PDL_IO_PORT_F_2 0x0F04u /* PF2 */ +#define PDL_IO_PORT_F_3 0x0F08u /* PF3 */ +#define PDL_IO_PORT_F_4 0x0F10u /* PF4 */ + +#define PDL_IO_PORT_G_0 0x1001u /* PG0 */ +#define PDL_IO_PORT_G_1 0x1002u /* PG1 */ +#define PDL_IO_PORT_G_2 0x1004u /* PG2 */ +#define PDL_IO_PORT_G_3 0x1008u /* PG3 */ +#define PDL_IO_PORT_G_4 0x1010u /* PG4 */ +#define PDL_IO_PORT_G_5 0x1020u /* PG5 */ +#define PDL_IO_PORT_G_6 0x1040u /* PG6 */ +#define PDL_IO_PORT_G_7 0x1080u /* PG7 */ + +/* Settings */ +#define PDL_IO_PORT_INPUT 0x01u /* Input port */ +#define PDL_IO_PORT_OUTPUT 0x02u /* Output port */ +#define PDL_IO_PORT_INPUT_BUFFER_ON 0x04u /* The input buffer is enabled */ +#define PDL_IO_PORT_INPUT_BUFFER_OFF 0x08u /* The input buffer is disabled */ +#define PDL_IO_PORT_PULL_UP_ON 0x10u /* Pulled high */ +#define PDL_IO_PORT_PULL_UP_OFF 0x20u /* Not pulled high */ +#define PDL_IO_PORT_OPEN_DRAIN 0x40u /* NMOS open-drain output */ +#define PDL_IO_PORT_CMOS 0x80u /* CMOS output */ + +/* Control register selection */ +#define PDL_IO_PORT_DIRECTION 0x01u +#define PDL_IO_PORT_INPUT_BUFFER 0x02u +#define PDL_IO_PORT_PULL_UP 0x04u +#define PDL_IO_PORT_TYPE 0x08u + +/* Logical operations */ +#define PDL_IO_PORT_AND 0x10u +#define PDL_IO_PORT_OR 0x20u +#define PDL_IO_PORT_XOR 0x40u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_io_port_rx62nxbg.h b/bsp/rx/RPDL/r_pdl_io_port_rx62nxbg.h new file mode 100644 index 0000000000000000000000000000000000000000..53f7aeea86110a19106abad814d9591fd298ac6d --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_io_port_rx62nxbg.h @@ -0,0 +1,200 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I/O Port API for RX62N (176-pin LFBGA) +* File Name : r_pdl_io_port_RX62NxBG.h +* Version : 1.02 +* Contents : I/O Port API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IO_PORT_RX62NxBG_H +#define R_PDL_IO_PORT_RX62NxBG_H + +/* Library prototypes */ +bool R_IO_PORT_SetAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadControlRegisterAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ModifyControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyControlRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadDataAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadDataRegisterAll( + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_WriteAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WriteRegisterAll( + const uint8_t, + const uint8_t +); +bool R_IO_PORT_CompareAll( + const uint8_t, + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_CompareRegisterAll( + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_ModifyDataAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyDataRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitRegisterAll( + const uint8_t, + const uint8_t +); +bool ReturnFalse(void); + +/* Macro definitions */ + +/* R_IO_PORT_Set */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Set(a, b) \ +( \ +( ((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7) ) ? \ +R_IO_PORT_SetAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ReadControl */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_ReadControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7)) ) ? \ +R_IO_PORT_ReadControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_G) ) ? \ +R_IO_PORT_ReadControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ModifyControl */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_ModifyControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7)) ) ? \ +R_IO_PORT_ModifyControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_G) ) ? \ +R_IO_PORT_ModifyControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Read */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Read(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7)) ) ? \ +R_IO_PORT_ReadDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_G) ) ? \ +R_IO_PORT_ReadDataRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Write */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Write(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7)) ) ? \ +R_IO_PORT_WriteAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_G) ) ? \ +R_IO_PORT_WriteRegisterAll( (uint8_t)(a), (b) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Compare */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Compare(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7)) ) ? \ +R_IO_PORT_CompareAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_G) ) ? \ +R_IO_PORT_CompareRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Modify */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Modify(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7)) ) ? \ +R_IO_PORT_ModifyDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_G) ) ? \ +R_IO_PORT_ModifyDataRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Wait */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Wait(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7)) && (b == 1u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)(a) ) : \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_G_7)) && (b == 0u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), 0 ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_G) ) ? \ +R_IO_PORT_WaitRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_io_port_rx62nxfb.h b/bsp/rx/RPDL/r_pdl_io_port_rx62nxfb.h new file mode 100644 index 0000000000000000000000000000000000000000..7c3e19187f386cf3ec95b7756af8c315da537b02 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_io_port_rx62nxfb.h @@ -0,0 +1,201 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I/O Port API for RX62N (144-pin LQFP) +* File Name : r_pdl_io_port_RX62NxFB.h +* Version : 1.02 +* Contents : I/O Port API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IO_PORT_RX62NxFB_H +#define R_PDL_IO_PORT_RX62NxFB_H + +/* Library prototypes */ +/* Library prototypes */ +bool R_IO_PORT_SetAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadControlRegisterAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ModifyControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyControlRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadDataAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadDataRegisterAll( + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_WriteAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WriteRegisterAll( + const uint8_t, + const uint8_t +); +bool R_IO_PORT_CompareAll( + const uint8_t, + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_CompareRegisterAll( + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_ModifyDataAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyDataRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitRegisterAll( + const uint8_t, + const uint8_t +); +bool ReturnFalse(void); + +/* Macro definitions */ + +/* R_IO_PORT_Set */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Set(a, b) \ +( \ +( ((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7) ) ? \ +R_IO_PORT_SetAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ReadControl */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_ReadControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ReadControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ReadControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ModifyControl */ +/* Call the function if the port number is valid (0 to E). */ +#define R_IO_PORT_ModifyControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ModifyControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ModifyControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Read */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Read(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ReadDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ReadDataRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Write */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Write(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_WriteAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_WriteRegisterAll( (uint8_t)(a), (b) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Compare */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Compare(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_CompareAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_CompareRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Modify */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Modify(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ModifyDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ModifyDataRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Wait */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Wait(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) && (b == 1u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)(a) ) : \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) && (b == 0u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), 0u ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_WaitRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_io_port_rx62nxfp.h b/bsp/rx/RPDL/r_pdl_io_port_rx62nxfp.h new file mode 100644 index 0000000000000000000000000000000000000000..3efd70e492c5c3fa3161d44466050f4e58654bae --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_io_port_rx62nxfp.h @@ -0,0 +1,201 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I/O Port API for RX62N (100-pin LQFP) +* File Name : r_pdl_io_port_RX62NxFP.h +* Version : 1.02 +* Contents : I/O Port API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IO_PORT_RX62NxFP_H +#define R_PDL_IO_PORT_RX62NxFP_H + +/* Library prototypes */ +/* Library prototypes */ +bool R_IO_PORT_SetAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadControlRegisterAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ModifyControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyControlRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadDataAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadDataRegisterAll( + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_WriteAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WriteRegisterAll( + const uint8_t, + const uint8_t +); +bool R_IO_PORT_CompareAll( + const uint8_t, + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_CompareRegisterAll( + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_ModifyDataAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyDataRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitRegisterAll( + const uint8_t, + const uint8_t +); +bool ReturnFalse(void); + +/* Macro definitions */ + +/* R_IO_PORT_Set */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Set(a, b) \ +( \ +( ((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7) ) ? \ +R_IO_PORT_SetAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ReadControl */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_ReadControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ReadControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ReadControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ModifyControl */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_ModifyControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ModifyControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ModifyControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Read */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Read(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ReadDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ReadDataRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Write */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Write(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_WriteAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_WriteRegisterAll( (uint8_t)(a), (b) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Compare */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Compare(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_CompareAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_CompareRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Modify */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Modify(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ModifyDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ModifyDataRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Wait */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Wait(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7)) && (b == 1u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)(a) ) : \ +( (((a) >= PDL_IO_PORT_0_5) && ((a) <= PDL_IO_PORT_E_7)) && (b == 0u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), 0u ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_WaitRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_io_port_rx62nxld.h b/bsp/rx/RPDL/r_pdl_io_port_rx62nxld.h new file mode 100644 index 0000000000000000000000000000000000000000..7f7f4799524a8cf3c75027f2021d0af8daafdbe9 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_io_port_rx62nxld.h @@ -0,0 +1,201 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I/O Port API for RX62N (85-pin TFLGA) +* File Name : r_pdl_io_port_RX62NxLD.h +* Version : 1.02 +* Contents : I/O Port API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IO_PORT_RX62NxLD_H +#define R_PDL_IO_PORT_RX62NxLD_H + +/* Library prototypes */ +/* Library prototypes */ +bool R_IO_PORT_SetAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadControlRegisterAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ModifyControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyControlRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadDataAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadDataRegisterAll( + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_WriteAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WriteRegisterAll( + const uint8_t, + const uint8_t +); +bool R_IO_PORT_CompareAll( + const uint8_t, + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_CompareRegisterAll( + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_ModifyDataAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyDataRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitRegisterAll( + const uint8_t, + const uint8_t +); +bool ReturnFalse(void); + +/* Macro definitions */ + +/* R_IO_PORT_Set */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Set(a, b) \ +( \ +( ((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7) ) ? \ +R_IO_PORT_SetAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ReadControl */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_ReadControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7)) ) ? \ +R_IO_PORT_ReadControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_D) ) ? \ +R_IO_PORT_ReadControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ModifyControl */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_ModifyControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7)) ) ? \ +R_IO_PORT_ModifyControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_D) ) ? \ +R_IO_PORT_ModifyControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Read */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Read(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7)) ) ? \ +R_IO_PORT_ReadDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_D) ) ? \ +R_IO_PORT_ReadDataRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Write */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Write(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7)) ) ? \ +R_IO_PORT_WriteAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_D) ) ? \ +R_IO_PORT_WriteRegisterAll( (uint8_t)(a), (b) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Compare */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Compare(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7)) ) ? \ +R_IO_PORT_CompareAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_D) ) ? \ +R_IO_PORT_CompareRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Modify */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Modify(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7)) ) ? \ +R_IO_PORT_ModifyDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_D) ) ? \ +R_IO_PORT_ModifyDataRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Wait */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Wait(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7)) && (b == 1u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)(a) ) : \ +( (((a) >= PDL_IO_PORT_0_3) && ((a) <= PDL_IO_PORT_D_7)) && (b == 0u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), 0u ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_D) ) ? \ +R_IO_PORT_WaitRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_io_port_rx62nxle.h b/bsp/rx/RPDL/r_pdl_io_port_rx62nxle.h new file mode 100644 index 0000000000000000000000000000000000000000..44d7e58cb915f5b3170c556b96282cbb3753cbf3 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_io_port_rx62nxle.h @@ -0,0 +1,201 @@ +/*""FILE COMMENT""******************************************************* +* System Name : I/O Port API for RX62N (145-pin TFLGA) +* File Name : r_pdl_io_port_RX62NxLE.h +* Version : 1.02 +* Contents : I/O Port API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IO_PORT_RX62NxLE_H +#define R_PDL_IO_PORT_RX62NxLE_H + +/* Library prototypes */ +/* Library prototypes */ +bool R_IO_PORT_SetAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadControlRegisterAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ModifyControlAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyControlRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ReadDataAll( + const uint8_t, + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_ReadDataRegisterAll( + const uint8_t, + volatile uint8_t * const +); +bool R_IO_PORT_WriteAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WriteRegisterAll( + const uint8_t, + const uint8_t +); +bool R_IO_PORT_CompareAll( + const uint8_t, + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_CompareRegisterAll( + const uint8_t, + const uint8_t, + VoidCallBackFunc const +); +bool R_IO_PORT_ModifyDataAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_ModifyDataRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_IO_PORT_WaitRegisterAll( + const uint8_t, + const uint8_t +); +bool ReturnFalse(void); + +/* Macro definitions */ + +/* R_IO_PORT_Set */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Set(a, b) \ +( \ +( ((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7) ) ? \ +R_IO_PORT_SetAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ReadControl */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_ReadControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ReadControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ReadControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_ModifyControl */ +/* Call the function if the port number is valid (0 to E). */ +#define R_IO_PORT_ModifyControl(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ModifyControlAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ModifyControlRegisterAll( (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Read */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Read(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ReadDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ReadDataRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +/* R_IO_PORT_Write */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Write(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_WriteAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_WriteRegisterAll( (uint8_t)(a), (b) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Compare */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Compare(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_CompareAll( (uint8_t)((a) >> 8), (uint8_t)(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_CompareRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Modify */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Modify(a, b, c) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) ) ? \ +R_IO_PORT_ModifyDataAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)~(a), (b), (c) ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_ModifyDataRegisterAll( (uint8_t)(a), (b), (c) ): \ +ReturnFalse() \ +) + +/* R_IO_PORT_Wait */ +/* Call the function if the port number is valid. */ +#define R_IO_PORT_Wait(a, b) \ +( \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) && (b == 1u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), (uint8_t)(a) ) : \ +( (((a) >= PDL_IO_PORT_0_0) && ((a) <= PDL_IO_PORT_E_7)) && (b == 0u) ) ? \ +R_IO_PORT_WaitAll( (uint8_t)((a) >> 8), (uint8_t)(a), 0u ) : \ +( ((a) >= PDL_IO_PORT_0) && ((a) <= PDL_IO_PORT_E) ) ? \ +R_IO_PORT_WaitRegisterAll( (uint8_t)(a), (b) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_iwdt.h b/bsp/rx/RPDL/r_pdl_iwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..fd16c8ba902f5ec3d0bd084f469cb2cb76393c26 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_iwdt.h @@ -0,0 +1,55 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Independent Watchdog timer API for RX62Nxx +* File Name : r_pdl_iwdt.h +* Version : 1.02 +* Contents : IWDT API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IWDT_H +#define R_PDL_IWDT_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_IWDT_Set( + uint16_t +); +bool R_IWDT_Control( + uint8_t +); +bool R_IWDT_Read( + uint16_t * +); + +/* Calculation selection */ +#define PDL_IWDT_TIMEOUT_1024 0x0001u +#define PDL_IWDT_TIMEOUT_4096 0x0002u +#define PDL_IWDT_TIMEOUT_8192 0x0004u +#define PDL_IWDT_TIMEOUT_16384 0x0008u + +#define PDL_IWDT_CLOCK_OCO_1 0x0010u +#define PDL_IWDT_CLOCK_OCO_16 0x0020u +#define PDL_IWDT_CLOCK_OCO_32 0x0040u +#define PDL_IWDT_CLOCK_OCO_64 0x0080u +#define PDL_IWDT_CLOCK_OCO_128 0x0100u +#define PDL_IWDT_CLOCK_OCO_256 0x0200u + +#define PDL_IWDT_REFRESH 0x01u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_iwdt_RX62Nxx.h b/bsp/rx/RPDL/r_pdl_iwdt_RX62Nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..e793587e1f3f5be17e8522199385ce3a186eb4c4 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_iwdt_RX62Nxx.h @@ -0,0 +1,55 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Independent Watchdog timer API for RX62Nxx +* File Name : r_pdl_iwdt_RX62Nxx.h +* Version : 1.02 +* Contents : IWDT API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_IWDT_RX62Nxx_H +#define R_PDL_IWDT_RX62Nxx_H + +/* Library prototypes */ +bool R_IWDT_SetAll( + const uint16_t +); +bool R_IWDT_ControlAll( + const uint8_t +); +bool R_IWDT_ReadAll( + volatile uint16_t * const +); + +/* Macro definitions */ + +#define R_IWDT_Set(a) \ +( \ +R_IWDT_SetAll( (a) ) \ +) + +#define R_IWDT_Control(a) \ +( \ +R_IWDT_ControlAll( (a) ) \ +) + +#define R_IWDT_Read(a) \ +( \ +R_IWDT_ReadAll( (a) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_lpc.h b/bsp/rx/RPDL/r_pdl_lpc.h new file mode 100644 index 0000000000000000000000000000000000000000..2905d6bcd2e0b635c83ea465b229a175b93816e3 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_lpc.h @@ -0,0 +1,125 @@ +/*""FILE COMMENT""******************************************************* +* System Name : LPC API for RX62Nxx +* File Name : r_pdl_lpc.h +* Version : 1.02 +* Contents : LPC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_LPC_H +#define R_PDL_LPC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_LPC_Create( + uint32_t, + uint32_t +); +bool R_LPC_Control( + uint16_t +); +bool R_LPC_WriteBackup( + uint8_t *, + uint8_t +); +bool R_LPC_ReadBackup( + uint8_t *, + uint8_t +); +bool R_LPC_GetStatus( + uint16_t * +); + +/* Software and Deep Software Standby mode output port control */ +#define PDL_LPC_EXT_BUS_ON 0x00000001ul +#define PDL_LPC_EXT_BUS_HI_Z 0x00000002ul + +/* On-chip RAM power / USB resume detection control */ +#define PDL_LPC_RAM_USB_DETECT_ON 0x00000004ul +#define PDL_LPC_RAM_USB_DETECT_OFF 0x00000008ul + +/* I/O port retention control */ +#define PDL_LPC_IO_SAME 0x00000010ul +#define PDL_LPC_IO_DELAY 0x00000020ul + +/* Deep software standby cancel control */ +#define PDL_LPC_CANCEL_IRQ0_DISABLE 0x00000040ul +#define PDL_LPC_CANCEL_IRQ0_FALLING 0x00000080ul +#define PDL_LPC_CANCEL_IRQ0_RISING 0x00000100ul +#define PDL_LPC_CANCEL_IRQ1_DISABLE 0x00000200ul +#define PDL_LPC_CANCEL_IRQ1_FALLING 0x00000400ul +#define PDL_LPC_CANCEL_IRQ1_RISING 0x00000800ul +#define PDL_LPC_CANCEL_IRQ2_DISABLE 0x00001000ul +#define PDL_LPC_CANCEL_IRQ2_FALLING 0x00002000ul +#define PDL_LPC_CANCEL_IRQ2_RISING 0x00004000ul +#define PDL_LPC_CANCEL_IRQ3_DISABLE 0x00008000ul +#define PDL_LPC_CANCEL_IRQ3_FALLING 0x00010000ul +#define PDL_LPC_CANCEL_IRQ3_RISING 0x00020000ul +#define PDL_LPC_CANCEL_NMI_DISABLE 0x00040000ul +#define PDL_LPC_CANCEL_NMI_FALLING 0x00080000ul +#define PDL_LPC_CANCEL_NMI_RISING 0x00100000ul +#define PDL_LPC_CANCEL_LVD_DISABLE 0x00200000ul +#define PDL_LPC_CANCEL_LVD_ENABLE 0x00400000ul +#define PDL_LPC_CANCEL_RTC_DISABLE 0x00800000ul +#define PDL_LPC_CANCEL_RTC_ENABLE 0x01000000ul +#define PDL_LPC_CANCEL_USB_DISABLE 0x02000000ul +#define PDL_LPC_CANCEL_USB_ENABLE 0x04000000ul + +/* Software Standby waiting time */ +#define PDL_LPC_STANDBY_64 0x00000001ul +#define PDL_LPC_STANDBY_512 0x00000002ul +#define PDL_LPC_STANDBY_1024 0x00000004ul +#define PDL_LPC_STANDBY_2048 0x00000008ul +#define PDL_LPC_STANDBY_4096 0x00000010ul +#define PDL_LPC_STANDBY_16384 0x00000020ul +#define PDL_LPC_STANDBY_32768 0x00000040ul +#define PDL_LPC_STANDBY_65536 0x00000080ul +#define PDL_LPC_STANDBY_131072 0x00000100ul +#define PDL_LPC_STANDBY_262144 0x00000200ul +#define PDL_LPC_STANDBY_524288 0x00000400ul + +/* Deep Software Standby waiting time */ +#define PDL_LPC_DEEP_STANDBY_64 0x00000800ul +#define PDL_LPC_DEEP_STANDBY_512 0x00001000ul +#define PDL_LPC_DEEP_STANDBY_1024 0x00002000ul +#define PDL_LPC_DEEP_STANDBY_2048 0x00004000ul +#define PDL_LPC_DEEP_STANDBY_4096 0x00008000ul +#define PDL_LPC_DEEP_STANDBY_16384 0x00010000ul +#define PDL_LPC_DEEP_STANDBY_32768 0x00020000ul +#define PDL_LPC_DEEP_STANDBY_65536 0x00040000ul +#define PDL_LPC_DEEP_STANDBY_131072 0x00080000ul +#define PDL_LPC_DEEP_STANDBY_262144 0x00100000ul +#define PDL_LPC_DEEP_STANDBY_524288 0x00200000ul + +/* Error monitoring */ +#define PDL_LPC_MODE_SLEEP 0x0001u +#define PDL_LPC_MODE_ALL_MODULE_CLOCK_STOP 0x0002u +#define PDL_LPC_MODE_SOFTWARE_STANDBY 0x0004u +#define PDL_LPC_MODE_DEEP_SOFTWARE_STANDBY 0x0008u + +/* All-module clock stop cancellation modification */ +#define PDL_LPC_TMR_OFF 0x0010u +#define PDL_LPC_TMR_UNIT_0 0x0020u +#define PDL_LPC_TMR_UNIT_1 0x0040u +#define PDL_LPC_TMR_BOTH 0x0080u + +/* I/O port retention cancellation */ +#define PDL_LPC_IO_RELEASE 0x0100u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_lpc_rx62nxx.h b/bsp/rx/RPDL/r_pdl_lpc_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..2962644cfac8098461ea1eb372a4f6523016e83c --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_lpc_rx62nxx.h @@ -0,0 +1,81 @@ +/*""FILE COMMENT""******************************************************* +* System Name : LPC API for RX62Nxx +* File Name : r_pdl_lpc_RX62Nxx.h +* Version : 1.02 +* Contents : LPC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_LPC_RX62Nxx_H +#define R_PDL_LPC_RX62Nxx_H + +#define R_PDL_LPC_BACKUP_AREA_SIZE 32 + +/* Library prototypes */ +bool R_LPC_CreateAll( + const uint32_t, + const uint32_t +); +bool R_LPC_ControlAll( + const uint16_t +); +bool R_LPC_WriteBackupAll( + volatile const uint8_t * const, + const uint8_t +); +bool R_LPC_ReadBackupAll( + volatile uint8_t * const, + const uint8_t +); +bool R_LPC_GetStatusAll( + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_LPC_Create(a, b) \ +( \ +R_LPC_CreateAll( (a), (b) ) \ +) + +#define R_LPC_Control(a) \ +( \ +R_LPC_ControlAll( (a) ) \ +) + +#define R_LPC_WriteBackup(a, b) \ +( \ +( ( ((b) > 0) && ((b) <= R_PDL_LPC_BACKUP_AREA_SIZE) ) ) ? \ +R_LPC_WriteBackupAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_LPC_ReadBackup(a, b) \ +( \ +( ( ((b) > 0) && ((b) <= R_PDL_LPC_BACKUP_AREA_SIZE) ) ) ? \ +R_LPC_ReadBackupAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_LPC_GetStatus(a) \ +( \ +R_LPC_GetStatusAll( (a) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_lvd.h b/bsp/rx/RPDL/r_pdl_lvd.h new file mode 100644 index 0000000000000000000000000000000000000000..3f1c22dcc8d69d22f7b839311f1f2e66e2f47c4d --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_lvd.h @@ -0,0 +1,42 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Voltage detection circuit API for RX62Nxx +* File Name : r_pdl_lvd.h +* Version : 1.02 +* Contents : LVD API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_LVD_H +#define R_PDL_LVD_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool LVD_Control( + uint8_t +); + +/* LVD2 and LVD1 control */ +#define PDL_LVD_VDET2_DISABLE_VDET1_DISABLE 0x01u +#define PDL_LVD_VDET2_DISABLE_VDET1_RESET 0x02u +#define PDL_LVD_VDET2_DISABLE_VDET1_INTERRUPT 0x04u +#define PDL_LVD_VDET2_RESET_VDET1_DISABLE 0x08u +#define PDL_LVD_VDET2_INTERRUPT_VDET1_DISABLE 0x10u +#define PDL_LVD_VDET2_INTERRUPT_VDET1_RESET 0x20u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_lvd_RX62Nxx.h b/bsp/rx/RPDL/r_pdl_lvd_RX62Nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..a1c0cd4c332768414a01da7a3b18bf05ca47b8dd --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_lvd_RX62Nxx.h @@ -0,0 +1,39 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Voltage detection circuit API for RX62Nxx +* File Name : r_pdl_lvd_RX62Nxx.h +* Version : 1.02 +* Contents : LVD API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_LVD_RX62Nxx_H +#define R_PDL_LVD_RX62Nxx_H + +/* Library prototypes */ +bool R_LVD_ControlAll( + const uint8_t +); + +/* Macro definitions */ + +#define R_LVD_Control(a) \ +( \ +R_LVD_ControlAll( (a) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_mcu.h b/bsp/rx/RPDL/r_pdl_mcu.h new file mode 100644 index 0000000000000000000000000000000000000000..14c73c726229c763aa4016db72ba571f266b2cb7 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_mcu.h @@ -0,0 +1,45 @@ +/*""FILE COMMENT""******************************************************* +* System Name : MCU API for RX62Nxx +* File Name : r_pdl_mcu.h +* Version : 1.02 +* Contents : MCU API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_MCU_H +#define R_PDL_MCU_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_MCU_Control( + uint8_t +); +bool R_MCU_GetStatus( + uint16_t * +); + +/* On-chip ROM control */ +#define PDL_MCU_ROM_ENABLE 0x01u +#define PDL_MCU_ROM_DISABLE 0x02u + +/* On-chip RAM control */ +#define PDL_MCU_RAM_ENABLE 0x04u +#define PDL_MCU_RAM_DISABLE 0x08u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_mcu_rx62nxx.h b/bsp/rx/RPDL/r_pdl_mcu_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..824b203c25bf796fa28f4ff77195ec8b57786e23 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_mcu_rx62nxx.h @@ -0,0 +1,46 @@ +/*""FILE COMMENT""******************************************************* +* System Name : MCU API for RX62Nxx +* File Name : r_pdl_mcu_RX62Nxx.h +* Version : 1.02 +* Contents : MCU API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_MCU_RX62Nxx_H +#define R_PDL_MCU_RX62Nxx_H + +/* Library prototypes */ +bool R_MCU_ControlAll( + const uint8_t +); +bool R_MCU_GetStatusAll( + volatile uint16_t * const +); + +/* Macro definitions */ +#define R_MCU_Control(a) \ +( \ +R_MCU_ControlAll( (a) ) \ +) + +#define R_MCU_GetStatus(a) \ +( \ +R_MCU_GetStatusAll( (a) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_mtu2.h b/bsp/rx/RPDL/r_pdl_mtu2.h new file mode 100644 index 0000000000000000000000000000000000000000..608852858f57c9877bda3b06a3b48e124c32320f --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_mtu2.h @@ -0,0 +1,522 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Multi-function Timer Pulse Unit API for RX62N +* File Name : r_pdl_mtu2.h +* Version : 1.02 +* Contents : MTU2 API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_MTU2_H +#define R_PDL_MTU2_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_MTU2_Set( + uint16_t +); +bool R_MTU2_Create( + uint8_t, + void * +); +bool R_MTU2_Destroy( + uint8_t +); +bool R_MTU2_ControlChannel( + uint8_t, + void * +); +bool R_MTU2_ControlUnit( + uint8_t, + void * +); +bool R_MTU2_ReadChannel( + uint8_t, + uint8_t *, + uint16_t *, + uint16_t *, + uint16_t *, + uint16_t *, + uint16_t *, + uint16_t *, + uint16_t * +); +bool R_MTU2_ReadUnit( + uint8_t, + uint16_t *, + uint8_t * +); + +/* Pin selection */ +#define PDL_MTU2_PIN_3C_A 0x0001u +#define PDL_MTU2_PIN_3C_B 0x0002u +#define PDL_MTU2_PIN_3BD_A 0x0004u +#define PDL_MTU2_PIN_3BD_B 0x0008u +#define PDL_MTU2_PIN_4AC_A 0x0010u +#define PDL_MTU2_PIN_4AC_B 0x0020u +#define PDL_MTU2_PIN_4BD_A 0x0040u +#define PDL_MTU2_PIN_4BD_B 0x0080u +#define PDL_MTU2_PIN_5UVW_A 0x0100u +#define PDL_MTU2_PIN_5UVW_B 0x0200u +#define PDL_MTU2_PIN_CLKABCD_A 0x0400u +#define PDL_MTU2_PIN_CLKABCD_B 0x0800u +#define PDL_MTU2_PIN_11UVW_A 0x1000u +#define PDL_MTU2_PIN_11UVW_B 0x2000u +#define PDL_MTU2_PIN_CLKEFGH_A 0x4000u +#define PDL_MTU2_PIN_CLKEFGH_B 0x8000u + +/* Operation mode */ +#define PDL_MTU2_MODE_NORMAL 0x00000001u +#define PDL_MTU2_MODE_PWM1 0x00000002u +#define PDL_MTU2_MODE_PWM2 0x00000004u +#define PDL_MTU2_MODE_PHASE1 0x00000008u +#define PDL_MTU2_MODE_PHASE2 0x00000010u +#define PDL_MTU2_MODE_PHASE3 0x00000020u +#define PDL_MTU2_MODE_PHASE4 0x00000040u +#define PDL_MTU2_MODE_PWM_RS 0x00000080u +#define PDL_MTU2_MODE_PWM_COMP1 0x00000100u +#define PDL_MTU2_MODE_PWM_COMP2 0x00000200u +#define PDL_MTU2_MODE_PWM_COMP3 0x00000400u + +/* Synchronous mode control */ +#define PDL_MTU2_SYNC_DISABLE 0x00000800u +#define PDL_MTU2_SYNC_ENABLE 0x00001000u + +/* TGRA DMAC / DTC trigger control */ +#define PDL_MTU2_TGRA_DMAC_DTC_TRIGGER_DISABLE 0x00002000u +#define PDL_MTU2_TGRA_DMAC_TRIGGER_ENABLE 0x00004000u +#define PDL_MTU2_TGRA_DTC_TRIGGER_ENABLE 0x00008000u + +/* TGRB DTC trigger control */ +#define PDL_MTU2_TGRB_DTC_TRIGGER_DISABLE 0x00010000u +#define PDL_MTU2_TGRB_DTC_TRIGGER_ENABLE 0x00020000u + +/* TGRC DTC trigger control */ +#define PDL_MTU2_TGRC_DTC_TRIGGER_DISABLE 0x00040000u +#define PDL_MTU2_TGRC_DTC_TRIGGER_ENABLE 0x00080000u + +/* TGRD DTC trigger control */ +#define PDL_MTU2_TGRD_DTC_TRIGGER_DISABLE 0x00100000u +#define PDL_MTU2_TGRD_DTC_TRIGGER_ENABLE 0x00200000u + +/* TGRU DTC trigger control */ +#define PDL_MTU2_TGRU_DTC_TRIGGER_DISABLE 0x00400000u +#define PDL_MTU2_TGRU_DTC_TRIGGER_ENABLE 0x00800000u + +/* TGRV DTC trigger control */ +#define PDL_MTU2_TGRV_DTC_TRIGGER_DISABLE 0x01000000u +#define PDL_MTU2_TGRV_DTC_TRIGGER_ENABLE 0x02000000u + +/* TGRW DTC trigger control */ +#define PDL_MTU2_TGRW_DTC_TRIGGER_DISABLE 0x04000000u +#define PDL_MTU2_TGRW_DTC_TRIGGER_ENABLE 0x08000000u + +/* TCIV DTC trigger control */ +#define PDL_MTU2_TCIV_DTC_TRIGGER_DISABLE 0x10000000u +#define PDL_MTU2_TCIV_DTC_TRIGGER_ENABLE 0x20000000u + +/* TCNT counter clock sources */ +#define PDL_MTU2_CLK_PCLK_DIV_1 0x00000001ul +#define PDL_MTU2_CLK_PCLK_DIV_4 0x00000002ul +#define PDL_MTU2_CLK_PCLK_DIV_16 0x00000004ul +#define PDL_MTU2_CLK_PCLK_DIV_64 0x00000008ul +#define PDL_MTU2_CLK_PCLK_DIV_256 0x00000010ul +#define PDL_MTU2_CLK_PCLK_DIV_1024 0x00000020ul +#define PDL_MTU2_CLK_MTCLKA 0x00000040ul +#define PDL_MTU2_CLK_MTCLKB 0x00000080ul +#define PDL_MTU2_CLK_MTCLKC 0x00000100ul +#define PDL_MTU2_CLK_MTCLKD 0x00000200ul +#define PDL_MTU2_CLK_MTCLKE 0x00000400ul +#define PDL_MTU2_CLK_MTCLKF 0x00000800ul +#define PDL_MTU2_CLK_MTCLKG 0x00001000ul +#define PDL_MTU2_CLK_MTCLKH 0x00002000ul +#define PDL_MTU2_CLK_CASCADE 0x00004000ul + +/* TNCT counter clock edge selection */ +#define PDL_MTU2_CLK_RISING 0x00008000ul +#define PDL_MTU2_CLK_FALLING 0x00010000ul +#define PDL_MTU2_CLK_BOTH 0x00020000ul + +/* TCNT counter clearing options */ +#define PDL_MTU2_CLEAR_DISABLE 0x00040000ul +#define PDL_MTU2_CLEAR_TGRA 0x00080000ul +#define PDL_MTU2_CLEAR_TGRB 0x00100000ul +#define PDL_MTU2_CLEAR_SYNC 0x00200000ul +#define PDL_MTU2_CLEAR_TGRC 0x00400000ul +#define PDL_MTU2_CLEAR_TGRD 0x00800000ul + +/* TCNTU counter clock sources */ +#define PDL_MTU2_CLKU_PCLK_DIV_1 0x00000001ul +#define PDL_MTU2_CLKU_PCLK_DIV_4 0x00000002ul +#define PDL_MTU2_CLKU_PCLK_DIV_16 0x00000004ul +#define PDL_MTU2_CLKU_PCLK_DIV_64 0x00000008ul + +/* TCNTV counter clock sources */ +#define PDL_MTU2_CLKV_PCLK_DIV_1 0x00000010ul +#define PDL_MTU2_CLKV_PCLK_DIV_4 0x00000020ul +#define PDL_MTU2_CLKV_PCLK_DIV_16 0x00000040ul +#define PDL_MTU2_CLKV_PCLK_DIV_64 0x00000080ul + +/* TCNTW counter clock sources */ +#define PDL_MTU2_CLKW_PCLK_DIV_1 0x00000100ul +#define PDL_MTU2_CLKW_PCLK_DIV_4 0x00000200ul +#define PDL_MTU2_CLKW_PCLK_DIV_16 0x00000400ul +#define PDL_MTU2_CLKW_PCLK_DIV_64 0x00000800ul + +/* U,V,W counter clearing options */ +#define PDL_MTU2_CLEAR_TGRU_DISABLE 0x00001000ul +#define PDL_MTU2_CLEAR_TGRU_ENABLE 0x00002000ul +#define PDL_MTU2_CLEAR_TGRV_DISABLE 0x00004000ul +#define PDL_MTU2_CLEAR_TGRV_ENABLE 0x00008000ul +#define PDL_MTU2_CLEAR_TGRW_DISABLE 0x00010000ul +#define PDL_MTU2_CLEAR_TGRW_ENABLE 0x00020000ul + +/* ADC conversion trigger control */ +#define PDL_MTU2_ADC_TRIG_TGRA_DISABLE 0x00000001ul +#define PDL_MTU2_ADC_TRIG_TGRA_ENABLE 0x00000002ul +#define PDL_MTU2_ADC_TRIG_TROUGH_DISABLE 0x00000004ul +#define PDL_MTU2_ADC_TRIG_TROUGH_ENABLE 0x00000008ul + +/* ADC trigger interrupt skipping */ +#define PDL_MTU2_ADC_TRIG_A_TROUGH_INT_SKIP_DISABLE 0x00000010ul +#define PDL_MTU2_ADC_TRIG_A_TROUGH_INT_SKIP_ENABLE 0x00000020ul +#define PDL_MTU2_ADC_TRIG_B_TROUGH_INT_SKIP_DISABLE 0x00000040ul +#define PDL_MTU2_ADC_TRIG_B_TROUGH_INT_SKIP_ENABLE 0x00000080ul +#define PDL_MTU2_ADC_TRIG_A_CREST_INT_SKIP_DISABLE 0x00000100ul +#define PDL_MTU2_ADC_TRIG_A_CREST_INT_SKIP_ENABLE 0x00000200ul +#define PDL_MTU2_ADC_TRIG_B_CREST_INT_SKIP_DISABLE 0x00000400ul +#define PDL_MTU2_ADC_TRIG_B_CREST_INT_SKIP_ENABLE 0x00000800ul + +/* ADC trigger control */ +#define PDL_MTU2_ADC_TRIG_A_DOWN_DISABLE 0x00001000ul +#define PDL_MTU2_ADC_TRIG_A_DOWN_ENABLE 0x00002000ul +#define PDL_MTU2_ADC_TRIG_B_DOWN_DISABLE 0x00004000ul +#define PDL_MTU2_ADC_TRIG_B_DOWN_ENABLE 0x00008000ul +#define PDL_MTU2_ADC_TRIG_A_UP_DISABLE 0x00010000ul +#define PDL_MTU2_ADC_TRIG_A_UP_ENABLE 0x00020000ul +#define PDL_MTU2_ADC_TRIG_B_UP_DISABLE 0x00040000ul +#define PDL_MTU2_ADC_TRIG_B_UP_ENABLE 0x00080000ul + +/* Cycle set buffer transfer timing */ +#define PDL_MTU2_CSB_DISABLE 0x0001u +#define PDL_MTU2_CSB_CREST 0x0002u +#define PDL_MTU2_CSB_TROUGH 0x0004u +#define PDL_MTU2_CSB_BOTH 0x0008u + +/* Buffer operation */ +#define PDL_MTU2_BUFFER_AC_DISABLE 0x0010u +#define PDL_MTU2_BUFFER_AC_ENABLE 0x0020u +#define PDL_MTU2_BUFFER_BD_DISABLE 0x0040u +#define PDL_MTU2_BUFFER_BD_ENABLE 0x0080u +#define PDL_MTU2_BUFFER_EF_DISABLE 0x0100u +#define PDL_MTU2_BUFFER_EF_ENABLE 0x0200u + +/* Buffer data transfer */ +#define PDL_MTU2_BUFFER_AC_CM_A 0x0400u +#define PDL_MTU2_BUFFER_AC_TCNT_CLR 0x0800u +#define PDL_MTU2_BUFFER_BD_CM_B 0x1000u +#define PDL_MTU2_BUFFER_BD_TCNT_CLR 0x2000u +#define PDL_MTU2_BUFFER_EF_CM_E 0x4000u +#define PDL_MTU2_BUFFER_EF_TCNT_CLR 0x8000u + +/* TGRA options */ +#define PDL_MTU2_A_OC_DISABLED 0x00000001ul +#define PDL_MTU2_A_OC_LOW 0x00000002ul +#define PDL_MTU2_A_OC_LOW_CM_HIGH 0x00000004ul +#define PDL_MTU2_A_OC_LOW_CM_INV 0x00000008ul +#define PDL_MTU2_A_OC_HIGH_CM_LOW 0x00000010ul +#define PDL_MTU2_A_OC_HIGH 0x00000020ul +#define PDL_MTU2_A_OC_HIGH_CM_INV 0x00000040ul +#define PDL_MTU2_A_IC_RISING_EDGE 0x00000080ul +#define PDL_MTU2_A_IC_FALLING_EDGE 0x00000100ul +#define PDL_MTU2_A_IC_BOTH_EDGES 0x00000200ul +#define PDL_MTU2_A_IC_COUNT 0x00000400ul +#define PDL_MTU2_A_IC_CM_IC 0x00000800ul + +/* TGRB options */ +#define PDL_MTU2_B_OC_DISABLED 0x00001000ul +#define PDL_MTU2_B_OC_LOW 0x00002000ul +#define PDL_MTU2_B_OC_LOW_CM_HIGH 0x00004000ul +#define PDL_MTU2_B_OC_LOW_CM_INV 0x00008000ul +#define PDL_MTU2_B_OC_HIGH_CM_LOW 0x00010000ul +#define PDL_MTU2_B_OC_HIGH 0x00020000ul +#define PDL_MTU2_B_OC_HIGH_CM_INV 0x00040000ul +#define PDL_MTU2_B_IC_RISING_EDGE 0x00080000ul +#define PDL_MTU2_B_IC_FALLING_EDGE 0x00100000ul +#define PDL_MTU2_B_IC_BOTH_EDGES 0x00200000ul +#define PDL_MTU2_B_IC_COUNT 0x00400000ul +#define PDL_MTU2_B_IC_CM_IC 0x00800000ul + +/* Cascade input capture control */ +#define PDL_MTU2_CASCADE_AL_IC_EXC_H 0x01000000ul +#define PDL_MTU2_CASCADE_AL_IC_INC_H 0x02000000ul +#define PDL_MTU2_CASCADE_BL_IC_EXC_H 0x04000000ul +#define PDL_MTU2_CASCADE_BL_IC_INC_H 0x08000000ul +#define PDL_MTU2_CASCADE_AH_IC_EXC_L 0x10000000ul +#define PDL_MTU2_CASCADE_AH_IC_INC_L 0x20000000ul +#define PDL_MTU2_CASCADE_BH_IC_EXC_L 0x40000000ul +#define PDL_MTU2_CASCADE_BH_IC_INC_L 0x80000000ul + +/* TGRC options */ +#define PDL_MTU2_C_OC_DISABLED 0x00000001ul +#define PDL_MTU2_C_OC_LOW 0x00000002ul +#define PDL_MTU2_C_OC_LOW_CM_HIGH 0x00000004ul +#define PDL_MTU2_C_OC_LOW_CM_INV 0x00000008ul +#define PDL_MTU2_C_OC_HIGH_CM_LOW 0x00000010ul +#define PDL_MTU2_C_OC_HIGH 0x00000020ul +#define PDL_MTU2_C_OC_HIGH_CM_INV 0x00000040ul +#define PDL_MTU2_C_IC_RISING_EDGE 0x00000080ul +#define PDL_MTU2_C_IC_FALLING_EDGE 0x00000100ul +#define PDL_MTU2_C_IC_BOTH_EDGES 0x00000200ul +#define PDL_MTU2_C_IC_COUNT 0x00000400ul + +/* TGRD options */ +#define PDL_MTU2_D_OC_DISABLED 0x00000800ul +#define PDL_MTU2_D_OC_LOW 0x00001000ul +#define PDL_MTU2_D_OC_LOW_CM_HIGH 0x00002000ul +#define PDL_MTU2_D_OC_LOW_CM_INV 0x00004000ul +#define PDL_MTU2_D_OC_HIGH_CM_LOW 0x00008000ul +#define PDL_MTU2_D_OC_HIGH 0x00010000ul +#define PDL_MTU2_D_OC_HIGH_CM_INV 0x00020000ul +#define PDL_MTU2_D_IC_RISING_EDGE 0x00040000ul +#define PDL_MTU2_D_IC_FALLING_EDGE 0x00080000ul +#define PDL_MTU2_D_IC_BOTH_EDGES 0x00100000ul +#define PDL_MTU2_D_IC_COUNT 0x00200000ul + +/* TGRU options */ +#define PDL_MTU2_U_CM 0x00000001ul +#define PDL_MTU2_U_IC_RISING_EDGE 0x00000002ul +#define PDL_MTU2_U_IC_FALLING_EDGE 0x00000004ul +#define PDL_MTU2_U_IC_BOTH_EDGES 0x00000008ul +#define PDL_MTU2_U_IC_PWM_LOW_TROUGH 0x00000010ul +#define PDL_MTU2_U_IC_PWM_LOW_CREST 0x00000020ul +#define PDL_MTU2_U_IC_PWM_LOW_BOTH 0x00000040ul +#define PDL_MTU2_U_IC_PWM_HIGH_TROUGH 0x00000080ul +#define PDL_MTU2_U_IC_PWM_HIGH_CREST 0x00000100ul +#define PDL_MTU2_U_IC_PWM_HIGH_BOTH 0x00000200ul + +/* TGRV options */ +#define PDL_MTU2_V_CM 0x00000400ul +#define PDL_MTU2_V_IC_RISING_EDGE 0x00000800ul +#define PDL_MTU2_V_IC_FALLING_EDGE 0x00001000ul +#define PDL_MTU2_V_IC_BOTH_EDGES 0x00002000ul +#define PDL_MTU2_V_IC_PWM_LOW_TROUGH 0x00004000ul +#define PDL_MTU2_V_IC_PWM_LOW_CREST 0x00008000ul +#define PDL_MTU2_V_IC_PWM_LOW_BOTH 0x00010000ul +#define PDL_MTU2_V_IC_PWM_HIGH_TROUGH 0x00020000ul +#define PDL_MTU2_V_IC_PWM_HIGH_CREST 0x00040000ul +#define PDL_MTU2_V_IC_PWM_HIGH_BOTH 0x00080000ul + +/* TGRW options */ +#define PDL_MTU2_W_CM 0x00100000ul +#define PDL_MTU2_W_IC_RISING_EDGE 0x00200000ul +#define PDL_MTU2_W_IC_FALLING_EDGE 0x00400000ul +#define PDL_MTU2_W_IC_BOTH_EDGES 0x00800000ul +#define PDL_MTU2_W_IC_PWM_LOW_TROUGH 0x01000000ul +#define PDL_MTU2_W_IC_PWM_LOW_CREST 0x02000000ul +#define PDL_MTU2_W_IC_PWM_LOW_BOTH 0x04000000ul +#define PDL_MTU2_W_IC_PWM_HIGH_TROUGH 0x08000000ul +#define PDL_MTU2_W_IC_PWM_HIGH_CREST 0x10000000ul +#define PDL_MTU2_W_IC_PWM_HIGH_BOTH 0x20000000ul + +/* Counter stop / re-start */ +#define PDL_MTU2_STOP 0x01u +#define PDL_MTU2_START 0x02u +#define PDL_MTU2_STOP_U 0x04u +#define PDL_MTU2_START_U 0x08u +#define PDL_MTU2_STOP_V 0x10u +#define PDL_MTU2_START_V 0x20u +#define PDL_MTU2_STOP_W 0x40u +#define PDL_MTU2_START_W 0x80u + +/* The registers to be modified (n = 0 to 4 or 6 to 10) */ +#define PDL_MTU2_REGISTER_COUNTER 0x0001u +#define PDL_MTU2_REGISTER_TGRA 0x0002u +#define PDL_MTU2_REGISTER_TGRB 0x0004u +#define PDL_MTU2_REGISTER_TGRC 0x0008u +#define PDL_MTU2_REGISTER_TGRD 0x0010u +#define PDL_MTU2_REGISTER_TGRE 0x0020u +#define PDL_MTU2_REGISTER_TGRF 0x0040u +#define PDL_MTU2_REGISTER_TADCOBRA 0x0080u +#define PDL_MTU2_REGISTER_TADCOBRB 0x0100u + +/* The registers to be modified (n = 5 or 11) */ +#define PDL_MTU2_REGISTER_COUNTER_U 0x01u +#define PDL_MTU2_REGISTER_COUNTER_V 0x02u +#define PDL_MTU2_REGISTER_COUNTER_W 0x04u +#define PDL_MTU2_REGISTER_TGRU 0x08u +#define PDL_MTU2_REGISTER_TGRV 0x10u +#define PDL_MTU2_REGISTER_TGRW 0x20u + +/* Simultaneous stop control */ +#define PDL_MTU2_STOP_CH_0 0x0001u +#define PDL_MTU2_STOP_CH_1 0x0002u +#define PDL_MTU2_STOP_CH_2 0x0004u +#define PDL_MTU2_STOP_CH_3 0x0008u +#define PDL_MTU2_STOP_CH_4 0x0010u +#define PDL_MTU2_STOP_CH_6 PDL_MTU2_STOP_CH_0 +#define PDL_MTU2_STOP_CH_7 PDL_MTU2_STOP_CH_1 +#define PDL_MTU2_STOP_CH_8 PDL_MTU2_STOP_CH_2 +#define PDL_MTU2_STOP_CH_9 PDL_MTU2_STOP_CH_3 +#define PDL_MTU2_STOP_CH_10 PDL_MTU2_STOP_CH_4 + +/* Simultaneous start control */ +#define PDL_MTU2_START_CH_0 0x0020u +#define PDL_MTU2_START_CH_1 0x0040u +#define PDL_MTU2_START_CH_2 0x0080u +#define PDL_MTU2_START_CH_3 0x0100u +#define PDL_MTU2_START_CH_4 0x0200u +#define PDL_MTU2_START_CH_6 PDL_MTU2_START_CH_0 +#define PDL_MTU2_START_CH_7 PDL_MTU2_START_CH_1 +#define PDL_MTU2_START_CH_8 PDL_MTU2_START_CH_2 +#define PDL_MTU2_START_CH_9 PDL_MTU2_START_CH_3 +#define PDL_MTU2_START_CH_10 PDL_MTU2_START_CH_4 + +/* Output control */ +#define PDL_MTU2_OUT_P_PHASE_1_ENABLE 0x00000001ul +#define PDL_MTU2_OUT_P_PHASE_1_DISABLE 0x00000002ul +#define PDL_MTU2_OUT_N_PHASE_1_ENABLE 0x00000004ul +#define PDL_MTU2_OUT_N_PHASE_1_DISABLE 0x00000008ul +#define PDL_MTU2_OUT_P_PHASE_2_ENABLE 0x00000010ul +#define PDL_MTU2_OUT_P_PHASE_2_DISABLE 0x00000020ul +#define PDL_MTU2_OUT_N_PHASE_2_ENABLE 0x00000040ul +#define PDL_MTU2_OUT_N_PHASE_2_DISABLE 0x00000080ul +#define PDL_MTU2_OUT_P_PHASE_3_ENABLE 0x00000100ul +#define PDL_MTU2_OUT_P_PHASE_3_DISABLE 0x00000200ul +#define PDL_MTU2_OUT_N_PHASE_3_ENABLE 0x00000400ul +#define PDL_MTU2_OUT_N_PHASE_3_DISABLE 0x00000800ul + +#define PDL_MTU2_OUT_P_PHASE_ALL_ENABLE (PDL_MTU2_OUT_P_PHASE_1_ENABLE | PDL_MTU2_OUT_P_PHASE_2_ENABLE | PDL_MTU2_OUT_P_PHASE_3_ENABLE) +#define PDL_MTU2_OUT_P_PHASE_ALL_DISABLE (PDL_MTU2_OUT_P_PHASE_1_DISABLE | PDL_MTU2_OUT_P_PHASE_2_DISABLE | PDL_MTU2_OUT_P_PHASE_3_DISABLE) +#define PDL_MTU2_OUT_N_PHASE_ALL_ENABLE (PDL_MTU2_OUT_N_PHASE_1_ENABLE | PDL_MTU2_OUT_N_PHASE_2_ENABLE | PDL_MTU2_OUT_N_PHASE_3_ENABLE) +#define PDL_MTU2_OUT_N_PHASE_ALL_DISABLE (PDL_MTU2_OUT_N_PHASE_1_DISABLE | PDL_MTU2_OUT_N_PHASE_2_DISABLE | PDL_MTU2_OUT_N_PHASE_3_DISABLE) + +/* Inversion control */ +#define PDL_MTU2_OUT_P_PHASE_ALL_HIGH_LOW 0x00001000ul +#define PDL_MTU2_OUT_P_PHASE_ALL_LOW_HIGH 0x00002000ul +#define PDL_MTU2_OUT_N_PHASE_ALL_HIGH_LOW 0x00004000ul +#define PDL_MTU2_OUT_N_PHASE_ALL_LOW_HIGH 0x00008000ul + +#define PDL_MTU2_OUT_P_PHASE_1_HIGH_LOW 0x00010000ul +#define PDL_MTU2_OUT_P_PHASE_1_LOW_HIGH 0x00020000ul +#define PDL_MTU2_OUT_N_PHASE_1_HIGH_LOW 0x00040000ul +#define PDL_MTU2_OUT_N_PHASE_1_LOW_HIGH 0x00080000ul +#define PDL_MTU2_OUT_P_PHASE_2_HIGH_LOW 0x00100000ul +#define PDL_MTU2_OUT_P_PHASE_2_LOW_HIGH 0x00200000ul +#define PDL_MTU2_OUT_N_PHASE_2_HIGH_LOW 0x00400000ul +#define PDL_MTU2_OUT_N_PHASE_2_LOW_HIGH 0x00800000ul +#define PDL_MTU2_OUT_P_PHASE_3_HIGH_LOW 0x01000000ul +#define PDL_MTU2_OUT_P_PHASE_3_LOW_HIGH 0x02000000ul +#define PDL_MTU2_OUT_N_PHASE_3_HIGH_LOW 0x04000000ul +#define PDL_MTU2_OUT_N_PHASE_3_LOW_HIGH 0x08000000ul + +/* Write access control */ +#define PDL_MTU2_OUT_LOCK_ENABLE 0x10000000ul + +/* Toggle output control */ +#define PDL_MTU2_OUT_TOGGLE_ENABLE 0x20000000ul +#define PDL_MTU2_OUT_TOGGLE_DISABLE 0x40000000ul + +/* Output level buffer control */ +#define PDL_MTU2_OUT_BUFFER_P_PHASE_1_LOW 0x00000001ul +#define PDL_MTU2_OUT_BUFFER_P_PHASE_1_HIGH 0x00000002ul +#define PDL_MTU2_OUT_BUFFER_N_PHASE_1_LOW 0x00000004ul +#define PDL_MTU2_OUT_BUFFER_N_PHASE_1_HIGH 0x00000008ul +#define PDL_MTU2_OUT_BUFFER_P_PHASE_2_LOW 0x00000010ul +#define PDL_MTU2_OUT_BUFFER_P_PHASE_2_HIGH 0x00000020ul +#define PDL_MTU2_OUT_BUFFER_N_PHASE_2_LOW 0x00000040ul +#define PDL_MTU2_OUT_BUFFER_N_PHASE_2_HIGH 0x00000080ul +#define PDL_MTU2_OUT_BUFFER_P_PHASE_3_LOW 0x00000100ul +#define PDL_MTU2_OUT_BUFFER_P_PHASE_3_HIGH 0x00000200ul +#define PDL_MTU2_OUT_BUFFER_N_PHASE_3_LOW 0x00000400ul +#define PDL_MTU2_OUT_BUFFER_N_PHASE_3_HIGH 0x00000800ul + +/* Transfer timing (complementary PWM) */ +#define PDL_MTU2_OUT_BUFFER_TRANSFER_DISABLE 0x00001000ul +#define PDL_MTU2_OUT_BUFFER_TRANSFER_CREST 0x00002000ul +#define PDL_MTU2_OUT_BUFFER_TRANSFER_TROUGH 0x00004000ul +#define PDL_MTU2_OUT_BUFFER_TRANSFER_BOTH 0x00008000ul + +/* Transfer timing (reset-synchronised PWM) */ +#define PDL_MTU2_OUT_BUFFER_TRANSFER_CLEAR PDL_MTU2_OUT_BUFFER_TRANSFER_CREST + +/* Buffer transfer to temporary transfer control */ +#define PDL_MTU2_BUFFER_TRANSFER_DISABLE 0x00020000ul +#define PDL_MTU2_BUFFER_TRANSFER_ENABLE 0x00040000ul +#define PDL_MTU2_BUFFER_TRANSFER_LINK 0x00080000ul + +/* Brushless DC motor waveform control */ +#define PDL_MTU2_BDCM_ENABLE 0x0001u +#define PDL_MTU2_BDCM_DISABLE 0x0002u +#define PDL_MTU2_BDCM_P_PHASE_ENABLE 0x0004u +#define PDL_MTU2_BDCM_P_PHASE_DISABLE 0x0008u +#define PDL_MTU2_BDCM_N_PHASE_ENABLE 0x0010u +#define PDL_MTU2_BDCM_N_PHASE_DISABLE 0x0020u +#define PDL_MTU2_BDCM_OPS_FB 0x0040u +#define PDL_MTU2_BDCM_OPS_000 0x0080u +#define PDL_MTU2_BDCM_OPS_001 0x0100u +#define PDL_MTU2_BDCM_OPS_010 0x0200u +#define PDL_MTU2_BDCM_OPS_011 0x0400u +#define PDL_MTU2_BDCM_OPS_100 0x0800u +#define PDL_MTU2_BDCM_OPS_101 0x1000u +#define PDL_MTU2_BDCM_OPS_110 0x2000u +#define PDL_MTU2_BDCM_OPS_111 0x4000u + +/* Interrupt skipping control */ +#define PDL_MTU2_INT_SKIP_TROUGH_DISABLE 0x00000001ul +#define PDL_MTU2_INT_SKIP_TROUGH_1 0x00000002ul +#define PDL_MTU2_INT_SKIP_TROUGH_2 0x00000004ul +#define PDL_MTU2_INT_SKIP_TROUGH_3 0x00000008ul +#define PDL_MTU2_INT_SKIP_TROUGH_4 0x00000010ul +#define PDL_MTU2_INT_SKIP_TROUGH_5 0x00000020ul +#define PDL_MTU2_INT_SKIP_TROUGH_6 0x00000040ul +#define PDL_MTU2_INT_SKIP_TROUGH_7 0x00000080ul +#define PDL_MTU2_INT_SKIP_CREST_DISABLE 0x00000100ul +#define PDL_MTU2_INT_SKIP_CREST_1 0x00000200ul +#define PDL_MTU2_INT_SKIP_CREST_2 0x00000400ul +#define PDL_MTU2_INT_SKIP_CREST_3 0x00000800ul +#define PDL_MTU2_INT_SKIP_CREST_4 0x00001000ul +#define PDL_MTU2_INT_SKIP_CREST_5 0x00002000ul +#define PDL_MTU2_INT_SKIP_CREST_6 0x00004000ul +#define PDL_MTU2_INT_SKIP_CREST_7 0x00008000ul + +/* Dead time generation control */ +#define PDL_MTU2_DEAD_TIME_DISABLE 0x00010000ul +#define PDL_MTU2_DEAD_TIME_ENABLE 0x00020000ul + +/* Waveform retention control */ +#define PDL_MTU2_WAVEFORM_RETAIN_DISABLE 0x00040000ul +#define PDL_MTU2_WAVEFORM_RETAIN_ENABLE 0x00080000ul + +/* Compare match clearing control */ +#define PDL_MTU2_CNT_CLEAR_CM_A_DISABLE 0x00100000ul +#define PDL_MTU2_CNT_CLEAR_CM_A_ENABLE 0x00200000ul + +/* Reset-synchronised or complementary PWM control */ +#define PDL_MTU2_PWM_RS_COMP_ENABLE 0x00400000ul + +/* Register protection */ +#define PDL_MTU2_ACCESS_DISABLE 0x00800000ul +#define PDL_MTU2_ACCESS_ENABLE 0x01000000ul + +/* Unit registers to be modified */ +#define PDL_MTU2_REGISTER_DEAD_TIME 0x01u +#define PDL_MTU2_REGISTER_CYCLE_DATA 0x02u +#define PDL_MTU2_REGISTER_CYCLE_BUFFER 0x04u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_mtu2_rx62nxx.h b/bsp/rx/RPDL/r_pdl_mtu2_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..0881209a96e751b11d597ddeb32e2bfd748cc350 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_mtu2_rx62nxx.h @@ -0,0 +1,187 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Multi-function Timer Pulse Unit API for RX62N +* File Name : r_pdl_MTU2_RX62Nxx.h +* Version : 1.02 +* Contents : MTU2 API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_MTU2_RX62Nxx_H +#define R_PDL_MTU2_RX62Nxx_H + +#define MTU2_UNITS 2 +#define MTU2_CHANNELS_PER_UNIT 6 +#define MTU2_CHANNELS (uint8_t)(MTU2_UNITS * MTU2_CHANNELS_PER_UNIT) + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_MTU2_func1_callback_func[MTU2_CHANNELS]; +extern VoidCallBackFunc rpdl_MTU2_func2_callback_func[MTU2_CHANNELS]; +extern VoidCallBackFunc rpdl_MTU2_func3_callback_func[MTU2_CHANNELS]; +extern VoidCallBackFunc rpdl_MTU2_func4_callback_func[MTU2_CHANNELS]; +extern VoidCallBackFunc rpdl_MTU2_TGRE_callback_func[MTU2_CHANNELS]; +extern VoidCallBackFunc rpdl_MTU2_TGRF_callback_func[MTU2_CHANNELS]; +extern VoidCallBackFunc rpdl_MTU2_Overflow_callback_func[MTU2_CHANNELS]; +extern VoidCallBackFunc rpdl_MTU2_Underflow_callback_func[MTU2_CHANNELS]; + +typedef struct R_MTU2_Create_parameters +{ + uint32_t data2; + uint32_t data3; + uint32_t data4; + uint16_t data5; + uint32_t data6; + uint32_t data7; + uint32_t data8; + uint16_t data9; + uint16_t data10; + uint16_t data11; + uint16_t data12; + uint16_t data13; + uint16_t data14; + uint16_t data15; + uint16_t data16; + uint16_t data17; + uint16_t data18; + VoidCallBackFunc func1; + VoidCallBackFunc func2; + VoidCallBackFunc func3; + VoidCallBackFunc func4; + uint8_t data19; + VoidCallBackFunc func5; + VoidCallBackFunc func6; + VoidCallBackFunc func7; + VoidCallBackFunc func8; + uint8_t data20; +} R_MTU2_Create_structure; + +typedef struct R_MTU2_ControlChannel_parameters +{ + uint8_t data2; + uint16_t data3; + uint16_t data4; + uint16_t data5; + uint16_t data6; + uint16_t data7; + uint16_t data8; + uint16_t data9; + uint16_t data10; + uint16_t data11; + uint16_t data12; +} R_MTU2_ControlChannel_structure; + +typedef struct R_MTU2_ControlUnit_parameters +{ + uint16_t data2; + uint32_t data3; + uint32_t data4; + uint16_t data5; + uint32_t data6; + uint8_t data7; + uint16_t data8; + uint16_t data9; + uint16_t data10; +} R_MTU2_ControlUnit_structure; + +/* Library prototypes */ +bool R_MTU2_SetAll( + const uint16_t +); +bool R_MTU2_CreateAll( + const uint8_t, + R_MTU2_Create_structure * const +); +bool R_MTU2_DestroyAll( + const uint8_t +); +bool R_MTU2_ControlChannelAll( + const uint8_t, + R_MTU2_ControlChannel_structure * const +); +bool R_MTU2_ControlUnitAll( + const uint8_t, + R_MTU2_ControlUnit_structure * const +); +bool R_MTU2_ReadChannelAll( + const uint8_t, + volatile uint8_t * const, + volatile uint16_t * const, + volatile uint16_t * const, + volatile uint16_t * const, + volatile uint16_t * const, + volatile uint16_t * const, + volatile uint16_t * const, + volatile uint16_t * const +); +bool R_MTU2_ReadUnitAll( + const uint8_t, + volatile uint16_t * const, + volatile uint8_t * const +); +bool ReturnFalse(void); +void R_MTU2_Create_load_defaults(R_MTU2_Create_structure * const); + +/* Macro definitions */ + +#define R_MTU2_Set(a) \ +( \ +R_MTU2_SetAll( (a) ) \ +) + +#define R_MTU2_Create(a, b) \ +( \ +( (a) < MTU2_CHANNELS ) ? \ +R_MTU2_CreateAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_MTU2_ControlChannel(a, b) \ +( \ +( (a) < MTU2_CHANNELS ) ? \ +R_MTU2_ControlChannelAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_MTU2_ControlUnit(a, b) \ +( \ +( (a) < MTU2_UNITS ) ? \ +R_MTU2_ControlUnitAll( (a), (b) ) : \ +ReturnFalse() \ +) + +#define R_MTU2_ReadChannel(a, b, c, d, e, f, g, h, i) \ +( \ +( (a) < MTU2_CHANNELS ) ? \ +R_MTU2_ReadChannelAll( (a), (b), (c), (d), (e), (f), (g), (h), (i) ) : \ +ReturnFalse() \ +) + +#define R_MTU2_ReadUnit(a, b, c) \ +( \ +( (a) < MTU2_UNITS ) ? \ +R_MTU2_ReadUnitAll( (a), (b), (c) ) : \ +ReturnFalse() \ +) + +#define R_MTU2_Destroy(a) \ +( \ +( (a) < MTU2_UNITS ) ? \ +R_MTU2_DestroyAll( (a) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_pfc.h b/bsp/rx/RPDL/r_pdl_pfc.h new file mode 100644 index 0000000000000000000000000000000000000000..302a94988e775fefda5be8952f456640be5a1430 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_pfc.h @@ -0,0 +1,74 @@ +/*""FILE COMMENT""******************************************************* +* System Name : PFC API +* File Name : r_pdl_pfc.h +* Version : 1.02 +* Contents : PFC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_PFC_H +#define R_PDL_PFC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_PFC_Read( + uint8_t, + uint8_t * +); +bool R_PFC_Write( + uint8_t, + uint8_t +); +bool R_PFC_Modify( + uint8_t, + uint8_t, + uint8_t +); + +/* PFC register definitions */ +#define PDL_PFC_PF0CSE 0x00u +#define PDL_PFC_PF1CSS 0x01u +#define PDL_PFC_PF2CSS 0x02u +#define PDL_PFC_PF3BUS 0x03u +#define PDL_PFC_PF4BUS 0x04u +#define PDL_PFC_PF5BUS 0x05u +#define PDL_PFC_PF6BUS 0x06u +#define PDL_PFC_PF7DMA 0x07u +#define PDL_PFC_PF8IRQ 0x08u +#define PDL_PFC_PF9IRQ 0x09u +#define PDL_PFC_PFAADC 0x0Au +#define PDL_PFC_PFBTMR 0x0Bu +#define PDL_PFC_PFCMTU 0x0Cu +#define PDL_PFC_PFDMTU 0x0Du +#define PDL_PFC_PFENET 0x0Eu +#define PDL_PFC_PFFSCI 0x0Fu +#define PDL_PFC_PFGSPI 0x10u +#define PDL_PFC_PFHSPI 0x11u +#define PDL_PFC_PFJCAN 0x13u +#define PDL_PFC_PFKUSB 0x14u +#define PDL_PFC_PFLUSB 0x15u +#define PDL_PFC_PFMPOE 0x16u +#define PDL_PFC_PFNPOE 0x17u + +/* Logical operations */ +#define PDL_PFC_AND 0x01u +#define PDL_PFC_OR 0x02u +#define PDL_PFC_XOR 0x04u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_pfc_rx62nxx.h b/bsp/rx/RPDL/r_pdl_pfc_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..89448abbf5cdd69fb0f0b103fdb5f6fed0315f05 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_pfc_rx62nxx.h @@ -0,0 +1,72 @@ +/*""FILE COMMENT""******************************************************* +* System Name : PFC API for RX62Nxx +* File Name : r_pdl_pfc_RX62Nxx.h +* Version : 1.02 +* Contents : PFC API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_PFC_RX62Nxx_H +#define R_PDL_PFC_RX62Nxx_H + +/* Library prototypes */ +bool R_PFC_ReadRegisterAll( + const uint8_t, + volatile uint8_t * const +); +bool R_PFC_WriteRegisterAll( + const uint8_t, + const uint8_t +); +bool R_PFC_ModifyRegisterAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool ReturnFalse(void); + +/* Macro definitions */ + +/* R_PFC_Read */ +/* Call the function if the PFC number is valid (0 to 9). */ +#define R_PFC_Read(a, b) \ +( \ +((a) <= PDL_PFC_PFNPOE) ? \ +R_PFC_ReadRegisterAll( (a), (b) ) : \ +ReturnFalse() \ +) + +/* R_PFC_Write */ +/* Call the function if the PFC number is valid (0 to 9). */ +#define R_PFC_Write(a, b) \ +( \ +((a) <= PDL_PFC_PFNPOE) ? \ +R_PFC_WriteRegisterAll( (a), (b) ) : \ +ReturnFalse() \ +) + +/* R_PFC_Modify */ +/* Call the function if the PFC number is valid (0 to 9). */ +#define R_PFC_Modify(a, b, c) \ +( \ +((a) <= PDL_PFC_PFNPOE) ? \ +R_PFC_ModifyRegisterAll( (a), (b), (c) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_poe.h b/bsp/rx/RPDL/r_pdl_poe.h new file mode 100644 index 0000000000000000000000000000000000000000..0bc94dedf26bcbfff5f4a87130ffc66686fef7d1 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_poe.h @@ -0,0 +1,178 @@ +/*""FILE COMMENT""******************************************************* +* System Name : POE API for RX62Nxx +* File Name : r_pdl_poe.h +* Version : 1.02 +* Contents : POE API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_POE_H +#define R_PDL_POE_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_POE_Set( + uint32_t, + uint8_t, + uint32_t +); +bool R_POE_Create( + uint16_t, + void *, + void *, + void *, + void *, + uint8_t +); +bool POE_Control( + uint8_t, + uint16_t, + uint16_t +); +bool R_POE_GetStatus( + uint16_t * +); + +/* Pin selection */ +#define PDL_POE_PINS_0_TO_3 0x01u +#define PDL_POE_PINS_4_TO_7 0x02u +#define PDL_POE_PIN_8 0x04u +#define PDL_POE_PIN_9 0x08u + +/* Input pin detection */ +#define PDL_POE_0_MODE_EDGE 0x00000001ul +#define PDL_POE_0_MODE_LOW_8 0x00000002ul +#define PDL_POE_0_MODE_LOW_16 0x00000004ul +#define PDL_POE_0_MODE_LOW_128 0x00000008ul + +#define PDL_POE_1_MODE_EDGE 0x00000010ul +#define PDL_POE_1_MODE_LOW_8 0x00000020ul +#define PDL_POE_1_MODE_LOW_16 0x00000040ul +#define PDL_POE_1_MODE_LOW_128 0x00000080ul + +#define PDL_POE_2_MODE_EDGE 0x00000100ul +#define PDL_POE_2_MODE_LOW_8 0x00000200ul +#define PDL_POE_2_MODE_LOW_16 0x00000400ul +#define PDL_POE_2_MODE_LOW_128 0x00000800ul + +#define PDL_POE_3_MODE_EDGE 0x00001000ul +#define PDL_POE_3_MODE_LOW_8 0x00002000ul +#define PDL_POE_3_MODE_LOW_16 0x00004000ul +#define PDL_POE_3_MODE_LOW_128 0x00008000ul + +#define PDL_POE_4_MODE_EDGE 0x00010000ul +#define PDL_POE_4_MODE_LOW_8 0x00020000ul +#define PDL_POE_4_MODE_LOW_16 0x00040000ul +#define PDL_POE_4_MODE_LOW_128 0x00080000ul + +#define PDL_POE_5_MODE_EDGE 0x00100000ul +#define PDL_POE_5_MODE_LOW_8 0x00200000ul +#define PDL_POE_5_MODE_LOW_16 0x00400000ul +#define PDL_POE_5_MODE_LOW_128 0x00800000ul + +#define PDL_POE_6_MODE_EDGE 0x01000000ul +#define PDL_POE_6_MODE_LOW_8 0x02000000ul +#define PDL_POE_6_MODE_LOW_16 0x04000000ul +#define PDL_POE_6_MODE_LOW_128 0x08000000ul + +#define PDL_POE_7_MODE_EDGE 0x10000000ul +#define PDL_POE_7_MODE_LOW_8 0x20000000ul +#define PDL_POE_7_MODE_LOW_16 0x40000000ul +#define PDL_POE_7_MODE_LOW_128 0x80000000ul + +#define PDL_POE_8_MODE_EDGE 0x01u +#define PDL_POE_8_MODE_LOW_8 0x02u +#define PDL_POE_8_MODE_LOW_16 0x04u +#define PDL_POE_8_MODE_LOW_128 0x08u + +#define PDL_POE_9_MODE_EDGE 0x10u +#define PDL_POE_9_MODE_LOW_8 0x20u +#define PDL_POE_9_MODE_LOW_16 0x40u +#define PDL_POE_9_MODE_LOW_128 0x80u + +/* Pin output control */ + +/* High impedance request detection */ +#define PDL_POE_HI_Z_REQ_8_ENABLE 0x00000001ul +#define PDL_POE_HI_Z_REQ_MTIOC0A 0x00000002ul +#define PDL_POE_HI_Z_REQ_MTIOC0B 0x00000004ul +#define PDL_POE_HI_Z_REQ_MTIOC0C 0x00000008ul +#define PDL_POE_HI_Z_REQ_MTIOC0D 0x00000010ul + +#define PDL_POE_HI_Z_REQ_9_ENABLE 0x00000020ul +#define PDL_POE_HI_Z_REQ_MTIOC6A 0x00000040ul +#define PDL_POE_HI_Z_REQ_MTIOC6B 0x00000080ul +#define PDL_POE_HI_Z_REQ_MTIOC6C 0x00000100ul +#define PDL_POE_HI_Z_REQ_MTIOC6D 0x00000200ul + +/* Output short detection */ +#define PDL_POE_SHORT_3_4_HI_Z 0x00000400ul +#define PDL_POE_SHORT_MTIOC4BD_B 0x00000800ul +#define PDL_POE_SHORT_MTIOC4AC_B 0x00001000ul +#define PDL_POE_SHORT_MTIOC3BD_B 0x00002000ul +#define PDL_POE_SHORT_MTIOC4BD_A 0x00004000ul +#define PDL_POE_SHORT_MTIOC4AC_A 0x00008000ul +#define PDL_POE_SHORT_MTIOC3BD_A 0x00010000ul + +#define PDL_POE_SHORT_9_10_HI_Z 0x00020000ul +#define PDL_POE_SHORT_MTIOC10BD 0x00040000ul +#define PDL_POE_SHORT_MTIOC10AC 0x00080000ul +#define PDL_POE_SHORT_MTIOC9BD 0x00100000ul + +/* High impedance request response */ +#define PDL_POE_IRQ_HI_Z_0_3_DISABLE 0x0001u +#define PDL_POE_IRQ_HI_Z_0_3_ENABLE 0x0002u +#define PDL_POE_IRQ_HI_Z_4_7_DISABLE 0x0004u +#define PDL_POE_IRQ_HI_Z_4_7_ENABLE 0x0008u +#define PDL_POE_IRQ_HI_Z_8_DISABLE 0x0010u +#define PDL_POE_IRQ_HI_Z_8_ENABLE 0x0020u +#define PDL_POE_IRQ_HI_Z_9_DISABLE 0x0040u +#define PDL_POE_IRQ_HI_Z_9_ENABLE 0x0080u + +/* Output short detection response */ +#define PDL_POE_IRQ_SHORT_3_4_ENABLE 0x0100u +#define PDL_POE_IRQ_SHORT_3_4_DISABLE 0x0200u +#define PDL_POE_IRQ_SHORT_9_10_ENABLE 0x0400u +#define PDL_POE_IRQ_SHORT_9_10_DISABLE 0x0800u + +/* MTU channel high impedance control */ +#define PDL_POE_MTU3_MTU4_HI_Z_ON 0x01u +#define PDL_POE_MTU3_MTU4_HI_Z_OFF 0x02u +#define PDL_POE_MTU0_HI_Z_ON 0x04u +#define PDL_POE_MTU0_HI_Z_OFF 0x08u +#define PDL_POE_MTU9_MTU10_HI_Z_ON 0x10u +#define PDL_POE_MTU9_MTU10_HI_Z_OFF 0x20u +#define PDL_POE_MTU6_HI_Z_ON 0x40u +#define PDL_POE_MTU6_HI_Z_OFF 0x80u + +/* Event flag control */ +#define PDL_POE_FLAG_POE0_CLEAR 0x0001u +#define PDL_POE_FLAG_POE1_CLEAR 0x0002u +#define PDL_POE_FLAG_POE2_CLEAR 0x0004u +#define PDL_POE_FLAG_POE3_CLEAR 0x0008u +#define PDL_POE_FLAG_POE4_CLEAR 0x0010u +#define PDL_POE_FLAG_POE5_CLEAR 0x0020u +#define PDL_POE_FLAG_POE6_CLEAR 0x0040u +#define PDL_POE_FLAG_POE7_CLEAR 0x0080u +#define PDL_POE_FLAG_POE8_CLEAR 0x0100u +#define PDL_POE_FLAG_POE9_CLEAR 0x0200u +#define PDL_POE_FLAG_SHORT_3_4_CLEAR 0x0400u +#define PDL_POE_FLAG_SHORT_9_10_CLEAR 0x0800u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_poe_rx62nxx.h b/bsp/rx/RPDL/r_pdl_poe_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..898af219792bc7cea82f41cd4d8d2379ae097c09 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_poe_rx62nxx.h @@ -0,0 +1,80 @@ +/*""FILE COMMENT""******************************************************* +* System Name : POE API for RX62Nxx +* File Name : r_pdl_poe_RX62Nxx.h +* Version : 1.02 +* Contents : POE API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_POE_RX62Nxx_H +#define R_PDL_POE_RX62Nxx_H + +#define POE_INTERRUPTS 4 + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_POE_callback_func[]; + +/* Library prototypes */ +bool R_POE_SetAll( + const uint32_t, + const uint8_t, + const uint32_t +); +bool R_POE_CreateAll( + const uint16_t, + VoidCallBackFunc const, + VoidCallBackFunc const, + VoidCallBackFunc const, + VoidCallBackFunc const, + const uint8_t +); +bool R_POE_ControlAll( + const uint8_t, + const uint16_t, + const uint16_t +); +bool R_POE_GetStatusAll( + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_POE_Set(a, b, c) \ +( \ +R_POE_SetAll( (a), (b), (c) ) \ +) + +#define R_POE_Create(a, b, c, d, e, f) \ +( \ +( ((f) <= IPL_MAX) ) ? \ +R_POE_CreateAll( (a), (b), (c), (d), (e), (f) ) : \ +ReturnFalse() \ +) + +#define R_POE_Control(a, b, c) \ +( \ +R_POE_ControlAll( (a), (b), (c) ) \ +) + +#define R_POE_GetStatus(a) \ +( \ +R_POE_GetStatusAll( (a) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_ppg.h b/bsp/rx/RPDL/r_pdl_ppg.h new file mode 100644 index 0000000000000000000000000000000000000000..d1d1604333630fa6bf0c2ac29904ab5a19dabf49 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_ppg.h @@ -0,0 +1,105 @@ +/*""FILE COMMENT""******************************************************* +* System Name : PPG API for RX62Nxx +* File Name : r_pdl_PPG.h +* Version : 1.02 +* Contents : PPG API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_PPG_H +#define R_PDL_PPG_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_PPG_Create( + uint32_t, + uint16_t, + uint8_t +); +bool R_PPG_Destroy( + uint32_t +); +bool R_PPG_Control( + uint32_t, + uint8_t +); + +/* Output pin selection */ +#define PDL_PPG_PO0 (PDL_PPG_GROUP_0 | 0x01u) +#define PDL_PPG_PO1 (PDL_PPG_GROUP_0 | 0x02u) +#define PDL_PPG_PO2 (PDL_PPG_GROUP_0 | 0x04u) +#define PDL_PPG_PO3 (PDL_PPG_GROUP_0 | 0x08u) +#define PDL_PPG_PO4 (PDL_PPG_GROUP_1 | 0x10u) +#define PDL_PPG_PO5 (PDL_PPG_GROUP_1 | 0x20u) +#define PDL_PPG_PO6 (PDL_PPG_GROUP_1 | 0x40u) +#define PDL_PPG_PO7 (PDL_PPG_GROUP_1 | 0x80u) +#define PDL_PPG_PO8 (PDL_PPG_GROUP_2 | 0x01u) +#define PDL_PPG_PO9 (PDL_PPG_GROUP_2 | 0x02u) +#define PDL_PPG_PO10 (PDL_PPG_GROUP_2 | 0x04u) +#define PDL_PPG_PO11 (PDL_PPG_GROUP_2 | 0x08u) +#define PDL_PPG_PO12 (PDL_PPG_GROUP_3 | 0x10u) +#define PDL_PPG_PO13 (PDL_PPG_GROUP_3 | 0x20u) +#define PDL_PPG_PO14 (PDL_PPG_GROUP_3 | 0x40u) +#define PDL_PPG_PO15 (PDL_PPG_GROUP_3 | 0x80u) +#define PDL_PPG_PO16 (PDL_PPG_GROUP_4 | 0x01u) +#define PDL_PPG_PO17 (PDL_PPG_GROUP_4 | 0x02u) +#define PDL_PPG_PO18 (PDL_PPG_GROUP_4 | 0x04u) +#define PDL_PPG_PO19 (PDL_PPG_GROUP_4 | 0x08u) +#define PDL_PPG_PO20 (PDL_PPG_GROUP_5 | 0x10u) +#define PDL_PPG_PO21 (PDL_PPG_GROUP_5 | 0x20u) +#define PDL_PPG_PO22 (PDL_PPG_GROUP_5 | 0x40u) +#define PDL_PPG_PO23 (PDL_PPG_GROUP_5 | 0x80u) +#define PDL_PPG_PO24 (PDL_PPG_GROUP_6 | 0x01u) +#define PDL_PPG_PO25 (PDL_PPG_GROUP_6 | 0x02u) +#define PDL_PPG_PO26 (PDL_PPG_GROUP_6 | 0x04u) +#define PDL_PPG_PO27 (PDL_PPG_GROUP_6 | 0x08u) +#define PDL_PPG_PO28 (PDL_PPG_GROUP_7 | 0x10u) +#define PDL_PPG_PO29 (PDL_PPG_GROUP_7 | 0x20u) +#define PDL_PPG_PO30 (PDL_PPG_GROUP_7 | 0x40u) +#define PDL_PPG_PO31 (PDL_PPG_GROUP_7 | 0x80u) + +/* Output trigger selection */ +#define PDL_PPG_TRIGGER_MTU0 0x0001u +#define PDL_PPG_TRIGGER_MTU1 0x0002u +#define PDL_PPG_TRIGGER_MTU2 0x0004u +#define PDL_PPG_TRIGGER_MTU3 0x0008u +#define PDL_PPG_TRIGGER_MTU6 0x0010u +#define PDL_PPG_TRIGGER_MTU7 0x0020u +#define PDL_PPG_TRIGGER_MTU8 0x0040u +#define PDL_PPG_TRIGGER_MTU9 0x0080u + +/* Non-overlap control */ +#define PDL_PPG_NORMAL 0x0100u +#define PDL_PPG_NON_OVERLAP 0x0200u + +/* Invert control */ +#define PDL_PPG_DIRECT 0x0400u +#define PDL_PPG_INVERT 0x0800u + +/* Group selection */ +#define PDL_PPG_GROUP_0 0x00000100u +#define PDL_PPG_GROUP_1 0x00110200u +#define PDL_PPG_GROUP_2 0x00220400u +#define PDL_PPG_GROUP_3 0x00330800u +#define PDL_PPG_GROUP_4 0x01041000u +#define PDL_PPG_GROUP_5 0x01152000u +#define PDL_PPG_GROUP_6 0x01264000u +#define PDL_PPG_GROUP_7 0x01378000u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_ppg_rx62nxx.h b/bsp/rx/RPDL/r_pdl_ppg_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..218f300e7b3c60d615e717364076f8f2529d73ca --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_ppg_rx62nxx.h @@ -0,0 +1,76 @@ +/*""FILE COMMENT""******************************************************* +* System Name : PPG API for RX62Nxx +* File Name : r_pdl_ppg_RX62Nxx.h +* Version : 1.02 +* Contents : PPG API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_PPG_RX62Nxx_H +#define R_PDL_PPG_RX62Nxx_H + +#define PPG_UNITS 2 +#define PPG_GROUPS_PER_UNIT 4 +#define PPG_GROUPS (uint8_t)(PPG_UNITS * PPG_GROUPS_PER_UNIT) + +/* Library prototypes */ +bool R_PPG_CreateAll( + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint16_t, + const uint8_t +); +bool R_PPG_DestroyAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_PPG_ControlAll( + const uint8_t, + const uint8_t, + const uint8_t +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_PPG_Create(a, b, c) \ +( \ +( (a) != 0x00000000u ) ? \ +R_PPG_CreateAll( (uint8_t)(((a) & 0x0F000000ul) >> 24), (uint8_t)(((a) & 0x00F00000ul) >> 20), (uint8_t)(((a) & 0x000F0000ul) >> 16), (uint8_t)(((a) & 0x0000FF00ul) >> 8), (uint8_t)(a), (b), (c) ) : \ +ReturnFalse() \ +) + +#define R_PPG_Destroy(a) \ +( \ +( (a) != 0x00000000u ) ? \ +R_PPG_DestroyAll( (uint8_t)(((a) & 0x0F000000ul) >> 24), (uint8_t)(((a) & 0x0000FF00ul) >> 8), (uint8_t)(a) ) : \ +ReturnFalse() \ +) + +#define R_PPG_Control(a, b ) \ +( \ +( (a) != 0x00u ) ? \ +R_PPG_ControlAll( (uint8_t)(((a) & 0x0F000000ul) >> 24), (uint8_t)(((a) & 0x0000FF00ul) >> 8), (b) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_rtc.h b/bsp/rx/RPDL/r_pdl_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..2cdc21786824b51b72672d52e5d47003529ec75a --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_rtc.h @@ -0,0 +1,136 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Real-time clock API for RX62Nxx +* File Name : r_pdl_rtc.h +* Version : 1.02 +* Contents : RTC function prototypes +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_RTC_H +#define R_PDL_RTC_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_RTC_Create( + uint32_t, + uint32_t, + uint32_t, + uint32_t, + uint32_t, + void *, + uint8_t, + void *, + uint8_t +); +bool R_RTC_Control( + uint32_t, + uint16_t, + uint32_t, + uint32_t, + uint32_t, + uint32_t +); +bool R_RTC_Read( + uint8_t *, + uint32_t *, + uint32_t * +); + +/* Alarm control */ +#define PDL_RTC_ALARM_HOUR_DISABLE 0x00000001ul +#define PDL_RTC_ALARM_HOUR_ENABLE 0x00000002ul +#define PDL_RTC_ALARM_MINUTE_DISABLE 0x00000004ul +#define PDL_RTC_ALARM_MINUTE_ENABLE 0x00000008ul +#define PDL_RTC_ALARM_SECOND_DISABLE 0x00000010ul +#define PDL_RTC_ALARM_SECOND_ENABLE 0x00000020ul +#define PDL_RTC_ALARM_YEAR_DISABLE 0x00000040ul +#define PDL_RTC_ALARM_YEAR_ENABLE 0x00000080ul +#define PDL_RTC_ALARM_MONTH_DISABLE 0x00000100ul +#define PDL_RTC_ALARM_MONTH_ENABLE 0x00000200ul +#define PDL_RTC_ALARM_DAY_DISABLE 0x00000400ul +#define PDL_RTC_ALARM_DAY_ENABLE 0x00000800ul +#define PDL_RTC_ALARM_DOW_DISABLE 0x00001000ul +#define PDL_RTC_ALARM_DOW_ENABLE 0x00002000ul + +#define PDL_RTC_ALARM_TIME_DISABLE \ +(PDL_RTC_ALARM_HOUR_DISABLE | PDL_RTC_ALARM_MINUTE_DISABLE | PDL_RTC_ALARM_SECOND_DISABLE) +#define PDL_RTC_ALARM_TIME_ENABLE \ +(PDL_RTC_ALARM_HOUR_ENABLE | PDL_RTC_ALARM_MINUTE_ENABLE | PDL_RTC_ALARM_SECOND_ENABLE) +#define PDL_RTC_ALARM_DATE_DISABLE \ + (PDL_RTC_ALARM_YEAR_DISABLE | PDL_RTC_ALARM_MONTH_DISABLE | \ + PDL_RTC_ALARM_DAY_DISABLE | PDL_RTC_ALARM_DOW_DISABLE) +#define PDL_RTC_ALARM_DATE_ENABLE \ + (PDL_RTC_ALARM_YEAR_ENABLE | PDL_RTC_ALARM_MONTH_ENABLE | \ + PDL_RTC_ALARM_DAY_ENABLE | PDL_RTC_ALARM_DOW_ENABLE) + +/* Periodic interrupt selection */ +#define PDL_RTC_PERIODIC_DISABLE 0x00004000ul +#define PDL_RTC_PERIODIC_256_HZ 0x00008000ul +#define PDL_RTC_PERIODIC_64_HZ 0x00010000ul +#define PDL_RTC_PERIODIC_16_HZ 0x00020000ul +#define PDL_RTC_PERIODIC_4_HZ 0x00040000ul +#define PDL_RTC_PERIODIC_2_HZ 0x00080000ul +#define PDL_RTC_PERIODIC_1_HZ 0x00100000ul +#define PDL_RTC_PERIODIC_2S 0x00200000ul + +/* Clock output control */ +#define PDL_RTC_OUTPUT_DISABLE 0x00400000ul +#define PDL_RTC_OUTPUT_ENABLE 0x00800000ul + +/* Clock control */ +#define PDL_RTC_CLOCK_STOP 0x01000000ul +#define PDL_RTC_CLOCK_START 0x02000000ul + +/* 30-second adjustment control */ +#define PDL_RTC_ADJUST_START 0x04000000ul + +/* Reset control */ +#define PDL_RTC_RESET_START 0x08000000ul + +/* Current time counter selection */ +#define PDL_RTC_UPDATE_CURRENT_HOUR 0x0001u +#define PDL_RTC_UPDATE_CURRENT_MINUTE 0x0002u +#define PDL_RTC_UPDATE_CURRENT_SECOND 0x0004u +#define PDL_RTC_UPDATE_CURRENT_TIME \ +(PDL_RTC_UPDATE_CURRENT_HOUR | PDL_RTC_UPDATE_CURRENT_MINUTE | PDL_RTC_UPDATE_CURRENT_SECOND) + +/* Current date counter selection */ +#define PDL_RTC_UPDATE_CURRENT_YEAR 0x0008u +#define PDL_RTC_UPDATE_CURRENT_MONTH 0x0010u +#define PDL_RTC_UPDATE_CURRENT_DAY 0x0020u +#define PDL_RTC_UPDATE_CURRENT_DOW 0x0040u +#define PDL_RTC_UPDATE_CURRENT_DATE \ +(PDL_RTC_UPDATE_CURRENT_YEAR | PDL_RTC_UPDATE_CURRENT_MONTH | PDL_RTC_UPDATE_CURRENT_DAY | PDL_RTC_UPDATE_CURRENT_DOW) + +/* Alarm time counter selection */ +#define PDL_RTC_UPDATE_ALARM_HOUR 0x0080u +#define PDL_RTC_UPDATE_ALARM_MINUTE 0x0100u +#define PDL_RTC_UPDATE_ALARM_SECOND 0x0200u +#define PDL_RTC_UPDATE_ALARM_TIME \ +(PDL_RTC_UPDATE_ALARM_HOUR | PDL_RTC_UPDATE_ALARM_MINUTE | PDL_RTC_UPDATE_ALARM_SECOND) + +/* Alarm date counter selection */ +#define PDL_RTC_UPDATE_ALARM_YEAR 0x0400u +#define PDL_RTC_UPDATE_ALARM_MONTH 0x0800u +#define PDL_RTC_UPDATE_ALARM_DAY 0x1000u +#define PDL_RTC_UPDATE_ALARM_DOW 0x2000u +#define PDL_RTC_UPDATE_ALARM_DATE \ +(PDL_RTC_UPDATE_ALARM_YEAR | PDL_RTC_UPDATE_ALARM_MONTH | PDL_RTC_UPDATE_ALARM_DAY | PDL_RTC_UPDATE_ALARM_DOW) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_rtc_RX62Nxx.h b/bsp/rx/RPDL/r_pdl_rtc_RX62Nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..bc243cd0b41cc5d41394b2ac78409835d2a0f1ca --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_rtc_RX62Nxx.h @@ -0,0 +1,76 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Real-time clock API for RX62Nxx +* File Name : r_pdl_rtc_RX62Nxx.h +* Version : 1.02 +* Contents : RTC header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_RTC_RX62Nxx_H +#define R_PDL_RTC_RX62Nxx_H + +extern VoidCallBackFunc rpdl_RTC_Periodic_callback_func; +extern VoidCallBackFunc rpdl_RTC_Alarm_callback_func; + +/* Library prototypes */ +bool R_RTC_CreateAll( + const uint32_t, + const uint32_t, + const uint32_t, + const uint32_t, + const uint32_t, + VoidCallBackFunc const, + const uint8_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_RTC_ControlAll( + const uint32_t, + const uint16_t, + const uint32_t, + const uint32_t, + const uint32_t, + const uint32_t +); +bool R_RTC_ReadAll( + volatile uint8_t * const, + volatile uint32_t * const, + volatile uint32_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_RTC_Create(a, b, c, d, e, f, g, h, i) \ +( \ +( ((g) <= IPL_MAX) && ((i) <= IPL_MAX) ) ? \ +R_RTC_CreateAll( (a), (b), (c), (d), (e), (f), (g), (h), (i) ): \ +ReturnFalse() \ +) + +#define R_RTC_Control(a, b, c, d, e, f) \ +( \ +R_RTC_ControlAll( (a), (b), (c), (d), (e), (f) ) \ +) + +#define R_RTC_Read(a, b, c) \ +( \ +R_RTC_ReadAll( (a), (b), (c) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_sci.h b/bsp/rx/RPDL/r_pdl_sci.h new file mode 100644 index 0000000000000000000000000000000000000000..62a636c14aa46e5d3548e16788a10b3e8aad64d7 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_sci.h @@ -0,0 +1,203 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Serial Communication Interface API for RX62Nxx +* File Name : r_pdl_sci.h +* Version : 1.02 +* Contents : Serial Interface API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_SCI_H +#define R_PDL_SCI_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_SCI_Set( + uint8_t +); +bool R_SCI_Create( + uint8_t, + uint32_t, + uint32_t, + uint8_t +); +bool R_SCI_Destroy( + uint8_t +); +bool R_SCI_Send( + uint8_t, + uint16_t, + uint8_t *, + uint16_t, + void * +); +bool R_SCI_Receive( + uint8_t, + uint16_t, + uint8_t *, + uint16_t, + void *, + void * +); +bool R_SCI_Control( + uint8_t, + uint8_t +); +bool R_SCI_GetStatus( + uint8_t, + uint8_t *, + uint8_t *, + uint16_t *, + uint16_t * +); + +/* ------------------------ */ +/* R_SCI_Set, Configuration */ +/* ------------------------ */ +/* Pin selection */ +#define PDL_SCI_PIN_SCI1_A 0x01u +#define PDL_SCI_PIN_SCI1_B 0x02u +#define PDL_SCI_PIN_SCI2_A 0x04u +#define PDL_SCI_PIN_SCI2_B 0x08u +#define PDL_SCI_PIN_SCI3_A 0x10u +#define PDL_SCI_PIN_SCI3_B 0x20u +#define PDL_SCI_PIN_SCI6_A 0x40u +#define PDL_SCI_PIN_SCI6_B 0x80u + +/* ----------------------------------------- */ +/* R_SCI_Create, data2 Channel configuration */ +/* ----------------------------------------- */ +/* Operation mode */ +#define PDL_SCI_ASYNC 0x00000001ul +#define PDL_SCI_SYNC 0x00000002ul +#define PDL_SCI_SMART 0x00000004ul +#define PDL_SCI_ASYNC_MP 0x00000008ul + +/* Common selections */ + +/* Transmit / Receive connections */ +#define PDL_SCI_TX_CONNECTED 0x00000010ul +#define PDL_SCI_TX_DISCONNECTED 0x00000020ul +#define PDL_SCI_RX_CONNECTED 0x00000040ul +#define PDL_SCI_RX_DISCONNECTED 0x00000080ul + +/* Data clock source */ +#define PDL_SCI_CLK_INT_OUT 0x00000100ul +#define PDL_SCI_CLK_EXT 0x00000200ul + +/* Parity selection */ +#define PDL_SCI_PARITY_EVEN 0x00000400ul +#define PDL_SCI_PARITY_ODD 0x00000800ul + +/* Asynchronous-only selections */ + +/* Data clock source */ +#define PDL_SCI_CLK_INT_IO 0x00001000ul +#define PDL_SCI_CLK_TMR 0x00002000ul + +/* Data length */ +#define PDL_SCI_8_BIT_LENGTH 0x00004000ul +#define PDL_SCI_7_BIT_LENGTH 0x00008000ul + +/* Parity selection */ +#define PDL_SCI_PARITY_NONE 0x00010000ul + +/* Stop bit length */ +#define PDL_SCI_STOP_1 0x00020000ul +#define PDL_SCI_STOP_2 0x00040000ul + +#define PDL_SCI_8N1 (PDL_SCI_8_BIT_LENGTH | PDL_SCI_PARITY_NONE | PDL_SCI_STOP_1) + +/* Smart card-only selections */ + +/* Data transfer format */ +#define PDL_SCI_LSB_FIRST 0x00001000ul +#define PDL_SCI_MSB_FIRST 0x00002000ul + +/* Data inversion */ +#define PDL_SCI_INVERSION_OFF 0x00004000ul +#define PDL_SCI_INVERSION_ON 0x00008000ul + +/* Base clock pulse cycle count */ +#define PDL_SCI_BCP_32 0x00010000ul +#define PDL_SCI_BCP_64 0x00020000ul +#define PDL_SCI_BCP_93 0x00040000ul +#define PDL_SCI_BCP_128 0x00080000ul +#define PDL_SCI_BCP_186 0x00100000ul +#define PDL_SCI_BCP_256 0x00200000ul +#define PDL_SCI_BCP_372 0x00400000ul +#define PDL_SCI_BCP_512 0x00800000ul + +/* Block transfer mode */ +#define PDL_SCI_BLOCK_MODE_OFF 0x01000000ul +#define PDL_SCI_BLOCK_MODE_ON 0x02000000ul + +/* GSM mode */ +#define PDL_SCI_GSM_MODE_OFF 0x04000000ul +#define PDL_SCI_GSM_MODE_ON 0x08000000ul + +/* Clock output control */ +#define PDL_SCI_SCK_OUTPUT_OFF 0x10000000ul +#define PDL_SCI_SCK_OUTPUT_LOW 0x20000000ul +#define PDL_SCI_SCK_OUTPUT_ON 0x40000000ul +#define PDL_SCI_SCK_OUTPUT_HIGH 0x80000000ul + +/* ----------------------------------- */ +/* R_SCI_Create, data3 register value */ +/* ----------------------------------- */ +/* Transfer clock control */ + +/* CKS selection (optional) */ +#define PDL_SCI_PCLK_DIV_1 0x01000000ul +#define PDL_SCI_PCLK_DIV_4 0x02000000ul +#define PDL_SCI_PCLK_DIV_16 0x03000000ul +#define PDL_SCI_PCLK_DIV_64 0x04000000ul + +/* ABCS selection (optional) */ +#define PDL_SCI_CYCLE_BIT_16 0x10000000ul +#define PDL_SCI_CYCLE_BIT_8 0x20000000ul + +/* ----------------------------------------------- */ +/* R_SCI_Send/R_SCI_Receive, Channel configuration */ +/* ----------------------------------------------- */ +/* DMAC / DTC trigger control */ +#define PDL_SCI_DMAC_DTC_TRIGGER_DISABLE 0x0001u +#define PDL_SCI_DMAC_TRIGGER_ENABLE 0x0002u +#define PDL_SCI_DTC_TRIGGER_ENABLE 0x0004u +#define PDL_SCI_MP_ID_CYCLE 0x0008u + +/* ------------------------------ */ +/* R_SCI_Control, Channel control */ +/* ------------------------------ */ +/* Stop control */ +#define PDL_SCI_STOP_TX 0x01u +#define PDL_SCI_STOP_RX 0x02u +#define PDL_SCI_STOP_TX_AND_RX (PDL_SCI_STOP_TX | PDL_SCI_STOP_RX) + +/* Break output control */ +#define PDL_SCI_OUTPUT_MARK 0x04u +#define PDL_SCI_OUTPUT_SPACE 0x08u + +/* Error flag control */ +#define PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS 0x10u + +/* Manual SCK control */ +#define PDL_SCI_GSM_SCK_STOP 0x20u +#define PDL_SCI_GSM_SCK_START 0x40u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_sci_rx62nxx.h b/bsp/rx/RPDL/r_pdl_sci_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..d1177c4b01ac39d5e8924aa1c29e8eb9d1e33a71 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_sci_rx62nxx.h @@ -0,0 +1,178 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Serial Communication Interface API for RX62Nxx +* File Name : r_pdl_sci_RX62Nxx.h +* Version : 1.02 +* Contents : Serial Interface API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_SCI_RX62Nxx_H +#define R_PDL_SCI_RX62Nxx_H + +#define SCI_CHANNELS 7 + +/* Globals */ +extern volatile const uint8_t * rpdl_SCI_tx_string_pointer[SCI_CHANNELS]; +extern volatile uint8_t * rpdl_SCI_rx_string_pointer[SCI_CHANNELS]; +extern volatile uint8_t * rpdl_SCI_rx_string_start[SCI_CHANNELS]; +extern volatile uint16_t rpdl_SCI_rx_counter[SCI_CHANNELS]; +extern volatile uint16_t rpdl_SCI_tx_counter[SCI_CHANNELS]; +extern volatile uint16_t rpdl_SCI_rx_threshold[SCI_CHANNELS]; +extern volatile uint16_t rpdl_SCI_tx_threshold[SCI_CHANNELS]; +extern volatile uint8_t rpdl_SCI_tx_using_irq[SCI_CHANNELS]; +extern volatile uint8_t rpdl_SCI_rx_using_irq[SCI_CHANNELS]; +extern volatile uint8_t rpdl_SCI_sync_simultaneous[SCI_CHANNELS]; +extern volatile uint8_t rpdl_SCI_MP_mode[SCI_CHANNELS]; +extern volatile uint8_t rpdl_SCI_MP_rx_stationID[SCI_CHANNELS]; + +/* Callback function prototypes */ +extern VoidCallBackFunc rpdl_SCI_TX_End_callback_func[SCI_CHANNELS]; +extern VoidCallBackFunc rpdl_SCI_RX_End_callback_func[SCI_CHANNELS]; +extern VoidCallBackFunc rpdl_SCI_RX_Error_callback_func[SCI_CHANNELS]; + +/* Library prototypes */ +bool R_SCI_SetAll( + const uint8_t +); +bool R_SCI_CreateAll( + const uint8_t, + const uint32_t, + const uint32_t, + const uint8_t +); +bool R_SCI_CreateAsyncAll( + const uint8_t, + const uint32_t, + const uint32_t, + const uint8_t +); +bool R_SCI_CreateSyncAll( + const uint8_t, + const uint32_t, + const uint32_t, + const uint8_t +); +bool R_SCI_CreateSmartAll( + const uint8_t, + const uint32_t, + const uint32_t, + const uint8_t +); +bool R_SCI_DestroyAll( + const uint8_t +); +bool R_SCI_SendAll( + const uint8_t, + const uint16_t, + volatile const uint8_t * const, + const uint16_t, + VoidCallBackFunc const +); +bool R_SCI_SendStationID( + const uint8_t, + const uint16_t +); +bool R_SCI_SendData( + const uint8_t, + const uint16_t, + volatile const uint8_t * const, + const uint16_t, + VoidCallBackFunc const +); +bool R_SCI_ReceiveAll( + const uint8_t, + const uint16_t, + volatile uint8_t * const, + const uint16_t, + VoidCallBackFunc const, + VoidCallBackFunc const +); +bool R_SCI_ReceiveStationID( + const uint8_t, + const uint16_t, + VoidCallBackFunc const, + VoidCallBackFunc const +); +bool R_SCI_ReceiveData( + const uint8_t, + const uint16_t, + volatile uint8_t * const, + const uint16_t, + VoidCallBackFunc const, + VoidCallBackFunc const +); +bool R_SCI_ControlAll( + const uint8_t, + const uint8_t +); +bool R_SCI_GetStatusAll( + const uint8_t, + volatile uint8_t * const, + volatile uint8_t * const, + volatile uint16_t * const, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ +#define R_SCI_Set(a) \ +( R_SCI_SetAll( (a) ) ) + +#define R_SCI_Create(a, b, c, d) \ +( \ +( ((a) >= SCI_CHANNELS) || ((a) == 4) || ((c) == 0) || ((d) > IPL_MAX) )? \ +ReturnFalse(): \ +R_SCI_CreateAll( (a), (b), (c), (d) )\ +) + +#define R_SCI_Destroy(a) \ +( \ +(((a) < SCI_CHANNELS) && ((a) != 4)) ? \ +R_SCI_DestroyAll( (a) ): \ +ReturnFalse() \ +) + +#define R_SCI_Send(a, b, c, d, e) \ +( \ +(((a) < SCI_CHANNELS) && ((a) != 4)) ? \ +R_SCI_SendAll( (a), (b), (c), (d), (e) ): \ +ReturnFalse() \ +) + +#define R_SCI_Receive(a, b, c, d, e, f) \ +( \ +(((a) < SCI_CHANNELS) && ((a) != 4)) ? \ +R_SCI_ReceiveAll( (a), (b), (c), (d), (e), (f) ): \ +ReturnFalse() \ +) + +#define R_SCI_Control(a, b) \ +( \ +(((a) < SCI_CHANNELS) && ((a) != 4)) ? \ +R_SCI_ControlAll( (a), (b) ): \ +ReturnFalse() \ +) + +#define R_SCI_GetStatus(a, b, c, d, e) \ +( \ +(((a) < SCI_CHANNELS) && ((a) != 4)) ? \ +R_SCI_GetStatusAll( (a), (b), (c), (d), (e) ): \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_spi.h b/bsp/rx/RPDL/r_pdl_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..cd3a5514829e3e52576b641c92715e73c37d0b6a --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_spi.h @@ -0,0 +1,222 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Serial Peripheral Interface API for RX62Nxx +* File Name : r_pdl_spi.h +* Version : 1.02 +* Contents : SPI API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_SPI_H +#define R_PDL_SPI_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_SPI_Create( + uint8_t, + uint32_t, + uint32_t, + uint32_t, + uint32_t +); +bool R_SPI_Destroy( + uint8_t +); +bool R_SPI_Command( + uint8_t, + uint8_t, + uint32_t, + uint8_t +); +bool R_SPI_Transfer( + uint8_t, + uint8_t, + uint32_t *, + uint32_t *, + uint16_t, + void *, + uint8_t +); +bool R_SPI_Control( + uint8_t, + uint8_t, + uint32_t +); +bool R_SPI_GetStatus( + uint8_t, + uint16_t *, + uint16_t * +); + +/* Connection mode */ +#define PDL_SPI_MODE_SPI_MASTER 0x00000001ul +#define PDL_SPI_MODE_SPI_MULTI_MASTER 0x00000002ul +#define PDL_SPI_MODE_SPI_SLAVE 0x00000004ul +#define PDL_SCI_MODE_SYNC_MASTER 0x00000008ul +#define PDL_SCI_MODE_SYNC_SLAVE 0x00000010ul + +/* Reception control */ +#define PDL_SPI_FULL_DUPLEX 0x00000020ul +#define PDL_SPI_TRANSMIT_ONLY 0x00000040ul + +/* Pin selection and control */ +#define PDL_SPI_PIN_CMOS 0x00000080ul +#define PDL_SPI_PIN_OPEN_DRAIN 0x00000100ul +#define PDL_SPI_PIN_A 0x00000200ul +#define PDL_SPI_PIN_B 0x00000400ul +#define PDL_SPI_PIN_RSPCK_ENABLE 0x00000800ul +#define PDL_SPI_PIN_RSPCK_DISABLE 0x00001000ul +#define PDL_SPI_PIN_MOSI_ENABLE 0x00002000ul +#define PDL_SPI_PIN_MOSI_DISABLE 0x00004000ul +#define PDL_SPI_PIN_MISO_ENABLE 0x00008000ul +#define PDL_SPI_PIN_MISO_DISABLE 0x00010000ul +#define PDL_SPI_PIN_SSL0_LOW 0x00020000ul +#define PDL_SPI_PIN_SSL0_HIGH 0x00040000ul +#define PDL_SPI_PIN_SSL0_DISABLE 0x00080000ul +#define PDL_SPI_PIN_SSL1_LOW 0x00100000ul +#define PDL_SPI_PIN_SSL1_HIGH 0x00200000ul +#define PDL_SPI_PIN_SSL1_DISABLE 0x00400000ul +#define PDL_SPI_PIN_SSL2_LOW 0x00800000ul +#define PDL_SPI_PIN_SSL2_HIGH 0x01000000ul +#define PDL_SPI_PIN_SSL2_DISABLE 0x02000000ul +#define PDL_SPI_PIN_SSL3_LOW 0x04000000ul +#define PDL_SPI_PIN_SSL3_HIGH 0x08000000ul +#define PDL_SPI_PIN_SSL3_DISABLE 0x10000000ul +#define PDL_SPI_PIN_MOSI_IDLE_LAST 0x20000000ul +#define PDL_SPI_PIN_MOSI_IDLE_LOW 0x40000000ul +#define PDL_SPI_PIN_MOSI_IDLE_HIGH 0x80000000ul + +/* Buffer size */ +#define PDL_SPI_BUFFER_64 0x00000001ul +#define PDL_SPI_BUFFER_128 0x00000002ul + +/* Frame configuration selection */ +#define PDL_SPI_FRAME_1_1 0x00000004ul +#define PDL_SPI_FRAME_1_2 0x00000008ul +#define PDL_SPI_FRAME_1_3 0x00000010ul +#define PDL_SPI_FRAME_1_4 0x00000020ul +#define PDL_SPI_FRAME_2_1 0x00000040ul +#define PDL_SPI_FRAME_2_2 0x00000080ul +#define PDL_SPI_FRAME_3 0x00000100ul +#define PDL_SPI_FRAME_4 0x00000200ul +#define PDL_SPI_FRAME_5 0x00000400ul +#define PDL_SPI_FRAME_6 0x00000800ul +#define PDL_SPI_FRAME_7 0x00001000ul +#define PDL_SPI_FRAME_8 0x00002000ul + +/* Parity bit control */ +#define PDL_SPI_PARITY_NONE 0x00004000ul +#define PDL_SPI_PARITY_EVEN 0x00008000ul +#define PDL_SPI_PARITY_ODD 0x00010000ul + +/* Extended clock delay */ +#define PDL_SPI_CLOCK_DELAY_1 0x00000001ul +#define PDL_SPI_CLOCK_DELAY_2 0x00000002ul +#define PDL_SPI_CLOCK_DELAY_3 0x00000004ul +#define PDL_SPI_CLOCK_DELAY_4 0x00000008ul +#define PDL_SPI_CLOCK_DELAY_5 0x00000010ul +#define PDL_SPI_CLOCK_DELAY_6 0x00000020ul +#define PDL_SPI_CLOCK_DELAY_7 0x00000040ul +#define PDL_SPI_CLOCK_DELAY_8 0x00000080ul + +/* Extended SSL negation delay */ +#define PDL_SPI_SSL_DELAY_1 0x00000100ul +#define PDL_SPI_SSL_DELAY_2 0x00000200ul +#define PDL_SPI_SSL_DELAY_3 0x00000400ul +#define PDL_SPI_SSL_DELAY_4 0x00000800ul +#define PDL_SPI_SSL_DELAY_5 0x00001000ul +#define PDL_SPI_SSL_DELAY_6 0x00002000ul +#define PDL_SPI_SSL_DELAY_7 0x00004000ul +#define PDL_SPI_SSL_DELAY_8 0x00008000ul + +/* Extended next-access delay */ +#define PDL_SPI_NEXT_DELAY_1 0x00010000ul +#define PDL_SPI_NEXT_DELAY_2 0x00020000ul +#define PDL_SPI_NEXT_DELAY_3 0x00040000ul +#define PDL_SPI_NEXT_DELAY_4 0x00080000ul +#define PDL_SPI_NEXT_DELAY_5 0x00100000ul +#define PDL_SPI_NEXT_DELAY_6 0x00200000ul +#define PDL_SPI_NEXT_DELAY_7 0x00400000ul +#define PDL_SPI_NEXT_DELAY_8 0x00800000ul + +/* Channel control */ +#define PDL_SPI_DISABLE 0x01u + +/* Loopback control */ +#define PDL_SPI_LOOPBACK_DISABLE 0x02u +#define PDL_SPI_LOOPBACK_DIRECT 0x04u +#define PDL_SPI_LOOPBACK_REVERSED 0x08u + +/* Clock phase and polarity */ +#define PDL_SPI_CLOCK_MODE_0 0x00000001ul +#define PDL_SPI_CLOCK_MODE_1 0x00000002ul +#define PDL_SPI_CLOCK_MODE_2 0x00000004ul +#define PDL_SPI_CLOCK_MODE_3 0x00000008ul + +/* Clock division */ +#define PDL_SPI_DIV_1 0x00000010ul +#define PDL_SPI_DIV_2 0x00000020ul +#define PDL_SPI_DIV_4 0x00000040ul +#define PDL_SPI_DIV_8 0x00000080ul + +/* SSL assertion */ +#define PDL_SPI_ASSERT_SSL0 0x00000100ul +#define PDL_SPI_ASSERT_SSL1 0x00000200ul +#define PDL_SPI_ASSERT_SSL2 0x00000400ul +#define PDL_SPI_ASSERT_SSL3 0x00000800ul + +/* SSL negation */ +#define PDL_SPI_SSL_NEGATE 0x00001000ul +#define PDL_SPI_SSL_KEEP 0x00002000ul + +/* Frame data length */ +#define PDL_SPI_LENGTH_8 0x00004000ul +#define PDL_SPI_LENGTH_9 0x00008000ul +#define PDL_SPI_LENGTH_10 0x00010000ul +#define PDL_SPI_LENGTH_11 0x00020000ul +#define PDL_SPI_LENGTH_12 0x00040000ul +#define PDL_SPI_LENGTH_13 0x00080000ul +#define PDL_SPI_LENGTH_14 0x00100000ul +#define PDL_SPI_LENGTH_15 0x00200000ul +#define PDL_SPI_LENGTH_16 0x00400000ul +#define PDL_SPI_LENGTH_20 0x00800000ul +#define PDL_SPI_LENGTH_24 0x01000000ul +#define PDL_SPI_LENGTH_32 0x02000000ul + +/* Data transfer format */ +#define PDL_SPI_MSB_FIRST 0x04000000ul +#define PDL_SPI_LSB_FIRST 0x08000000ul + +/* Extended timing selection */ +#define PDL_SPI_CLOCK_DELAY_MINIMUM 0x01u +#define PDL_SPI_CLOCK_DELAY_EXTENDED 0x02u + +/* Extended timing selection */ +#define PDL_SPI_SSL_DELAY_MINIMUM 0x04u +#define PDL_SPI_SSL_DELAY_EXTENDED 0x08u + +/* Next-access delay */ +#define PDL_SPI_NEXT_DELAY_MINIMUM 0x10u +#define PDL_SPI_NEXT_DELAY_EXTENDED 0x20u + +/* DMAC / DTC trigger control */ +#define PDL_SPI_DMAC_DTC_TRIGGER_DISABLE 0x01u +#define PDL_SPI_DMAC_TRIGGER_ENABLE 0x02u +#define PDL_SPI_DTC_TRIGGER_ENABLE 0x04u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_spi_rx62nxx.h b/bsp/rx/RPDL/r_pdl_spi_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..a64a6e333324e947688d17ff2bd350499b613c5c --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_spi_rx62nxx.h @@ -0,0 +1,131 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Serial Peripheral Interface API for RX62Nxx +* File Name : r_pdl_spi_RX62Nxx.h +* Version : 1.02 +* Contents : SPI API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_SPI_RX62Nxx_H +#define R_PDL_SPI_RX62Nxx_H + +#define SPI_CHANNELS 2 +#define SPI_COMMANDS 8 + +/* Globals */ +extern volatile uint8_t rpdl_SPI_method[SPI_CHANNELS]; +extern volatile uint16_t rpdl_SPI_sequence_count[SPI_CHANNELS]; +extern volatile uint16_t rpdl_SPI_tx_sequence_counter[SPI_CHANNELS]; +extern volatile uint16_t rpdl_SPI_rx_sequence_counter[SPI_CHANNELS]; +extern volatile uint8_t rpdl_SPI_tx_frame_counter[SPI_CHANNELS]; +extern volatile uint8_t rpdl_SPI_frame_total[SPI_CHANNELS]; +extern volatile uint8_t rpdl_SPI_rx_frame_counter[SPI_CHANNELS]; +extern volatile const uint32_t * rpdl_SPI_tx_ptr[SPI_CHANNELS]; +extern volatile uint32_t * rpdl_SPI_rx_ptr[SPI_CHANNELS]; + +/* Callback function prototypes */ +extern VoidCallBackFunc rpdl_SPI_callback_func[SPI_CHANNELS]; + +/* Request trigger options */ +typedef enum { + SPI_USING_POLLING, + SPI_USING_IRQ, + SPI_USING_DMAC_DTC +} rpdl_spi_transfer_options; + +bool R_SPI_CreateAll( + const uint8_t, + const uint32_t, + const uint32_t, + const uint32_t, + const uint32_t +); +bool R_SPI_DestroyAll( + const uint8_t +); +bool R_SPI_CommandAll( + const uint8_t, + const uint8_t, + const uint32_t, + const uint8_t +); +bool R_SPI_TransferAll( + const uint8_t, + const uint8_t, + volatile const uint32_t * const, + volatile uint32_t * const, + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_SPI_ControlAll( + const uint8_t, + const uint8_t, + const uint32_t +); +bool R_SPI_GetStatusAll( + const uint8_t, + volatile uint16_t * const, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ +#define R_SPI_Create(a, b, c, d, e) \ +( \ +( (a) < SPI_CHANNELS) ? \ +R_SPI_CreateAll( (a), (b), (c), (d), (e) ): \ +ReturnFalse() \ +) + +#define R_SPI_Destroy(a) \ +( \ +( (a) < SPI_CHANNELS) ? \ +R_SPI_DestroyAll( (a) ): \ +ReturnFalse() \ +) + +#define R_SPI_Command(a, b, c, d) \ +( \ +( ( ((a) < SPI_CHANNELS) && ((b) < SPI_COMMANDS) ) ) ? \ +R_SPI_CommandAll( (a), (b), (c), (d) ): \ +ReturnFalse() \ +) + +#define R_SPI_Transfer(a, b, c, d, e, f, g) \ +( \ +( ( ((a) < SPI_CHANNELS) && ((g) <= IPL_MAX) ) ) ? \ +R_SPI_TransferAll( (a), (b), (c), (d), (e), (f), (g) ): \ +ReturnFalse() \ +) + +#define R_SPI_Control(a, b, c) \ +( \ +( (a) < SPI_CHANNELS) ? \ +R_SPI_ControlAll( (a), (b), (c) ): \ +ReturnFalse() \ +) + +#define R_SPI_GetStatus(a, b, c) \ +( \ +( (a) < SPI_CHANNELS) ? \ +R_SPI_GetStatusAll( (a), (b), (c) ): \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_tmr.h b/bsp/rx/RPDL/r_pdl_tmr.h new file mode 100644 index 0000000000000000000000000000000000000000..0c903b9817ab22c4a5db9cb43b4417b693a2f363 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_tmr.h @@ -0,0 +1,211 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Timer TMR API for RX62Nxx +* File Name : r_pdl_tmr.h +* Version : 1.02 +* Contents : Timer TMR API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_TMR_H +#define R_PDL_TMR_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_TMR_Set( + uint8_t +); +bool R_TMR_CreateChannel( + uint8_t, + uint32_t, + uint8_t, + uint8_t, + uint8_t, + uint8_t, + void *, + void *, + void *, + uint8_t +); +bool R_TMR_CreateUnit( + uint8_t, + uint32_t, + uint8_t, + uint16_t, + uint16_t, + uint16_t, + void *, + void *, + void *, + uint8_t +); +bool R_TMR_CreatePeriodic( + uint8_t, + uint32_t, + float, + float, + void *, + void *, + uint8_t +); +bool R_TMR_CreateOneShot( + uint8_t, + uint32_t, + float, + void *, + uint8_t +); +bool R_TMR_Destroy( + uint8_t +); +bool R_TMR_ControlChannel( + uint8_t, + uint32_t, + uint8_t, + uint8_t, + uint8_t +); +bool R_TMR_ControlUnit( + uint8_t, + uint32_t, + uint16_t, + uint16_t, + uint16_t +); +bool R_TMR_ControlPeriodic( + uint8_t, + uint32_t, + float, + float +); +bool R_TMR_ReadChannel( + uint8_t, + uint8_t *, + uint8_t *, + uint8_t *, + uint8_t * +); +bool R_TMR_ReadUnit( + uint8_t, + uint8_t *, + uint16_t *, + uint16_t *, + uint16_t * +); + +/* Pin selection */ +#define PDL_TMR_PIN_TMR0_A 0x01u +#define PDL_TMR_PIN_TMR0_B 0x02u +#define PDL_TMR_PIN_TMR1_A 0x04u +#define PDL_TMR_PIN_TMR1_B 0x08u +#define PDL_TMR_PIN_TMR2_A 0x10u +#define PDL_TMR_PIN_TMR2_B 0x20u +#define PDL_TMR_PIN_TMR3_A 0x40u +#define PDL_TMR_PIN_TMR3_B 0x80u + +/* Counter clock sources */ +#define PDL_TMR_CLK_OFF 0x00000001ul +#define PDL_TMR_CLK_EXT_RISING 0x00000002ul +#define PDL_TMR_CLK_EXT_FALLING 0x00000004ul +#define PDL_TMR_CLK_EXT_BOTH 0x00000008ul +#define PDL_TMR_CLK_PCLK_DIV_1 0x00000010ul +#define PDL_TMR_CLK_PCLK_DIV_2 0x00000020ul +#define PDL_TMR_CLK_PCLK_DIV_8 0x00000040ul +#define PDL_TMR_CLK_PCLK_DIV_32 0x00000080ul +#define PDL_TMR_CLK_PCLK_DIV_64 0x00000100ul +#define PDL_TMR_CLK_PCLK_DIV_1024 0x00000200ul +#define PDL_TMR_CLK_PCLK_DIV_8192 0x00000400ul +#define PDL_TMR_CLK_TMR1_OVERFLOW 0x00000800ul +#define PDL_TMR_CLK_TMR3_OVERFLOW 0x00001000ul +#define PDL_TMR_CLK_TMR0_CM_A 0x00002000ul +#define PDL_TMR_CLK_TMR2_CM_A 0x00004000ul + +/* A/D trigger control */ +#define PDL_TMR_ADC_TRIGGER_DISABLE 0x00008000ul +#define PDL_TMR_ADC_TRIGGER_ENABLE 0x00010000ul + +/* Counter clearing options */ +#define PDL_TMR_CLEAR_DISABLE 0x00020000ul +#define PDL_TMR_CLEAR_CM_A 0x00040000ul +#define PDL_TMR_CLEAR_CM_B 0x00080000ul +#define PDL_TMR_CLEAR_RESET_RISING 0x00100000ul +#define PDL_TMR_CLEAR_RESET_HIGH 0x00200000ul + +/* DTC CMA trigger control */ +#define PDL_TMR_CM_A_DTC_TRIGGER_DISABLE 0x00400000ul +#define PDL_TMR_CM_A_DTC_TRIGGER_ENABLE 0x00800000ul + +/* DTC CMB trigger control */ +#define PDL_TMR_CM_B_DTC_TRIGGER_DISABLE 0x01000000ul +#define PDL_TMR_CM_B_DTC_TRIGGER_ENABLE 0x02000000ul + +/* Output control options */ +#define PDL_TMR_OUTPUT_IGNORE_CM_A 0x01u +#define PDL_TMR_OUTPUT_LOW_CM_A 0x02u +#define PDL_TMR_OUTPUT_HIGH_CM_A 0x04u +#define PDL_TMR_OUTPUT_INV_CM_A 0x08u +#define PDL_TMR_OUTPUT_IGNORE_CM_B 0x10u +#define PDL_TMR_OUTPUT_LOW_CM_B 0x20u +#define PDL_TMR_OUTPUT_HIGH_CM_B 0x40u +#define PDL_TMR_OUTPUT_INV_CM_B 0x80u + +/* Channels and units */ +#define PDL_TMR_TMR0 0 +#define PDL_TMR_TMR1 1 +#define PDL_TMR_TMR2 2 +#define PDL_TMR_TMR3 3 +#define PDL_TMR_UNIT0 4 +#define PDL_TMR_UNIT1 5 + +/* Period or frequency selection */ +#define PDL_TMR_PERIOD 0x00000001ul +#define PDL_TMR_FREQUENCY 0x00000002ul + +/* Output pin control */ +#define PDL_TMR_OUTPUT_HIGH 0x00000004ul +#define PDL_TMR_OUTPUT_LOW 0x00000008ul +#define PDL_TMR_OUTPUT_OFF 0x00000010ul +#define PDL_TMR_OUTPUT_ENABLE 0x00000020ul +#define PDL_TMR_OUTPUT_DISABLE 0x00000040ul + +/* ADC trigger control */ +#define PDL_TMR_ADC_TRIGGER_ON 0x00000080ul +#define PDL_TMR_ADC_TRIGGER_OFF 0x00000100ul + +/* Pulse DTC trigger control */ +#define PDL_TMR_PULSE_DTC_TRIGGER_DISABLE 0x00000200ul +#define PDL_TMR_PULSE_DTC_TRIGGER_ENABLE 0x00000400ul + +/* Period DTC trigger control */ +#define PDL_TMR_PERIOD_DTC_TRIGGER_DISABLE 0x00000800ul +#define PDL_TMR_PERIOD_DTC_TRIGGER_ENABLE 0x00001000ul + +/* CPU control */ +#define PDL_TMR_CPU_ON 0x00002000ul +#define PDL_TMR_CPU_OFF 0x00004000ul + +/* Timer counter control */ +#define PDL_TMR_STOP 0x00008000ul +#define PDL_TMR_START 0x00010000ul + +/* Register selections */ +#define PDL_TMR_COUNTER 0x00020000ul +#define PDL_TMR_TIME_CONSTANT_A 0x00040000ul +#define PDL_TMR_TIME_CONSTANT_B 0x00080000ul + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_tmr_rx62nxx.h b/bsp/rx/RPDL/r_pdl_tmr_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..d1e2978dce60dc827f16f834441dc5e2507fb4ff --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_tmr_rx62nxx.h @@ -0,0 +1,238 @@ +/*""FILE COMMENT""******************************************************* +* System Name : Timer TMR API for RX62Nxx +* File Name : r_pdl_tmr_RX62Nxx.h +* Version : 1.02 +* Contents : Timer TMR API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_TMR_RX62Nxx_H +#define R_PDL_TMR_RX62Nxx_H + +#define TMR_UNITS 2 +#define TMR_CHANNELS_PER_UNIT 2 +#define TMR_CHANNELS (uint8_t)(TMR_UNITS * TMR_CHANNELS_PER_UNIT) + +/* One-shot modes */ +#define CHANNEL_MODE 0x01u +#define UNIT_MODE 0x02u + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_TMR_Overflow_callback_func[TMR_CHANNELS]; +extern VoidCallBackFunc rpdl_TMR_CMA_callback_func[TMR_CHANNELS]; +extern VoidCallBackFunc rpdl_TMR_CMB_callback_func[TMR_CHANNELS]; + +/* Global variables */ +extern volatile uint8_t rpdl_TMR_tcsr_setting[TMR_CHANNELS]; +extern volatile uint8_t rpdl_TMR_tccr8_setting[TMR_CHANNELS]; +extern volatile uint16_t rpdl_TMR_tccr16_setting[TMR_UNITS]; +extern volatile uint8_t rpdl_TMR_one_shot[TMR_CHANNELS]; + +/* Library prototypes */ +bool R_TMR_SetAll( + const uint8_t +); +bool R_TMR_CreateChannelAll( + const uint8_t, + const uint32_t, + const uint8_t, + const uint8_t, + const uint8_t, + const uint8_t, + VoidCallBackFunc const, + VoidCallBackFunc const, + VoidCallBackFunc const, + const uint8_t +); +bool R_TMR_CreateUnitAll( + const uint8_t, + const uint32_t, + const uint8_t, + const uint16_t, + const uint16_t, + const uint16_t, + VoidCallBackFunc const, + VoidCallBackFunc const, + VoidCallBackFunc const, + const uint8_t +); +bool R_TMR_CreatePeriodicChannelAll( + const uint8_t, + const uint32_t, + const float, + const float, + VoidCallBackFunc const, + VoidCallBackFunc const, + const uint8_t +); +bool R_TMR_CreatePeriodicUnitAll( + const uint8_t, + const uint32_t, + const float, + const float, + VoidCallBackFunc const, + VoidCallBackFunc const, + const uint8_t +); +bool R_TMR_CreateOneShotChannelAll( + const uint8_t, + const uint32_t, + const float, + VoidCallBackFunc const, + const uint8_t +); +bool R_TMR_CreateOneShotUnitAll( + const uint8_t, + const uint32_t, + const float, + VoidCallBackFunc const, + const uint8_t +); +bool R_TMR_DestroyAll( + const uint8_t +); +bool R_TMR_ControlChannelAll( + const uint8_t, + const uint32_t, + const uint8_t, + const uint8_t, + const uint8_t +); +bool R_TMR_ControlUnitAll( + const uint8_t, + const uint32_t, + const uint16_t, + const uint16_t, + const uint16_t +); +bool R_TMR_ControlPeriodicChannelAll( + const uint8_t, + const uint32_t, + const float, + const float +); +bool R_TMR_ControlPeriodicUnitAll( + const uint8_t, + const uint32_t, + const float, + const float +); +bool R_TMR_ReadChannelAll( + const uint8_t, + volatile uint8_t * const, + volatile uint8_t * const, + volatile uint8_t * const, + volatile uint8_t * const +); +bool R_TMR_ReadUnitAll( + const uint8_t, + volatile uint8_t * const, + volatile uint16_t * const, + volatile uint16_t * const, + volatile uint16_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#if defined (DEVICE_PACKAGE_LFBGA_176) || defined (DEVICE_PACKAGE_TFLGA_145) || \ + defined (DEVICE_PACKAGE_LQFP_144) +#define R_TMR_Set(a) \ +( R_TMR_SetAll( (a) ) ) +#else +#define R_TMR_Set(a) \ +( ReturnFalse() ) +#endif + +#define R_TMR_CreateChannel(a, b, c, d, e, f, g, h, i, j) \ +( \ +( ((a) < TMR_CHANNELS) && ((j) <= IPL_MAX) ) ? \ +R_TMR_CreateChannelAll( (a), (b), (c), (d), (e), (f), (g), (h), (i), (j) ) : \ +ReturnFalse() \ +) + +#define R_TMR_CreateUnit(a, b, c, d, e, f, g, h, i, j) \ +( \ +( ((a) < TMR_UNITS) && ((j) <= IPL_MAX) ) ? \ +R_TMR_CreateUnitAll( (a), (b), (c), (d), (e), (f), (g), (h), (i), (j) ): \ +ReturnFalse() \ +) + +#define R_TMR_CreatePeriodic(a, b, c, d, e, f, g) \ +( \ +( ((a) > PDL_TMR_UNIT1) || ((g) > IPL_MAX) ) ? \ +ReturnFalse() : \ +( (a) <= PDL_TMR_TMR3) ? \ +R_TMR_CreatePeriodicChannelAll( (a), (b), (c), (d), (e), (f), (g) ) : \ +R_TMR_CreatePeriodicUnitAll( (a - PDL_TMR_UNIT0), (b), (c), (d), (e), (f), (g) ) \ +) + +#define R_TMR_CreateOneShot(a, b, c, d, e) \ +( \ +( ((a) > PDL_TMR_UNIT1) || ((e) > IPL_MAX) ) ? \ +ReturnFalse() : \ +( (a) <= PDL_TMR_TMR3 ) ? \ +R_TMR_CreateOneShotChannelAll( (a), (b), (c), (d), (e) ) : \ +R_TMR_CreateOneShotUnitAll( (a - PDL_TMR_UNIT0), (b), (c), (d), (e) ) \ +) + +#define R_TMR_Destroy(a) \ +( \ +( (a) < TMR_UNITS ) ? \ +R_TMR_DestroyAll( (a) ) : \ +ReturnFalse() \ +) + +#define R_TMR_ControlChannel(a, b, c, d, e) \ +( \ +( (a) < TMR_CHANNELS ) ? \ +R_TMR_ControlChannelAll( (a), (b), (c), (d), (e) ) : \ +ReturnFalse() \ +) + +#define R_TMR_ControlUnit(a, b, c, d, e) \ +( \ +( (a) < TMR_UNITS ) ? \ +R_TMR_ControlUnitAll( (a), (b), (c), (d), (e) ): \ +ReturnFalse() \ +) + +#define R_TMR_ControlPeriodic(a, b, c, d) \ +( \ +( (a) > PDL_TMR_UNIT1 ) ? \ +ReturnFalse() : \ +( (a) <= PDL_TMR_TMR3 ) ? \ +R_TMR_ControlPeriodicChannelAll( (a), (b), (float)(c), (float)(d) ) : \ +R_TMR_ControlPeriodicUnitAll( (a - PDL_TMR_UNIT0), (b), (float)(c), (float)(d) ) \ +) + +#define R_TMR_ReadChannel(a, b, c, d, e) \ +( \ +( (a) < TMR_CHANNELS ) ? \ +R_TMR_ReadChannelAll( (a), (b), (c), (d), (uint8_t *)(e) ) : \ +ReturnFalse() \ +) + +#define R_TMR_ReadUnit(a, b, c, d, e) \ +( \ +( (a) < TMR_UNITS ) ? \ +R_TMR_ReadUnitAll( (a), (b), (c), (d), (e) ) : \ +ReturnFalse() \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_user_definitions.h b/bsp/rx/RPDL/r_pdl_user_definitions.h new file mode 100644 index 0000000000000000000000000000000000000000..b207b498b0a9d753efb2cf89062ab0a39d4576f4 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_user_definitions.h @@ -0,0 +1,14 @@ +/*""FILE COMMENT""******************************************************* +* System Name : RPDL driver API +* File Name : r_pdl_user_definitions.h +* Contents : User-modifiable definitions +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_USER_DEFS_H +#define R_PDL_USER_DEFS_H + +/* The vector number to be used with fast interrupt processing */ +#define FAST_INTC_VECTOR 0 + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_wdt.h b/bsp/rx/RPDL/r_pdl_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..fcaeecbe2fe8b21ded2a55b186e8bfd182ee5737 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_wdt.h @@ -0,0 +1,60 @@ +/*""FILE COMMENT""******************************************************* +* System Name : WDT API for RX62Nxx +* File Name : r_pdl_wdt.h +* Version : 1.02 +* Contents : WDT API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_WDT_H +#define R_PDL_WDT_H + +#include "r_pdl_common_defs_RX62Nxx.h" + +/* Function prototypes */ +bool R_WDT_Create( + uint16_t, + void *, + uint8_t +); +bool R_WDT_Control( + uint8_t +); +bool R_WDT_Read( + uint8_t * +); + +/* Calculation selection */ +#define PDL_WDT_PCLK_DIV_4 0x0001u +#define PDL_WDT_PCLK_DIV_64 0x0002u +#define PDL_WDT_PCLK_DIV_128 0x0004u +#define PDL_WDT_PCLK_DIV_512 0x0008u +#define PDL_WDT_PCLK_DIV_2048 0x0010u +#define PDL_WDT_PCLK_DIV_8192 0x0020u +#define PDL_WDT_PCLK_DIV_32768 0x0040u +#define PDL_WDT_PCLK_DIV_131072 0x0080u + +/* MCU reset control */ +#define PDL_WDT_RESET_DISABLE 0x0100u +#define PDL_WDT_RESET_ENABLE 0x0200u + +/* Timer counter control */ +#define PDL_WDT_STOP 0x01u +#define PDL_WDT_RESET_COUNTER 0x02u + +#endif +/* End of file */ diff --git a/bsp/rx/RPDL/r_pdl_wdt_rx62nxx.h b/bsp/rx/RPDL/r_pdl_wdt_rx62nxx.h new file mode 100644 index 0000000000000000000000000000000000000000..7d646d5ed3ce98fb37cf9f40208619846081d780 --- /dev/null +++ b/bsp/rx/RPDL/r_pdl_wdt_rx62nxx.h @@ -0,0 +1,63 @@ +/*""FILE COMMENT""******************************************************* +* System Name : WDT API for RX62Nxx +* File Name : r_pdl_wdt_RX62Nxx.h +* Version : 1.02 +* Contents : WDT API header +* Customer : +* Model : +* Order : +* CPU : RX +* Compiler : RXC +* OS : Nothing +* Programmer : +* Note : +************************************************************************ +* Copyright, 2011. Renesas Electronics Corporation +* and Renesas Solutions Corporation +************************************************************************ +* History : 2011.04.08 +* : Ver 1.02 +* : CS-5 release. +*""FILE COMMENT END""**************************************************/ + +#ifndef R_PDL_WDT_RX62Nxx_H +#define R_PDL_WDT_RX62Nxx_H + +/* Callback function storage */ +extern VoidCallBackFunc rpdl_WDT_callback_func; + +/* Library prototypes */ +bool R_WDT_CreateAll( + const uint16_t, + VoidCallBackFunc const, + const uint8_t +); +bool R_WDT_ControlAll( + const uint8_t +); +bool R_WDT_ReadAll( + volatile uint8_t * const +); +bool ReturnFalse(void); + +/* Macro definitions */ + +#define R_WDT_Create(a, b, c) \ +( \ +( (c) <= IPL_MAX) ? \ +R_WDT_CreateAll( (a), (b), (c) ) : \ +ReturnFalse() \ +) + +#define R_WDT_Control(a) \ +( \ +R_WDT_ControlAll( (a) ) \ +) + +#define R_WDT_Read(a) \ +( \ +R_WDT_ReadAll( (a) ) \ +) + +#endif +/* End of file */ diff --git a/bsp/rx/ReadMe.txt b/bsp/rx/ReadMe.txt new file mode 100644 index 0000000000000000000000000000000000000000..956e2e00a1db816693b9729bb3445087fd7d6925 --- /dev/null +++ b/bsp/rx/ReadMe.txt @@ -0,0 +1,5 @@ +board：Renesas YRDKRX62N +chip： R5F562N8BDFP RX62N8 +Tool: IAR Embedded Workbench for Renesas RX 2.60.5 + IAR Embedded Workbench common components 7.0.6.3257 + (30-day limited) diff --git a/bsp/rx/applications/SConscript b/bsp/rx/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..01eb940dfb35f92c503a78b0b49a4354590f9f3a --- /dev/null +++ b/bsp/rx/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/rx/applications/application.c b/bsp/rx/applications/application.c new file mode 100644 index 0000000000000000000000000000000000000000..92ecaad7232ac9c9d28943eb510a6f435e64651a --- /dev/null +++ b/bsp/rx/applications/application.c @@ -0,0 +1,250 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + * 2013-07-12 aozima update for auto initial. + */ + +/** + * @addtogroup STM32 + */ +/*@{*/ + +#include +#include + +#ifdef RT_USING_COMPONENTS_INIT +#include +#endif /* RT_USING_COMPONENTS_INIT */ + +#ifdef RT_USING_DFS +/* dfs filesystem:ELM filesystem init */ +#include +/* dfs Filesystem APIs */ +#include +#endif + +#ifdef RT_USING_RTGUI +#include +#include +#include +#include +#include +#endif + + +#ifdef RT_USING_RTGUI +rt_bool_t cali_setup(void) +{ + rt_kprintf("cali setup entered\n"); + return RT_FALSE; +} + +void cali_store(struct calibration_data *data) +{ + rt_kprintf("cali finished (%d, %d), (%d, %d)\n", + data->min_x, + data->max_x, + data->min_y, + data->max_y); +} +#endif /* RT_USING_RTGUI */ + +void rt_init_thread_entry(void* parameter) +{ + + #ifdef RT_USING_MODULE + rt_system_module_init(); +#endif + +#ifdef RT_USING_FINSH + /* initialize finsh */ + finsh_system_init(); + finsh_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_LWIP + /* initialize lwip stack */ + /* register ethernetif device */ + eth_system_device_init(); + + /* initialize lwip system */ + lwip_system_init(); + rt_kprintf("TCP/IP initialized!\n"); +#endif + +#ifdef RT_USING_DFS + /* initialize the device file system */ + dfs_init(); + +#ifdef RT_USING_DFS_ELMFAT + /* initialize the elm chan FatFS file system*/ + elm_init(); +#endif + +#if defined(RT_USING_DFS_NFS) && defined(RT_USING_LWIP) + /* initialize NFSv3 client file system */ + nfs_init(); +#endif + +#ifdef RT_USING_DFS_YAFFS2 + dfs_yaffs2_init(); +#endif + +#ifdef RT_USING_DFS_UFFS + dfs_uffs_init(); +#endif + +#ifdef RT_USING_DFS_JFFS2 + dfs_jffs2_init(); +#endif + +#ifdef RT_USING_DFS_ROMFS + dfs_romfs_init(); +#endif + +#ifdef RT_USING_DFS_RAMFS + dfs_ramfs_init(); +#endif + +#ifdef RT_USING_DFS_DEVFS + devfs_init(); +#endif +#endif /* end of RT_USING_DFS */ + +#ifdef RT_USING_NEWLIB + libc_system_init(RT_CONSOLE_DEVICE_NAME); +#else + /* the pthread system initialization will be initiallized in libc */ +#ifdef RT_USING_PTHREADS + pthread_system_init(); +#endif +#endif + +#ifdef RT_USING_RTGUI + rtgui_system_server_init(); +#endif + +#ifdef RT_USING_USB_HOST + rt_usb_host_init(); +#endif + +#ifdef RT_USING_FINSH + finsh_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_FINSH */ + + /* Filesystem Initialization */ +#if defined(RT_USING_DFS) && defined(RT_USING_DFS_ELMFAT) + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!\n"); +#endif /* RT_USING_DFS */ + +#ifdef RT_USING_RTGUI + { + extern void rt_hw_lcd_init(); + extern void rtgui_touch_hw_init(void); + + rt_device_t lcd; + + /* init lcd */ + rt_hw_lcd_init(); + + /* init touch panel */ + rtgui_touch_hw_init(); + + /* find lcd device */ + lcd = rt_device_find("lcd"); + + /* set lcd device as rtgui graphic driver */ + rtgui_graphic_set_device(lcd); + +#ifndef RT_USING_COMPONENTS_INIT + /* init rtgui system server */ + rtgui_system_server_init(); +#endif + + calibration_set_restore(cali_setup); + calibration_set_after(cali_store); + calibration_init(); + } +#endif /* #ifdef RT_USING_RTGUI */ +} + + + +ALIGN(RT_ALIGN_SIZE) +static rt_uint8_t led_stack[ 512 ]; +static struct rt_thread led_thread; +static void led_thread_entry(void* parameter) +{ + unsigned int count=0; + +// rt_hw_led_init(); + + while (1) + { + /* led1 on */ +#ifndef RT_USING_FINSH + rt_kprintf("led on, count : %d\r\n",count); +#endif + count++; + + rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */ + + /* led1 off */ +#ifndef RT_USING_FINSH + rt_kprintf("led off\r\n"); +#endif + rt_thread_delay( RT_TICK_PER_SECOND/2 ); + } +} +int rt_application_init(void) +{ + rt_thread_t init_thread; + #if 1 + rt_err_t result; + /* init led thread */ + result = rt_thread_init(&led_thread, + "led", + led_thread_entry, + RT_NULL, + (rt_uint8_t*)&led_stack[0], + sizeof(led_stack), + 20, + 5); + if (result == RT_EOK) + { + rt_thread_startup(&led_thread); + } + + #endif +#if (RT_THREAD_PRIORITY_MAX == 32) + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 1024, 8, 20); +#else + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, 80, 20); +#endif + + if (init_thread != RT_NULL) + rt_thread_startup(init_thread); + + return 0; +} + +/*@}*/ diff --git a/bsp/rx/applications/startup.c b/bsp/rx/applications/startup.c new file mode 100644 index 0000000000000000000000000000000000000000..4b195492f61df0b9d493db615778e0d09925c6ca --- /dev/null +++ b/bsp/rx/applications/startup.c @@ -0,0 +1,104 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "intrinsics.h" +/** + * @addtogroup rx62n + */ + +/*@{*/ + +extern int rt_application_init(void); + + +#pragma section="HEAP" + +/******************************************************************************* +* Function Name : assert_failed +* Description : Reports the name of the source file and the source line number +* where the assert error has occurred. +* Input : - file: pointer to the source file name +* - line: assert error line source number +* Output : None +* Return : None +*******************************************************************************/ +void assert_failed(unsigned char * file, unsigned long line) +{ + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); + + while (1) ; +} + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); +#ifdef RT_USING_CONSOLE + /* show version */ + rt_show_version(); +#endif + +#ifdef RT_USING_HEAP + + rt_system_heap_init(__segment_end("HEAP"), (void*)RX62N_SRAM_END); + +#endif /* RT_USING_HEAP */ + + /* init scheduler system */ + rt_system_scheduler_init(); + + /* initialize timer */ + rt_system_timer_init(); + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init application */ + rt_application_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + + rt_hw_system_freq_init(); + + __enable_interrupt(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/rx/drivers/Uart.h b/bsp/rx/drivers/Uart.h new file mode 100644 index 0000000000000000000000000000000000000000..9354861ca3705f7f2f7575bba62302be08d3c5bc --- /dev/null +++ b/bsp/rx/drivers/Uart.h @@ -0,0 +1,6 @@ + +#ifndef __UART_H__ +#define __UART_H__ + +void rt_hw_uart_init(void); +#endif /* UART_H_ */ diff --git a/bsp/rx/drivers/board.c b/bsp/rx/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..4e023253251ca88c18780b7120545350e5af71bd --- /dev/null +++ b/bsp/rx/drivers/board.c @@ -0,0 +1,96 @@ +#include +#include +#include "board.h" +#include "uart.h" +#include +#include +#include "r_pdl_cgc.h" +/* General RPDL function definitions */ +#include "r_pdl_definitions.h" +#include "intrinsics.h" +#include "iorx62n.h" + + + +/** + * This is the timer interrupt service routine. + * + */ +#pragma vector = VECT_CMT0_CMI0 +__interrupt +void SysTick_Handler(void) +{ + // __enable_interrupt(); + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + + +void rt_hw_systick_init(void) +{ + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) (((XTAL_FREQUENCY * PCLK_MUL) / RT_TICK_PER_SECOND)/8 -1); + + /* Divide the PCLK by 128. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = 4; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} + +void rt_hw_system_freq_init(void) +{ + /* Declare error flag */ + bool err = true; + + /* Modify the MCU clocks, all are based off Epson 12 MHz clock */ + err &= R_CGC_Set + ( + 12E6, + 96E6, + 48E6, + 24E6, + PDL_NO_DATA + ); + /* + Clock Description Frequency + ---------------------------------------- + Input Clock Frequency..............12MHz + Internal Clock Frequency...........96MHz + Peripheral Clock Frequency.........48MHz + External Bus Clock Frequency.......24MHz */ + + /* Halt in while loop when RPDL errors detected */ + while (!err); +} + +/** + * This function will initial rx62n board + */ +void rt_hw_board_init() +{ + + rt_hw_system_freq_init(); + rt_hw_systick_init(); + rt_hw_uart_init(); +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/rx/drivers/board.h b/bsp/rx/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..870e805a99e260b88ee83372b4488bff16a54b6a --- /dev/null +++ b/bsp/rx/drivers/board.h @@ -0,0 +1,16 @@ +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +#define XTAL_FREQUENCY (12000000L) +#define ICLK_MUL (8) +#define PCLK_MUL (4) +#define BCLK_MUL (2) + +#define RX62N_SRAM_END 0x0000ffff + +#define RT_USING_UART2 + +void rt_hw_board_init(void); +void rt_hw_system_freq_init(void); +#endif diff --git a/bsp/rx/drivers/uart.c b/bsp/rx/drivers/uart.c new file mode 100644 index 0000000000000000000000000000000000000000..9e304ac95cce2f9d67a06234a1bdd958048da66f --- /dev/null +++ b/bsp/rx/drivers/uart.c @@ -0,0 +1,545 @@ +/* +********************************************************************************************************* +* Filename : uart.c +********************************************************************************************************* +*/ + + +#include +#include +#include +#include "board.h" +#include "uart.h" +#include +#include +#include "r_pdl_sci.h" +/* General RPDL function definitions */ +#include "r_pdl_definitions.h" +#include "intrinsics.h" +#include "iorx62n.h" + +//#include + + + /* Clock selection control */ +#define SCI_CKS_MIN 0 +#define SCI_CKS_MAX 3 +#define SCI_CKS_STEP 1 + + +#define IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a]) +//#define IER_ADDRESS(a) ((volatile unsigned char *)&(ICU.IER[IER_SCI0_ERI0 + a])/sizeof(unsigned char)) +#define ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) ) +#define IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) ) +#define RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) ) +#define TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) ) +#define TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) ) +#define RXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_RXI0]+ ((4*a)/sizeof(unsigned char))) +#define TXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_TXI0]+ ((4*a) / sizeof(unsigned char))) +//#define SCI1_USE_B +//#define SCI2_USE_B +//#define SCI3_USE_B +//#define SCI6_USE_B + +#define SourceClk 12000000 +#define rpdl_CGC_f_pclk SourceClk * 4 +/* Idle output options */ +#define SPACE 0 +#define MARK 1 + +typedef int UART_ID_Type; +typedef int IRQn_Type; + +#define SCI2_USE_B + +struct rx_uart +{ + UART_ID_Type UART; + volatile struct st_sci __sfr * sci; +}; + +static rt_err_t rx_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + #if 1 + struct rx_uart *uart; + + unsigned char smr_copy; + unsigned char semr_copy; + unsigned char scr_copy; + unsigned char scmr_copy; + unsigned long brr_divider; + unsigned long bit_interval_counter; + RT_ASSERT(serial != RT_NULL); + uart = (struct rx_uart *)serial->parent.user_data; + + if (uart->UART > 6) { + return RT_ERROR; + } + /* Initialise the working copies */ + smr_copy = 0x00u; + scr_copy = 0x00u; + semr_copy = 0x00u; + scmr_copy = 0x72u; + brr_divider = 0; + + switch (uart->UART) { +case 0: + SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; + /* Enable the input buffer */ + PORT2.ICR.BIT.B2 = 1; + /* Ensure the pin is set to input */ + PORT2.DDR.BIT.B2 = 0; + /* Disable the USB0_DRPD output */ + IOPORT.PFKUSB.BIT.USBE = 0; + /* Disable the MTIOC3B-A output */ + MTU3.TIORH.BIT.IOB = 0; + /* Disable the TMO0 output */ + TMR0.TCSR.BIT.OSA = 0; + TMR0.TCSR.BIT.OSB = 0; + /* Disable the MTIOC1A output */ + MTU1.TIOR.BIT.IOA = 0; + /* Set the idle state direction */ + PORT2.DDR.BIT.B0 = 1; + PORT2.DR.BIT.B0 = 1; + PORT2.ICR.BIT.B0 = 1; + PORT2.ICR.BIT.B1 = 1; + break; + case 1: + SYSTEM.MSTPCRB.BIT.MSTPB30 = 0; + + /* Disable the CS6#-C output */ + IOPORT.PF0CSE.BIT.CS6E = 0; + /* Disable the MOSIB-A output */ + IOPORT.PFHSPI.BIT.MOSIE = 0; + /* Disable the MTIOC2A output */ + MTU2.TIOR.BIT.IOA = 0; + /* Disable the TMO1 output */ + TMR1.TCSR.BYTE = 0xF0u; +#ifdef SCI1_USE_B + + IOPORT.PFFSCI.BIT.SCI1S = 1; + PORTF.DDR.BIT.B2 = 0; + PORTF.ICR.BIT.B2 = 1; + PORTF.DDR.BIT.B0 = 1; + PORTF.DR.BIT.B0 = 1; +#else + IOPORT.PFFSCI.BIT.SCI1S = 0; + + /* Set the idle state direction */ + PORT2.DDR.BIT.B6 = 1; + PORT2.DR.BIT.B6 = 1; +// PORT2.DR.BIT.B6 = 1; + /* Enable the input buffer */ + //PORT3.ICR.BIT.B0 = 1; + /* Ensure the pin is set to input */ + PORT3.DDR.BIT.B0 = 0; + + +#endif + + break; + case 2: + SYSTEM.MSTPCRB.BIT.MSTPB29 = 0; + /* Disable the SSLB2-A output */ + IOPORT.PFHSPI.BIT.SSL2E = 0; + +#ifdef SCI2_USE_B + IOPORT.PFFSCI.BIT.SCI2S = 1; + PORT5.DDR.BIT.B0 = 1; + PORT5.DR.BIT.B0 = 1; + PORT5.DDR.BIT.B2 = 0; + PORT5.ICR.BIT.B2 = 1; + /* Disable the SSLB1-A output */ + IOPORT.PFHSPI.BIT.SSL1E = 0; + +#else + IOPORT.PFFSCI.BIT.SCI2S = 0; + /* Enable the input buffer */ + PORT1.ICR.BIT.B2 = 1; + /* Ensure the pin is set to input */ + PORT1.DDR.BIT.B2 = 0; + PORT1.DDR.BIT.B3 = 1; + PORT1.DR.BIT.B3 = 1; + /* Disable the TMO3 output */ + TMR3.TCSR.BYTE = 0xF0u; +#endif + break; + case 3: + SYSTEM.MSTPCRB.BIT.MSTPB28 = 0; +#ifdef SCI3_USE_B + IOPORT.PFFSCI.BIT.SCI3S = 1; + PORT2.DDR.BIT.B5 = 0; + PORT2.ICR.BIT.B5 = 1; + PORT2.DDR.BIT.B3 = 1; + PORT2.DR.BIT.B3 = 1; + IOPORT.PF0CSE.BIT.CS4E = 0; + /* Disable the USB0_VBUSEN-A output */ + IOPORT.PFKUSB.BIT.USBE = 0; + /* Disable the MTIOC4A-A output */ + MTU4.TIORH.BIT.IOA = 0; + /* Disable the USB0_DPUPE-A output */ + IOPORT.PFKUSB.BIT.USBE = 0; + /* Disable the EDACK0-B output */ + EXDMAC0.EDMOMD.BIT.DACKE = 0; + /* Disable the MTIOC3D-A output */ + MTU3.TIORL.BIT.IOD = 0; + +#else + + IOPORT.PFFSCI.BIT.SCI3S = 0; + /* Disable the MTIOC0B output */ + MTU0.TIORH.BIT.IOB = 0; + PORT1.DDR.BIT.B6 = 0; + PORT1.ICR.BIT.B6 = 1; + PORT1.DDR.BIT.B7 = 1; + PORT1.DR.BIT.B7 = 1; + MTU3.TIORH.BIT.IOA = 0; + /* Set the idle state direction */ +#endif + break; + //case UartPort4: + // SYSTEM.MSTPCRB.BIT.MSTPB27 = 0; + // break; + case 5: + SYSTEM.MSTPCRB.BIT.MSTPB26 = 0; + /* Enable the input buffer */ + PORTC.ICR.BIT.B1 = 1; + /* Ensure the pin is set to input */ + PORTC.DDR.BIT.B1 = 0; + PORTC.DDR.BIT.B3 = 1; + PORTC.DR.BIT.B3 = 1; + /* Disable the A17-A output */ + IOPORT.PF3BUS.BIT.A17E = 0; + break; + case 6: + + + SYSTEM.MSTPCRB.BIT.MSTPB25 = 0; + +#ifdef SCI6_USE_B + IOPORT.PFFSCI.BIT.SCI6S = 1; + PORT3.DDR.BIT.B3 = 0; + //PORT3.ICR.BIT.B3 = 1; + PORT3.DDR.BIT.B2 = 1; + PORT3.DR.BIT.B2 = 1; + /* Disable the MTIOC0A output */ + MTU0.TIORH.BIT.IOA = 0; + /* Disable the CTX0 output */ + IOPORT.PFJCAN.BIT.CAN0E = 0; + /* Disable the MTIOC0C output */ + MTU0.TIORL.BIT.IOC = 0; +#else + IOPORT.PFFSCI.BIT.SCI6S = 0; + PORT0.DDR.BIT.B0 = 1; + PORT0.DR.BIT.B0 = 1; + PORT0.ICR.BIT.B1 = 1; + PORT0.DDR.BIT.B1 = 0; + +#endif + break; + default: + break; + } + + + /*stop bit*/ + if (cfg->stop_bits == STOP_BITS_2) { + smr_copy |= BIT_3; + } else if (cfg->stop_bits != STOP_BITS_1) { + return RT_ERROR; + } + + /*data bit*/ + if (cfg->data_bits == 7) { + smr_copy |= BIT_6; + } else if (cfg->data_bits != DATA_BITS_8) { + return RT_ERROR; + } + + /*parity*/ + if (cfg->parity == PARITY_ODD) + smr_copy |= BIT_5; + else if (cfg->parity == PARITY_EVEN) + smr_copy |= BIT_4 | BIT_5; + + + + brr_divider = rpdl_CGC_f_pclk / cfg->baud_rate; + /* There is a fixed division by 2 */ + brr_divider /= 16; + + /* Select 8 base clock cycles (ABCS = 1) */ + semr_copy |= (unsigned char)BIT_4; + //brr_divider /= 8; + /* More division required? */ + if (brr_divider > 256) { + /* Select 16 base clock cycles (ABCS = 0) */ + semr_copy &= (unsigned char)INV_BIT_4; + brr_divider /= 2; + } + + /* Load the BRR reset value */ + //brr_copy = 0xFFu; + + + /* Ensure bits TIE, RIE, TE, RE and TEIE in the SCR are 0 */ + uart->sci->SCR.BYTE = 0x00; + + /* Configure the CKE & MPIE bits */ + uart->sci->SCR.BYTE = scr_copy & (BIT_0 | BIT_1 | BIT_3); + + /* Configure the SMR register */ + uart->sci->SMR.BYTE = smr_copy; + /* Configure the SCMR register */ + uart->sci->SCMR.BYTE = scmr_copy; + /* Configure the SEMR register */ + uart->sci->SEMR.BYTE = semr_copy; + /* Configure the BRR register */ + uart->sci->BRR = brr_divider - 1; + + bit_interval_counter = rpdl_CGC_f_pclk / cfg->baud_rate; + /* Wait for at least a 1-bit duration */ + do { + bit_interval_counter--; + }while (bit_interval_counter != 0); + + scr_copy = 0x00u; + + /*enable rx an tx*/ + scr_copy |= BIT_5 | BIT_4 ; + + uart->sci->SCR.BYTE &= 0x5B; + uart->sci->SCR.BYTE |= scr_copy; + + *(IPR_ADDRESS(uart->UART)) = 5; + uart->sci->SSR.BYTE = 0xC0; + uart->sci->SSR.BYTE &= INV_BIT_5; + while (uart->sci->SSR.BYTE & BIT_4); + uart->sci->SSR.BYTE &= INV_BIT_3; + #else + struct rx_uart *uart; + /* Declare error flag */ + bool err = true; + uint32_t flag = 0; + RT_ASSERT(serial != RT_NULL); + uart = (struct rx_uart *)serial->parent.user_data; + + + /* Configure the pin selection of SCI channel */ + err &= R_SCI_Set + ( + PDL_SCI_PIN_SCI2_B + ); + + uart->sci->SCR.BYTE |= BIT_4 | BIT_5; + switch (cfg->parity) { + case PARITY_ODD: + flag |= PDL_SCI_PARITY_ODD; + break; + case PARITY_EVEN: + flag |= PDL_SCI_PARITY_EVEN; + break; + default: + flag |= PDL_SCI_PARITY_NONE; + break; + + } + + switch (cfg->data_bits) { + case DATA_BITS_7: + flag |= PDL_SCI_7_BIT_LENGTH; + break; + case DATA_BITS_8: + flag |= PDL_SCI_8_BIT_LENGTH; + break; + } + + switch (cfg->stop_bits) { + case STOP_BITS_1: + flag |= PDL_SCI_STOP_1; + break; + case STOP_BITS_2: + flag |= PDL_SCI_STOP_2; + break; + } + + flag |= PDL_SCI_ASYNC | + PDL_SCI_TX_CONNECTED | + PDL_SCI_RX_CONNECTED | + PDL_SCI_CLK_INT_IO ; + /* Configure the RS232 port */ + err &= R_SCI_Create( + uart->UART, + flag, + cfg->baud_rate, + 5); + + uart->sci->SCR.BYTE |= BIT_4|BIT_5; + + __enable_interrupt(); + #endif + + switch (uart->UART) { + case 0: + + //ier_copy |= BIT_6 | BIT_7; + ICU.IER[IER_SCI0_ERI0].BIT.IEN_SCI0_ERI0 = 1; + ICU.IER[IER_SCI0_RXI0].BIT.IEN_SCI0_RXI0 = 1; + ICU.IER[IER_SCI0_TEI0].BIT.IEN_SCI0_TEI0 = 1; + ICU.IER[IER_SCI0_TXI0].BIT.IEN_SCI0_TXI0 = 1; + + break; + case 1: + + ICU.IER[IER_SCI1_ERI1].BIT.IEN_SCI1_ERI1 = 1; + ICU.IER[IER_SCI1_RXI1].BIT.IEN_SCI1_RXI1 = 1; + //ICU.IER[IER_SCI1_TEI1].BIT.IEN_SCI1_TEI1 = 1; + //ICU.IER[IER_SCI1_TXI1].BIT.IEN_SCI1_TXI1 = 1; + + break; + case 2: + + ICU.IER[IER_SCI2_ERI2].BIT.IEN_SCI2_ERI2 = 1; + ICU.IER[IER_SCI2_RXI2].BIT.IEN_SCI2_RXI2 = 1; + ICU.IER[IER_SCI2_RXI2].BIT.IEN_SCI2_TEI2 = 0; + ICU.IER[IER_SCI2_TXI2].BIT.IEN_SCI2_TXI2 = 0; + + break; + case 3: + + ICU.IER[IER_SCI3_ERI3].BIT.IEN_SCI3_ERI3 = 1; + ICU.IER[IER_SCI3_RXI3].BIT.IEN_SCI3_RXI3 = 1; + ICU.IER[IER_SCI3_TEI3].BIT.IEN_SCI3_TEI3 = 1; + ICU.IER[IER_SCI3_TXI3].BIT.IEN_SCI3_TXI3 = 1; + + break; + case 5: + + ICU.IER[IER_SCI5_ERI5].BIT.IEN_SCI5_ERI5 = 1; + ICU.IER[IER_SCI5_RXI5].BIT.IEN_SCI5_RXI5 = 1; + ICU.IER[IER_SCI5_TEI5].BIT.IEN_SCI5_TEI5 = 1; + ICU.IER[IER_SCI5_TXI5].BIT.IEN_SCI5_TXI5 = 1; + + break; + case 6: + + ICU.IER[IER_SCI6_ERI6].BIT.IEN_SCI6_ERI6 = 1; + ICU.IER[IER_SCI6_RXI6].BIT.IEN_SCI6_RXI6 = 1; + ICU.IER[IER_SCI6_TEI6].BIT.IEN_SCI6_TEI6 = 1; + ICU.IER[IER_SCI6_TXI6].BIT.IEN_SCI6_TXI6 = 1; + + break; + } + + return RT_EOK; +} + +static rt_err_t rx_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct rx_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct rx_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + uart->sci->SCR.BIT.RIE = 0; + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + (void)(uart->sci->RDR); + uart->sci->SCR.BIT.RIE = 1; + break; + } + + return RT_EOK; +} + +static int rx_putc(struct rt_serial_device *serial, char c) +{ + struct rx_uart *uart; + + uart = (struct rx_uart *)serial->parent.user_data; + while (uart->sci->SSR.BIT.TDRE == 0); + uart->sci->TDR = c; + return 1; +} + +static int rx_getc(struct rt_serial_device *serial) +{ + + struct rx_uart *uart; + + uart = (struct rx_uart *)serial->parent.user_data; + if (uart->sci->SSR.BIT.RDRF) + return (int) (uart->sci->RDR); + + return -1; +} + +static const struct rt_uart_ops rx_uart_ops = +{ + rx_configure, + rx_control, + rx_putc, + rx_getc, +}; + +#if defined(RT_USING_UART2) +/* UART0 device driver structure */ +struct rx_uart uart2 = +{ + 2, + &SCI2, +}; +struct rt_serial_device serial2; + + +#pragma vector = VECT_SCI2_ERI2 +__interrupt void Interrupt_SCI2_ERI2(void) +{ + /* Will the user handle the errors? */ + /* Clear the error flags */ + SCI2.SSR.BYTE = (uint8_t)(BIT_7 | BIT_6); +} + +#pragma vector = VECT_SCI2_RXI2 +__interrupt void Interrupt_SCI2_RXI2(void) +{ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); +} + +#endif + +void rt_hw_uart_init(void) +{ + struct rx_uart *uart; + struct serial_configure config; + +#ifdef RT_USING_UART2 + uart = &uart2; + config.baud_rate = BAUD_RATE_38400; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial2.ops = &rx_uart_ops; + serial2.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_STREAM, + uart); +#endif + +} + diff --git a/bsp/rx/lnkr5f562n8.icf b/bsp/rx/lnkr5f562n8.icf new file mode 100644 index 0000000000000000000000000000000000000000..38790c05d5d78e794b1eb31df5c63c5a09636de5 --- /dev/null +++ b/bsp/rx/lnkr5f562n8.icf @@ -0,0 +1,51 @@ +//----------------------------------------------------------------------------- +// ILINK command file template for the Renesas RX microcontroller R5F562N8 +//----------------------------------------------------------------------------- +define memory mem with size = 4G; + +define region ROM_region16 = mem:[from 0xFFFF8000 to 0xFFFFFFFF]; +define region RAM_region16 = mem:[from 0x00000004 to 0x00007FFF]; +define region ROM_region24 = mem:[from 0xFFF80000 to 0xFFFFFFFF]; +define region RAM_region24 = mem:[from 0x00000004 to 0x00017FFF]; +define region ROM_region32 = mem:[from 0xFFF80000 to 0xFFFFFFFF]; +define region RAM_region32 = mem:[from 0x00000004 to 0x00017FFF]; +define region DATA_FLASH_region = mem:[from 0x00100000 to 0x00107FFF]; + +initialize by copy { rw, ro section D, ro section D_1, ro section D_2 }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; +do not initialize { section .*.noinit }; + +define block HEAP with alignment = 4, size = _HEAP_SIZE { }; +define block USTACK with alignment = 4, size = _USTACK_SIZE { }; +define block ISTACK with alignment = 4, size = _ISTACK_SIZE { }; + +define block STACKS with fixed order { block ISTACK, + block USTACK }; +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; +place at address mem:0xFFFFFF80 { ro section .nmivec }; + +"ROM16":place in ROM_region16 { ro section .code16*, + ro section .data16* }; +"RAM16":place in RAM_region16 { rw section .data16*, + rw section __DLIB_PERTHREAD }; +"ROM24":place in ROM_region24 { ro section .code24*, + ro section .data24* }; +"RAM24":place in RAM_region24 { rw section .data24* }; +"ROM32":place in ROM_region32 { ro, + ro section FSymTab, + ro section VSymTab, + ro section .rti_fn*, + }; +"RAM32":place in RAM_region32 { rw, + ro section D, + ro section D_1, + ro section D_2, + block STACKS, + block HEAP, + }; + +"DATAFLASH":place in DATA_FLASH_region + { ro section .dataflash* }; + diff --git a/bsp/rx/project.vpj b/bsp/rx/project.vpj new file mode 100644 index 0000000000000000000000000000000000000000..9e8b56055fe32c20bc2f5e8c0d5145ff00055857 --- /dev/null +++ b/bsp/rx/project.vpj @@ -0,0 +1,328 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/rx/project.vpw b/bsp/rx/project.vpw new file mode 100644 index 0000000000000000000000000000000000000000..db5528329f4438d52a0634816505578dd869c921 --- /dev/null +++ b/bsp/rx/project.vpw @@ -0,0 +1,6 @@ + + + + + + diff --git a/bsp/rx/project.vpwhist b/bsp/rx/project.vpwhist new file mode 100644 index 0000000000000000000000000000000000000000..6bddeb5fea08739032a7a89d55656d068ad27692 --- /dev/null +++ b/bsp/rx/project.vpwhist @@ -0,0 +1,150 @@ +[Global] +CurrentProject=project.vpj +[ProjectDates] +project.vpj=20141105163139555 +[ActiveConfig] +project.vpj=Debug +[TreeExpansion2] +-@ project.vpj + + applications + + ..\..\components + - drivers + - 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+FILEHIST: 9 +rtconfig.h +drivers\uart.c +RPDL\interrupt_sci.c +..\..\include\rthw.h +..\..\components\finsh\finsh.h +RPDL\Interrupt_INTC.c +..\..\libcpu\rx\context_iar.S +..\..\libcpu\rx\cpuconfig.h +..\..\libcpu\rx\cpuport.c +TBCLASS: 0 0 +DEBUG: 0 0 0 0 3 0 gdb +printf +strcpy +std::* +DEBUG2: 0 diff --git a/bsp/rx/project.vtg b/bsp/rx/project.vtg new file mode 100644 index 0000000000000000000000000000000000000000..eaa059472d657f80f5dc6d7722277589f190113c Binary files /dev/null and b/bsp/rx/project.vtg differ diff --git a/bsp/rx/rt.ewd b/bsp/rx/rt.ewd new file mode 100644 index 0000000000000000000000000000000000000000..ad4829054fe236ca1b9ebf35a7f2ff8d2670d48f --- /dev/null +++ b/bsp/rx/rt.ewd @@ -0,0 +1,332 @@ + + + + 2 + + Debug + + RX + + 1 + + C-SPY + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 1 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/rx/rt.ewp b/bsp/rx/rt.ewp new file mode 100644 index 0000000000000000000000000000000000000000..cde5ccb52f4cd265b970d91fd82d22d5d778c2b6 --- /dev/null +++ b/bsp/rx/rt.ewp @@ -0,0 +1,1164 @@ + + + + 2 + + Debug + + RX + + 1 + + General + 4 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 7 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + RPDL + + $PROJ_DIR$\RPDL\interrupt_adc_10.c + + + $PROJ_DIR$\RPDL\interrupt_adc_12.c + + + $PROJ_DIR$\RPDL\interrupt_bsc.c + + + $PROJ_DIR$\RPDL\interrupt_cmt.c + + + $PROJ_DIR$\RPDL\interrupt_dmac.c + + + $PROJ_DIR$\RPDL\interrupt_exdmac.c + + + $PROJ_DIR$\RPDL\interrupt_iic.c + + + $PROJ_DIR$\RPDL\Interrupt_INTC.c + + + $PROJ_DIR$\RPDL\interrupt_mtu2.c + + + $PROJ_DIR$\RPDL\interrupt_not_rpdl.c + + + $PROJ_DIR$\RPDL\interrupt_poe.c + + + $PROJ_DIR$\RPDL\Interrupt_RTC.c + + + $PROJ_DIR$\RPDL\interrupt_sci.c + + + $PROJ_DIR$\RPDL\Interrupt_SPI.c + + + $PROJ_DIR$\RPDL\Interrupt_TMR.c + + + $PROJ_DIR$\RPDL\interrupt_wdt.c + + + + rtos + + components + + drivers + + $PROJ_DIR$\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\src\portal.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c + + + + finsh + + $PROJ_DIR$\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\components\finsh\msh_cmd.c + + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\symbol.c + + + + init + + $PROJ_DIR$\..\..\components\init\components.c + + + + + src + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\module.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\slab.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + + target + + app + + $PROJ_DIR$\applications\application.c + + + $PROJ_DIR$\applications\startup.c + + + + cpu + + $PROJ_DIR$\..\..\libcpu\rx\context_iar.S + + + $PROJ_DIR$\..\..\libcpu\rx\cpuport.c + + + + drivers + + $PROJ_DIR$\drivers\board.c + + + $PROJ_DIR$\drivers\uart.c + + + + + + diff --git a/bsp/rx/rtconfig.h b/bsp/rx/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..69d71c24115b3f454fe440538baf64f364d0ec84 --- /dev/null +++ b/bsp/rx/rtconfig.h @@ -0,0 +1,187 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +#define RT_DEBUG +#define RT_THREAD_DEBUG + +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +#define RT_USING_HOOK + +/* Using Software Timer */ +/* #define RT_USING_TIMER_SOFT */ +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 + +/* SECTION: IPC */ +/* Using Semaphore*/ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +// +#define RT_USING_COMPONENTS_INIT + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE +// +#define RT_USING_DEVICE_IPC +// +#define RT_USING_SERIAL + +/* SECTION: Console options */ +#define RT_USING_CONSOLE +/* the buffer size of console*/ +#define RT_CONSOLEBUF_SIZE 128 +// +#define RT_CONSOLE_DEVICE_NAME "uart2" + +/* SECTION: finsh, a C-Express shell */ +#define RT_USING_FINSH +/* Using symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION + +/* SECTION: device filesystem */ +/* #define RT_USING_DFS */ + +#define RT_USING_DFS_ELMFAT +/* Reentrancy (thread safe) of the FatFs module. */ +#define RT_DFS_ELM_REENTRANT +/* Number of volumes (logical drives) to be used. */ +#define RT_DFS_ELM_DRIVES 2 +/* #define RT_DFS_ELM_USE_LFN 1 */ +/* #define RT_DFS_ELM_CODE_PAGE 936 */ +#define RT_DFS_ELM_MAX_LFN 255 +/* Maximum sector size to be handled. */ +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 + +/* the max number of mounted filesystem */ +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 + +/* SECTION: lwip, a lighwight TCP/IP protocol stack */ +/* #define RT_USING_LWIP */ +/* LwIP uses RT-Thread Memory Management */ +#define RT_LWIP_USING_RT_MEM +/* Enable ICMP protocol*/ +#define RT_LWIP_ICMP +/* Enable UDP protocol*/ +#define RT_LWIP_UDP +/* Enable TCP protocol*/ +#define RT_LWIP_TCP +/* Enable DNS */ +#define RT_LWIP_DNS + +/* the number of simulatenously active TCP connections*/ +#define RT_LWIP_TCP_PCB_NUM 5 + +/* Using DHCP */ +/* #define RT_LWIP_DHCP */ + +/* ip address of target*/ +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 + +/* gateway address of target*/ +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 + +/* mask address of target*/ +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 + +/* tcp thread options */ +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 + +/* ethernet if thread options */ +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 + +/* TCP sender buffer space */ +#define RT_LWIP_TCP_SND_BUF 8192 +/* TCP receive window. */ +#define RT_LWIP_TCP_WND 8192 + +/* SECTION: RT-Thread/GUI */ +/* #define RT_USING_RTGUI */ + +/* name length of RTGUI object */ +#define RTGUI_NAME_MAX 12 +/* support 16 weight font */ +#define RTGUI_USING_FONT16 +/* support Chinese font */ +#define RTGUI_USING_FONTHZ +/* use DFS as file interface */ +#define RTGUI_USING_DFS_FILERW +/* use font file as Chinese font */ +#define RTGUI_USING_HZ_FILE +/* use Chinese bitmap font */ +#define RTGUI_USING_HZ_BMP +/* use small size in RTGUI */ +#define RTGUI_USING_SMALL_SIZE +/* use mouse cursor */ +/* #define RTGUI_USING_MOUSE_CURSOR */ +/* default font size in RTGUI */ +#define RTGUI_DEFAULT_FONT_SIZE 16 + +/* image support */ +/* #define RTGUI_IMAGE_XPM */ +/* #define RTGUI_IMAGE_BMP */ + +// +// #define RT_USING_CMSIS_OS +// +//#define RT_USING_RTT_CMSIS +// +// #define RT_USING_BSP_CMSIS + +#endif diff --git a/bsp/rx/rx62n.eww b/bsp/rx/rx62n.eww new file mode 100644 index 0000000000000000000000000000000000000000..9487a4201d5a3788c3983abe677002545ad39a34 --- /dev/null +++ b/bsp/rx/rx62n.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rt.ewp + + + + + diff --git a/components/external/freetype/docs/VERSION.DLL b/components/external/freetype/docs/VERSION.DLL deleted file mode 100644 index bb55c3dda9336b05fdd1737abf616b72fb65f401..0000000000000000000000000000000000000000 --- a/components/external/freetype/docs/VERSION.DLL +++ /dev/null @@ -1,138 +0,0 @@ -Due to our use of `libtool' to generate and install the FreeType 2 -libraries on Unix systems, as well as other historical events, it is -generally very difficult to know precisely which release of the font -engine is installed on a given system. - -This file tries to explain why and to document ways to properly detect -FreeType on Unix. - - -1. Version and Release numbers ------------------------------- - -For each new public release of FreeType 2, there are generally *three* -distinct `version' numbers to consider: - - * The official FreeType 2 release number, like 2.0.9 or 2.1.3. - - * The libtool (and Unix) specific version number, like 9.2.3. This is - what `freetype-config --version' returns. - - * The platform-specific shared object number, used for example when - the library is installed as `/usr/lib/libfreetype.so.6.3.2'. - -The platform-specific number is, unsurprisingly, platform-specific and -varies with the operating system you are using (several variants of -Linux, FreeBSD, Solaris, etc.). You should thus _never_ use it, even -for simple tests. - -The libtool-specific number does not equal the release number but is -tied to it. - -The release number is available at *compile* time through the following -macros defined in FT_FREETYPE_H: - - - FREETYPE_MAJOR: major release number - - FREETYPE_MINOR: minor release number - - FREETYPE_PATCH: patch release number - -See below for a small autoconf fragment. - -The release number is also available at *runtime* through the -`FT_Library_Version' API. Unfortunately, this one wasn't available or -working correctly before the 2.1.3 official release. - - -2. History ----------- - -The following table gives, for each official release, the corresponding -libtool number, as well as the shared object number found on _most_ -systems, but not all of them: - - - release libtool so - ------------------------------- - 2.3.12 10.0.4 6.4.0 - 2.3.11 9.22.3 6.3.22 - 2.3.10 9.21.3 6.3.21 - 2.3.9 9.20.3 6.3.20 - 2.3.8 9.19.3 6.3.19 - 2.3.7 9.18.3 6.3.18 - 2.3.6 9.17.3 6.3.17 - 2.3.5 9.16.3 6.3.16 - 2.3.4 9.15.3 6.3.15 - 2.3.3 9.14.3 6.3.14 - 2.3.2 9.13.3 6.3.13 - 2.3.1 9.12.3 6.3.12 - 2.3.0 9.11.3 6.3.11 - 2.2.1 9.10.3 6.3.10 - 2.2.0 9.9.3 6.3.9 - 2.1.10 9.8.3 6.3.8 - 2.1.9 9.7.3 6.3.7 - 2.1.8 9.6.3 6.3.6 - 2.1.7 9.5.3 6.3.5 - 2.1.6 9.5.3 6.3.5 - 2.1.5 9.4.3 6.3.4 - 2.1.4 9.3.3 6.3.3 - 2.1.3 9.2.3 6.3.2 - 2.1.2 9.1.3 6.3.1 - 2.1.1 9.0.3 ? - 2.1.0 8.0.2 ? - 2.0.9 9.0.3 ? - 2.0.8 8.0.2 ? - 2.0.4 7.0.1 ? - 2.0.1 6.1.0 ? - -The libtool numbers are a bit inconsistent due to the library's history: - - - 2.1.0 was created as a development branch from 2.0.8 (hence the same - libtool numbers). - - - 2.0.9 was a bug-fix release of the `stable' branch, and we - incorrectly increased its libtool number. - - - 2.1.4 was a development version, however it was stable enough to be - the basis of the 2.2.0 release. - - -3. Autoconf Code Fragment -------------------------- - -Lars Clausen contributed the following autoconf fragment to detect which -version of FreeType is installed on a system. This one tests for a -version that is at least 2.0.9; you should change it to check against -other release numbers. - - - AC_MSG_CHECKING([whether FreeType version is 2.0.9 or higher]) - old_CPPFLAGS="$CPPFLAGS" - CPPFLAGS=`freetype-config --cflags` - AC_TRY_CPP([ - -#include -#include FT_FREETYPE_H -#if (FREETYPE_MAJOR*1000 + FREETYPE_MINOR)*1000 + FREETYPE_PATCH < 2000009 -#error Freetype version too low. -#endif - ], - [AC_MSG_RESULT(yes) - FREETYPE_LIBS=`freetype-config --libs` - AC_SUBST(FREETYPE_LIBS) - AC_DEFINE(HAVE_FREETYPE,1,[Define if you have the FreeType2 library]) - CPPFLAGS="$old_CPPFLAGS"], - [AC_MSG_ERROR([Need FreeType library version 2.0.9 or higher])]) - ------------------------------------------------------------------------- - -Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 by -David Turner, Robert Wilhelm, and Werner Lemberg. - -This file is part of the FreeType project, and may only be used, -modified, and distributed under the terms of the FreeType project -license, LICENSE.TXT. By continuing to use, modify, or distribute this -file you indicate that you have read the license and understand and -accept it fully. - - ---- end of VERSION.DLL --- diff --git a/components/finsh/shell.c b/components/finsh/shell.c index ccdb7bc864d08e5bb9217ce475e690500eef75f3..ad3b49534d5ad3bcd9fcefea3887306b28fd3c95 100644 --- a/components/finsh/shell.c +++ b/components/finsh/shell.c @@ -553,7 +553,7 @@ void finsh_system_var_init(const void* begin, const void* end) _sysvar_table_end = (struct finsh_sysvar*) end; } -#if defined(__ICCARM__) /* for IAR compiler */ +#if defined(__ICCARM__) || defined(__ICCRX__) /* for IAR compiler */ #ifdef FINSH_USING_SYMTAB #pragma section="FSymTab" #pragma section="VSymTab" @@ -606,7 +606,7 @@ int finsh_system_init(void) #ifndef FINSH_USING_MSH_ONLY finsh_system_var_init(&VSymTab$$Base, &VSymTab$$Limit); #endif -#elif defined (__ICCARM__) /* for IAR Compiler */ +#elif defined (__ICCARM__) || defined(__ICCRX__) /* for IAR Compiler */ finsh_system_function_init(__section_begin("FSymTab"), __section_end("FSymTab")); finsh_system_var_init(__section_begin("VSymTab"), diff --git a/libcpu/rx/context_iar.S b/libcpu/rx/context_iar.S new file mode 100644 index 0000000000000000000000000000000000000000..143ae003156146d343714ea617aa03cebccf24f0 --- /dev/null +++ b/libcpu/rx/context_iar.S @@ -0,0 +1,132 @@ +#include "cpuconfig.h" + +//#include "iorx62n.h" + EXTERN _rt_thread_switch_interrupt_flag + EXTERN _rt_interrupt_from_thread + EXTERN _rt_interrupt_to_thread + EXTERN _rt_hw_hard_fault_exception + EXTERN _rt_hw_cpu_shutdown + + /*PUBLIC _Interrupt_SWINT*/ + PUBLIC ___interrupt_27 + PUBLIC ___interrupt_0 + RSEG CODE:CODE(4) + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + PUBLIC _rt_hw_interrupt_disable +_rt_hw_interrupt_disable: + MVTIPL #MAX_SYSCALL_INTERRUPT_PRIORITY + RTS + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + PUBLIC _rt_hw_interrupt_enable +_rt_hw_interrupt_enable: + MVTIPL #KERNEL_INTERRUPT_PRIORITY + RTS + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +___interrupt_27: + +/* enable interrupt because enter the interrupt,it will be clear */ + SETPSW I + MVTIPL #MAX_SYSCALL_INTERRUPT_PRIORITY + PUSH.L R15 + +/* justage if it should switch thread*/ + MOV.L #_rt_thread_switch_interrupt_flag, R15 + MOV.L [ R15 ], R15 + CMP #0, R15 + BEQ notask_exit +/* clean the flag*/ + MOV.L #_rt_thread_switch_interrupt_flag, R15 + MOV.L #0, [ R15 ] + +/* justage if it should save the register*/ + MOV.L #_rt_interrupt_from_thread, R15 + MOV.L [ R15 ], R15 + CMP #0, R15 + BEQ need_modify_isp + /*save register*/ + MVFC USP, R15 + SUB #12, R15 + MVTC R15, USP + MOV.L [ R0 ], [ R15 ] ;PSW + MOV.L 4[ R0 ], 4[ R15 ];PC + MOV.L 8[ R0 ], 8[ R15 ] ;R15 + ADD #12, R0 + SETPSW U + PUSHM R1-R14 + MVFC FPSW, R15 + PUSH.L R15 + MVFACHI R15 + PUSH.L R15 + MVFACMI R15 ; Middle order word. + SHLL #16, R15 ; Shifted left as it is restored to the low orde r w + PUSH.L R15 + /*save thread stack pointer and switch to new thread*/ + MOV.L #_rt_interrupt_from_thread, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + BRA swtich_to_thread +need_modify_isp: + MVFC ISP, R15 + ADD #12, R15 + MVTC R15, ISP +swtich_to_thread: + SETPSW U + MOV.L #_rt_interrupt_to_thread, R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + BRA pendsv_exit +notask_exit: + POP R15 +pendsv_exit: + + MVTIPL #KERNEL_INTERRUPT_PRIORITY + RTE + NOP + NOP +/*exception interrupt*/ +___interrupt_0: + PUSH.L R15 + /*save the register for infomation*/ + MVFC USP, R15 + SUB #12, R15 + MVTC R15, USP + MOV.L [ R0 ], [ R15 ] ;PSW + MOV.L 4[ R0 ], 4[ R15 ];PC + MOV.L 8[ R0 ], 8[ R15 ] ;R15 + ADD #12, R0 + SETPSW U + PUSHM R1-R14 + MVFC FPSW, R15 + PUSH.L R15 + MVFACHI R15 + PUSH.L R15 + MVFACMI R15 ; Middle order word. + SHLL #16, R15 ; Shifted left as it is restored to the low orde r w + PUSH.L R15 + /*save the exception infomation add R1 as a parameter of + * function rt_hw_hard_fault_exception + */ + MOV.L R0, R1 + BRA _rt_hw_hard_fault_exception + BRA _rt_hw_cpu_shutdown + RTE + NOP + NOP + END + diff --git a/libcpu/rx/cpuconfig.h b/libcpu/rx/cpuconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..8b0fd37ce8b98cad9af9ab4ce29562e450b0ad89 --- /dev/null +++ b/libcpu/rx/cpuconfig.h @@ -0,0 +1,7 @@ +#ifndef __CPU_CONFIG_H__ +#define __CPU_CONFIG_H__ + +#define MAX_SYSCALL_INTERRUPT_PRIORITY 10 +#define KERNEL_INTERRUPT_PRIORITY 1 + +#endif diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c new file mode 100644 index 0000000000000000000000000000000000000000..e8a75c629e78bb19df682f98b1d02754721b055e --- /dev/null +++ b/libcpu/rx/cpuport.c @@ -0,0 +1,216 @@ +/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-23 Bernard the first version + * 2012-03-03 xuzhenglim modify for rx62N + */ +#include +#include + +#include "cpuconfig.h" + +#include "machine.h" +#include "iorx62n.h" + +#define ENTER_INTERRUPT() ICU.SWINTR.BIT.SWINT = 1; + +extern volatile rt_uint8_t rt_interrupt_nest; + + +/* switch flag on interrupt and thread pointer to save switch record */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + + +/* stack frame*/ +struct stack_frame +{ + rt_uint32_t ACCLO; + rt_uint32_t ACCHI; + rt_uint32_t FPSW; + rt_uint32_t R1; + rt_uint32_t R2; + rt_uint32_t R3; + rt_uint32_t R4; + rt_uint32_t R5; + rt_uint32_t R6; + rt_uint32_t R7; + rt_uint32_t R8; + rt_uint32_t R9; + rt_uint32_t R10; + rt_uint32_t R11; + rt_uint32_t R12; + rt_uint32_t R13; + rt_uint32_t R14; + rt_uint32_t R15; + //there is not R0 register,it is special for stack pointer + rt_uint32_t PC; + rt_uint32_t PSW; +}; + +/** + * Initilial the threah stack. + * + * @author LXZ (2014/11/8) + * + * @param void* tentry + * @param void* parameter + * @param rt_uint8_t* stack_addr + * @param void* texit + * + * @return rt_uint8_t* + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + struct stack_frame *stack_frame; + unsigned long i; + + stk = (unsigned long *)stack_addr; + *(stk) = (unsigned long)texit; + stack_frame = (struct stack_frame *)(stack_addr - sizeof(struct stack_frame)) ; + + //Initilial all register + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) + { + ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->PSW = (unsigned long)0x00030000 ; /* psw */ + stack_frame->PC = (unsigned long)tentry; /* thread entery*/ + stack_frame->R1 = (unsigned long )parameter; /* r1 : parameter */ + stack_frame->FPSW = 0x00000100; /* fpsw */ + + return(rt_uint8_t *)stack_frame; +} + +#ifdef RT_USING_FINSH +extern void list_thread(void); +#endif +extern rt_thread_t rt_current_thread; +/** + * deal exception + * + * @author LXZ (2014/11/8) + * + * @param struct stack_frame* exception_contex + */ +void rt_hw_hard_fault_exception(struct stack_frame* exception_contex) +{ + if (exception_contex != RT_NULL) { + rt_kprintf("psw: 0x%08x\n", exception_contex->PSW); + rt_kprintf("pc: 0x%08x\n", exception_contex->PC); + rt_kprintf("r0: 0x%08x\n", exception_contex->R1); + rt_kprintf("r0: 0x%08x\n", exception_contex->R2); + rt_kprintf("r0: 0x%08x\n", exception_contex->R3); + rt_kprintf("r0: 0x%08x\n", exception_contex->R4); + rt_kprintf("r0: 0x%08x\n", exception_contex->R5); + rt_kprintf("r0: 0x%08x\n", exception_contex->R6); + rt_kprintf("r0: 0x%08x\n", exception_contex->R7); + rt_kprintf("r0: 0x%08x\n", exception_contex->R8); + rt_kprintf("r0: 0x%08x\n", exception_contex->R9); + rt_kprintf("r0: 0x%08x\n", exception_contex->R10); + rt_kprintf("r0: 0x%08x\n", exception_contex->R11); + rt_kprintf("r0: 0x%08x\n", exception_contex->R12); + rt_kprintf("r0: 0x%08x\n", exception_contex->R13); + rt_kprintf("r0: 0x%08x\n", exception_contex->R14); + rt_kprintf("r0: 0x%08x\n", exception_contex->R15); + rt_kprintf("fpsw: 0x%08x\n", exception_contex->FPSW); + rt_kprintf("acchi: 0x%08x\n", exception_contex->ACCHI); + rt_kprintf("acclo: 0x%08x\n", exception_contex->ACCLO); + } + rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name); + #ifdef RT_USING_FINSH + list_thread(); + #endif + while (1); + +} + + +/** + * switch thread in interrupt + * + * @author LXZ (2014/11/8) + * + * @param rt_uint32_t from + * @param rt_uint32_t to + */ +void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + { + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = from; + } + + rt_interrupt_to_thread = to; + ENTER_INTERRUPT(); +} +/** + * swithc thread out the interrupt + * + * @author LXZ (2014/11/8) + * + * @param rt_uint32_t from + * @param rt_uint32_t to + */ +void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + { + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = from; + } + + rt_interrupt_to_thread = to; + ENTER_INTERRUPT(); +} + +/** + * shut down the chip + * + * @author LXZ (2014/11/8) + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + RT_ASSERT(0); +} +/** + * switch to the first thread,it just call one time + * + * @author LXZ (2014/11/8) + * + * @param rt_uint32_t to + */ +void rt_hw_context_switch_to(rt_uint32_t to) +{ + + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + /* enable interrupt*/ + _IEN( _ICU_SWINT ) = 1; + + /*clear the interrupt flag*/ + _IR( _ICU_SWINT ) = 0; + _IPR( _ICU_SWINT ) = MAX_SYSCALL_INTERRUPT_PRIORITY + 1; + + /*touch the software interrupt*/ + ENTER_INTERRUPT(); + /*wait for first thread start up*/ + while(1); +} +