diff --git a/bsp/essemi/es8p508x/.config b/bsp/essemi/es8p508x/.config new file mode 100644 index 0000000000000000000000000000000000000000..ff8ee21d05ce8e7445c2e2b659376c105f9d9e6c --- /dev/null +++ b/bsp/essemi/es8p508x/.config @@ -0,0 +1,405 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart5" +CONFIG_RT_VER_NUM=0x40002 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=2048 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_ES8P508x=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +CONFIG_BSP_USING_UART5=y + +# +# Onboard Peripheral Drivers +# + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/essemi/es8p508x/Kconfig b/bsp/essemi/es8p508x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..57778bdbef4cc6021a119e3386d1d2d76fee5bfc --- /dev/null +++ b/bsp/essemi/es8p508x/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ES8P508x + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "drivers/Kconfig" diff --git a/bsp/essemi/es8p508x/README.md b/bsp/essemi/es8p508x/README.md new file mode 100644 index 0000000000000000000000000000000000000000..68c95b3ede1753b033830c85a95551b262a8c3a8 --- /dev/null +++ b/bsp/essemi/es8p508x/README.md @@ -0,0 +1,91 @@ +# HRSDK-GDB-ES8P508 开发板 BSP 说明 +标签： EastSoft、国产MCU、Cortex-M0、ES8P5088FLLQ + +## 1. 简介 + +本文档为上海东软载波微电子开发团队为 HRSDK-GDB-ES8P508 开发板提供的 BSP (板级支持包) 说明。 +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +主要内容如下： +HRSDK-GDB-ES8P508x 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。 + +开发板外观如下图所示： + +HRSDK-GDB-ES8P508x-V1.0 + +![ES8P508](figures/HRSDK-GDB-ES8P508x-V1.0.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：ES8P5088FLLQ，主频 48MHz，24KB SRAM，128KB FLASH，45 GPIOs +- 常用外设 + - LED：1个，(PA14) + - 按键：1个(MRSTN) +- 常用接口：GPIO、UART、SPI、I2C +- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 + +外设支持: + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :---------------- | :----------: | :-----------------------------------| +| GPIO | 支持 | 45 GPIOs | +| UART | 支持 | UART0/1/2/3/4/5 | + + +更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) + +## 2. 快速上手 + +本 BSP 为开发者提供 MDK4 工程。下面以 MDK4 开发环境为例，介绍如何将系统运行起来。 + +### 硬件连接 + +使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART5_TX(PB13)、UART5_RX(PB12)、GND 接到串口工具上。 + +使用ESlinkⅡ(mini)连接开发板如下图所示： + +ESLinkⅡ(mini) + HRSDK-GDB-ES8P508-V1.0 + +![ESLinkII](figures/ESLinkII-mini.jpg) + +### 编译下载 + +双击 project.uvprojx 文件，打开 MDK4 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 + +### 运行结果 + +下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Jul 12 2019 + 2006 - 2019 Copyright by rt-thread team +msh /> +``` +## 3. 进阶使用 + +此 BSP 默认只开启了 GPIO 和 uart5 的功能，如果需使用 SPI 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=MDK4` 命令重新生成工程。 + +更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) + +## 4. 联系人信息 + +- [wangyongquan](https://github.com/wangyq2018) + +## 5. 参考 + +- [ EastSoft 官网](http://www.essemi.com) + diff --git a/bsp/essemi/es8p508x/SConscript b/bsp/essemi/es8p508x/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..468297b6a99ab9c400a87ed01dcdedc3d60da45d --- /dev/null +++ b/bsp/essemi/es8p508x/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +objs = [] +cwd = str(Dir('#')) +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/essemi/es8p508x/SConstruct b/bsp/essemi/es8p508x/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..164265293da6f0f0240d637f812532529b46881b --- /dev/null +++ b/bsp/essemi/es8p508x/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/essemi/es8p508x/applications/SConscript b/bsp/essemi/es8p508x/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e0c84e8f1426ab2abb2c870cea377371a7c752f3 --- /dev/null +++ b/bsp/essemi/es8p508x/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') + +CPPPATH = [cwd, str(Dir('#'))] +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es8p508x/applications/main.c b/bsp/essemi/es8p508x/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..6494a970b5b73a9bd2b2b9c195f71d1f9fdb2b06 --- /dev/null +++ b/bsp/essemi/es8p508x/applications/main.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-12 wangyq the first version + */ + +#include +#include +#include + +#define LED_PIN 29 + +int main(void) +{ + int count = 1; + + /* set PA14 pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} + diff --git a/bsp/essemi/es8p508x/drivers/Kconfig b/bsp/essemi/es8p508x/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..98a7d173b3341fde4ff241e4b5a9e2cefa55aa8f --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/Kconfig @@ -0,0 +1,51 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menu "UART Drivers" + config BSP_USING_UART0 + bool "Enable UART0 PB00/PB01(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART1 + bool "Enable UART1 PA18/PA17(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Enable UART2 PA04/PA05(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Enable UART3 PA30/PA29(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART4 + bool "Enable UART4 PB10/PB11(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART5 + bool "Enable UART5 PB12/PB13(R/T)" + select RT_USING_SERIAL + default y + endmenu + + endmenu + + menu "Onboard Peripheral Drivers" + + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + +endmenu diff --git a/bsp/essemi/es8p508x/drivers/SConscript b/bsp/essemi/es8p508x/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..f2b341e073f4c2d428b078f5af8887cc60f4faf8 --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/SConscript @@ -0,0 +1,21 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(''' +board.c +''') + +# add gpio code +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5'): + src += ['drv_uart.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es8p508x/drivers/board.c b/bsp/essemi/es8p508x/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..b013fa327ca4888b307349c1e28faf2b7c5f05ff --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/board.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-11 wangyq the first version + */ + +#include +#include +#include "board.h" +#include "drv_uart.h" +#include "drv_gpio.h" +#include +#include + +/** + * @addtogroup es8p + */ + +/*@{*/ + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures Vector Table base location. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ +} + +/******************************************************************************* + * Function Name : SystemClock_Configuration + * Description : Configures the System Clock. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SystemClock_Config(void) +{ + /* system clock 48MHz */ + PLLClock_Config(ENABLE, SCU_PLL_HRC, SCU_PLL_48M, ENABLE); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + /* ticks = SYS_CLK / RT_TICK_PER_SECOND */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); +} + +/** + * This is the timer interrupt service routine. + * + */ +void systick_irq_cbk(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/*@}*/ +/** + * This function will initial es8p board. + */ +void rt_hw_board_init(void) +{ + /* NVIC Configuration */ + NVIC_Configuration(); + + /*System Clock Configuration */ + SystemClock_Config(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + unsigned int start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} diff --git a/bsp/essemi/es8p508x/drivers/board.h b/bsp/essemi/es8p508x/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..0dcfdd432f8b76ab275ecc43212cb37b95be9e15 --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/board.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-11 wangyq the first version + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#define ES8P_SRAM_SIZE 0x6000 +#define ES8P_SRAM_END (0x20000000 + ES8P_SRAM_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END ES8P_SRAM_END + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/essemi/es8p508x/drivers/drv_gpio.c b/bsp/essemi/es8p508x/drivers/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..b91532a7067e8e4056be6d41e857347c98cd2b4e --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/drv_gpio.c @@ -0,0 +1,478 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-11 wangyq the first version + */ + +#include +#include +#include "board.h" +#include "drv_gpio.h" +#include +#include + +#ifdef RT_USING_PIN + +#define __ES8P_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_Pin_##gpio_index} +#define __ES8P_PIN_DEFAULT {-1, GPIOA, GPIO_Pin_0} + +/* es8p GPIO driver */ +struct pin_index +{ + int index; + GPIO_TYPE gpio; + GPIO_TYPE_PIN pin; +}; + +static const struct pin_index pins[] = +{ + __ES8P_PIN_DEFAULT, + __ES8P_PIN(1, B, 0), + __ES8P_PIN(2, B, 1), + __ES8P_PIN(3, B, 2), + __ES8P_PIN(4, B, 3), + __ES8P_PIN(5, B, 4), + __ES8P_PIN(6, B, 5), + __ES8P_PIN(7, B, 6), + __ES8P_PIN(8, B, 7), + __ES8P_PIN(9, B, 8), + __ES8P_PIN(10, B, 9), + __ES8P_PIN(11, B, 10), + __ES8P_PIN(12, B, 11), + __ES8P_PIN(13, B, 12), + __ES8P_PIN(14, B, 13), + __ES8P_PIN(15, A, 0), + __ES8P_PIN(16, A, 1), + __ES8P_PIN(17, A, 2), + __ES8P_PIN(18, A, 3), + __ES8P_PIN(19, A, 4), + __ES8P_PIN(20, A, 5), + __ES8P_PIN(21, A, 6), + __ES8P_PIN(22, A, 7), + __ES8P_PIN(23, A, 8), + __ES8P_PIN(24, A, 9), + __ES8P_PIN(25, A, 10), + __ES8P_PIN(26, A, 11), + __ES8P_PIN(27, A, 12), + __ES8P_PIN(28, A, 13), + __ES8P_PIN(29, A, 14), + __ES8P_PIN(30, A, 15), + __ES8P_PIN(31, A, 16), + __ES8P_PIN_DEFAULT, + __ES8P_PIN_DEFAULT, + __ES8P_PIN(34, A, 17), + __ES8P_PIN(35, A, 18), + __ES8P_PIN_DEFAULT, + __ES8P_PIN(37, A, 20), + __ES8P_PIN(38, A, 21), + __ES8P_PIN(39, A, 22), + __ES8P_PIN(40, A, 23), + __ES8P_PIN(41, A, 24), + __ES8P_PIN(42, A, 25), + __ES8P_PIN(43, A, 26), + __ES8P_PIN(44, A, 27), + __ES8P_PIN(45, A, 28), + __ES8P_PIN(46, A, 29), + __ES8P_PIN(47, A, 30), + __ES8P_PIN(48, A, 31), +}; + +struct irq_map +{ + PINT_TYPE pinno; + IRQn_Type irqno; +}; +static const struct irq_map irq_map[] = +{ + {PINT0, PINT0_IRQn}, + {PINT1, PINT1_IRQn}, + {PINT2, PINT2_IRQn}, + {PINT3, PINT3_IRQn}, + {PINT4, PINT4_IRQn}, + {PINT5, PINT5_IRQn}, + {PINT6, PINT6_IRQn}, + {PINT7, PINT7_IRQn}, +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +void es8p_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + if (value == 0) + { + if (index->gpio == GPIOA) + GPIOA_ResetBit(index->pin); + else if (index->gpio == GPIOB) + GPIOB_ResetBit(index->pin); + } + else + { + if (index->gpio == GPIOA) + GPIOA_SetBit(index->pin); + else if (index->gpio == GPIOB) + GPIOB_SetBit(index->pin); + } +} + +int es8p_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + value = PIN_LOW; + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + value = GPIO_ReadBit(index->gpio, index->pin); + return value; +} + +void es8p_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitStruType gpio_initstruct; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Configure GPIO_InitStructure */ + gpio_initstruct.GPIO_Signal = GPIO_Pin_Signal_Digital; + gpio_initstruct.GPIO_Func = GPIO_Func_0; + gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Disable; + gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable; + gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable; + gpio_initstruct.GPIO_DS = GPIO_DS_Output_Normal; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Enable; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Enable; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; + gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Enable; + } + GPIO_Init(index->gpio, index->pin, &gpio_initstruct); +} + +rt_inline const struct irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) +{ + rt_int32_t mapindex = gpio_pin & 0x00FF; + if (mapindex < 0 || mapindex >= 32) + { + return RT_NULL; + } + return &irq_map[mapindex % 8]; +}; + +rt_err_t es8p_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irqindex = index->pin % 8; + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t es8p_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = index->pin % 8; + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es8p_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + /* Configure GPIO_InitStructure */ + GPIO_InitStruType gpio_initstruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = pin % 8; + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + irqmap = &irq_map[irqindex]; + + /* Configure GPIO_InitStructure */ + gpio_initstruct.GPIO_Signal = GPIO_Pin_Signal_Digital; + gpio_initstruct.GPIO_Func = GPIO_Func_0; + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Disable; + gpio_initstruct.GPIO_DS = GPIO_DS_Output_Normal; + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable; + gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Enable; + if (index->gpio == GPIOA) + PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Rise); + else + PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Rise); + break; + + case PIN_IRQ_MODE_FALLING: + gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Enable; + gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable; + if (index->gpio == GPIOA) + PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Fall); + else + PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Fall); + break; + + case PIN_IRQ_MODE_RISING_FALLING: + gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable; + gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable; + if (index->gpio == GPIOA) + PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Change); + else + PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Change); + break; + + default: + break; + } + GPIO_Init(index->gpio, index->pin, &gpio_initstruct); + NVIC_EnableIRQ(irqmap->irqno); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + NVIC_DisableIRQ(irqmap->irqno); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops _es8p_pin_ops = +{ + es8p_pin_mode, + es8p_pin_write, + es8p_pin_read, + es8p_pin_attach_irq, + es8p_pin_detach_irq, + es8p_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + int result; + SCU_GPIOCLK_Enable(); + result = rt_device_pin_register("pin", &_es8p_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(PINT_TYPE_IT GPIO_Pin) +{ + uint16_t irqno; + /* pin no. convert to dec no. */ + for (irqno = 0; irqno < 16; irqno++) + { + if ((0x01 << irqno) == GPIO_Pin) + { + break; + } + } + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +rt_inline void GPIO_EXTI_Callback(PINT_TYPE_IT GPIO_Pin) +{ + if (PINT_GetIFStatus(GPIO_Pin) != RESET) + { + PINT_ClearITPendingBit(GPIO_Pin); + pin_irq_hdr(GPIO_Pin); + } +} + +void PINT0_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(PINT_IT_PINT0); + rt_interrupt_leave(); +} + +void PINT1_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(PINT_IT_PINT1); + rt_interrupt_leave(); +} + +void PINT2_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(PINT_IT_PINT2); + rt_interrupt_leave(); +} + +void PINT3_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(PINT_IT_PINT3); + rt_interrupt_leave(); +} + +void PINT4_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(PINT_IT_PINT4); + rt_interrupt_leave(); +} + +void PINT5_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(PINT_IT_PINT5); + rt_interrupt_leave(); +} + +void PINT6_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(PINT_IT_PINT6); + rt_interrupt_leave(); +} + +void PINT7_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(PINT_IT_PINT7); + rt_interrupt_leave(); +} + +#endif diff --git a/bsp/essemi/es8p508x/drivers/drv_gpio.h b/bsp/essemi/es8p508x/drivers/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..28a5987f20d8eef988f09219863bc4de6f2860a2 --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/drv_gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-11 wangyq the first version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/essemi/es8p508x/drivers/drv_uart.c b/bsp/essemi/es8p508x/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..3fb1410a4833a3e7c5ab1975a4dc20a9d946f5d5 --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/drv_uart.c @@ -0,0 +1,444 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-12 wangyq the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_uart.h" +#include +#include + +#ifdef RT_USING_SERIAL + +/* es8p uart driver */ +struct es8p_uart +{ + UART_TypeDef *huart; + IRQn_Type irq; +}; + +static rt_err_t es8px_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + GPIO_InitStruType gpio_initstruct; + UART_InitStruType uart_initstruct; + struct es8p_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es8p_uart *)serial->parent.user_data; + + gpio_initstruct.GPIO_Signal = GPIO_Pin_Signal_Digital; + gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Disable; + gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Enable; + gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable; + gpio_initstruct.GPIO_DS = GPIO_DS_Output_Normal; + +#ifdef BSP_USING_UART0 + gpio_initstruct.GPIO_Func = GPIO_Func_2; + /* Initialize rx pin */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + GPIO_Init(GPIOB, GPIO_Pin_0, &gpio_initstruct); + /* Initialize tx pin ,the same as rx pin except mode */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; + GPIO_Init(GPIOB, GPIO_Pin_1, &gpio_initstruct); +#endif + +#ifdef BSP_USING_UART1 + gpio_initstruct.GPIO_Func = GPIO_Func_1; + /* Initialize rx pin */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + GPIO_Init(GPIOA, GPIO_Pin_18, &gpio_initstruct); + /* Initialize tx pin ,the same as rx pin except mode */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; + GPIO_Init(GPIOA, GPIO_Pin_17, &gpio_initstruct); +#endif + +#ifdef BSP_USING_UART2 + gpio_initstruct.GPIO_Func = GPIO_Func_2; + /* Initialize rx pin */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + GPIO_Init(GPIOA, GPIO_Pin_4, &gpio_initstruct); + /* Initialize tx pin ,the same as rx pin except mode */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; + GPIO_Init(GPIOA, GPIO_Pin_5, &gpio_initstruct); +#endif + +#ifdef BSP_USING_UART3 + gpio_initstruct.GPIO_Func = GPIO_Func_2; + /* Initialize rx pin */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + GPIO_Init(GPIOA, GPIO_Pin_30, &gpio_initstruct); + /* Initialize tx pin ,the same as rx pin except mode */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; + GPIO_Init(GPIOA, GPIO_Pin_29, &gpio_initstruct); +#endif + +#ifdef BSP_USING_UART4 + gpio_initstruct.GPIO_Func = GPIO_Func_1; + /* Initialize rx pin */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + GPIO_Init(GPIOB, GPIO_Pin_10, &gpio_initstruct); + /* Initialize tx pin ,the same as rx pin except mode */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; + GPIO_Init(GPIOB, GPIO_Pin_11, &gpio_initstruct); +#endif + +#ifdef BSP_USING_UART5 + gpio_initstruct.GPIO_Func = GPIO_Func_1; + /* Initialize rx pin */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_In; + GPIO_Init(GPIOB, GPIO_Pin_12, &gpio_initstruct); + /* Initialize tx pin ,the same as rx pin except mode */ + gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; + GPIO_Init(GPIOB, GPIO_Pin_13, &gpio_initstruct); +#endif + + uart_initstruct.UART_ClockSet = UART_Clock_1; + uart_initstruct.UART_BaudRate = cfg->baud_rate; + uart_initstruct.UART_RxPolar = UART_Polar_Normal; + uart_initstruct.UART_TxPolar = UART_Polar_Normal; + + if (cfg->data_bits == DATA_BITS_7) + { + uart_initstruct.UART_RxMode = UART_DataMode_7; + uart_initstruct.UART_TxMode = UART_DataMode_7; + + if (cfg->parity == PARITY_EVEN) + { + uart_initstruct.UART_RxMode = UART_DataMode_7Even; + uart_initstruct.UART_TxMode = UART_DataMode_7Even; + } + else if (cfg->parity == PARITY_ODD) + { + uart_initstruct.UART_RxMode = UART_DataMode_7Odd; + uart_initstruct.UART_TxMode = UART_DataMode_7Odd; + } + } + else if (cfg->data_bits == DATA_BITS_8) + { + uart_initstruct.UART_RxMode = UART_DataMode_8; + uart_initstruct.UART_TxMode = UART_DataMode_8; + + if (cfg->parity == PARITY_EVEN) + { + uart_initstruct.UART_RxMode = UART_DataMode_8Even; + uart_initstruct.UART_TxMode = UART_DataMode_8Even; + } + else if (cfg->parity == PARITY_ODD) + { + uart_initstruct.UART_RxMode = UART_DataMode_8Odd; + uart_initstruct.UART_TxMode = UART_DataMode_8Odd; + } + } + else if (cfg->data_bits == DATA_BITS_9) + { + uart_initstruct.UART_RxMode = UART_DataMode_9; + uart_initstruct.UART_TxMode = UART_DataMode_9; + } + + if (cfg->bit_order == BIT_ORDER_MSB) + { + return RT_EINVAL; + } + + if (cfg->invert == NRZ_INVERTED) + { + uart_initstruct.UART_RxPolar = UART_Polar_Opposite; + uart_initstruct.UART_TxPolar = UART_Polar_Opposite; + } + + /* config uart function */ + UART_Init(uart->huart, &uart_initstruct); + /* enable rx and tx */ + uart->huart->CON.RXEN = 1; + uart->huart->CON.TXEN = 1; + + NVIC_SetPriority(uart->irq, 1); + + return RT_EOK; +} + +static rt_err_t es8px_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es8p_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es8p_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + UART_ITConfig(uart->huart, UART_IT_RB, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + UART_ITConfig(uart->huart, UART_IT_RB, ENABLE); + break; + } + + return RT_EOK; +} + +static int es8px_putc(struct rt_serial_device *serial, char c) +{ + struct es8p_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es8p_uart *)serial->parent.user_data; + + while (UART_GetFlagStatus(uart->huart, UART_FLAG_TB) == RESET) ; + UART_SendByte(uart->huart, c); + + return 1; +} + +static int es8px_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es8p_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es8p_uart *)serial->parent.user_data; + + if (UART_GetFlagStatus(uart->huart, UART_FLAG_RB)) + { + ch = UART_RecByte(uart->huart); + } + + return ch; +} + +static const struct rt_uart_ops es8px_uart_ops = +{ + es8px_configure, + es8px_control, + es8px_putc, + es8px_getc, +}; + +#ifdef BSP_USING_UART0 +/* UART0 device driver structure */ +struct es8p_uart uart0 = +{ + UART0, + UART0_IRQn +}; + +struct rt_serial_device serial0; + +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART0->IF.RBIF) + { + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +/* UART1 device driver structure */ +struct es8p_uart uart1 = +{ + UART1, + UART1_IRQn +}; + +struct rt_serial_device serial1; + +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART1->IF.RBIF) + { + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +/* UART1 device driver structure */ +struct es8p_uart uart2 = +{ + UART2, + UART2_IRQn +}; + +struct rt_serial_device serial2; + +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART2->IF.RBIF) + { + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +/* UART3 device driver structure */ +struct es8p_uart uart3 = +{ + UART3, + UART3_IRQn +}; + +struct rt_serial_device serial3; + +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART3->IF.RBIF) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#ifdef BSP_USING_UART4 +/* UART4 device driver structure */ +struct es8p_uart uart4 = +{ + UART4, + UART4_IRQn +}; + +struct rt_serial_device serial4; + +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART4->IF.RBIF) + { + rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#ifdef BSP_USING_UART5 +/* UART5 device driver structure */ +struct es8p_uart uart5 = +{ + UART5, + UART5_IRQn +}; + +struct rt_serial_device serial5; + +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART5->IF.RBIF) + { + rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART5 */ + +int rt_hw_uart_init(void) +{ + struct es8p_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef BSP_USING_UART0 + uart = &uart0; + serial0.ops = &es8px_uart_ops; + serial0.config = config; + + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 + uart = &uart1; + serial1.ops = &es8px_uart_ops; + serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 + uart = &uart2; + serial2.ops = &es8px_uart_ops; + serial2.config = config; + + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 + uart = &uart3; + serial3.ops = &es8px_uart_ops; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); +#endif /* BSP_USING_UART3 */ + +#ifdef BSP_USING_UART4 + uart = &uart4; + serial4.ops = &es8px_uart_ops; + serial4.config = config; + + /* register UART4 device */ + rt_hw_serial_register(&serial4, "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); +#endif /* BSP_USING_UART4 */ + +#ifdef BSP_USING_UART5 + uart = &uart5; + serial5.ops = &es8px_uart_ops; + serial5.config = config; + + /* register UART5 device */ + rt_hw_serial_register(&serial5, "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); +#endif /* BSP_USING_UART5 */ + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif diff --git a/bsp/essemi/es8p508x/drivers/drv_uart.h b/bsp/essemi/es8p508x/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..77abf1cfd444cedbb3daa25008c3235e4c42626b --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-12 wangyq the first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/essemi/es8p508x/drivers/linker_scripts/link.sct b/bsp/essemi/es8p508x/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..47ab250a8baf590cf57b4b2c1a24c59ffb896f10 --- /dev/null +++ b/bsp/essemi/es8p508x/drivers/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00006000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/essemi/es8p508x/figures/ESLinkII-mini.jpg b/bsp/essemi/es8p508x/figures/ESLinkII-mini.jpg new file mode 100644 index 0000000000000000000000000000000000000000..7dfc7aa1aeebc6864d5cd818713cb67150980765 Binary files /dev/null and b/bsp/essemi/es8p508x/figures/ESLinkII-mini.jpg differ diff --git a/bsp/essemi/es8p508x/figures/HRSDK-GDB-ES8P508x-V1.0.jpg b/bsp/essemi/es8p508x/figures/HRSDK-GDB-ES8P508x-V1.0.jpg new file mode 100644 index 0000000000000000000000000000000000000000..a31b7c07040adcf836a46f4a914ac14d2f0ba7dd Binary files /dev/null and b/bsp/essemi/es8p508x/figures/HRSDK-GDB-ES8P508x-V1.0.jpg differ diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/ES8P508x.h b/bsp/essemi/es8p508x/libraries/CMSIS/ES8P508x.h new file mode 100644 index 0000000000000000000000000000000000000000..e6eab20bc46872860d6a335bf6fa0f5c5c66cb8e --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/CMSIS/ES8P508x.h @@ -0,0 +1,3117 @@ +/******************************************************************* +* *file : ES8P508x.h +* *description: ES8P508x Device Head File +* *author : Eastsoft MCU Software Team +* *version : V0.01 +* *data : 7/11/2017 +* +* *Copyright (C) 2017 Shanghai Eastsoft Microelectronics Co., Ltd. +*******************************************************************/ +#ifndef __ES8P508x_H__ +#define __ES8P508x_H__ + +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +#define __CM0_REV 0 /* Core Revision r0p0 */ +#define __NVIC_PRIO_BITS 2 /* ES8P508x uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +typedef enum IRQn +{ + /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + RST_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVC_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + PINT0_IRQn = 0, + PINT1_IRQn = 1, + PINT2_IRQn = 2, + PINT3_IRQn = 3, + PINT4_IRQn = 4, + PINT5_IRQn = 5, + PINT6_IRQn = 6, + PINT7_IRQn = 7, + T16N0_IRQn = 8, + T16N1_IRQn = 9, + T16N2_IRQn = 10, + T16N3_IRQn = 11, + T32N0_IRQn = 12, + Reserved0_IRQn = 13, + IWDT_IRQn = 14, + WWDT_IRQn = 15, + CCM_IRQn = 16, + PLK_IRQn = 17, + LVD_IRQn = 18, + KINT_IRQn = 19, + RTC_IRQn = 20, + ADC_IRQn = 21, + Reserved1_IRQn = 22, + AES_IRQn = 23, + UART0_IRQn = 24, + UART1_IRQn = 25, + UART2_IRQn = 26, + UART3_IRQn = 27, + UART4_IRQn = 28, + UART5_IRQn = 29, + SPI0_IRQn = 30, + I2C0_IRQn = 31, +} IRQn_Type; + + +#include "core_cm0.h" +#include + + +/******************************************************************************/ +/* 设备特殊寄存器结构定䷿ */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联县 */ +#pragma anon_unions + +typedef union +{ + struct + { + uint32_t PROT: 1; + uint32_t RESERVED0: 31; + }; + uint32_t Word; +} SCU_PROT_Typedef; + +typedef union +{ + struct + { + uint32_t NMIEN: 1; + uint32_t NMICS: 5; + uint32_t RESERVED0: 26; + }; + uint32_t Word; +} SCU_NMICON_Typedef; + +typedef union +{ + struct + { + uint32_t PORF: 1; + uint32_t PORRCF: 1; + uint32_t PORRSTF: 1; + uint32_t BORF: 1; + uint32_t WWDTRSTF: 1; + uint32_t IWDTRSTF: 1; + uint32_t MRSTF: 1; + uint32_t SOFT_RSTF: 1; + uint32_t POR_LOST: 1; + uint32_t CFG_RST: 1; + uint32_t LOCKUP_RST: 1; + uint32_t RESERVED0: 21; + }; + uint32_t Word; +} SCU_PWRC_Typedef; + +typedef union +{ + struct + { + uint32_t FLAG0: 1; + uint32_t FLAG1: 1; + uint32_t FLAG2: 1; + uint32_t FLAG3: 1; + uint32_t FLAG4: 1; + uint32_t RESERVED0: 27; + }; + uint32_t Word; +} SCU_FAULTFLAG_Typedef; + +typedef union +{ + struct + { + uint32_t WAKEUPTIME: 12; + uint32_t MOSC_EN: 1; + uint32_t CLKFLT_EN: 1; + uint32_t FLASHPW_PD: 1; + uint32_t RESERVED0: 1; + uint32_t LDOLP_VOSEL: 3; + uint32_t LDOHP_SOFT: 1; + uint32_t RESERVED1: 12; + }; + uint32_t Word; +} SCU_WAKEUPTIME_Typedef; + +typedef union +{ + struct + { + uint32_t PINST: 1; + uint32_t RESERVED0: 31; + }; + uint32_t Word; +} SCU_MRSTN_SOFT_Typedef; + +typedef union +{ + struct + { + uint32_t T16N0HT: 1; + uint32_t T16N1HT: 1; + uint32_t T16N2HT: 1; + uint32_t T16N3HT: 1; + uint32_t RESERVED0: 4; + uint32_t T32N0HT: 1; + uint32_t RESERVED1: 7; + uint32_t IWDTHT: 1; + uint32_t WWDTHT: 1; + uint32_t RESERVED2: 14; + }; + uint32_t Word; +} SCU_DBGHALT_Typedef; + +typedef union +{ + struct + { + uint32_t ACCT: 4; + uint32_t HS: 1; + uint32_t RESERVED0: 27; + }; + uint32_t Word; +} SCU_FLASHWAIT_Typedef; + +typedef union +{ + struct + { + uint32_t RESERVED0: 1; + uint32_t BORV: 4; + uint32_t BORFLT: 3; + uint32_t RESERVED1: 24; + }; + uint32_t Word; +} SCU_SOFTCFG_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t FLTEN: 1; + uint32_t RESERVED0: 2; + uint32_t VS: 4; + uint32_t IF: 1; + uint32_t IE: 1; + uint32_t IFS: 3; + uint32_t RESERVED1: 2; + uint32_t LVDO: 1; + uint32_t RESERVED2: 16; + }; + uint32_t Word; +} SCU_LVDCON_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t RESERVED0: 3; + uint32_t IE: 1; + uint32_t IFS: 3; + uint32_t IF: 1; + uint32_t RESERVED1: 7; + uint32_t FLAG: 1; + uint32_t RESERVED2: 15; + }; + uint32_t Word; +} SCU_CCM_Typedef; + +typedef union +{ + struct + { + uint32_t IE: 1; + uint32_t RESERVED0: 3; + uint32_t LK_IFS: 3; + uint32_t RESERVED1: 1; + uint32_t IF: 1; + uint32_t RESERVED2: 7; + uint32_t LK_FLAG: 1; + uint32_t RESERVED3: 15; + }; + uint32_t Word; +} SCU_PLLLKCON_Typedef; + +typedef union +{ + struct + { + uint32_t CLK_SEL: 2; + uint32_t XTAL_LP: 1; + uint32_t RESERVED0: 5; + uint32_t PLL_MUX: 1; + uint32_t RESERVED1: 3; + uint32_t SYSCLK_DIV: 3; + uint32_t RESERVED2: 1; + uint32_t CLKFLT_BY: 8; + uint32_t CLKOUT0_SEL: 2; + uint32_t CLKOUT1_SEL: 2; + uint32_t RESERVED3: 4; + }; + uint32_t Word; +} SCU_SCLKEN0_Typedef; + +typedef union +{ + struct + { + uint32_t XTAL_EN: 1; + uint32_t HRC_EN: 1; + uint32_t RESERVED0: 6; + uint32_t PLL_REF_SEL: 3; + uint32_t PLL_48M_SEL: 1; + uint32_t PLL_EN: 1; + uint32_t PLL_BYLOCK: 1; + uint32_t RESERVED1: 2; + uint32_t XTAL_RDY: 1; + uint32_t HRC_RDY: 1; + uint32_t PLL_RDY: 1; + uint32_t RESERVED2: 13; + }; + uint32_t Word; +} SCU_SCLKEN1_Typedef; + +typedef union +{ + struct + { + uint32_t SCU_EN: 1; + uint32_t GPIO_EN: 1; + uint32_t IAP_EN: 1; + uint32_t CRC_EN: 1; + uint32_t ADC_EN: 1; + uint32_t RTC_EN: 1; + uint32_t RESERVED0: 1; + uint32_t IWDT_EN: 1; + uint32_t WWDT_EN: 1; + uint32_t AES_EN: 1; + uint32_t RESERVED1: 22; + }; + uint32_t Word; +} SCU_PCLKEN0_Typedef; + +typedef union +{ + struct + { + uint32_t T16N0_EN: 1; + uint32_t T16N1_EN: 1; + uint32_t T16N2_EN: 1; + uint32_t T16N3_EN: 1; + uint32_t RESERVED0: 4; + uint32_t T32N0_EN: 1; + uint32_t RESERVED1: 7; + uint32_t UART0_EN: 1; + uint32_t UART1_EN: 1; + uint32_t UART2_EN: 1; + uint32_t UART3_EN: 1; + uint32_t UART4_EN: 1; + uint32_t UART5_EN: 1; + uint32_t RESERVED2: 2; + uint32_t SPI0_EN: 1; + uint32_t RESERVED3: 3; + uint32_t I2C0_EN: 1; + uint32_t RESERVED4: 3; + }; + uint32_t Word; +} SCU_PCLKEN1_Typedef; + +typedef union +{ + struct + { + uint32_t RESERVED0: 1; + uint32_t GPIO_RST: 1; + uint32_t IAP_RST: 1; + uint32_t CRC_RST: 1; + uint32_t ADC_RST: 1; + uint32_t RTC_RST: 1; + uint32_t RESERVED1: 1; + uint32_t IWDT_RST: 1; + uint32_t WWDT_RST: 1; + uint32_t AES_RST: 1; + uint32_t RESERVED2: 22; + }; + uint32_t Word; +} SCU_PRSTEN0_Typedef; + +typedef union +{ + struct + { + uint32_t T16N0_RST: 1; + uint32_t T16N1_RST: 1; + uint32_t T16N2_RST: 1; + uint32_t T16N3_RST: 1; + uint32_t RESERVED0: 4; + uint32_t T32N0_RST: 1; + uint32_t RESERVED1: 7; + uint32_t UART0_RST: 1; + uint32_t UART1_RST: 1; + uint32_t UART2_RST: 1; + uint32_t UART3_RST: 1; + uint32_t UART4_RST: 1; + uint32_t UART5_RST: 1; + uint32_t RESERVED2: 2; + uint32_t SPI0_RST: 1; + uint32_t RESERVED3: 3; + uint32_t I2C0_RST: 1; + uint32_t RESERVED4: 3; + }; + uint32_t Word; +} SCU_PRSTEN1_Typedef; + +typedef union +{ + struct + { + uint32_t T16N0EN: 1; + uint32_t T16N1EN: 1; + uint32_t T16N2EN: 1; + uint32_t T16N3EN: 1; + uint32_t RESERVED0: 4; + uint32_t T32N0EN: 1; + uint32_t RESERVED1: 23; + }; + uint32_t Word; +} SCU_TIMEREN_Typedef; + +typedef union +{ + struct + { + uint32_t T16N0DIS: 1; + uint32_t T16N1DIS: 1; + uint32_t T16N2DIS: 1; + uint32_t T16N3DIS: 1; + uint32_t RESERVED0: 4; + uint32_t T32N0DIS: 1; + uint32_t RESERVED1: 23; + }; + uint32_t Word; +} SCU_TIMERDIS_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t RESERVED0: 31; + }; + uint32_t Word; +} SCU_TBLREMAPEN_Typedef; + +typedef union +{ + struct + { + uint32_t TBLOFF: 32; + }; + uint32_t Word; +} SCU_TBLOFF_Typedef; + +typedef struct +{ + __IO SCU_PROT_Typedef PROT; + __IO SCU_NMICON_Typedef NMICON; + __IO SCU_PWRC_Typedef PWRC; + __IO SCU_FAULTFLAG_Typedef FAULTFLAG; + __IO SCU_WAKEUPTIME_Typedef WAKEUPTIME; + __IO SCU_MRSTN_SOFT_Typedef MRSTN_SOFT; + __IO SCU_DBGHALT_Typedef DBGHALT; + uint32_t RESERVED0 ; + __IO SCU_FLASHWAIT_Typedef FLASHWAIT; + __IO SCU_SOFTCFG_Typedef SOFTCFG; + __IO SCU_LVDCON_Typedef LVDCON; + __IO SCU_CCM_Typedef CCM; + __IO SCU_PLLLKCON_Typedef PLLLKCON; + uint32_t RESERVED1[3] ; + __IO SCU_SCLKEN0_Typedef SCLKEN0; + __IO SCU_SCLKEN1_Typedef SCLKEN1; + __IO SCU_PCLKEN0_Typedef PCLKEN0; + __IO SCU_PCLKEN1_Typedef PCLKEN1; + __IO SCU_PRSTEN0_Typedef PRSTEN0; + __IO SCU_PRSTEN1_Typedef PRSTEN1; + __O SCU_TIMEREN_Typedef TIMEREN; + __IO SCU_TIMERDIS_Typedef TIMERDIS; + __IO SCU_TBLREMAPEN_Typedef TBLREMAPEN; + __IO SCU_TBLOFF_Typedef TBLOFF; +} SCU_TypeDef; + +typedef union +{ + struct + { + uint32_t UL: 32; + }; + uint32_t Word; +} CRC_UL_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t RST: 1; + uint32_t HS: 1; + uint32_t DS: 1; + uint32_t REQ: 1; + uint32_t ACK: 1; + uint32_t RESERVED0: 2; + uint32_t MOD: 2; + uint32_t BYTE: 2; + uint32_t REFIN: 1; + uint32_t REFOUT: 1; + uint32_t XOROUT: 1; + uint32_t RESERVED1: 17; + }; + uint32_t Word; +} CRC_CON_Typedef; + +typedef union +{ + struct + { + uint32_t TRIG: 32; + }; + uint32_t Word; +} CRC_TRIG_Typedef; + +typedef union +{ + struct + { + uint32_t ADDR: 17; + uint32_t RESERVED0: 3; + uint32_t IFREN: 1; + uint32_t RESERVED1: 11; + }; + uint32_t Word; +} CRC_ADDR_Typedef; + +typedef union +{ + struct + { + uint32_t CRC_SIZE: 15; + uint32_t RESERVED0: 17; + }; + uint32_t Word; +} CRC_SIZE_Typedef; + +typedef union +{ + struct + { + uint32_t DI: 32; + }; + uint32_t Word; +} CRC_DI_Typedef; + +typedef union +{ + struct + { + uint32_t DO: 32; + }; + uint32_t Word; +} CRC_DO_Typedef; + +typedef union +{ + struct + { + uint32_t BUSY: 1; + uint32_t RSTF: 1; + uint32_t EMPTY_ERR: 1; + uint32_t RESERVED0: 29; + }; + uint32_t Word; +} CRC_STA_Typedef; + +typedef union +{ + struct + { + uint32_t FADR: 15; + uint32_t RESERVED0: 5; + uint32_t IFREN: 1; + uint32_t RESERVED1: 11; + }; + uint32_t Word; +} CRC_FA_Typedef; + +typedef struct +{ + __IO CRC_UL_Typedef UL; + __IO CRC_CON_Typedef CON; + __IO CRC_TRIG_Typedef TRIG; + __IO CRC_ADDR_Typedef ADDR; + __IO CRC_SIZE_Typedef SIZE; + __IO CRC_DI_Typedef DI; + __I CRC_DO_Typedef DO; + __IO CRC_STA_Typedef STA; + __I CRC_FA_Typedef FA; +} CRC_TypeDef; + +typedef union +{ + struct + { + uint32_t PORT_0: 1; + uint32_t PORT_1: 1; + uint32_t PORT_2: 1; + uint32_t PORT_3: 1; + uint32_t PORT_4: 1; + uint32_t PORT_5: 1; + uint32_t PORT_6: 1; + uint32_t PORT_7: 1; + uint32_t PORT_8: 1; + uint32_t PORT_9: 1; + uint32_t PORT_10: 1; + uint32_t PORT_11: 1; + uint32_t PORT_12: 1; + uint32_t PORT_13: 1; + uint32_t PORT_14: 1; + uint32_t PORT_15: 1; + uint32_t PORT_16: 1; + uint32_t PORT_17: 1; + uint32_t PORT_18: 1; + uint32_t PORT_19: 1; + uint32_t PORT_20: 1; + uint32_t PORT_21: 1; + uint32_t PORT_22: 1; + uint32_t PORT_23: 1; + uint32_t PORT_24: 1; + uint32_t PORT_25: 1; + uint32_t PORT_26: 1; + uint32_t PORT_27: 1; + uint32_t PORT_28: 1; + uint32_t PORT_29: 1; + uint32_t PORT_30: 1; + uint32_t PORT_31: 1; + }; + uint32_t Word; +} GPIO_PAPORT_Typedef; + +typedef union +{ + struct + { + uint32_t DATA_0: 1; + uint32_t DATA_1: 1; + uint32_t DATA_2: 1; + uint32_t DATA_3: 1; + uint32_t DATA_4: 1; + uint32_t DATA_5: 1; + uint32_t DATA_6: 1; + uint32_t DATA_7: 1; + uint32_t DATA_8: 1; + uint32_t DATA_9: 1; + uint32_t DATA_10: 1; + uint32_t DATA_11: 1; + uint32_t DATA_12: 1; + uint32_t DATA_13: 1; + uint32_t DATA_14: 1; + uint32_t DATA_15: 1; + uint32_t DATA_16: 1; + uint32_t DATA_17: 1; + uint32_t DATA_18: 1; + uint32_t DATA_19: 1; + uint32_t DATA_20: 1; + uint32_t DATA_21: 1; + uint32_t DATA_22: 1; + uint32_t DATA_23: 1; + uint32_t DATA_24: 1; + uint32_t DATA_25: 1; + uint32_t DATA_26: 1; + uint32_t DATA_27: 1; + uint32_t DATA_28: 1; + uint32_t DATA_29: 1; + uint32_t DATA_30: 1; + uint32_t DATA_31: 1; + }; + uint32_t Word; +} GPIO_PADATA_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PADATABSR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PADATABCR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PADATABRR_Typedef; + +typedef union +{ + struct + { + uint32_t DIR_0: 1; + uint32_t DIR_1: 1; + uint32_t DIR_2: 1; + uint32_t DIR_3: 1; + uint32_t DIR_4: 1; + uint32_t DIR_5: 1; + uint32_t DIR_6: 1; + uint32_t DIR_7: 1; + uint32_t DIR_8: 1; + uint32_t DIR_9: 1; + uint32_t DIR_10: 1; + uint32_t DIR_11: 1; + uint32_t DIR_12: 1; + uint32_t DIR_13: 1; + uint32_t DIR_14: 1; + uint32_t DIR_15: 1; + uint32_t DIR_16: 1; + uint32_t DIR_17: 1; + uint32_t DIR_18: 1; + uint32_t DIR_19: 1; + uint32_t DIR_20: 1; + uint32_t DIR_21: 1; + uint32_t DIR_22: 1; + uint32_t DIR_23: 1; + uint32_t DIR_24: 1; + uint32_t DIR_25: 1; + uint32_t DIR_26: 1; + uint32_t DIR_27: 1; + uint32_t DIR_28: 1; + uint32_t DIR_29: 1; + uint32_t DIR_30: 1; + uint32_t DIR_31: 1; + }; + uint32_t Word; +} GPIO_PADIR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PADIRBSR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PADIRBCR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PADIRBRR_Typedef; + +typedef union +{ + struct + { + uint32_t PA0: 2; + uint32_t RESERVED0: 2; + uint32_t PA1: 2; + uint32_t RESERVED1: 2; + uint32_t PA2: 2; + uint32_t RESERVED2: 2; + uint32_t PA3: 2; + uint32_t RESERVED3: 2; + uint32_t PA4: 2; + uint32_t RESERVED4: 2; + uint32_t PA5: 2; + uint32_t RESERVED5: 2; + uint32_t PA6: 2; + uint32_t RESERVED6: 2; + uint32_t PA7: 2; + uint32_t RESERVED7: 2; + }; + uint32_t Word; +} GPIO_PAFUNC0_Typedef; + +typedef union +{ + struct + { + uint32_t PA8: 2; + uint32_t RESERVED0: 2; + uint32_t PA9: 2; + uint32_t RESERVED1: 2; + uint32_t PA10: 2; + uint32_t RESERVED2: 2; + uint32_t PA11: 2; + uint32_t RESERVED3: 2; + uint32_t PA12: 2; + uint32_t RESERVED4: 2; + uint32_t PA13: 2; + uint32_t RESERVED5: 2; + uint32_t PA14: 2; + uint32_t RESERVED6: 2; + uint32_t PA15: 2; + uint32_t RESERVED7: 2; + }; + uint32_t Word; +} GPIO_PAFUNC1_Typedef; + +typedef union +{ + struct + { + uint32_t PA16: 2; + uint32_t RESERVED0: 2; + uint32_t PA17: 2; + uint32_t RESERVED1: 2; + uint32_t PA18: 2; + uint32_t RESERVED2: 2; + uint32_t PA19: 2; + uint32_t RESERVED3: 2; + uint32_t PA20: 2; + uint32_t RESERVED4: 2; + uint32_t PA21: 2; + uint32_t RESERVED5: 2; + uint32_t PA22: 2; + uint32_t RESERVED6: 2; + uint32_t PA23: 2; + uint32_t RESERVED7: 2; + }; + uint32_t Word; +} GPIO_PAFUNC2_Typedef; + +typedef union +{ + struct + { + uint32_t PA24: 2; + uint32_t RESERVED0: 2; + uint32_t PA25: 2; + uint32_t RESERVED1: 2; + uint32_t PA26: 2; + uint32_t RESERVED2: 2; + uint32_t PA27: 2; + uint32_t RESERVED3: 2; + uint32_t PA28: 2; + uint32_t RESERVED4: 2; + uint32_t PA29: 2; + uint32_t RESERVED5: 2; + uint32_t PA30: 2; + uint32_t RESERVED6: 2; + uint32_t PA31: 2; + uint32_t RESERVED7: 2; + }; + uint32_t Word; +} GPIO_PAFUNC3_Typedef; + +typedef union +{ + struct + { + uint32_t INEB_0: 1; + uint32_t INEB_1: 1; + uint32_t INEB_2: 1; + uint32_t INEB_3: 1; + uint32_t INEB_4: 1; + uint32_t INEB_5: 1; + uint32_t INEB_6: 1; + uint32_t INEB_7: 1; + uint32_t INEB_8: 1; + uint32_t INEB_9: 1; + uint32_t INEB_10: 1; + uint32_t INEB_11: 1; + uint32_t INEB_12: 1; + uint32_t INEB_13: 1; + uint32_t INEB_14: 1; + uint32_t INEB_15: 1; + uint32_t INEB_16: 1; + uint32_t INEB_17: 1; + uint32_t INEB_18: 1; + uint32_t INEB_19: 1; + uint32_t INEB_20: 1; + uint32_t INEB_21: 1; + uint32_t INEB_22: 1; + uint32_t INEB_23: 1; + uint32_t INEB_24: 1; + uint32_t INEB_25: 1; + uint32_t INEB_26: 1; + uint32_t INEB_27: 1; + uint32_t INEB_28: 1; + uint32_t INEB_29: 1; + uint32_t INEB_30: 1; + uint32_t INEB_31: 1; + }; + uint32_t Word; +} GPIO_PAINEB_Typedef; + +typedef union +{ + struct + { + uint32_t ODE_0: 1; + uint32_t ODE_1: 1; + uint32_t ODE_2: 1; + uint32_t ODE_3: 1; + uint32_t ODE_4: 1; + uint32_t ODE_5: 1; + uint32_t ODE_6: 1; + uint32_t ODE_7: 1; + uint32_t ODE_8: 1; + uint32_t ODE_9: 1; + uint32_t ODE_10: 1; + uint32_t ODE_11: 1; + uint32_t ODE_12: 1; + uint32_t ODE_13: 1; + uint32_t ODE_14: 1; + uint32_t ODE_15: 1; + uint32_t ODE_16: 1; + uint32_t ODE_17: 1; + uint32_t ODE_18: 1; + uint32_t ODE_19: 1; + uint32_t ODE_20: 1; + uint32_t ODE_21: 1; + uint32_t ODE_22: 1; + uint32_t ODE_23: 1; + uint32_t ODE_24: 1; + uint32_t ODE_25: 1; + uint32_t ODE_26: 1; + uint32_t ODE_27: 1; + uint32_t ODE_28: 1; + uint32_t ODE_29: 1; + uint32_t ODE_30: 1; + uint32_t ODE_31: 1; + }; + uint32_t Word; +} GPIO_PAODE_Typedef; + +typedef union +{ + struct + { + uint32_t PUE_0: 1; + uint32_t PUE_1: 1; + uint32_t PUE_2: 1; + uint32_t PUE_3: 1; + uint32_t PUE_4: 1; + uint32_t PUE_5: 1; + uint32_t PUE_6: 1; + uint32_t PUE_7: 1; + uint32_t PUE_8: 1; + uint32_t PUE_9: 1; + uint32_t PUE_10: 1; + uint32_t PUE_11: 1; + uint32_t PUE_12: 1; + uint32_t PUE_13: 1; + uint32_t PUE_14: 1; + uint32_t PUE_15: 1; + uint32_t PUE_16: 1; + uint32_t PUE_17: 1; + uint32_t PUE_18: 1; + uint32_t PUE_19: 1; + uint32_t PUE_20: 1; + uint32_t PUE_21: 1; + uint32_t PUE_22: 1; + uint32_t PUE_23: 1; + uint32_t PUE_24: 1; + uint32_t PUE_25: 1; + uint32_t PUE_26: 1; + uint32_t PUE_27: 1; + uint32_t PUE_28: 1; + uint32_t PUE_29: 1; + uint32_t PUE_30: 1; + uint32_t PUE_31: 1; + }; + uint32_t Word; +} GPIO_PAPUE_Typedef; + +typedef union +{ + struct + { + uint32_t PDE_0: 1; + uint32_t PDE_1: 1; + uint32_t PDE_2: 1; + uint32_t PDE_3: 1; + uint32_t PDE_4: 1; + uint32_t PDE_5: 1; + uint32_t PDE_6: 1; + uint32_t PDE_7: 1; + uint32_t PDE_8: 1; + uint32_t PDE_9: 1; + uint32_t PDE_10: 1; + uint32_t PDE_11: 1; + uint32_t PDE_12: 1; + uint32_t PDE_13: 1; + uint32_t PDE_14: 1; + uint32_t PDE_15: 1; + uint32_t PDE_16: 1; + uint32_t PDE_17: 1; + uint32_t PDE_18: 1; + uint32_t PDE_19: 1; + uint32_t PDE_20: 1; + uint32_t PDE_21: 1; + uint32_t PDE_22: 1; + uint32_t PDE_23: 1; + uint32_t PDE_24: 1; + uint32_t PDE_25: 1; + uint32_t PDE_26: 1; + uint32_t PDE_27: 1; + uint32_t PDE_28: 1; + uint32_t PDE_29: 1; + uint32_t PDE_30: 1; + uint32_t PDE_31: 1; + }; + uint32_t Word; +} GPIO_PAPDE_Typedef; + +typedef union +{ + struct + { + uint32_t DS_0: 1; + uint32_t DS_1: 1; + uint32_t DS_2: 1; + uint32_t DS_3: 1; + uint32_t DS_4: 1; + uint32_t DS_5: 1; + uint32_t DS_6: 1; + uint32_t DS_7: 1; + uint32_t DS_8: 1; + uint32_t DS_9: 1; + uint32_t DS_10: 1; + uint32_t DS_11: 1; + uint32_t DS_12: 1; + uint32_t DS_13: 1; + uint32_t DS_14: 1; + uint32_t DS_15: 1; + uint32_t DS_16: 1; + uint32_t DS_17: 1; + uint32_t DS_18: 1; + uint32_t DS_19: 1; + uint32_t DS_20: 1; + uint32_t DS_21: 1; + uint32_t DS_22: 1; + uint32_t DS_23: 1; + uint32_t DS_24: 1; + uint32_t DS_25: 1; + uint32_t DS_26: 1; + uint32_t DS_27: 1; + uint32_t DS_28: 1; + uint32_t DS_29: 1; + uint32_t DS_30: 1; + uint32_t DS_31: 1; + }; + uint32_t Word; +} GPIO_PADS_Typedef; + +typedef union +{ + struct + { + uint32_t PORT_0: 1; + uint32_t PORT_1: 1; + uint32_t PORT_2: 1; + uint32_t PORT_3: 1; + uint32_t PORT_4: 1; + uint32_t PORT_5: 1; + uint32_t PORT_6: 1; + uint32_t PORT_7: 1; + uint32_t PORT_8: 1; + uint32_t PORT_9: 1; + uint32_t PORT_10: 1; + uint32_t PORT_11: 1; + uint32_t PORT_12: 1; + uint32_t PORT_13: 1; + uint32_t RESERVED0: 18; + }; + uint32_t Word; +} GPIO_PBPORT_Typedef; + +typedef union +{ + struct + { + uint32_t DATA_0: 1; + uint32_t DATA_1: 1; + uint32_t DATA_2: 1; + uint32_t DATA_3: 1; + uint32_t DATA_4: 1; + uint32_t DATA_5: 1; + uint32_t DATA_6: 1; + uint32_t DATA_7: 1; + uint32_t DATA_8: 1; + uint32_t DATA_9: 1; + uint32_t DATA_10: 1; + uint32_t DATA_11: 1; + uint32_t DATA_12: 1; + uint32_t DATA_13: 1; + uint32_t RESERVED0: 18; + }; + uint32_t Word; +} GPIO_PBDATA_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PBDATABSR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PBDATABCR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PBDATABRR_Typedef; + +typedef union +{ + struct + { + uint32_t DIR_0: 1; + uint32_t DIR_1: 1; + uint32_t DIR_2: 1; + uint32_t DIR_3: 1; + uint32_t DIR_4: 1; + uint32_t DIR_5: 1; + uint32_t DIR_6: 1; + uint32_t DIR_7: 1; + uint32_t DIR_8: 1; + uint32_t DIR_9: 1; + uint32_t DIR_10: 1; + uint32_t DIR_11: 1; + uint32_t DIR_12: 1; + uint32_t DIR_13: 1; + uint32_t RESERVED0: 18; + }; + uint32_t Word; +} GPIO_PBDIR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PBDIRBSR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PBDIRBCR_Typedef; + +typedef union +{ + uint32_t Word; +} GPIO_PBDIRBRR_Typedef; + +typedef union +{ + struct + { + uint32_t PB0: 2; + uint32_t RESERVED0: 2; + uint32_t PB1: 2; + uint32_t RESERVED1: 2; + uint32_t PB2: 2; + uint32_t RESERVED2: 2; + uint32_t PB3: 2; + uint32_t RESERVED3: 2; + uint32_t PB4: 2; + uint32_t RESERVED4: 2; + uint32_t PB5: 2; + uint32_t RESERVED5: 2; + uint32_t PB6: 2; + uint32_t RESERVED6: 2; + uint32_t PB7: 2; + uint32_t RESERVED7: 2; + }; + uint32_t Word; +} GPIO_PBFUNC0_Typedef; + +typedef union +{ + struct + { + uint32_t PB8: 2; + uint32_t RESERVED0: 2; + uint32_t PB9: 2; + uint32_t RESERVED1: 2; + uint32_t PB10: 2; + uint32_t RESERVED2: 2; + uint32_t PB11: 2; + uint32_t RESERVED3: 2; + uint32_t PB12: 2; + uint32_t RESERVED4: 2; + uint32_t PB13: 2; + uint32_t RESERVED5: 10; + }; + uint32_t Word; +} GPIO_PBFUNC1_Typedef; + +typedef union +{ + struct + { + uint32_t INEB_0: 1; + uint32_t INEB_1: 1; + uint32_t INEB_2: 1; + uint32_t INEB_3: 1; + uint32_t INEB_4: 1; + uint32_t INEB_5: 1; + uint32_t INEB_6: 1; + uint32_t INEB_7: 1; + uint32_t INEB_8: 1; + uint32_t INEB_9: 1; + uint32_t INEB_10: 1; + uint32_t INEB_11: 1; + uint32_t INEB_12: 1; + uint32_t INEB_13: 1; + uint32_t RESERVED0: 18; + }; + uint32_t Word; +} GPIO_PBINEB_Typedef; + +typedef union +{ + struct + { + uint32_t ODE_0: 1; + uint32_t ODE_1: 1; + uint32_t ODE_2: 1; + uint32_t ODE_3: 1; + uint32_t ODE_4: 1; + uint32_t ODE_5: 1; + uint32_t ODE_6: 1; + uint32_t ODE_7: 1; + uint32_t ODE_8: 1; + uint32_t ODE_9: 1; + uint32_t ODE_10: 1; + uint32_t ODE_11: 1; + uint32_t ODE_12: 1; + uint32_t ODE_13: 1; + uint32_t RESERVED0: 18; + }; + uint32_t Word; +} GPIO_PBODE_Typedef; + +typedef union +{ + struct + { + uint32_t PUEN_0: 1; + uint32_t PUEN_1: 1; + uint32_t PUEN_2: 1; + uint32_t PUEN_3: 1; + uint32_t PUEN_4: 1; + uint32_t PUEN_5: 1; + uint32_t PUEN_6: 1; + uint32_t PUEN_7: 1; + uint32_t PUEN_8: 1; + uint32_t PUEN_9: 1; + uint32_t PUEN_10: 1; + uint32_t PUEN_11: 1; + uint32_t PUEN_12: 1; + uint32_t PUEN_13: 1; + uint32_t RESERVED0: 18; + }; + uint32_t Word; +} GPIO_PBPUE_Typedef; + +typedef union +{ + struct + { + uint32_t PDEN_0: 1; + uint32_t PDEN_1: 1; + uint32_t PDEN_2: 1; + uint32_t PDEN_3: 1; + uint32_t PDEN_4: 1; + uint32_t PDEN_5: 1; + uint32_t PDEN_6: 1; + uint32_t PDEN_7: 1; + uint32_t PDEN_8: 1; + uint32_t PDEN_9: 1; + uint32_t PDEN_10: 1; + uint32_t PDEN_11: 1; + uint32_t PDEN_12: 1; + uint32_t PDEN_13: 1; + uint32_t RESERVED0: 18; + }; + uint32_t Word; +} GPIO_PBPDE_Typedef; + +typedef union +{ + struct + { + uint32_t DS_0: 1; + uint32_t DS_1: 1; + uint32_t DS_2: 1; + uint32_t DS_3: 1; + uint32_t DS_4: 1; + uint32_t DS_5: 1; + uint32_t DS_6: 1; + uint32_t DS_7: 1; + uint32_t DS_8: 1; + uint32_t DS_9: 1; + uint32_t DS_10: 1; + uint32_t DS_11: 1; + uint32_t DS_12: 1; + uint32_t DS_13: 1; + uint32_t RESERVED0: 18; + }; + uint32_t Word; +} GPIO_PBDS_Typedef; + +typedef union +{ + struct + { + uint32_t PINTIE: 8; + uint32_t PMASK: 8; + uint32_t RESERVED0: 16; + }; + uint32_t Word; +} GPIO_PINTIE_Typedef; + +typedef union +{ + struct + { + uint32_t PINTIF_0: 1; + uint32_t PINTIF_1: 1; + uint32_t PINTIF_2: 1; + uint32_t PINTIF_3: 1; + uint32_t PINTIF_4: 1; + uint32_t PINTIF_5: 1; + uint32_t PINTIF_6: 1; + uint32_t PINTIF_7: 1; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} GPIO_PINTIF_Typedef; + +typedef union +{ + struct + { + uint32_t PINT0SEL: 3; + uint32_t RESERVED0: 1; + uint32_t PINT1SEL: 3; + uint32_t RESERVED1: 1; + uint32_t PINT2SEL: 3; + uint32_t RESERVED2: 1; + uint32_t PINT3SEL: 3; + uint32_t RESERVED3: 1; + uint32_t PINT4SEL: 3; + uint32_t RESERVED4: 1; + uint32_t PINT5SEL: 3; + uint32_t RESERVED5: 1; + uint32_t PINT6SEL: 3; + uint32_t RESERVED6: 1; + uint32_t PINT7SEL: 3; + uint32_t RESERVED7: 1; + }; + uint32_t Word; +} GPIO_PINTSEL_Typedef; + +typedef union +{ + struct + { + uint32_t PINT0CFG: 3; + uint32_t RESERVED0: 1; + uint32_t PINT1CFG: 3; + uint32_t RESERVED1: 1; + uint32_t PINT2CFG: 3; + uint32_t RESERVED2: 1; + uint32_t PINT3CFG: 3; + uint32_t RESERVED3: 1; + uint32_t PINT4CFG: 3; + uint32_t RESERVED4: 1; + uint32_t PINT5CFG: 3; + uint32_t RESERVED5: 1; + uint32_t PINT6CFG: 3; + uint32_t RESERVED6: 1; + uint32_t PINT7CFG: 3; + uint32_t RESERVED7: 1; + }; + uint32_t Word; +} GPIO_PINTCFG_Typedef; + +typedef union +{ + struct + { + uint32_t KINTIE: 8; + uint32_t KMASK: 8; + uint32_t RESERVED0: 16; + }; + uint32_t Word; +} GPIO_KINTIE_Typedef; + +typedef union +{ + struct + { + uint32_t KINTIF_0: 1; + uint32_t KINTIF_1: 1; + uint32_t KINTIF_2: 1; + uint32_t KINTIF_3: 1; + uint32_t KINTIF_4: 1; + uint32_t KINTIF_5: 1; + uint32_t KINTIF_6: 1; + uint32_t KINTIF_7: 1; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} GPIO_KINTIF_Typedef; + +typedef union +{ + struct + { + uint32_t KINT0SEL: 3; + uint32_t RESERVED0: 1; + uint32_t KINT1SEL: 3; + uint32_t RESERVED1: 1; + uint32_t KINT2SEL: 3; + uint32_t RESERVED2: 1; + uint32_t KINT3SEL: 3; + uint32_t RESERVED3: 1; + uint32_t KINT4SEL: 3; + uint32_t RESERVED4: 1; + uint32_t KINT5SEL: 3; + uint32_t RESERVED5: 1; + uint32_t KINT6SEL: 3; + uint32_t RESERVED6: 1; + uint32_t KINT7SEL: 3; + uint32_t RESERVED7: 1; + }; + uint32_t Word; +} GPIO_KINTSEL_Typedef; + +typedef union +{ + struct + { + uint32_t KINT0CFG: 3; + uint32_t RESERVED0: 1; + uint32_t KINT1CFG: 3; + uint32_t RESERVED1: 1; + uint32_t KINT2CFG: 3; + uint32_t RESERVED2: 1; + uint32_t KINT3CFG: 3; + uint32_t RESERVED3: 1; + uint32_t KINT4CFG: 3; + uint32_t RESERVED4: 1; + uint32_t KINT5CFG: 3; + uint32_t RESERVED5: 1; + uint32_t KINT6CFG: 3; + uint32_t RESERVED6: 1; + uint32_t KINT7CFG: 3; + uint32_t RESERVED7: 1; + }; + uint32_t Word; +} GPIO_KINTCFG_Typedef; + +typedef union +{ + struct + { + uint32_t FLT_S_0: 1; + uint32_t FLT_S_1: 1; + uint32_t FLT_S_2: 1; + uint32_t FLT_S_3: 1; + uint32_t FLT_S_4: 1; + uint32_t FLT_S_5: 1; + uint32_t FLT_S_6: 1; + uint32_t FLT_S_7: 1; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} GPIO_IOINTFLTS_Typedef; + +typedef union +{ + struct + { + uint32_t FLT0_SEL: 4; + uint32_t FLT1_SEL: 4; + uint32_t FLT2_SEL: 4; + uint32_t FLT3_SEL: 4; + uint32_t RESERVED0: 16; + }; + uint32_t Word; +} GPIO_TMRFLTSEL_Typedef; + +typedef union +{ + struct + { + uint32_t TX0PS: 2; + uint32_t RESERVED0: 2; + uint32_t TX0PLV: 1; + uint32_t TX0_S: 2; + uint32_t RESERVED1: 1; + uint32_t TX1PS: 2; + uint32_t RESERVED2: 2; + uint32_t TX1PLV: 1; + uint32_t TX1_S: 2; + uint32_t RESERVED3: 1; + uint32_t TX2PS: 2; + uint32_t RESERVED4: 2; + uint32_t TX2PLV: 1; + uint32_t TX2_S: 2; + uint32_t RESERVED5: 1; + uint32_t TX3PS: 2; + uint32_t RESERVED6: 2; + uint32_t TX3PLV: 1; + uint32_t TX3_S: 2; + uint32_t RESERVED7: 1; + }; + uint32_t Word; +} GPIO_TXPWM_Typedef; + +typedef union +{ + struct + { + uint32_t BUZEN: 1; + uint32_t RESERVED0: 7; + uint32_t BUZ_LOAD: 20; + uint32_t RESERVED1: 4; + }; + uint32_t Word; +} GPIO_BUZC_Typedef; + +typedef struct +{ + __I GPIO_PAPORT_Typedef PAPORT; + uint32_t RESERVED0[3] ; + __IO GPIO_PADATA_Typedef PADATA; + __O GPIO_PADATABSR_Typedef PADATABSR; + __O GPIO_PADATABCR_Typedef PADATABCR; + __O GPIO_PADATABRR_Typedef PADATABRR; + __IO GPIO_PADIR_Typedef PADIR; + __O GPIO_PADIRBSR_Typedef PADIRBSR; + __O GPIO_PADIRBCR_Typedef PADIRBCR; + __O GPIO_PADIRBRR_Typedef PADIRBRR; + __IO GPIO_PAFUNC0_Typedef PAFUNC0; + __IO GPIO_PAFUNC1_Typedef PAFUNC1; + __IO GPIO_PAFUNC2_Typedef PAFUNC2; + __IO GPIO_PAFUNC3_Typedef PAFUNC3; + __IO GPIO_PAINEB_Typedef PAINEB; + __IO GPIO_PAODE_Typedef PAODE; + __IO GPIO_PAPUE_Typedef PAPUE; + __IO GPIO_PAPDE_Typedef PAPDE; + __IO GPIO_PADS_Typedef PADS; + uint32_t RESERVED1[11] ; + __I GPIO_PBPORT_Typedef PBPORT; + uint32_t RESERVED2[3] ; + __IO GPIO_PBDATA_Typedef PBDATA; + __O GPIO_PBDATABSR_Typedef PBDATABSR; + __O GPIO_PBDATABCR_Typedef PBDATABCR; + __O GPIO_PBDATABRR_Typedef PBDATABRR; + __IO GPIO_PBDIR_Typedef PBDIR; + __O GPIO_PBDIRBSR_Typedef PBDIRBSR; + __O GPIO_PBDIRBCR_Typedef PBDIRBCR; + __O GPIO_PBDIRBRR_Typedef PBDIRBRR; + __IO GPIO_PBFUNC0_Typedef PBFUNC0; + __IO GPIO_PBFUNC1_Typedef PBFUNC1; + uint32_t RESERVED3[2] ; + __IO GPIO_PBINEB_Typedef PBINEB; + __IO GPIO_PBODE_Typedef PBODE; + __IO GPIO_PBPUE_Typedef PBPUE; + __IO GPIO_PBPDE_Typedef PBPDE; + __IO GPIO_PBDS_Typedef PBDS; + uint32_t RESERVED4[139] ; + __IO GPIO_PINTIE_Typedef PINTIE; + __IO GPIO_PINTIF_Typedef PINTIF; + __IO GPIO_PINTSEL_Typedef PINTSEL; + __IO GPIO_PINTCFG_Typedef PINTCFG; + __IO GPIO_KINTIE_Typedef KINTIE; + __IO GPIO_KINTIF_Typedef KINTIF; + __IO GPIO_KINTSEL_Typedef KINTSEL; + __IO GPIO_KINTCFG_Typedef KINTCFG; + uint32_t RESERVED5[4] ; + __IO GPIO_IOINTFLTS_Typedef IOINTFLTS; + uint32_t RESERVED6[3] ; + __IO GPIO_TMRFLTSEL_Typedef TMRFLTSEL; + uint32_t RESERVED7[15] ; + __IO GPIO_TXPWM_Typedef TXPWM; + uint32_t RESERVED8[3] ; + __IO GPIO_BUZC_Typedef BUZC; +} GPIO_TypeDef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t RST: 1; + uint32_t RESERVED0: 2; + uint32_t FLASH_REQ: 1; + uint32_t FLASH_ACK: 1; + uint32_t RESERVED1: 1; + uint32_t FLASH_FAIL: 1; + uint32_t FEWE: 1; + uint32_t SEWE: 1; + uint32_t RESERVED2: 22; + }; + uint32_t Word; +} IAP_CON_Typedef; + +typedef union +{ + struct + { + uint32_t RESERVED0: 2; + uint32_t IAPCA: 8; + uint32_t IAPPA: 7; + uint32_t RESERVED1: 3; + uint32_t IFREN: 1; + uint32_t RESERVED2: 11; + }; + uint32_t Word; +} IAP_ADDR_Typedef; + +typedef union +{ + struct + { + uint32_t DATA: 32; + }; + uint32_t Word; +} IAP_DATA_Typedef; + +typedef union +{ + struct + { + uint32_t TRIG: 32; + }; + uint32_t Word; +} IAP_TRIG_Typedef; + +typedef union +{ + struct + { + uint32_t UL: 32; + }; + uint32_t Word; +} IAP_UL_Typedef; + +typedef union +{ + struct + { + uint32_t BSY: 1; + uint32_t PERASE_END: 1; + uint32_t PROG_END: 1; + uint32_t TIMEOUT_ERR: 1; + uint32_t OP_ERR: 1; + uint32_t MERASE_END: 1; + uint32_t UERASE_END: 1; + uint32_t RESERVED0: 25; + }; + uint32_t Word; +} IAP_STA_Typedef; + +typedef union +{ + struct + { + uint32_t IAP_WPROT: 32; + }; + uint32_t Word; +} IAP_WPROT0_Typedef; + +typedef union +{ + struct + { + uint32_t IAP_WPROT: 32; + }; + uint32_t Word; +} IAP_WPROT1_Typedef; + +typedef union +{ + struct + { + uint32_t IAP_WPROT: 1; + uint32_t RESERVED0: 31; + }; + uint32_t Word; +} IAP_WPROT2_Typedef; + +typedef struct +{ + __IO IAP_CON_Typedef CON; + __IO IAP_ADDR_Typedef ADDR; + __IO IAP_DATA_Typedef DATA; + __IO IAP_TRIG_Typedef TRIG; + __IO IAP_UL_Typedef UL; + __IO IAP_STA_Typedef STA; + __IO IAP_WPROT0_Typedef WPROT0; + __IO IAP_WPROT1_Typedef WPROT1; + __IO IAP_WPROT2_Typedef WPROT2; +} IAP_TypeDef; + +typedef union +{ + struct + { + uint32_t DR: 12; + uint32_t RESERVED0: 20; + }; + uint32_t Word; +} ADC_DR_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t TRIG: 1; + uint32_t ACP_EN: 1; + uint32_t RESERVED0: 1; + uint32_t BIT_SEL: 2; + uint32_t RESERVED1: 26; + }; + uint32_t Word; +} ADC_CON0_Typedef; + +typedef union +{ + struct + { + uint32_t CLKDIV: 3; + uint32_t RESERVED0: 1; + uint32_t CLKS: 2; + uint32_t RESERVED1: 2; + uint32_t VREFP: 2; + uint32_t VREFN: 1; + uint32_t VRBUF_EN: 1; + uint32_t SMPS: 1; + uint32_t SMPON: 1; + uint32_t HSEN: 1; + uint32_t RESERVED2: 1; + uint32_t ST: 5; + uint32_t RESERVED3: 3; + uint32_t VCMBUF_EN: 1; + uint32_t VCMBUF_HS: 1; + uint32_t RESERVED4: 6; + }; + uint32_t Word; +} ADC_CON1_Typedef; + +typedef union +{ + struct + { + uint32_t CHS: 5; + uint32_t RESERVED0: 3; + uint32_t VDD5_FLAG_EN: 1; + uint32_t RESERVED1: 23; + }; + uint32_t Word; +} ADC_CHS_Typedef; + +typedef union +{ + struct + { + uint32_t IE: 1; + uint32_t ACPMINIE: 1; + uint32_t ACPMAXIE: 1; + uint32_t ACPOVIE: 1; + uint32_t RESERVED0: 28; + }; + uint32_t Word; +} ADC_IE_Typedef; + +typedef union +{ + struct + { + uint32_t IF: 1; + uint32_t ACPMINIF: 1; + uint32_t ACPMAXIF: 1; + uint32_t ACPOVIF: 1; + uint32_t RESERVED0: 28; + }; + uint32_t Word; +} ADC_IF_Typedef; + +typedef union +{ + struct + { + uint32_t OVFL_TIME: 12; + uint32_t RESERVED0: 4; + uint32_t TIMES: 2; + uint32_t RESERVED1: 2; + uint32_t CLKS: 1; + uint32_t RESERVED2: 11; + }; + uint32_t Word; +} ADC_ACPC_Typedef; + +typedef union +{ + struct + { + uint32_t CMP_MIN: 12; + uint32_t RESERVED0: 4; + uint32_t CMP_MAX: 12; + uint32_t RESERVED1: 4; + }; + uint32_t Word; +} ADC_ACPCMP_Typedef; + +typedef union +{ + struct + { + uint32_t MEAN_DATA: 12; + uint32_t RESERVED0: 20; + }; + uint32_t Word; +} ADC_ACPMEAN_Typedef; + +typedef union +{ + struct + { + uint32_t VREF_EN: 1; + uint32_t RESERVED2: 1; + uint32_t IREF_EN: 1; + uint32_t RESERVED0: 1; + uint32_t VDET_EN: 1; + uint32_t VDET_SEL: 1; + uint32_t RESERVED1: 26; + }; + uint32_t Word; +} ADC_VREFCON_Typedef; + +typedef struct +{ + __I ADC_DR_Typedef DR; + __IO ADC_CON0_Typedef CON0; + __IO ADC_CON1_Typedef CON1; + __IO ADC_CHS_Typedef CHS; + __IO ADC_IE_Typedef IE; + __IO ADC_IF_Typedef IF; + uint32_t RESERVED0[4] ; + __IO ADC_ACPC_Typedef ACPC; + uint32_t RESERVED1 ; + __IO ADC_ACPCMP_Typedef ACPCMP; + __I ADC_ACPMEAN_Typedef ACPMEAN; + uint32_t RESERVED2[2] ; + __IO ADC_VREFCON_Typedef VREFCON; +} ADC_TypeDef; + +typedef union +{ + struct + { + uint32_t TMUP: 1; + uint32_t TMWR: 1; + uint32_t HSWI: 1; + uint32_t RESERVED0: 1; + uint32_t CLKS: 2; + uint32_t XST: 1; + uint32_t PON: 1; + uint32_t RESERVED1: 24; + }; + uint32_t Word; +} RTC_CON_Typedef; + +typedef union +{ + struct + { + uint32_t CALF: 8; + uint32_t DEV: 1; + uint32_t COCR: 3; + uint32_t CLKC: 1; + uint32_t RESERVED0: 19; + }; + uint32_t Word; +} RTC_CAL_Typedef; + +typedef union +{ + struct + { + uint32_t WM: 7; + uint32_t RESERVED0: 1; + uint32_t WH: 6; + uint32_t RESERVED1: 2; + uint32_t WW: 7; + uint32_t RESERVED2: 9; + }; + uint32_t Word; +} RTC_WA_Typedef; + +typedef union +{ + struct + { + uint32_t DM: 7; + uint32_t RESERVED0: 1; + uint32_t DH: 6; + uint32_t RESERVED1: 18; + }; + uint32_t Word; +} RTC_DA_Typedef; + +typedef union +{ + struct + { + uint32_t SEC: 7; + uint32_t RESERVED0: 1; + uint32_t MIN: 7; + uint32_t RESERVED1: 1; + uint32_t HOUR: 6; + uint32_t RESERVED2: 10; + }; + uint32_t Word; +} RTC_HMS_Typedef; + +typedef union +{ + struct + { + uint32_t WEEK: 7; + uint32_t RESERVED0: 1; + uint32_t DAY: 6; + uint32_t RESERVED1: 2; + uint32_t MON: 5; + uint32_t RESERVED2: 3; + uint32_t YEAR: 8; + }; + uint32_t Word; +} RTC_YMDW_Typedef; + +typedef union +{ + struct + { + uint32_t SCDIE: 1; + uint32_t MINIE: 1; + uint32_t HORIE: 1; + uint32_t DAYIE: 1; + uint32_t MONIE: 1; + uint32_t RESERVED0: 3; + uint32_t DALE: 1; + uint32_t WALE: 1; + uint32_t RESERVED1: 22; + }; + uint32_t Word; +} RTC_IE_Typedef; + +typedef union +{ + struct + { + uint32_t SCDIF: 1; + uint32_t MINIF: 1; + uint32_t HORIF: 1; + uint32_t DAYIF: 1; + uint32_t MONIF: 1; + uint32_t RESERVED0: 3; + uint32_t DAFG: 1; + uint32_t WAFG: 1; + uint32_t RESERVED1: 22; + }; + uint32_t Word; +} RTC_IF_Typedef; + +typedef union +{ + struct + { + uint32_t WP: 32; + }; + uint32_t Word; +} RTC_WP_Typedef; + +typedef struct +{ + __IO RTC_CON_Typedef CON; + __IO RTC_CAL_Typedef CAL; + __IO RTC_WA_Typedef WA; + __IO RTC_DA_Typedef DA; + __IO RTC_HMS_Typedef HMS; + __IO RTC_YMDW_Typedef YMDW; + __IO RTC_IE_Typedef IE; + __IO RTC_IF_Typedef IF; + __IO RTC_WP_Typedef WP; +} RTC_TypeDef; + +typedef union +{ + struct + { + uint32_t LOAD: 32; + }; + uint32_t Word; +} IWDT_LOAD_Typedef; + +typedef union +{ + struct + { + uint32_t VALUE: 32; + }; + uint32_t Word; +} IWDT_VALUE_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t IE: 1; + uint32_t RSTEN: 1; + uint32_t CLKS: 1; + uint32_t RESERVED0: 28; + }; + uint32_t Word; +} IWDT_CON_Typedef; + +typedef union +{ + struct + { + uint32_t INTCLR: 32; + }; + uint32_t Word; +} IWDT_INTCLR_Typedef; + +typedef union +{ + struct + { + uint32_t WDTIF: 1; + uint32_t RESERVED0: 31; + }; + uint32_t Word; +} IWDT_RIS_Typedef; + +typedef union +{ + struct + { + uint32_t LOCK: 1; + uint32_t RESERVED0: 31; + }; + uint32_t Word; +} IWDT_LOCK_Typedef; + +typedef struct +{ + __O IWDT_LOAD_Typedef LOAD; + __I IWDT_VALUE_Typedef VALUE; + __IO IWDT_CON_Typedef CON; + __O IWDT_INTCLR_Typedef INTCLR; + __I IWDT_RIS_Typedef RIS; + uint32_t RESERVED0[59] ; + __IO IWDT_LOCK_Typedef LOCK; +} IWDT_TypeDef; + +typedef union +{ + struct + { + uint32_t LOAD: 32; + }; + uint32_t Word; +} WWDT_LOAD_Typedef; + +typedef union +{ + struct + { + uint32_t VALUE: 32; + }; + uint32_t Word; +} WWDT_VALUE_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t IE: 1; + uint32_t RSTEN: 1; + uint32_t CLKS: 1; + uint32_t WWDTWIN: 2; + uint32_t RESERVED0: 26; + }; + uint32_t Word; +} WWDT_CON_Typedef; + +typedef union +{ + struct + { + uint32_t INTCLR: 32; + }; + uint32_t Word; +} WWDT_INTCLR_Typedef; + +typedef union +{ + struct + { + uint32_t WWDTIF: 1; + uint32_t RESERVED0: 31; + }; + uint32_t Word; +} WWDT_RIS_Typedef; + +typedef union +{ + struct + { + uint32_t LOCK: 1; + uint32_t RESERVED0: 31; + }; + uint32_t Word; +} WWDT_LOCK_Typedef; + +typedef struct +{ + __O WWDT_LOAD_Typedef LOAD; + __I WWDT_VALUE_Typedef VALUE; + __IO WWDT_CON_Typedef CON; + __O WWDT_INTCLR_Typedef INTCLR; + __I WWDT_RIS_Typedef RIS; + uint32_t RESERVED0[59] ; + __IO WWDT_LOCK_Typedef LOCK; +} WWDT_TypeDef; + +typedef union +{ + struct + { + uint32_t CNT: 16; + uint32_t RESERVED0: 16; + }; + uint32_t Word; +} T16N_CNT_Typedef; + +typedef union +{ + struct + { + uint32_t PRECNT: 8; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} T16N_PRECNT_Typedef; + +typedef union +{ + struct + { + uint32_t PREMAT: 8; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} T16N_PREMAT_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t CS: 2; + uint32_t SYNC: 1; + uint32_t EDGE: 2; + uint32_t MOD: 2; + uint32_t MAT0S: 2; + uint32_t MAT1S: 2; + uint32_t MAT2S: 2; + uint32_t MAT3S: 2; + uint32_t ASYWEN: 1; + uint32_t RESERVED0: 15; + }; + uint32_t Word; +} T16N_CON0_Typedef; + +typedef union +{ + struct + { + uint32_t CAPPE: 1; + uint32_t CAPNE: 1; + uint32_t CAPIS0: 1; + uint32_t CAPIS1: 1; + uint32_t CAPT: 4; + uint32_t CAPL0: 1; + uint32_t CAPL1: 1; + uint32_t RESERVED0: 22; + }; + uint32_t Word; +} T16N_CON1_Typedef; + +typedef union +{ + struct + { + uint32_t MOE0: 1; + uint32_t MOE1: 1; + uint32_t POL0: 1; + uint32_t POL1: 1; + uint32_t MOM0: 2; + uint32_t MOM1: 2; + uint32_t MOM2: 2; + uint32_t MOM3: 2; + uint32_t PBKEN: 1; + uint32_t PBKPS: 1; + uint32_t PBKF: 1; + uint32_t RESERVED0: 1; + uint32_t PBKS: 3; + uint32_t RESERVED1: 1; + uint32_t PBKL0: 1; + uint32_t PBKL1: 1; + uint32_t RESERVED2: 10; + }; + uint32_t Word; +} T16N_CON2_Typedef; + +typedef union +{ + struct + { + uint32_t MAT0IE: 1; + uint32_t MAT1IE: 1; + uint32_t MAT2IE: 1; + uint32_t MAT3IE: 1; + uint32_t OVIE: 1; + uint32_t CAP0IE: 1; + uint32_t CAP1IE: 1; + uint32_t PBKIE: 1; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} T16N_IE_Typedef; + +typedef union +{ + struct + { + uint32_t MAT0IF: 1; + uint32_t MAT1IF: 1; + uint32_t MAT2IF: 1; + uint32_t MAT3IF: 1; + uint32_t OVIF: 1; + uint32_t CAP0IF: 1; + uint32_t CAP1IF: 1; + uint32_t PBKIF: 1; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} T16N_IF_Typedef; + +typedef union +{ + struct + { + uint32_t MAT0TAR: 1; + uint32_t MAT1TAR: 1; + uint32_t MAT2TAR: 1; + uint32_t MAT3TAR: 1; + uint32_t OVTAR: 1; + uint32_t RESERVED0: 27; + }; + uint32_t Word; +} T16N_TRG_Typedef; + +typedef union +{ + struct + { + uint32_t MAT0: 16; + uint32_t RESERVED0: 16; + }; + uint32_t Word; +} T16N_MAT0_Typedef; + +typedef union +{ + struct + { + uint32_t MAT1: 16; + uint32_t RESERVED0: 16; + }; + uint32_t Word; +} T16N_MAT1_Typedef; + +typedef union +{ + struct + { + uint32_t MAT2: 16; + uint32_t RESERVED0: 16; + }; + uint32_t Word; +} T16N_MAT2_Typedef; + +typedef union +{ + struct + { + uint32_t MAT3: 16; + uint32_t RESERVED0: 16; + }; + uint32_t Word; +} T16N_MAT3_Typedef; + +typedef struct +{ + __IO T16N_CNT_Typedef CNT; + uint32_t RESERVED0; + __IO T16N_PRECNT_Typedef PRECNT; + __IO T16N_PREMAT_Typedef PREMAT; + __IO T16N_CON0_Typedef CON0; + __IO T16N_CON1_Typedef CON1; + __IO T16N_CON2_Typedef CON2; + uint32_t RESERVED1; + __IO T16N_IE_Typedef IE; + __IO T16N_IF_Typedef IF; + __IO T16N_TRG_Typedef TRG; + uint32_t RESERVED2; + __IO T16N_MAT0_Typedef MAT0; + __IO T16N_MAT1_Typedef MAT1; + __IO T16N_MAT2_Typedef MAT2; + __IO T16N_MAT3_Typedef MAT3; +} T16N_TypeDef; + +typedef union +{ + struct + { + uint32_t CNT: 32; + }; + uint32_t Word; +} T32N_CNT_Typedef; + +typedef union +{ + struct + { + uint32_t PRECNT: 8; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} T32N_PRECNT_Typedef; + +typedef union +{ + struct + { + uint32_t PREMAT: 8; + uint32_t RESERVED0: 24; + }; + uint32_t Word; +} T32N_PREMAT_Typedef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t CS: 2; + uint32_t SYNC: 1; + uint32_t EDGE: 2; + uint32_t MOD: 2; + uint32_t MAT0S: 2; + uint32_t MAT1S: 2; + uint32_t MAT2S: 2; + uint32_t MAT3S: 2; + uint32_t ASYNC_WREN: 1; + uint32_t RESERVED0: 15; + }; + uint32_t Word; +} T32N_CON0_Typedef; + +typedef union +{ + struct + { + uint32_t CAPPE: 1; + uint32_t CAPNE: 1; + uint32_t CAPIS0: 1; + uint32_t CAPIS1: 1; + uint32_t CAPT: 4; + uint32_t CAPL0: 1; + uint32_t CAPL1: 1; + uint32_t RESERVED0: 22; + }; + uint32_t Word; +} T32N_CON1_Typedef; + +typedef union +{ + struct + { + uint32_t MOE0: 1; + uint32_t MOE1: 1; + uint32_t POL0: 1; + uint32_t POL1: 1; + uint32_t MOM0: 2; + uint32_t MOM1: 2; + uint32_t MOM2: 2; + uint32_t MOM3: 2; + uint32_t RESERVED0: 20; + }; + uint32_t Word; +} T32N_CON2_Typedef; + +typedef union +{ + struct + { + uint32_t MAT0IE: 1; + uint32_t MAT1IE: 1; + uint32_t MAT2IE: 1; + uint32_t MAT3IE: 1; + uint32_t OVIE: 1; + uint32_t CAP0IE: 1; + uint32_t CAP1IE: 1; + uint32_t RESERVED0: 25; + }; + uint32_t Word; +} T32N_IE_Typedef; + +typedef union +{ + struct + { + uint32_t MAT0IF: 1; + uint32_t MAT1IF: 1; + uint32_t MAT2IF: 1; + uint32_t MAT3IF: 1; + uint32_t OVIF: 1; + uint32_t CAP0IF: 1; + uint32_t CAP1IF: 1; + uint32_t RESERVED0: 25; + }; + uint32_t Word; +} T32N_IF_Typedef; + +typedef union +{ + struct + { + uint32_t MAT0TAR: 1; + uint32_t MAT1TAR: 1; + uint32_t MAT2TAR: 1; + uint32_t MAT3TAR: 1; + uint32_t OVTAR: 1; + uint32_t RESERVED0: 27; + }; + uint32_t Word; +} T32N_TRG_Typedef; + +typedef union +{ + struct + { + uint32_t MAT0: 32; + }; + uint32_t Word; +} T32N_MAT0_Typedef; + +typedef union +{ + struct + { + uint32_t MAT1: 32; + }; + uint32_t Word; +} T32N_MAT1_Typedef; + +typedef union +{ + struct + { + uint32_t MAT2: 32; + }; + uint32_t Word; +} T32N_MAT2_Typedef; + +typedef union +{ + struct + { + uint32_t MAT3: 32; + }; + uint32_t Word; +} T32N_MAT3_Typedef; + +typedef struct +{ + __IO T32N_CNT_Typedef CNT; + uint32_t RESERVED0; + __IO T32N_PRECNT_Typedef PRECNT; + __IO T32N_PREMAT_Typedef PREMAT; + __IO T32N_CON0_Typedef CON0; + __IO T32N_CON1_Typedef CON1; + __IO T32N_CON2_Typedef CON2; + uint32_t RESERVED1; + __IO T32N_IE_Typedef IE; + __IO T32N_IF_Typedef IF; + __IO T32N_TRG_Typedef TRG; + uint32_t RESERVED2; + __IO T32N_MAT0_Typedef MAT0; + __IO T32N_MAT1_Typedef MAT1; + __IO T32N_MAT2_Typedef MAT2; + __IO T32N_MAT3_Typedef MAT3; +} T32N_TypeDef; + +typedef union +{ + struct + { + uint32_t TXEN: 1; + uint32_t TRST: 1; + uint32_t TXFS: 1; + uint32_t RESERVED0: 1; + uint32_t TXMOD: 3; + uint32_t TXP: 1; + uint32_t RXEN: 1; + uint32_t RRST: 1; + uint32_t RESERVED1: 2; + uint32_t RXMOD: 3; + uint32_t RXP: 1; + uint32_t RESERVED2: 12; + uint32_t BCS: 3; + uint32_t RESERVED3: 1; + }; + uint32_t Word; +} UART_CON_Typedef; + +typedef union +{ + struct + { + uint32_t BRR: 11; + uint32_t RESERVED0: 21; + }; + uint32_t Word; +} UART_BRR_Typedef; + +typedef union +{ + uint8_t Byte[4]; + uint16_t HalfWord[2]; + uint32_t Word; +} UART_TBW_Typedef; + +typedef union +{ + uint8_t Byte[4]; + uint16_t HalfWord[2]; + uint32_t Word; +} UART_RBR_Typedef; + +typedef union +{ + struct + { + uint32_t TB0: 9; + uint32_t RESERVED0: 3; + uint32_t TP0: 1; + uint32_t TBEF0: 1; + uint32_t RESERVED1: 2; + uint32_t TB1: 9; + uint32_t RESERVED2: 3; + uint32_t TP1: 1; + uint32_t TBEF1: 1; + uint32_t RESERVED3: 2; + }; + uint32_t Word; +} UART_TB01_Typedef; + +typedef union +{ + struct + { + uint32_t TB2: 9; + uint32_t RESERVED0: 3; + uint32_t TP2: 1; + uint32_t TBEF2: 1; + uint32_t RESERVED1: 2; + uint32_t TB3: 9; + uint32_t RESERVED2: 3; + uint32_t TP3: 1; + uint32_t TBEF3: 1; + uint32_t RESERVED3: 2; + }; + uint32_t Word; +} UART_TB23_Typedef; + +typedef union +{ + struct + { + uint32_t RB0: 9; + uint32_t RESERVED0: 3; + uint32_t RP0: 1; + uint32_t RBFF0: 1; + uint32_t FE0: 1; + uint32_t PE0: 1; + uint32_t RB1: 9; + uint32_t RESERVED1: 3; + uint32_t RP1: 1; + uint32_t RBFF1: 1; + uint32_t FE1: 1; + uint32_t PE1: 1; + }; + uint32_t Word; +} UART_RB01_Typedef; + +typedef union +{ + struct + { + uint32_t RB2: 9; + uint32_t RESERVED0: 3; + uint32_t RP2: 1; + uint32_t RBFF2: 1; + uint32_t FE2: 1; + uint32_t PE2: 1; + uint32_t RB3: 9; + uint32_t RESERVED1: 3; + uint32_t RP3: 1; + uint32_t RBFF3: 1; + uint32_t FE3: 1; + uint32_t PE3: 1; + }; + uint32_t Word; +} UART_RB23_Typedef; + +typedef union +{ + struct + { + uint32_t TBIE: 1; + uint32_t RBIE: 1; + uint32_t ROIE: 1; + uint32_t FEIE: 1; + uint32_t PEIE: 1; + uint32_t TBEIE: 1; + uint32_t RESERVED0: 2; + uint32_t TBIM: 2; + uint32_t RBIM: 2; + uint32_t TIDIE: 1; + uint32_t RIDIE: 1; + uint32_t RESERVED1: 18; + }; + uint32_t Word; +} UART_IE_Typedef; + +typedef union +{ + struct + { + uint32_t TBIF: 1; + uint32_t RBIF: 1; + uint32_t ROIF: 1; + uint32_t FEIF: 1; + uint32_t PEIF: 1; + uint32_t TBEIF: 1; + uint32_t RESERVED0: 6; + uint32_t TIDIF: 1; + uint32_t RIDIF: 1; + uint32_t RESERVED1: 18; + }; + uint32_t Word; +} UART_IF_Typedef; + +typedef struct +{ + __IO UART_CON_Typedef CON; + __IO UART_BRR_Typedef BRR; + __O UART_TBW_Typedef TBW; + __I UART_RBR_Typedef RBR; + __I UART_TB01_Typedef TB01; + __I UART_TB23_Typedef TB23; + __I UART_RB01_Typedef RB01; + __I UART_RB23_Typedef RB23; + __IO UART_IE_Typedef IE; + __IO UART_IF_Typedef IF; +} UART_TypeDef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t RST: 1; + uint32_t MS: 1; + uint32_t REN: 1; + uint32_t RESERVED0: 1; + uint32_t DRE: 1; + uint32_t DFS: 2; + uint32_t RESERVED1: 8; + uint32_t TME: 1; + uint32_t TMS: 1; + uint32_t TMP: 6; + uint32_t DW: 3; + uint32_t RESERVED2: 3; + uint32_t TXCLR: 1; + uint32_t RXCLR: 1; + }; + uint32_t Word; +} SPI_CON_Typedef; + +typedef union +{ + uint8_t Byte[4]; + uint16_t HalfWord[2]; + uint32_t Word; +} SPI_TBW_Typedef; + +typedef union +{ + uint8_t Byte[4]; + uint16_t HalfWord[2]; + uint32_t Word; +} SPI_RBR_Typedef; + +typedef union +{ + struct + { + uint32_t TBIE: 1; + uint32_t RBIE: 1; + uint32_t TEIE: 1; + uint32_t ROIE: 1; + uint32_t IDIE: 1; + uint32_t NSSIE: 1; + uint32_t TBWEIE: 1; + uint32_t RESERVED0: 1; + uint32_t TBIM: 2; + uint32_t RBIM: 2; + uint32_t RESERVED1: 20; + }; + uint32_t Word; +} SPI_IE_Typedef; + +typedef union +{ + struct + { + uint32_t TBIF: 1; + uint32_t RBIF: 1; + uint32_t TEIF: 1; + uint32_t ROIF: 1; + uint32_t IDIF: 1; + uint32_t NSSIF: 1; + uint32_t TBWEIF: 1; + uint32_t RESERVED0: 25; + }; + uint32_t Word; +} SPI_IF_Typedef; + +typedef union +{ + struct + { + uint32_t TB0: 8; + uint32_t TB1: 8; + uint32_t TB2: 8; + uint32_t TB3: 8; + }; + uint32_t Word; +} SPI_TB_Typedef; + +typedef union +{ + struct + { + uint32_t RB0: 8; + uint32_t RB1: 8; + uint32_t RB2: 8; + uint32_t RB3: 8; + }; + uint32_t Word; +} SPI_RB_Typedef; + +typedef union +{ + struct + { + uint32_t RESERVED0: 7; + uint32_t NSS: 1; + uint32_t TBEF0: 1; + uint32_t TBEF1: 1; + uint32_t TBEF2: 1; + uint32_t TBEF3: 1; + uint32_t RBFF0: 1; + uint32_t RBFF1: 1; + uint32_t RBFF2: 1; + uint32_t RBFF3: 1; + uint32_t IDLE: 1; + uint32_t RESERVED1: 15; + }; + uint32_t Word; +} SPI_STA_Typedef; + +typedef union +{ + struct + { + uint32_t CKS: 10; + uint32_t RESERVED0: 22; + }; + uint32_t Word; +} SPI_CKS_Typedef; + +typedef struct +{ + __IO SPI_CON_Typedef CON; + uint32_t RESERVED0 ; + __O SPI_TBW_Typedef TBW; + __I SPI_RBR_Typedef RBR; + __IO SPI_IE_Typedef IE; + __IO SPI_IF_Typedef IF; + __I SPI_TB_Typedef TB; + __I SPI_RB_Typedef RB; + __I SPI_STA_Typedef STA; + __IO SPI_CKS_Typedef CKS; +} SPI_TypeDef; + +typedef union +{ + struct + { + uint32_t EN: 1; + uint32_t RST: 1; + uint32_t SCKOD: 1; + uint32_t SDAOD: 1; + uint32_t SCKSE: 1; + uint32_t SDASE: 1; + uint32_t RESERVED0: 1; + uint32_t TJE: 1; + uint32_t TJP: 8; + uint32_t RW: 1; + uint32_t SA: 7; + uint32_t RESERVED1: 8; + }; + uint32_t Word; +} I2C_CON_Typedef; + +typedef union +{ + struct + { + uint32_t MS: 1; + uint32_t RDM: 3; + uint32_t CSE: 1; + uint32_t ANAE: 1; + uint32_t SRAE: 1; + uint32_t SPAE: 1; + uint32_t ADLY: 3; + uint32_t ADE: 1; + uint32_t TIS: 4; + uint32_t SRT: 1; + uint32_t SPT: 1; + uint32_t RDT: 1; + uint32_t BLD: 1; + uint32_t RESERVED0: 4; + uint32_t TAS: 1; + uint32_t RESERVED1: 7; + }; + uint32_t Word; +} I2C_MOD_Typedef; + +typedef union +{ + struct + { + uint32_t SRIE: 1; + uint32_t SPIE: 1; + uint32_t TBIE: 1; + uint32_t RBIE: 1; + uint32_t TEIE: 1; + uint32_t ROIE: 1; + uint32_t NAIE: 1; + uint32_t TBWEIE: 1; + uint32_t TBIM: 2; + uint32_t RBIM: 2; + uint32_t TIDLEIE: 1; + uint32_t RESERVED0: 19; + }; + uint32_t Word; +} I2C_IE_Typedef; + +typedef union +{ + struct + { + uint32_t SRIF: 1; + uint32_t SPIF: 1; + uint32_t TBIF: 1; + uint32_t RBIF: 1; + uint32_t TEIF: 1; + uint32_t ROIF: 1; + uint32_t NAIF: 1; + uint32_t TBWEIF: 1; + uint32_t RESERVED0: 4; + uint32_t TIDLEIF: 1; + uint32_t RESERVED1: 19; + }; + uint32_t Word; +} I2C_IF_Typedef; + +typedef union +{ + uint8_t Byte[4]; + uint16_t HalfWord[2]; + uint32_t Word; +} I2C_TBW_Typedef; + +typedef union +{ + uint8_t Byte[4]; + uint16_t HalfWord[2]; + uint32_t Word; +} I2C_RBR_Typedef; + +typedef union +{ + struct + { + uint32_t TB0: 8; + uint32_t TB1: 8; + uint32_t TB2: 8; + uint32_t TB3: 8; + }; + uint32_t Word; +} I2C_TB_Typedef; + +typedef union +{ + struct + { + uint32_t RB0: 8; + uint32_t RB1: 8; + uint32_t RB2: 8; + uint32_t RB3: 8; + }; + uint32_t Word; +} I2C_RB_Typedef; + +typedef union +{ + struct + { + uint32_t RESERVED0: 8; + uint32_t TBEF0: 1; + uint32_t TBEF1: 1; + uint32_t TBEF2: 1; + uint32_t TBEF3: 1; + uint32_t RBFF0: 1; + uint32_t RBFF1: 1; + uint32_t RBFF2: 1; + uint32_t RBFF3: 1; + uint32_t ACK: 1; + uint32_t IDLE: 1; + uint32_t RESERVED1: 14; + }; + uint32_t Word; +} I2C_STA_Typedef; + +typedef struct +{ + __IO I2C_CON_Typedef CON; + __IO I2C_MOD_Typedef MOD; + __IO I2C_IE_Typedef IE; + __IO I2C_IF_Typedef IF; + __O I2C_TBW_Typedef TBW; + __I I2C_RBR_Typedef RBR; + __I I2C_TB_Typedef TB; + __I I2C_RB_Typedef RB; + __I I2C_STA_Typedef STA; +} I2C_TypeDef; + +typedef union +{ + struct + { + uint32_t AES_DATA0: 32; + }; + uint32_t Word; +} AES_DATA0_Typedef; + +typedef union +{ + struct + { + uint32_t AES_DATA1: 32; + }; + uint32_t Word; +} AES_DATA1_Typedef; + +typedef union +{ + struct + { + uint32_t AES_DATA2: 32; + }; + uint32_t Word; +} AES_DATA2_Typedef; + +typedef union +{ + struct + { + uint32_t AES_DATA3: 32; + }; + uint32_t Word; +} AES_DATA3_Typedef; + +typedef union +{ + struct + { + uint32_t AES_KEY0: 32; + }; + uint32_t Word; +} AES_KEY0_Typedef; + +typedef union +{ + struct + { + uint32_t AES_KEY1: 32; + }; + uint32_t Word; +} AES_KEY1_Typedef; + +typedef union +{ + struct + { + uint32_t AES_KEY2: 32; + }; + uint32_t Word; +} AES_KEY2_Typedef; + +typedef union +{ + struct + { + uint32_t AES_KEY3: 32; + }; + uint32_t Word; +} AES_KEY3_Typedef; + +typedef union +{ + struct + { + uint32_t GO_DONE: 1; + uint32_t ENCRYPT: 1; + uint32_t RESERVED0: 4; + uint32_t IE: 1; + uint32_t IF: 1; + uint32_t RESERVED1: 24; + }; + uint32_t Word; +} AES_CON_Typedef; + +typedef struct +{ + __IO AES_DATA0_Typedef DATA0; + __IO AES_DATA1_Typedef DATA1; + __IO AES_DATA2_Typedef DATA2; + __IO AES_DATA3_Typedef DATA3; + __IO AES_KEY0_Typedef KEY0; + __IO AES_KEY1_Typedef KEY1; + __IO AES_KEY2_Typedef KEY2; + __IO AES_KEY3_Typedef KEY3; + __IO AES_CON_Typedef CON; +} AES_TypeDef; + +/******************************************************************************/ +/* 物理地址映射 */ +/******************************************************************************/ + +/* Base addresses */ +#define FLASH_BASE (0x00000000UL) +#define SRAM_BASE (0x20000000UL) +#define APB_BASE (0x40000000UL) +#define RAM_BASE (0x60000000UL) + +/* APB peripherals */ +#define SCU_BASE (APB_BASE + 0x00000) +#define CRC_BASE (APB_BASE + 0x00C00) +#define GPIO_BASE (APB_BASE + 0x20000) +#define IAP_BASE (APB_BASE + 0x00800) +#define ADC_BASE (APB_BASE + 0x01000) +#define RTC_BASE (APB_BASE + 0x01400) +#define IWDT_BASE (APB_BASE + 0x01C00) +#define WWDT_BASE (APB_BASE + 0x01800) +#define T16N0_BASE (APB_BASE + 0x02000) +#define T16N1_BASE (APB_BASE + 0x02400) +#define T16N2_BASE (APB_BASE + 0x02800) +#define T16N3_BASE (APB_BASE + 0x02C00) +#define T32N0_BASE (APB_BASE + 0x04000) +#define UART0_BASE (APB_BASE + 0x06000) +#define UART1_BASE (APB_BASE + 0x06400) +#define UART2_BASE (APB_BASE + 0x06800) +#define UART3_BASE (APB_BASE + 0x06C00) +#define UART4_BASE (APB_BASE + 0x07000) +#define UART5_BASE (APB_BASE + 0x07400) +#define SPI0_BASE (APB_BASE + 0x08000) +#define I2C0_BASE (APB_BASE + 0x09000) +#define AES_BASE (APB_BASE + 0x0A000) + +/******************************************************************************/ +/* 外设定义 */ +/******************************************************************************/ +#define SCU ((SCU_TypeDef *) SCU_BASE ) +#define CRC ((CRC_TypeDef *) CRC_BASE ) +#define GPIO ((GPIO_TypeDef *) GPIO_BASE ) +#define IAP ((IAP_TypeDef *) IAP_BASE ) +#define ADC ((ADC_TypeDef *) ADC_BASE ) +#define RTC ((RTC_TypeDef *) RTC_BASE ) +#define IWDT ((IWDT_TypeDef *) IWDT_BASE ) +#define WWDT ((WWDT_TypeDef *) WWDT_BASE ) +#define T16N0 ((T16N_TypeDef *) T16N0_BASE ) +#define T16N1 ((T16N_TypeDef *) T16N1_BASE ) +#define T16N2 ((T16N_TypeDef *) T16N2_BASE ) +#define T16N3 ((T16N_TypeDef *) T16N3_BASE ) +#define T32N0 ((T32N_TypeDef *) T32N0_BASE ) +#define UART0 ((UART_TypeDef *) UART0_BASE ) +#define UART1 ((UART_TypeDef *) UART1_BASE ) +#define UART2 ((UART_TypeDef *) UART2_BASE ) +#define UART3 ((UART_TypeDef *) UART3_BASE ) +#define UART4 ((UART_TypeDef *) UART4_BASE ) +#define UART5 ((UART_TypeDef *) UART5_BASE ) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE ) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE ) +#define AES ((AES_TypeDef *) AES_BASE ) + + +#endif diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/core_cm0.h b/bsp/essemi/es8p508x/libraries/CMSIS/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..e788e0a60abc1b8fdb055c7f865d54256fadda0b --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/CMSIS/core_cm0.h @@ -0,0 +1,668 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.02 + * @date 16. July 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/core_cmFunc.h b/bsp/essemi/es8p508x/libraries/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000000000000000000000000000000000..0a18fafc301e003d348edf5cae39481d8e5fe7c3 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/CMSIS/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/core_cmInstr.h b/bsp/essemi/es8p508x/libraries/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000000000000000000000000000000000..d213f0eed7ca9335e883a5b55b6de14ba9507f1e --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/CMSIS/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/startup_ES8P508x.s b/bsp/essemi/es8p508x/libraries/CMSIS/startup_ES8P508x.s new file mode 100644 index 0000000000000000000000000000000000000000..69e528223e4d580eb84c89ad3633704fcf310af5 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/CMSIS/startup_ES8P508x.s @@ -0,0 +1,233 @@ +;******************************************************************************* +; *file : startup_ES8P508x.s +; *description: ES8P508x Device Startup File +; *author : Eastsoft MCU Software Team +; *version : V0.01 +; *data : 6/30/2017 +; +; *Copyright (C) 2017 Shanghai Eastsoft Microelectronics Co., Ltd. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +;******************************************************************************* + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_IRQHandler ; Reset Handler + DCD NMI_IRQHandler ; NMI Handler + DCD HardFault_IRQHandler ; HardFault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_IRQHandler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PINT0_IRQHandler ;16, PINT0 IRQHandler + DCD PINT1_IRQHandler ;17, PINT1 IRQHandler + DCD PINT2_IRQHandler ;18, PINT2 IRQHandler + DCD PINT3_IRQHandler ;19, PINT3 IRQHandler + DCD PINT4_IRQHandler ;20, PINT4 IRQHandler + DCD PINT5_IRQHandler ;21, PINT5 IRQHandler + DCD PINT6_IRQHandler ;22, PINT6 IRQHandler + DCD PINT7_IRQHandler ;23, PINT7 IRQHandler + DCD T16N0_IRQHandler ;24, T16N0 IRQHandler + DCD T16N1_IRQHandler ;25, T16N1 IRQHandler + DCD T16N2_IRQHandler ;26, T16N2 IRQHandler + DCD T16N3_IRQHandler ;27, T16N3 IRQHandler + DCD T32N0_IRQHandler ;28, T32N0 IRQHandler + DCD 0 ;29, Reserved + DCD IWDT_IRQHandler ;30, IWDT IRQHandler + DCD WWDT_IRQHandler ;31, WWDT IRQHandler + DCD CCM_IRQHandler ;32, WDT IRQHandler + DCD PLK_IRQHandler ;33, PLK IRQHandler + DCD LVD_IRQHandler ;34, LVD IRQHandler + DCD KINT_IRQHandler ;35, KINT IRQHandler + DCD RTC_IRQHandler ;36, RTC IRQHandler + DCD ADC_IRQHandler ;37, ADC IRQHandler + DCD 0 ;38, Reserved + DCD AES_IRQHandler ;39, AES IRQHandler + DCD UART0_IRQHandler ;40, UART0 IRQHandler + DCD UART1_IRQHandler ;41, UART1 IRQHandler + DCD UART2_IRQHandler ;42, UART2 IRQHandler + DCD UART3_IRQHandler ;43, UART3 IRQHandler + DCD UART4_IRQHandler ;44, UART4 IRQHandler + DCD UART5_IRQHandler ;45, UART5 IRQHandler + DCD SPI0_IRQHandler ;46, SPI0 IRQHandler + DCD I2C0_IRQHandler ;47, I2C0 IRQHandler + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_IRQHandler PROC + EXPORT Reset_IRQHandler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception IRQHandlers (infinite loops which can be modified) + +NMI_IRQHandler PROC + EXPORT NMI_IRQHandler [WEAK] + B . + ENDP +HardFault_IRQHandler PROC + EXPORT HardFault_IRQHandler [WEAK] + B . + ENDP +SVC_IRQHandler PROC + EXPORT SVC_IRQHandler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_IRQHandler PROC + EXPORT PINT0_IRQHandler [WEAK] + EXPORT PINT1_IRQHandler [WEAK] + EXPORT PINT2_IRQHandler [WEAK] + EXPORT PINT3_IRQHandler [WEAK] + EXPORT PINT4_IRQHandler [WEAK] + EXPORT PINT5_IRQHandler [WEAK] + EXPORT PINT6_IRQHandler [WEAK] + EXPORT PINT7_IRQHandler [WEAK] + EXPORT T16N0_IRQHandler [WEAK] + EXPORT T16N1_IRQHandler [WEAK] + EXPORT T16N2_IRQHandler [WEAK] + EXPORT T16N3_IRQHandler [WEAK] + EXPORT T32N0_IRQHandler [WEAK] + EXPORT IWDT_IRQHandler [WEAK] + EXPORT WWDT_IRQHandler [WEAK] + EXPORT CCM_IRQHandler [WEAK] + EXPORT PLK_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT KINT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + + + +PINT0_IRQHandler +PINT1_IRQHandler +PINT2_IRQHandler +PINT3_IRQHandler +PINT4_IRQHandler +PINT5_IRQHandler +PINT6_IRQHandler +PINT7_IRQHandler +T16N0_IRQHandler +T16N1_IRQHandler +T16N2_IRQHandler +T16N3_IRQHandler +T32N0_IRQHandler +IWDT_IRQHandler +WWDT_IRQHandler +CCM_IRQHandler +PLK_IRQHandler +LVD_IRQHandler +KINT_IRQHandler +RTC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +SPI0_IRQHandler +I2C0_IRQHandler + + B . + + ENDP + + + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.c b/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.c new file mode 100644 index 0000000000000000000000000000000000000000..eb22f8c9daad9a55d5be36b002d6c55d87bc11f4 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.c @@ -0,0 +1,76 @@ +/*************************************************************** +*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd +*ļ system_ES8P508x.c +* ߣ Liut +* V1.00 +* ڣ 2017/07/14 +* ⺯ļ +* ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ +***************************************************************/ +#include "system_ES8P508x.h" +#include "lib_config.h" + +uint32_t SystemCoreClock = 48000000; + + +/*************************************************************** +SystemCoreClockUpdate + ϵͳʱΪڲʱ20MHZͬʱSystemCoreClock +ֵ +ֵ +ֵ +***************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t Prot_Temp; + uint16_t Count=0; + SystemClockSelect(SCU_SysClk_HRC , CLK_SEL_HRC); //ѡϵͳʱΪHRCʱ + PLLClock_Config(DISABLE, SCU_PLL_HRC, SCU_PLL_48M,ENABLE); //PLLֹ + Prot_Temp = SCU->PROT.PROT; + if(Prot_Temp != 0) //д + {SCU->PROT.Word = 0x55AA6996;} // + + SCU->SCLKEN1.HRC_EN = 1; //ʹڲ20MHZ + do + { + Count++; + } + while((SCU->SCLKEN1.HRC_RDY == 0)&&(Count != 0xFFF)); //ȴʱӿ + + if(Count == 0xFFF) + { + return ; + } + + SCU->SCLKEN0.SYSCLK_DIV = 0; //ϵͳʱӺƵ1:1 + + switch(SCU->SCLKEN0.CLK_SEL) + { + case 0: + SystemCoreClock = 20000000; //HRC + break; + case 1: + SystemCoreClock = 32000; //LRC + break; + default: + break; + } + + if(Prot_Temp != 0) //д + {SCU->PROT.Word = 0x00000000;} //д +} + +/*************************************************************** +SystemInit + ϵͳʼʱ +ֵ +ֵ +ֵ +***************************************************************/ +void SystemInit (void) +{ + SystemCoreClockUpdate(); +} + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.h b/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.h new file mode 100644 index 0000000000000000000000000000000000000000..b0fa1595c914233dc1cef4ee75712003bf223971 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.h @@ -0,0 +1,23 @@ +/*************************************************************** +*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. +*ļ system_ES8P508x.h +* ߣ Liut +* V1.00 +* ڣ 2017/07/14 +* ⺯ļ +* ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ +***************************************************************/ +#ifndef __SYSTEMES8P508x_H__ +#define __SYSTEMES8P508x_H__ + +#include "ES8P508x.h" +#include "type.h" + +extern uint32_t SystemCoreClock; +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/irqhandler.h b/bsp/essemi/es8p508x/libraries/Library/Include/irqhandler.h new file mode 100644 index 0000000000000000000000000000000000000000..fec6f2d62d8be0156864fa072c4e3eb38e208118 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/irqhandler.h @@ -0,0 +1,17 @@ + +#ifndef __IRQHANDLER_H__ +#define __IRQHANDLER_H__ + +#include "ES8P508x.h" + +extern void systick_irq_cbk(void); + +/************жϺ***********/ +void NMI_IRQHandler(void); +void HardFault_IRQHandler(void); +void SVC_IRQHandler(void); +void PendSV_IRQHandler(void); +void SysTick_IRQHandler(void); + +#endif + diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_adc.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..afcb552435244979b4c0bf546478515aba9970bb --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_adc.h @@ -0,0 +1,239 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_timer.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ADCģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBADC_H__ +#define __LIBADC_H__ + +#include "ES8P508x.h" +#include "type.h" + +/* ڲοѹѡ */ +typedef enum { + ADC_VREF_SEL_2_0 = 0, /* ڲοѹ2.048v*/ + ADC_VREF_SEL_1_6 = 1, /* ڲοѹ1.6v*/ + ADC_VREF_SEL_MAX = 1, +}ADC_TYPE_VREF_SEL; + +/* ADCʱԴѡ */ +typedef enum +{ + ADC_ClkS_PCLK = 0x0 , //ʱӣPCLK + ADC_ClkS_PLL = 0x1 , //ʱӣPLL + ADC_ClkS_32K = 0x2 , //ʱӣADCCLK(32KHZ) +}ADC_TYPE_CLKS; + +/* ADCʱԴԤƵ */ +typedef enum +{ + ADC_ClkDiv_1 = 0x0 , //ԤƵ1:1 + ADC_ClkDiv_2 = 0x1 , //ԤƵ1:2 + ADC_ClkDiv_4 = 0x2 , //ԤƵ1:4 + ADC_ClkDiv_8 = 0x3 , //ԤƵ1:8 + ADC_ClkDiv_16 = 0x4 , //ԤƵ1:16 + ADC_ClkDiv_32 = 0x5 , //ԤƵ1:32 + ADC_ClkDiv_64 = 0x6 , //ԤƵ1:64 + ADC_ClkDiv_256 = 0x7 , //ԤƵ1:256 +}ADC_TYPE_CLKDIV; + +/* οѹѡ */ +typedef enum +{ + ADC_VrefP_Vcc = 0x0 , //οѹVDDѹ + ADC_VrefP_Exter = 0x3 , //οѹⲿοѹ +}ADC_TYPE_VREFP; + +/* ģʽѡ */ +typedef enum +{ + ADC_SMPS_SOFT = 0, /* */ + ADC_SMPS_HARD = 1, /* Ӳ */ +}ADC_TYPE_SMPS; + + +/* תٶѡ */ +typedef enum +{ + ADC_ConvSpeed_Low = 0x0 , //ADתٶȣ + ADC_ConvSpeed_High = 0x1 , //ADתٶȣ +}ADC_TYPE_HSEN; + +/* ADCͨѡ */ +typedef enum +{ + ADC_CHS_AIN0 = 0, /* ͨ 0 */ + ADC_CHS_AIN1 = 1, /* ͨ 1 */ + ADC_CHS_AIN2 = 2, /* ͨ 2 */ + ADC_CHS_AIN3 = 3, /* ͨ 3 */ + ADC_CHS_AIN4 = 4, /* ͨ 4 */ + ADC_CHS_AIN5 = 5, /* ͨ 5 */ + ADC_CHS_AIN6 = 6, /* ͨ 6 */ + ADC_CHS_AIN7 = 7, /* ͨ 7 */ + ADC_CHS_AIN8 = 8, /* ͨ 8 */ + ADC_CHS_AIN9 = 9, /* ͨ 9 */ + ADC_CHS_AIN10 = 10, /* ͨ 10 */ + ADC_CHS_AIN11 = 11, /* ͨ 11 */ + ADC_CHS_AIN12 = 12, /* ͨ 12 */ + ADC_CHS_AIN13 = 13, /* ͨ 13 */ + ADC_CHS_AIN14 = 14, /* ͨ 14 */ + ADC_CHS_AIN15 = 15, /* ͨ 15 */ +}ADC_TYPE_CHS; + +/*ADC coreѡλ*/ +typedef enum +{ + ADC_LP_86ua = 2, //ADC Core Ϊ86Ƽʹ + ADC_LP_215ua = 0, //ADC Core Ϊ215uA + ADC_LP_120ua = 1, //ADC Core Ϊ120uA + ADC_LP_70ua = 3, //ADC Core Ϊ70uA +}ADC_TYPE_BUFLP; + +/*ADC buffѡλ*/ +typedef enum +{ + ADC_BUFF_0ua = 0, //ADC buffΪ0uAƼʹ + ADC_BUFF_34ua = 1, //ADC buffΪ34uA + ADC_BUFF_95ua = 2, //ADC buffΪ95uA +}ADC_TYPE_BUFEN; + +/* ADC IF ״̬ */ +typedef enum +{ + ADC_IF = 0x01, + ADC_IF_ACPMIN = 0x02, + ADC_IF_ACPMAX =0x04, + ADC_IF_ACPOVER = 0x08, +}ADC_TYPE_IF; + +/* ADC IE ״̬ */ +typedef enum +{ + ADC_IE = 0x01, + ADC_IE_ACPMIN = 0x02, + ADC_IE_ACPMAX =0x04, + ADC_IE_ACPOVER = 0x08, +}ADC_TYPE_IE; + +/* ADCʼýṹ嶨 */ +typedef struct +{ + ADC_TYPE_CLKS ADC_ClkS; //ADCCON1:bit3 ADCʱԴѡ + ADC_TYPE_CLKDIV ADC_ClkDiv; //ADCCON1:bit2-0 ADCʱԴԤƵ + ADC_TYPE_VREFP ADC_VrefP; //ADCCON1:bit9-8 ADCοѹѡ + ADC_TYPE_SMPS ADC_SampS; //ADCCON1:bit12 ADCģʽѡ + ADC_TYPE_CHS ADC_ChS; //ADCCHS:bit0-3 ADCģͨѡ + //ADC_TYPE_VREF_SEL VREF_SEL; //οѹѡ + uint8_t ST; //Ӳʱ (ģʽΪӲʱ) 0~31 + TYPE_FUNCEN ADC_VREFN; //οѹѡλ + TYPE_FUNCEN ADC_VRBUF_EN; +}ADC_InitStruType; + +/* ԶȽϵͷֵ ѡ*/ +typedef enum +{ + ADC_ACP_MIN_MIN = 0x0, /* Сͷֵ*/ + ADC_ACP_MIN_MAX = 0xfff, /* ͷֵ*/ +}ADC_TYPE_ACP_MIN; + +/* ԶȽϸ߷ֵ ѡ*/ +typedef enum +{ + ADC_ACP_MAX_MIN = 0x0, /* С߷ֵ*/ + ADC_ACP_MAX_MAX = 0xfff, /* ߷ֵ*/ +}ADC_TYPE_ACP_MAX; + +/* ÿԶתȽʱѡ */ +typedef enum +{ + ADC_ACPC_OVFL_TIME_MAX = 0x9c3, /* ʱ */ +}ADC_TYPE_ACPC_OVFL_TIME; + +/* ԶתȽϴ */ +typedef enum +{ + ADC_ACPC_TIMES_1 = 0, /* 1 */ + ADC_ACPC_TIMES_2 = 1, /* 2 */ + ADC_ACPC_TIMES_4 = 2, /* 4 */ + ADC_ACPC_TIMES_8 = 3, /* 8 */ + ADC_ACPC_TIMES_MAX = 3, +}ADC_TYPE_ACPC_TIMES; + +/* ACPʱӵʱԴ */ +typedef enum +{ + ADC_ACPC_CLKS_PCLK = 0, /* PCLK */ + ADC_ACPC_CLKS_LRC = 1, /* LRC(32KHz) */ +}ADC_TYPE_ACPC_CLKS; + +typedef FuncState ADC_TYPE_CHOP_EN1, ADC_TYPE_CHOP_EN; +typedef FuncState ADC_TYPE_VREF_EN,ADC_TYPE_IREF_EN; +typedef FuncState ADC_TYPE_EN,ADC_TYPE_ACP_EN; + +/* ԶȽϹܳʼṹ*/ +typedef struct +{ + ADC_TYPE_ACP_EN ACP_EN; /* ԶȽϹʹλ*/ + uint16_t ACPC_OVER_TIME; /* ԶȽʱ(ʹó0) 0~0x9c3 */ + ADC_TYPE_ACPC_TIMES ACPC_TIMES; /* ԶȽϴ(ȼʱ) */ + uint16_t ACPC_MIN_TARGET; /* ƽֵͷֵ (0xfffر) 0~0xfff */ + uint16_t ACPC_MAX_TARGET; /* ƽֵ߷ֵ (0x0ر) 0~0xfff */ +}ADC_ACP_TypeDef; + +/************ADCģ궨***********/ +/* ADCʹܿ */ +#define ADC_Enable() (ADC->CON0.EN = 0x1) +#define ADC_Disable() (ADC->CON0.EN = 0x0) + +/* ԶȽϹʹ*/ +#define ADC_ACP_Enable() (ADC->CON0.ACP_EN = 1) +#define ADC_ACP_Disable() (ADC->CON0.ACP_EN = 0) + +/* ADCʼת */ +#define ADC_Start() (ADC->CON0.TRIG = 0x1) + +/* ADC */ +#define ADC_SampStart() (ADC->CON1.SMPON = 0x1) +#define ADC_SampStop() (ADC->CON1.SMPON = 0x0) + +/* ADC VDD */ +#define ADC_VDD5_FLAG_Enable() (ADC->CHS.VDD5_FLAG_EN = 0x1) +#define ADC_VDD5_FLAG_Disable() (ADC->CHS.VDD5_FLAG_EN = 0x0) + +/* ADCжʹܿ */ +#define ADC_IE_Enable() (ADC->IE.IE = 0x1) +#define ADC_IE_Disable() (ADC->IE.IE = 0x0) + +#define ADC_ACPMINIE_Enable() (ADC->IE.ACPMINIE = 1) +#define ADC_ACPMINIE_Disable() (ADC->IE.ACPMINIE = 0) + +#define ADC_ACPMAXIE_Enable() (ADC->IE.ACPMAXIE = 1) +#define ADC_ACPMAXIE_Disable() (ADC->IE.ACPMAXIE = 0) + +#define ADC_ACPOVIE_Enable() (ADC->IE.ACPOVIE = 1) +#define ADC_ACPOVIE_Disable() (ADC->IE.ACPOVIE = 0) + +/************ADCģ麯***********/ +void ADC_Init(ADC_InitStruType * ADC_InitStruct); +void ADC_Set_CH(ADC_TYPE_CHS AdcCH); +uint16_t ADC_GetConvValue(void); +FlagStatus ADC_GetConvStatus(void); +ErrorStatus ADC_ACPConfig(ADC_ACP_TypeDef *ADC_ACP_InitStruct); +ErrorStatus ADC_SoftStart(void); +ErrorStatus ADC_SoftStop(void); +uint16_t ADC_GetACPMeanValue(void); +uint16_t ADC_GetACPMinValue(void); +uint16_t ADC_GetACPMaxValue(void); +FlagStatus ADC_GetFlagStatus(ADC_TYPE_IF IFName); +ITStatus ADC_GetITStatus(ADC_TYPE_IE IEName); +ErrorStatus ADC_ClearIFStatus(ADC_TYPE_IF IFName); +void ADC_Reset(void); + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_aes.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..13c8046278b18a6b378159fc5506fda18622bc42 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_aes.h @@ -0,0 +1,74 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_aes.c + * ߣ zoux + * V1.00 + * ڣ 2017/07/14 + * AESģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBAES_H__ +#define __LIBAES_H__ + +#include "ES8P508x.h" +#include "type.h" + +/* ܽģʽѡλ */ +typedef enum { + AES_MODE_DECRYPT = 0, /* */ + AES_MODE_ENCRYPT = 1, /* */ +}AES_TYPE_MODE; + +/* /ܿλ */ +typedef enum { + AES_DONE_YES = 0, /* */ + AES_DONE_NO = 1, /* ڼ */ +}AES_TYPE_DONE; + +/* ӽݽṹ */ +typedef struct { + uint32_t DATA[4]; +}AES_DATA_TypeDef; + +typedef enum { + AES_IF_IF = 0x80, +}AES_TYPE_IF; + +typedef enum { + AES_IT_IT = 0x40, +}AES_TYPE_IT; + +/* ӽԿṹ */ +typedef struct { + uint32_t KEY[4]; +}AES_KEY_TypeDef; + +/* ӽܳʼṹ */ +typedef struct { + AES_TYPE_MODE MODE; /* ܻ߽ */ +}AES_InitStruType; + +/* ӽʹܣʼ */ +#define AES_Enable() (AES->CON.GO_DONE = 1) +/* ģر */ +#define AES_Disable() (AES->CON.GO_DONE = 0) + + +/********************* ADCģ麯 *********************/ +void AES_Init(AES_InitStruType * AES_InitStruct); +void AES_WriteKey(uint32_t *AES_KEY); +void AES_ReadKey(uint32_t * AES_KEY); + +void AES_WriteData(uint32_t *AES_DATA); +void AES_ReadData(uint32_t * AES_DATA); + +void AES_ITConfig(AES_TYPE_IT AES_IE, TYPE_FUNCEN NewState); +void AES_ClearITPendingBit(void); +FlagStatus AES_GetFlagStatus(AES_TYPE_IF Flag); + +AES_TYPE_DONE AES_GetDoneStatus(void); +void AES_Reset(void); + +#endif + diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_config.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_config.h new file mode 100644 index 0000000000000000000000000000000000000000..8178813ca9a8e7119fb94e59728f606419b9baeb --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_config.h @@ -0,0 +1,32 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_config.h + * : Liut + * : V1.00 + * : 2017/07/14 + * ⺯ļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBCONFIG_H__ +#define __LIBCONFIG_H__ + +#include "lib_adc.h" +#include "lib_iic.h" +#include "lib_scs.h" +#include "lib_scu.h" +#include "lib_spi.h" +#include "lib_timer.h" +#include "lib_uart.h" +#include "lib_wdt.h" +#include "lib_flashiap.h" +#include "lib_gpio.h" +#include "lib_printf.h" +#include "lib_iap.h" +#include "lib_crc.h" +#include "lib_aes.h" +#include "lib_rtc.h" + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_crc.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..1ab36cca7b66e6ba7c3e3b226c16ecd8fe3cb6eb --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_crc.h @@ -0,0 +1,93 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ + * : Liut + * : V1.00 + * : 2017/07/14 + * + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBCRC_H +#define __LIBCRC_H + +#include "ES8P508x.h" +#include "type.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define CRC_EmptayCheck_addr 0x10000010 +#define CRC_FlashVerify_addr 0x10000014 +#define CRC_UserCal_addr 0x10000018 +#define CRC_CheckReset_addr 0x1000001C + +typedef uint32_t (*CRC_EM)(void* address, uint32_t data_len); +typedef uint32_t (*CRC_FL)(void* address, uint32_t data_len, uint32_t type); +typedef uint32_t (*CRC_US)(void* address, uint32_t data_len, uint32_t type); +typedef uint32_t (*CRC_CH)(void); + + +typedef enum +{ + CRC_XOROUT_NORMAL = 0x0, //ȡ + CRC_XOROUT_ANTI = (1U<<14), //ȡ +} CRC_XOROUT; + +typedef enum +{ + CRC_REFOUT_NORMAL = 0x0, // + CRC_REFOUT_REVERSE = (1U<<13), // +} CRC_REFOUT; + +typedef enum +{ + CRC_REFIN_NORMAL = 0x0, // + CRC_REFIN_REVERSE = (1U<<12), //뵹 +} CRC_REFIN; + + +typedef enum +{ + CRC_MOD_CRC32 = 0x0, //CRCλΪֽ + CRC_MOD_CRC16 = (2U<<8), //CRCλΪ + CRC_MOD_CRC16_CCITT = (3U<<8), //CRCλΪ +} CRC_MOD_TYPE; + +typedef enum +{ + CRC_INIT_DATA_ALL_0 = 0x0, //CRCʼȫΪ0 + CRC_INIT_DATA_ALL_1 = (1U<<3), //CRCʼȫΪ1 +} CRC_INIT_DATA; + +typedef enum +{ + CRC_HS_TYPE_DISABLE = 0x0, //CRCģʽֹ + CRC_HS_TYPE_ENABLE = (1U<<2), //CRCģʽʹܣCRCʱС24Mʱʹ +} CRC_HS_TYPE; + + +/*CRC_CON ֵṹʼ*/ +typedef struct +{ + CRC_XOROUT xorout; + CRC_REFOUT refout; + CRC_REFIN refin; + CRC_MOD_TYPE mode; + CRC_INIT_DATA init_data_type; + CRC_HS_TYPE hs_type; +} CRC_CONValueStruType; + +uint32_t CRC_getTypeValue(CRC_CONValueStruType con_value); +uint32_t CRC_EmptayCheck(void* address, uint32_t data_len); +uint32_t CRC_FlashVerify(void* address, uint32_t data_len, uint32_t type); +uint32_t CRC_UserCal(void* address, uint32_t data_len, uint32_t type); +uint32_t CRC_CheckReset(void); + +#ifdef __cplusplus +} +#endif + +#endif +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_flashiap.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_flashiap.h new file mode 100644 index 0000000000000000000000000000000000000000..b297e0871283c340973bb47b39aace46bb8d95b9 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_flashiap.h @@ -0,0 +1,44 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_flashiap.h + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * flashд⺯ͷļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBIAP_H__ +#define __LIBIAP_H__ + +#include "ES8P508x.h" +#include "type.h" + +/*************IAPģ궨************/ + +/* Ĵ */ +#define FlashIAP_RegUnLock() (IAP->UL.UL = 0x49415055) +#define FlashIAP_RegLock() (IAP->UL.UL = 0x00000000) + +/* ʹIAP */ +#define FlashIAP_Enable() (IAP->CON.EN = 0x1) +#define FlashIAP_Disable() (IAP->CON.EN = 0x0) + +/* IAP */ +#define FlashIAP_REQ() (IAP->CON.FLASH_REQ = 0x1) + +/************Flashģ麯***********/ +ErrorStatus FlashIap_Close_WPROT(uint8_t Page); +ErrorStatus FlashIap_Open_WPROT(uint8_t Page); +ErrorStatus FlashIap_CloseAll_WPROT(void); +ErrorStatus FlashIap_OpenAll_WPROT(void); +ErrorStatus FlashIap_Unlock(void); +ErrorStatus FlashIap_WriteEnd(void); +ErrorStatus FlashIap_ErasePage(uint8_t Page_Addr); +ErrorStatus FlashIap_WriteCont(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32); +ErrorStatus FlashIap_WriteWord(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32); +ErrorStatus Flash_Read(uint32_t * Ram_Addr, uint32_t Flash_Addr, uint8_t Len); + +#endif +/*************************END OF FILE**********************/ + diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_gpio.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..301c6b286c8bd345e2cfd54e5b5d2a592a5a384c --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_gpio.h @@ -0,0 +1,243 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_gpio.h + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * GPIOģ鼰ⲿжϡжϿ⺯ͷļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBGPIO_H__ +#define __LIBGPIO_H__ + +#include "ES8P508x.h" +#include "type.h" + +/*״̬*/ + +/*˿ڶ*/ +typedef enum +{ + GPIOA = 0x0 , + GPIOB = 0x1 , +}GPIO_TYPE; + +/*Ŷ*/ +typedef enum +{ + GPIO_Pin_0 = 0x00, + GPIO_Pin_1 = 0x01, + GPIO_Pin_2 = 0x02, + GPIO_Pin_3 = 0x03, + GPIO_Pin_4 = 0x04, + GPIO_Pin_5 = 0x05, + GPIO_Pin_6 = 0x06, + GPIO_Pin_7 = 0x07, + GPIO_Pin_8 = 0x08, + GPIO_Pin_9 = 0x09, + GPIO_Pin_10 = 0x0A, + GPIO_Pin_11 = 0x0B, + GPIO_Pin_12 = 0x0C, + GPIO_Pin_13 = 0x0D, + GPIO_Pin_14 = 0x0E, + GPIO_Pin_15 = 0x0F, + GPIO_Pin_16 = 0x10, + GPIO_Pin_17 = 0x11, + GPIO_Pin_18 = 0x12, + GPIO_Pin_19 = 0x13, + GPIO_Pin_20 = 0x14, + GPIO_Pin_21 = 0x15, + GPIO_Pin_22 = 0x16, + GPIO_Pin_23 = 0x17, + GPIO_Pin_24 = 0x18, + GPIO_Pin_25 = 0x19, + GPIO_Pin_26 = 0x1A, + GPIO_Pin_27 = 0x1B, + GPIO_Pin_28 = 0x1C, + GPIO_Pin_29 = 0x1D, + GPIO_Pin_30 = 0x1E, + GPIO_Pin_31 = 0x1F, +}GPIO_TYPE_PIN; + +/* Źѡ */ +typedef enum +{ + GPIO_Func_0 = 0x0 , + GPIO_Func_1 = 0x1 , + GPIO_Func_2 = 0x2 , + GPIO_Func_3 = 0x3 , +}GPIO_TYPE_FUNC; + +/* ŷѡ */ +typedef enum +{ + GPIO_Dir_Out = 0x0 , + GPIO_Dir_In = 0x1 , +}GPIO_TYPE_DIR; + +/* ѡ */ +typedef enum +{ + GPIO_DS_Output_Normal = 0, // ͨ + GPIO_DS_Output_Strong = 1, // ǿ +} GPIO_TYPE_DS; + +/* ź */ +typedef enum { + GPIO_Pin_Signal_Digital = 0, // ź + GPIO_Pin_Signal_Analog = 1, // ģź +} GPIO_Pin_Signal; + +/* ʹ */ +typedef enum { + GPIO_PUE_Input_Disable = 0, // ֹ + GPIO_PUE_Input_Enable = 1, // ʹ +} GPIO_PUE_Input; + +/* ʹ */ +typedef enum { + GPIO_PDE_Input_Disable = 0, // ֹ + GPIO_PDE_Input_Enable = 1, // ʹ +} GPIO_PDE_Input; + + +/* ©ʹλ */ +typedef enum { + GPIO_ODE_Output_Disable = 0, // ©ֹ + GPIO_ODE_Output_Enable = 1, // ©ʹ +} GPIO_ODE_Output; + +/* GPIOʼýṹ嶨 */ +typedef struct +{ + GPIO_Pin_Signal GPIO_Signal; /* ϵźֻͣģ */ + GPIO_TYPE_FUNC GPIO_Func; //Źѡ + GPIO_TYPE_DIR GPIO_Direction; //ѡ + GPIO_PUE_Input GPIO_PUEN; //ʹ + GPIO_PDE_Input GPIO_PDEN; //ʹ + GPIO_ODE_Output GPIO_OD; //ģʽ©ʹ + GPIO_TYPE_DS GPIO_DS; // +}GPIO_InitStruType; + +/* PINT */ +typedef enum +{ + PINT0 = 0x0 , + PINT1 = 0x1 , + PINT2 = 0x2 , + PINT3 = 0x3 , + PINT4 = 0x4 , + PINT5 = 0x5 , + PINT6 = 0x6 , + PINT7 = 0x7 , +}PINT_TYPE; + +/* PINT SEL */ +typedef enum +{ + PINT_SEL0 = 0x0 , + PINT_SEL1 = 0x1 , + PINT_SEL2 = 0x2 , + PINT_SEL3 = 0x3 , + PINT_SEL4 = 0x4 , + PINT_SEL5 = 0x5 , + PINT_SEL6 = 0x6 , + PINT_SEL7 = 0x7 , +}PINT_TYPE_SEL; + +/* PINT Trigger */ +typedef enum +{ + PINT_Trig_Rise = 0x0 , + PINT_Trig_Fall = 0x1 , + PINT_Trig_High = 0x2 , + PINT_Trig_Low = 0x3 , + PINT_Trig_Change = 0x4 , +}PINT_TYPE_TRIG; + + +/* PINTжϱ־ */ +typedef enum +{ + PINT_IT_PINT0 = 0x01 , + PINT_IT_PINT1 = 0x02 , + PINT_IT_PINT2 = 0x04 , + PINT_IT_PINT3 = 0x08 , + PINT_IT_PINT4 = 0x10 , + PINT_IT_PINT5 = 0x20 , + PINT_IT_PINT6 = 0x40 , + PINT_IT_PINT7 = 0x80 , + PINT_IT_PINTAll = 0xFF , +}PINT_TYPE_IT; + +/* PINTʹܿ */ +#define PINT0_Enable() (GPIO->PINTIE.PINTIE |= 0X1) +#define PINT1_Enable() (GPIO->PINTIE.PINTIE |= 0x2) +#define PINT2_Enable() (GPIO->PINTIE.PINTIE |= 0x4) +#define PINT3_Enable() (GPIO->PINTIE.PINTIE |= 0x8) +#define PINT4_Enable() (GPIO->PINTIE.PINTIE |= 0x10) +#define PINT5_Enable() (GPIO->PINTIE.PINTIE |= 0x20) +#define PINT6_Enable() (GPIO->PINTIE.PINTIE |= 0x40) +#define PINT7_Enable() (GPIO->PINTIE.PINTIE |= 0x80) +#define PINT0_Disable() (GPIO->PINTIE.PINTIE &= ~0x01) +#define PINT1_Disable() (GPIO->PINTIE.PINTIE &= ~0x02) +#define PINT2_Disable() (GPIO->PINTIE.PINTIE &= ~0x04) +#define PINT3_Disable() (GPIO->PINTIE.PINTIE &= ~0x08) +#define PINT4_Disable() (GPIO->PINTIE.PINTIE &= ~0x10) +#define PINT5_Disable() (GPIO->PINTIE.PINTIE &= ~0x20) +#define PINT6_Disable() (GPIO->PINTIE.PINTIE &= ~0x40) +#define PINT7_Disable() (GPIO->PINTIE.PINTIE &= ~0x80) + +/* PINTʹܿ */ +#define PINT0_MaskEnable() (GPIO->PINTIE.PMASK |= 0X01) +#define PINT1_MaskEnable() (GPIO->PINTIE.PMASK |= 0x02) +#define PINT2_MaskEnable() (GPIO->PINTIE.PMASK |= 0x04) +#define PINT3_MaskEnable() (GPIO->PINTIE.PMASK |= 0x08) +#define PINT4_MaskEnable() (GPIO->PINTIE.PMASK |= 0x10) +#define PINT5_MaskEnable() (GPIO->PINTIE.PMASK |= 0x20) +#define PINT6_MaskEnable() (GPIO->PINTIE.PMASK |= 0x40) +#define PINT7_MaskEnable() (GPIO->PINTIE.PMASK |= 0x80) +#define PINT0_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x01) +#define PINT1_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x02) +#define PINT2_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x04) +#define PINT3_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x08) +#define PINT4_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x10) +#define PINT5_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x20) +#define PINT6_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x40) +#define PINT7_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x80) + +/* PINTжϱ */ +#define PINT_ClearAllITPending() (GPIO->PIF.Word = (uint32_t)0xff) + +void GPIO_Init(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_InitStruType* GPIO_InitStruct); +void GPIO_Write(GPIO_TYPE GPIOx, uint32_t Value); +uint32_t GPIO_Read(GPIO_TYPE GPIOx); +PinStatus GPIO_ReadBit(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx); +void GPIOA_SetBit(GPIO_TYPE_PIN PINx); +void GPIOA_ResetBit(GPIO_TYPE_PIN PINx); +void GPIOA_ToggleBit(GPIO_TYPE_PIN PINx); +void GPIOB_SetBit(GPIO_TYPE_PIN PINx); +void GPIOB_ResetBit(GPIO_TYPE_PIN PINx); +void GPIOB_ToggleBit(GPIO_TYPE_PIN PINx); +void GPIOA_SetDirection(GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir_Type); +void GPIOB_SetDirection(GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir_Type); +void PINT_Config(PINT_TYPE PINTx, PINT_TYPE_SEL SELx, PINT_TYPE_TRIG TRIGx); +void GPIO_SetSingalTypeFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_Pin_Signal GPIO_Signal); +void GPIO_SetDirRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir); +void GPIO_SetODERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_ODE_Output ODE); +void GPIO_SetDSRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DS DS); +void GPIO_SetPUERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PUE_Input PUE); +void GPIO_SetPDERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PDE_Input PDE); +void GPIO_SetFuncxRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_FUNC Func); +FlagStatus PINT_GetIFStatus(PINT_TYPE_IT PINT_Flag); +FlagStatus PINT_GetITStatus(PINT_TYPE_IT PINT_Flag); +void PINT_ClearITPendingBit(PINT_TYPE_IT PINT_Flag); + +#endif + + + + + + diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_iap.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_iap.h new file mode 100644 index 0000000000000000000000000000000000000000..61a404d3ea8444d7971abc5a26267fec77043139 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_iap.h @@ -0,0 +1,42 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ + * : Liut + * : V1.00 + * : 2017/07/14 + * + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __ES8P508x_IAP_TABLE_H +#define __ES8P508x_IAP_TABLE_H + +#include "ES8P508x.h" +#include "type.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IAP_PageProgram_addr 0x10000008 +#define IAP_PageErase_addr 0x10000000 +#define IAP_WordProgram_addr 0x10000004 + +typedef ErrorStatus (*IAP_PE)(uint32_t address); +typedef ErrorStatus (*IAP_WP)(uint32_t address, uint32_t data); +typedef ErrorStatus (*IAP_PP)(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase); + +ErrorStatus IAP_PageErase(uint32_t address); +ErrorStatus IAP_WordProgram(uint32_t address, uint32_t data); +ErrorStatus IAP_PageProgram(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase); +ErrorStatus IAPRead(uint32_t *Ram_Addr, uint32_t Flash_Addr, uint8_t Len); + +#define PageEraseEnable 0x00000001 +#define PageEraseDisable 0x00000000 + +#ifdef __cplusplus +} +#endif + +#endif +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_iic.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_iic.h new file mode 100644 index 0000000000000000000000000000000000000000..dae43c196478b52d17c20f2e96cdc4a35f751816 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_iic.h @@ -0,0 +1,229 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_iic.h + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * I2Cģ⺯ͷļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBIIC_H__ +#define __LIBIIC_H__ + +#include "ES8P508x.h" +#include "type.h" +#include "system_ES8P508x.h" + +/* ſ© */ +typedef enum +{ + I2C_PinMode_PP = 0x0 , //˿ģʽ: + I2C_PinMode_OD = 0x1 , //˿ģʽ:© +}I2C_TYPE_PINOD; + +/* ģʽ */ +typedef enum +{ + I2C_Mode_Master = 0x0 , //ģʽ + I2C_Mode_Slave = 0x1 , //ģʽ +}I2C_TYPE_MODE; + +/* Ӧʱ */ +typedef enum +{ + I2C_AckDelay_0P5 = 0x0 , //Ӧʱ:0.5ʱ + I2C_AckDelay_1 = 0x1 , //Ӧʱ:1ʱ + I2C_AckDelay_1P5 = 0x2 , //Ӧʱ:1.5ʱ + I2C_AckDelay_2 = 0x3 , //Ӧʱ:2ʱ + I2C_AckDelay_2P5 = 0x4 , //Ӧʱ:2.5ʱ + I2C_AckDelay_3 = 0x5 , //Ӧʱ:3ʱ + I2C_AckDelay_3P5 = 0x6 , //Ӧʱ:3.5ʱ + I2C_AckDelay_4 = 0x7 , //Ӧʱ:4ʱ +}I2C_TYPE_ADLY; + +/* ģʽ */ +typedef enum +{ + I2C_RecMode_0 = 0x0 , //ģʽ1ֽڣACK + I2C_RecMode_1 = 0x1 , //ģʽ1ֽڣNACK + I2C_RecMode_2 = 0x2 , //ģʽ2ֽڣÿֽڷACK + I2C_RecMode_3 = 0x3 , //ģʽ2ֽڣǰһֽڷACKһֽڷNACK + I2C_RecMode_4 = 0x4 , //ģʽ4ֽڣÿֽڷACK + I2C_RecMode_5 = 0x5 , //ģʽ4ֽڣǰ3ֽڷACKһֽڷNACK + I2C_RecMode_6 = 0x6, //ģʽգÿֽڷACK + I2C_RecMode_7 = 0x7, //ģʽɸֽڽգNACK +}I2C_TYPE_RECMODE; + +/* ֡ */ +typedef enum +{ + I2C_TI_Disable = 0x0 , //֡:0 + I2C_TI_1 = 0x1 , //֡:1 + I2C_TI_2 = 0x2 , //֡:2 + I2C_TI_3 = 0x3 , //֡:3 + I2C_TI_4 = 0x4 , //֡:4 + I2C_TI_5 = 0x5 , //֡:5 + I2C_TI_6 = 0x6 , //֡:6 + I2C_TI_7 = 0x7 , //֡:7 + I2C_TI_8 = 0x8 , //֡:8 + I2C_TI_9 = 0x9 , //֡:9 + I2C_TI_10 = 0xA , //֡:10 + I2C_TI_11 = 0xB , //֡:11 + I2C_TI_12 = 0xC , //֡:12 + I2C_TI_13 = 0xD , //֡:13 + I2C_TI_14 = 0xE , //֡:14 + I2C_TI_15 = 0xF , //֡:15 +}I2C_TYPE_TIS; + +/* I2Cʼýṹ嶨 */ +typedef struct +{ + I2C_TYPE_PINOD I2C_SclOd; //SCL˿ģʽ + + I2C_TYPE_PINOD I2C_SdaOd; //SDA˿ģʽ + + TYPE_FUNCEN I2C_16XSamp; //˿16ٲʹ + + uint32_t I2C_Clk; //I2CƵ + + I2C_TYPE_MODE I2C_Mode; //ģʽ + + TYPE_FUNCEN I2C_AutoStop; //Զֹͣ + + TYPE_FUNCEN I2C_AutoCall; //ԶѰ +}I2C_InitStruType; + +/* ͡жģʽ */ +typedef enum +{ + I2C_TRBIM_Byte = 0x0 , //ֽж + I2C_TRBIM_HalfWord = 0x1 , //ж + I2C_TRBIM_Word = 0x2 , //ж +}I2C_TYPE_TRBIM; + + +/* дģʽ */ +typedef enum +{ + I2C_Mode_Write = 0x0 , + I2C_Mode_Read = 0x1 , +}I2C_TYPE_RWMODE; + +/* жʹܱ־λ */ +typedef enum +{ + I2C_IT_SR = 0x0001 , //ʼλ + I2C_IT_SP = 0x0002 , //ֹͣλ + I2C_IT_TB = 0x0004 , //ͻ + I2C_IT_RB = 0x0008 , //ջ + I2C_IT_TE = 0x0010 , //ݴ + I2C_IT_RO = 0x0020 , // + I2C_IT_NA = 0x0040 , //δӦNACK + I2C_IT_TBWE = 0x0080 , //д + I2C_IT_TIDLE = 0x01000 , //Ϳж +}I2C_TYPE_IT; + +/* жϱ־λ */ +typedef enum +{ + I2C_Flag_SR = 0x0001 , //ʼλ + I2C_Flag_SP = 0x0002 , //ֹͣλ + I2C_Flag_TB = 0x0004 , //ͻ + I2C_Flag_RB = 0x0008 , //ջ + I2C_Flag_TE = 0x0010 , //ݴ + I2C_Flag_RO = 0x0020 , // + I2C_Flag_NA = 0x0040 , //δӦNACK + I2C_Flag_TBWE = 0x0080, //джϱ־λ + I2C_Flag_TIDLE= 0X1000, //I2C Ϳжϱ־λ +}I2C_TYPE_FLAG; + + +/* ־ */ +typedef enum +{ + I2C_Clr_SR = 0x0001 , //ʼλ + I2C_Clr_SP = 0x0002 , //ֹͣλ + I2C_Clr_TE = 0x0010 , //ݴ + I2C_Clr_RO = 0x0020 , // + I2C_Clr_NA = 0x0040 , //δӦNACK + I2C_Clr_TBWE = 0x0080 , //д + I2C_Clr_TIDLE= 0X01000, //I2C Ϳ +}I2C_CLR_IF; + + +/*************I2Cģ궨************/ + +/* I2Cģʹܿ */ +#define I2C_Enable() (I2C0->CON.EN = 1) +#define I2C_Disable() (I2C0->CON.EN = 0) + +/* I2Cģ鸴λ */ +#define I2C_Reset() (I2C0->CON.RST = 1) + +/* I2Cʱʹܿ */ +#define I2C_TJEnable() (I2C0->CON.TJE = 1) +#define I2C_TJDisable() (I2C0->CON.TJE = 0) + +/* I2Cģʽд */ +#define I2C_Read() (I2C0->CON.RW = 1) +#define I2C_Write() (I2C0->CON.RW = 0) + +/* I2CʱԶȴʹܿƣӻģʽ֧֣ */ +#define I2C_CSEnable() (I2C0->MOD.CSE = 1) +#define I2C_CSDisable() (I2C0->MOD.CSE = 0) + +/* I2CԶδӦʹܿƣӻģʽ֧֣ */ +#define I2C_ANAEnable() (I2C0->MOD.ANAE = 1) +#define I2C_ANADisable() (I2C0->MOD.ANAE = 0) + +/* I2CԶѰʹܿƣģʽ֧֣ */ +#define I2C_SRAEnable() (I2C0->MOD.SRAE = 1) +#define I2C_SRADisable() (I2C0->MOD.SRAE = 0) + +/* I2CԶʹܿƣģʽ֧֣ */ +#define I2C_SPAEnable() (I2C0->MOD.SPAE = 1) +#define I2C_SPADisable() (I2C0->MOD.SPAE = 0) + +/* I2Cʼλģʽ֧֣ */ +#define I2C_SRTrigger() (I2C0->MOD.SRT=1) + +/* I2Cֹͣλģʽ֧֣ */ +#define I2C_SPTrigger() (I2C0->MOD.SPT = 1) + +/* I2Cݴģʽ֧֣ */ +#define I2C_RDTrigger() (I2C0->MOD.RDT = 1) + + +/* I2Cͷ */ +#define I2C_Release() (I2C0->MOD.BLD = 1) + +/* I2CӦãӻģʽ֧֣ */ +#define I2C_TACK() (I2C0->MOD.TAS = 1) +#define I2C_TNACK() (I2C0->MOD.TAS = 0) + +/************I2Cģ麯***********/ +void I2C_Init(I2C_InitStruType* I2C_InitStruct); +void I2C_ITConfig(I2C_TYPE_IT I2C_IT,TYPE_FUNCEN NewState); +void I2C_SendAddress(uint8_t I2C_Address,I2C_TYPE_RWMODE Mode); +void I2C_SetAddress(uint8_t I2C_Address); +void I2C_RecModeConfig(I2C_TYPE_RECMODE RecType); +void I2C_TBIMConfig(I2C_TYPE_TRBIM Type); +void I2C_RBIMConfig(I2C_TYPE_TRBIM Type); +void I2C_AckDelay(I2C_TYPE_ADLY Type,TYPE_FUNCEN NewStatus); +void I2C_TISConfig(I2C_TYPE_TIS Time); +void I2C_SendByte(uint8_t Byte); +void I2C_SendHalfWord(uint16_t HalfWord); +void I2C_SendWord(uint32_t Word); +uint8_t I2C_RecByte(void); +uint16_t I2C_RecHalfWord(void); +uint32_t I2C_RecWord(void); +I2C_TYPE_RWMODE I2C_GetRWMode(void); +FlagStatus I2C_GetTBStatus(void); +FlagStatus I2C_GetFlagStatus(I2C_TYPE_FLAG I2C_Flag); +FlagStatus I2C_GetITStatus( I2C_TYPE_IT I2C_Flag); +void I2C_ClearITPendingBit(I2C_CLR_IF I2C_IT); + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_printf.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_printf.h new file mode 100644 index 0000000000000000000000000000000000000000..7bee613c8a586b4fb8a5e6041d69190a657e3b0b --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_printf.h @@ -0,0 +1,33 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_printf.h + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ڴӡ⺯ͷļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBPRINTF_H__ +#define __LIBPRINTF_H__ + +#include "lib_uart.h" +#include +#include "type.h" + +int fputc(int ch, FILE *f); +static char *itoa(int value, char *string, int radix); +ErrorStatus UART_printf(uint8_t *Data,...); + +#ifdef __clang__ +ErrorStatus UART_printf(uint8_t *Data, ...); + +#elif defined __CC_ARM + +#define UART_printf printf + +#endif + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_rtc.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..86dbb5bcc45548f020636166088b1078712d8cab --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_rtc.h @@ -0,0 +1,84 @@ +/********************************************************* + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ: lib_rtc.h + * : WangMX + * : V1.00 + * : 2017/07/14 + * : RTCģͷļ + * ע: HRSDK-GDB-ES8P508x V1.1 + ѧϰʾʹãûֱôķջеκηΡ + **********************************************************/ +#ifndef __LIBRTC_H__ +#define __LIBRTC_H__ + +#include "ES8P508x.h" +#include "type.h" + +/*RTCʱԴѡ*/ +typedef enum +{ + RTC_LOSC = 0x0, //ⲿ32768HZʱ RTCȷʱ + RTC_LRC = 0x1, //ڲLRCʱ RTCǾȷʱ + RTC_PLCK_256 = 0x2, //PLCLK/256 RTCͨ + RTC_PLCK = 0x3, //PCLK RTCͨ +}RTC_TYPE_CLKS; + +/*RTCʱ12/24Сʱѡ*/ +typedef enum +{ + RTC_HOUR12 = 0x0, //12Сʱ + RTC_HOUR24 = 0x1, //24Сʱ +}RTC_TYPE_TIME; + +/* RTCжԴѡ */ +typedef enum { + RTC_Interrupt_Source_Second = 0x001, // ж + RTC_Interrupt_Source_Minute = 0x002, // ж + RTC_Interrupt_Source_Hour = 0x004, // Сʱж + RTC_Interrupt_Source_Day = 0x008, // ж + RTC_Interrupt_Source_Month = 0x010, // ж + RTC_Interrupt_Source_DayALE = 0x100, // ж + RTC_Interrupt_Source_WeekALE = 0x200, // ж +} RTC_Interrupt_Source; + + +/********************* RTCģ麯 *********************/ +void RTC_Init(RTC_TYPE_CLKS CLKx,RTC_TYPE_TIME HOURx); +uint32_t RTC_ReadHourmode(void); +uint32_t RTC_ReadSecond(void); +uint32_t RTC_ReadMinute(void); +uint32_t RTC_ReadHour(uint32_t *meridiem); +uint32_t RTC_ReadDay(void); +uint32_t RTC_ReadMonth(void); +uint32_t RTC_ReadYear(void); +uint32_t RTC_ReadWeek(void); + +ErrorStatus RTC_WriteSecond(uint32_t second); +ErrorStatus RTC_WriteMinute(uint32_t minute); +ErrorStatus RTC_WriteHour(uint32_t hour, uint32_t meridiem); +ErrorStatus RTC_WriteDay(uint32_t day); +ErrorStatus RTC_WriteMonth(uint32_t month); +ErrorStatus RTC_WriteYear(uint32_t year); +ErrorStatus RTC_WriteWeek(uint32_t week); + +uint32_t RTC_ReadWeekAlarmMinute(void); +uint32_t RTC_ReadWeekAlarmHour(uint32_t *meridiem); +uint32_t RTC_ReadWeekAlarmWeek(void); +uint32_t RTC_ReadDayAlarmMinute(void); +uint32_t RTC_ReadDayAlarmHour(uint32_t *meridiem); + +ErrorStatus RTC_WriteWeekAlarmMinute(uint32_t minute); +ErrorStatus RTC_WriteWeekAlarmHour(uint32_t hour, uint32_t meridiem); +ErrorStatus RTC_WriteWeekAlarmWeek(uint32_t week); +ErrorStatus RTC_WriteDayAlarmMinute(uint32_t minute); +ErrorStatus RTC_WriteDayAlarmHour(uint32_t hour, uint32_t meridiem); + +void RTC_InterruptEnable(RTC_Interrupt_Source src); +void RTC_InterruptDisable(RTC_Interrupt_Source src); +ITStatus RTC_GetITStatus(RTC_Interrupt_Source src); +FlagStatus RTC_GetFlagStatus(RTC_Interrupt_Source src); +void RTC_ClearITPendingBit(RTC_Interrupt_Source src); + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_scs.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_scs.h new file mode 100644 index 0000000000000000000000000000000000000000..e69c9a674f2a811a81f9657848a82634b7cf51ed --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_scs.h @@ -0,0 +1,98 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_scs.h + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ںģ⺯ͷļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBNVIC_H__ +#define __LIBNVIC_H__ + +#include "ES8P508x.h" +#include "type.h" + +/* жԴѡ */ +typedef enum +{ + NVIC_PINT0_IRQn = 0, + NVIC_PINT1_IRQn = 1, + NVIC_PINT2_IRQn = 2, + NVIC_PINT3_IRQn = 3, + NVIC_PINT4_IRQn = 4, + NVIC_PINT5_IRQn = 5, + NVIC_PINT6_IRQn = 6, + NVIC_PINT7_IRQn = 7, + NVIC_T16N0_IRQn = 8, + NVIC_T16N1_IRQn = 9, + NVIC_T16N2_IRQn = 10, + NVIC_T16N3_IRQn = 11, + NVIC_T32N0_IRQn = 12, + NVIC_IWDT_IRQn = 14, + NVIC_WWDT_IRQn = 15, + NVIC_CCM_IRQn = 16, + NVIC_PLK_IRQn = 17, + NVIC_LVD_IRQn = 18, + NVIC_KINT_IRQn = 19, + NVIC_RTC_IRQn = 20, + NVIC_ADC_IRQn = 21, + NVIC_AES_IRQn = 23, + NVIC_UART0_IRQn = 24, + NVIC_UART1_IRQn = 25, + NVIC_UART2_IRQn = 26, + NVIC_UART3_IRQn = 27, + NVIC_UART4_IRQn = 28, + NVIC_UART5_IRQn = 29, + NVIC_SPI0_IRQn = 30, + NVIC_I2C0_IRQn = 31, +}NVIC_IRQChannel; + +/* ȼ */ +typedef enum +{ + NVIC_Priority_0 = 0x0 , + NVIC_Priority_1 = 0x1 , + NVIC_Priority_2 = 0x2 , + NVIC_Priority_3 = 0x3 , +}NVIC_IRQPriority; + +/* ģʽ */ +typedef enum +{ + SCB_LP_SleepOnExit = 0x02 , //ISRжϴ򷵻ص߳ģʽʱǷ + SCB_LP_SleepDeep = 0x04 , //˯ + SCB_LP_SEVOPend = 0x10 , //жϹʱǷΪѵѡλ +}SCB_TYPE_SCR; + +/* SysTickʱԴѡ */ +typedef enum +{ + SysTick_ClkS_Base = 0x0 , //׼ʱ(Hclk/3) + SysTick_ClkS_Cpu = 0x1 , //ʱ(Hclk) +}SYST_TYPE_CLKS; + +/* SysTickʼýṹ嶨 */ +typedef struct +{ + uint32_t SysTick_Value; //ݼֵ24λҶ + SYST_TYPE_CLKS SysTick_ClkSource; //ʱԴѡ + TYPE_FUNCEN SysTick_ITEnable; //жʹܡʧ +}SYSTICK_InitStruType; + +/**************ģ궨*************/ + +/*SysTickʹ*/ +#define SysTick_Enable() (SysTick->CTRL |= 0x00000001) +#define SysTick_Disable() (SysTick->CTRL &= 0xFFFFFFFE) + +/************SCSģ麯***********/ +void NVIC_Init(NVIC_IRQChannel Channel,NVIC_IRQPriority Priority,TYPE_FUNCEN Cmd); +void SCB_SystemLPConfig(SCB_TYPE_SCR LowPowerMode, TYPE_FUNCEN NewState); +uint32_t SCB_GetCpuID(void); +void SysTick_Init(SYSTICK_InitStruType* SysT_InitStruct); + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_scu.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_scu.h new file mode 100644 index 0000000000000000000000000000000000000000..a07440153b6a9f518ac85225eac473b910c9d48c --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_scu.h @@ -0,0 +1,314 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_scu.h + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ںģ⺯ͷļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBSCU_H +#define __LIBSCU_H + +#include "system_ES8P508x.h" +#include "ES8P508x.h" +#include "type.h" + +/* NMIжѡ */ +typedef enum +{ + SCU_PINT0_IRQn = 0, + SCU_PINT1_IRQn = 1, + SCU_PINT2_IRQn = 2, + SCU_PINT3_IRQn = 3, + SCU_PINT4_IRQn = 4, + SCU_PINT5_IRQn = 5, + SCU_PINT6_IRQn = 6, + SCU_PINT7_IRQn = 7, + SCU_T16N0_IRQn = 8, + SCU_T16N1_IRQn = 9, + SCU_T16N2_IRQn = 10, + SCU_T16N3_IRQn = 11, + SCU_T32N0_IRQn = 12, + SCU_IWDT_IRQn = 14, + SCU_WWDT_IRQn = 15, + SCU_CCM_IRQn = 16, + SCU_PLK_IRQn = 17, + SCU_LVD_IRQn = 18, + SCU_KINT_IRQn = 19, + SCU_RTC_IRQn = 20, + SCU_ADC_IRQn = 21, + SCU_AES_IRQn = 23, + SCU_UART0_IRQn = 24, + SCU_UART1_IRQn = 25, + SCU_UART2_IRQn = 26, + SCU_UART3_IRQn = 27, + SCU_UART4_IRQn = 28, + SCU_UART5_IRQn = 29, + SCU_SPI0_IRQn = 30, + SCU_I2C0_IRQn = 31, +}SCU_TYPE_NMICS; + +/* PWRCλ״̬Ĵ־λ */ +typedef enum +{ + SCU_PWRC_PORF= 0X00001, //PORλ־λ + SCU_PWRC_RRCF = 0X00002, //PORCλ־λ + SCU_PWRC_PORRSTF = 0x00004, //PORܸλ־ + SCU_PWRC_BORF = 0x00008, //BORܸλ־ + SCU_PWRC_WWDTRSTF = 0x00010, //WWDTλ־ + SCU_PWRC_IWDTRSTF = 0x00020, //IWDTλ־ + SCU_PWRC_MRSTF = 0x00040, //MRSTnλ־ + SCU_PWRC_SOFTRSTF = 0x00080, //λ־ +}SCU_TYPE_PWRC; + +/* LVDĴ־λ */ +typedef enum +{ + SCU_LVDFlag_IF = 0x0100, //LVDжϱ־ + SCU_LVDFlag_Out = 0x8000, //״̬λ +}SCU_TYPE_LVD0CON; + +/* ʱѡ */ +typedef enum +{ + SCU_SysClk_HRC = 0x0 , //ڲ20MHZ RCʱ + SCU_SysClk_XTAL = 0x1 , //ⲿʱ + SCU_SysClk_PLL = 0x2 , //PLL +}SCU_TYPE_SYSCLK; + +/*clk_selʱԴѡ*/ +typedef enum +{ + CLK_SEL_HRC = 0x0, //HRC 20M + CLK_SEL_LRC = 0x1, //LRC 32KHz + CLK_SEL_XTAL = 0x2, //ӾXTAL +}SCU_TYPE_CLK_SEL; + +/* PLLʱԴѡ */ +typedef enum +{ + SCU_PLL_HRC = 0x0 , //PLLʱԴHRC + SCU_PLL_LRC = 0x2 , //PLLʱԴLRC + SCU_PLL_XTAL_32K = 0x3 , //PLLʱԴXTAL + SCU_PLL_XTAL_4M = 0x4 , //PLLʱԴXTAL + SCU_PLL_XTAL_8M = 0x5, //PLLʱԴXTAL + SCU_PLL_XTAL_16M = 0x6, //PLLʱԴXTAL + SCU_PLL_XTAL_20M = 0x7, //PLLʱԴXTAL +} SCU_PLL_Origin; + +/* PLLʱƵ */ +typedef enum +{ + SCU_PLL_32M = 0x0 , //PLLʱΪ32MHz + SCU_PLL_48M = 0x1 , //PLLʱΪ48Mhz +} SCU_PLL_Out; + +/************SCUģ궨***********/ +/* SCUд */ +#define SCU_RegUnLock() (SCU->PROT.Word = 0x55AA6996) +#define SCU_RegLock() (SCU->PROT.Word = 0x00000000) + +/* NMIʹܿ */ +#define SCU_NMI_Enable() (SCU->NMICON.NMIEN = 0x1) +#define SCU_NMI_Disable() (SCU->NMICON.NMIEN = 0x0) + +/*-------LVDģ-------*/ + +/* LVDʹܿ */ +#define SCU_LVD_Enable() (SCU->LVDCON.EN = 0x1) +#define SCU_LVD_Disable() (SCU->LVDCON.EN = 0x0) + +/* LVD˲ʹܿ */ +#define SCU_LVDFLT_Enable() (SCU->LVDCON.FLTEN = 0x1) +#define SCU_LVDFLT_Disable() (SCU->LVDCON.FLTEN = 0x0) + +/* LVDѹѡ */ +#define SCU_LVDVS_2V0() (SCU->LVDCON.VS = 0x0) +#define SCU_LVDVS_2V1() (SCU->LVDCON.VS = 0x1) +#define SCU_LVDVS_2V2() (SCU->LVDCON.VS = 0x2) +#define SCU_LVDVS_2V4() (SCU->LVDCON.VS = 0x3) +#define SCU_LVDVS_2V6() (SCU->LVDCON.VS = 0x4) +#define SCU_LVDVS_2V8() (SCU->LVDCON.VS = 0x5) +#define SCU_LVDVS_3V0() (SCU->LVDCON.VS = 0x6) +#define SCU_LVDVS_3V6() (SCU->LVDCON.VS = 0x7) +#define SCU_LVDVS_4V() (SCU->LVDCON.VS = 0x8) +#define SCU_LVDVS_4V6() (SCU->LVDCON.VS = 0x9) +#define SCU_LVDVS_2V3() (SCU->LVDCON.VS = 0xA) +#define SCU_LVDVS_LVDIN() (SCU->LVDCON.VS = 0xE) + +/* LVDжʹܿ */ +#define SCU_LVDIT_Enable() (SCU->LVDCON.IE = 0x1) +#define SCU_LVDIT_Disable() (SCU->LVDCON.IE = 0x0) + +/* LVDжϱ־λ */ +#define SCU_LVDClearIFBit() (SCU->LVDCON.IF = 1) + +/* LVDжϲģʽѡ */ +#define SCU_LVDIFS_Rise() (SCU->LVDCON.IFS = 0x0) //LVDOزж +#define SCU_LVDIFS_Fall() (SCU->LVDCON.IFS = 0x1) //LVDO½زж +#define SCU_LVDIFS_High() (SCU->LVDCON.IFS = 0x2) //LVDOߵƽж +#define SCU_LVDIFS_Low() (SCU->LVDCON.IFS = 0x3) //LVDO͵ƽж +#define SCU_LVDIFS_Change() (SCU->LVDCON.IFS = 0x4) //LVDOƽ仯ж + +/* FLASHʵȴʱѡ */ +#define SCU_FlashWait_1Tclk() (SCU->FLASHWAIT.ACCT = 0x0) +#define SCU_FlashWait_2Tclk() (SCU->FLASHWAIT.ACCT = 0x1) +#define SCU_FlashWait_3Tclk() (SCU->FLASHWAIT.ACCT = 0x2) +#define SCU_FlashWait_4Tclk() (SCU->FLASHWAIT.ACCT = 0x3) +#define SCU_FlashWait_5Tclk() (SCU->FLASHWAIT.ACCT = 0x4) +#define SCU_FlashWait_6Tclk() (SCU->FLASHWAIT.ACCT = 0x5) +#define SCU_FlashWait_7Tclk() (SCU->FLASHWAIT.ACCT = 0x6) +#define SCU_FlashWait_8Tclk() (SCU->FLASHWAIT.ACCT = 0x7) +#define SCU_FlashWait_9Tclk() (SCU->FLASHWAIT.ACCT = 0x8) +#define SCU_FlashWait_10Tclk() (SCU->FLASHWAIT.ACCT = 0x9) +#define SCU_FlashWait_11Tclk() (SCU->FLASHWAIT.ACCT = 0xA) +#define SCU_FlashWait_12Tclk() (SCU->FLASHWAIT.ACCT = 0xB) +#define SCU_FlashWait_13Tclk() (SCU->FLASHWAIT.ACCT = 0xC) +#define SCU_FlashWait_14Tclk() (SCU->FLASHWAIT.ACCT = 0xD) +#define SCU_FlashWait_15Tclk() (SCU->FLASHWAIT.ACCT = 0xE) +#define SCU_FlashWait_16Tclk() (SCU->FLASHWAIT.ACCT = 0xF) + +/* ϵͳʱӺƵѡ */ +#define SCU_SysClk_Div1() (SCU->SCLKEN0.SYSCLK_DIV = 0) +#define SCU_SysClk_Div2() (SCU->SCLKEN0.SYSCLK_DIV = 1) +#define SCU_SysClk_Div4() (SCU->SCLKEN0.SYSCLK_DIV = 2) +#define SCU_SysClk_Div8() (SCU->SCLKEN0.SYSCLK_DIV = 3) +#define SCU_SysClk_Div16() (SCU->SCLKEN0.SYSCLK_DIV = 4) +#define SCU_SysClk_Div32() (SCU->SCLKEN0.SYSCLK_DIV = 5) +#define SCU_SysClk_Div64() (SCU->SCLKEN0.SYSCLK_DIV = 6) +#define SCU_SysClk_Div128() (SCU->SCLKEN0.SYSCLK_DIV = 7) + +/* HRCʹܿ (ڲ20Mhz) */ +#define SCU_HRC_Enable() (SCU->SCLKEN1.HRC_EN = 1) +#define SCU_HRC_Disable() (SCU->SCLKEN1.HRC_EN = 0) + +/* XTALʹܿ */ +#define SCU_XTAL_Enable() (SCU->SCLKEN1.XTAL_EN = 1) +#define SCU_XTAL_Disable() (SCU->SCLKEN1.XTAL_EN = 0) + +/* PLLģʽʹܿ */ +#define SCU_PLL_Enable() (SCU->SCLKEN1.PLL_EN = 1) +#define SCU_PLL_Disable() (SCU->SCLKEN1.PLL_EN = 0) + +/*-------ʱӿ-------*/ +/* SCUʱʹܿ */ +#define SCU_SCUCLK_Enable() (SCU->PCLKEN0.SCU_EN = 1) +#define SCU_SCUCLK_Disable() (SCU->PCLKEN0.SCU_EN = 0) + +/* GPIOʱʹܿ */ +#define SCU_GPIOCLK_Enable() (SCU->PCLKEN0.GPIO_EN = 1) +#define SCU_GPIOCLK_Disable() (SCU->PCLKEN0.GPIO_EN = 0) + +/* FLASH IAPʱʹܿ */ +#define SCU_IAPCLK_Enable() (SCU->PCLKEN0.IAP_EN = 1) +#define SCU_IAPCLK_Disable() (SCU->PCLKEN0.IAP_EN = 0) + +/* CRCʱʹܿ */ +#define SCU_CRCCLK_Enable() (SCU->PCLKEN0.CRC_EN = 1) +#define SCU_CRCCLK_Disable() (SCU->PCLKEN0.CRC_EN = 0) + +/* ADCʱʹܿ */ +#define SCU_ADCCLK_Enable() (SCU->PCLKEN0.ADC_EN = 1) +#define SCU_ADCCLK_Disable() (SCU->PCLKEN0.ADC_EN = 0) + +/* RTCʱʹܿ */ +#define SCU_RTCCLK_Enable() (SCU->PCLKEN0.RTC_EN = 1) +#define SCU_RTCCLK_Disable() (SCU->PCLKEN0.RTC_EN = 0) + +/* IWDTʱʹܿ */ +#define SCU_IWDTCLK_Enable() (SCU->PCLKEN0.IWDT_EN = 1) +#define SCU_IWDTCLK_Disable() (SCU->PCLKEN0.IWDT_EN = 0) + +/* WWDTʱʹܿ */ +#define SCU_WWDTCLK_Enable() (SCU->PCLKEN0.WWDT_EN = 1) +#define SCU_WWDTCLK_Disable() (SCU->PCLKEN0.WWDT_EN = 0) + +/* AESʱʹܿ */ +#define SCU_AESCLK_Enable() (SCU->PCLKEN0.AES_EN = 1) +#define SCU_AESCLK_Disable() (SCU->PCLKEN0.AES_EN = 0) + +/* T16N0ʱʹܿ */ +#define SCU_T16N0CLK_Enable() (SCU->PCLKEN1.T16N0_EN = 1) +#define SCU_T16N0CLK_Disable() (SCU->PCLKEN1.T16N0_EN = 0) + +/* T16N1ʱʹܿ */ +#define SCU_T16N1CLK_Enable() (SCU->PCLKEN1.T16N1_EN = 1) +#define SCU_T16N1CLK_Disable() (SCU->PCLKEN1.T16N1_EN = 0) + +/* T16N2ʱʹܿ */ +#define SCU_T16N2CLK_Enable() (SCU->PCLKEN1.T16N2_EN = 1) +#define SCU_T16N2CLK_Disable() (SCU->PCLKEN1.T16N2_EN = 0) + +/* T16N3ʱʹܿ */ +#define SCU_T16N3CLK_Enable() (SCU->PCLKEN1.T16N3_EN = 1) +#define SCU_T16N3CLK_Disable() (SCU->PCLKEN1.T16N3_EN = 0) + +/* T32N0ʱʹܿ */ +#define SCU_T32N0CLK_Enable() (SCU->PCLKEN1.T32N0_EN = 1) +#define SCU_T32N0CLK_Disable() (SCU->PCLKEN1.T32N0_EN = 0) + +/* UART0ʱʹܿ */ +#define SCU_UART0CLK_Enable() (SCU->PCLKEN1.UART0_EN = 1) +#define SCU_UART0CLK_Disable() (SCU->PCLKEN1.UART0_EN = 0) + +/* UART1ʱʹܿ */ +#define SCU_UART1CLK_Enable() (SCU->PCLKEN1.UART1_EN = 1) +#define SCU_UART1CLK_Disable() (SCU->PCLKEN1.UART1_EN = 0) + +/* UART2ʱʹܿ */ +#define SCU_UART2CLK_Enable() (SCU->PCLKEN1.UART2_EN = 1) +#define SCU_UART2CLK_Disable() (SCU->PCLKEN1.UART2_EN = 0) + +/* UART3ʱʹܿ */ +#define SCU_UART3CLK_Enable() (SCU->PCLKEN1.UART3_EN = 1) +#define SCU_UART3CLK_Disable() (SCU->PCLKEN1.UART3_EN = 0) + +/* UART4ʱʹܿ */ +#define SCU_UART4CLK_Enable() (SCU->PCLKEN1.UART4_EN = 1) +#define SCU_UART4CLK_Disable() (SCU->PCLKEN1.UART4_EN = 0) + +/* UART5ʱʹܿ */ +#define SCU_UART5CLK_Enable() (SCU->PCLKEN1.UART5_EN = 1) +#define SCU_UART5CLK_Disable() (SCU->PCLKEN1.UART5_EN = 0) + +/* SPI0ʱʹܿ */ +#define SCU_SPI0CLK_Enable() (SCU->PCLKEN1.SPI0_EN = 1) +#define SCU_SPI0CLK_Disable() (SCU->PCLKEN1.SPI0_EN = 0) + +/* IIC0ʱʹܿ */ +#define SCU_IIC0CLK_Enable() (SCU->PCLKEN1.I2C0_EN = 1) +#define SCU_IIC0CLK_Disable() (SCU->PCLKEN1.I2C0_EN = 0) + +/* жӳʹܿ */ +#define SCU_TBLRemap_Enable() (SCU->TBLREMAPEN.EN= 1) +#define SCU_TBLRemap_Disable() (SCU->TBLREMAPEN.EN= 0) + +/* жƫƼĴ xΪ2^24=16777216 */ +#define SCU_TBL_Offset(x) (SCU->TBLOFF.TBLOFF = (uint32_t)x) + +/************SCUģ麯***********/ +void SCU_OpenXTAL(void); +void SCU_NMISelect(SCU_TYPE_NMICS NMI_Type); +FlagStatus SCU_GetPWRCFlagStatus(SCU_TYPE_PWRC PWRC_Flag); +void SCU_ClearPWRCFlagBit(SCU_TYPE_PWRC PWRC_Flag); +FlagStatus SCU_GetLVDFlagStatus(SCU_TYPE_LVD0CON LVD_Flag); +void SCU_SysClkSelect(SCU_TYPE_SYSCLK Sysclk); +SCU_TYPE_SYSCLK SCU_GetSysClk(void); +FlagStatus SCU_HRCReadyFlag(void); +FlagStatus SCU_XTALReadyFlag(void); +FlagStatus SCU_PLLReadyFlag(void); +void SystemClockConfig(void); +void SystemClockConfig_1(void); +void DeviceClockAllEnable(void); +void DeviceClockAllDisable(void); +void SystemClockSelect(SCU_TYPE_SYSCLK SYSCLKx , SCU_TYPE_CLK_SEL CLK_SEL); +void PLLClock_Config(TYPE_FUNCEN pll_en , SCU_PLL_Origin pll_origin ,SCU_PLL_Out pll_out,TYPE_FUNCEN sys_pll); +#endif +/*************************END OF FILE**********************/ + + + + + diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_spi.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..8089ae8b66cf3a095b075968d3605b739b5383d7 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_spi.h @@ -0,0 +1,141 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_spi.h + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * SPIģ⺯ͷļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBSPI_H__ +#define __LIBSPI_H__ + +#include "system_ES8P508x.h" +#include "ES8P508x.h" +#include "type.h" + +/* ͨݸʽ */ +typedef enum +{ + SPI_RiseSendFallRec = 0x0 , //ͨݸʽطͣȣ½ؽգ + SPI_FallSendRiseRec = 0x1 , //ͨݸʽ½طͣȣؽգ + SPI_RiseRecFallSend = 0x2 , //ͨݸʽؽգȣ½طͣ + SPI_FallRecRiseSend = 0x3 , //ͨݸʽ½ؽգȣطͣ +}SPI_TYPE_DFS; + +/* ͨѶģʽ */ +typedef enum +{ + SPI_Mode_Master = 0x0 , //ͨѶģʽ + SPI_Mode_Slave = 0x1 , //ͨѶģʽӶ +}SPI_TYPE_MODE; + +/* ADCʼýṹ嶨 */ +typedef struct +{ + uint32_t SPI_Freq; //SPIƵ + + SPI_TYPE_DFS SPI_Df; //ͨѶݸʽ + + SPI_TYPE_MODE SPI_Mode; //ͨѶģʽ + + uint8_t SPI_DW; //֡λ + + TYPE_FUNCEN SPI_DelayRec; //ʱʹ + + TYPE_FUNCEN SPI_DelaySend; //ͼʹ + + uint8_t SPI_SendDelayPeroid;//ͼ + +}SPI_InitStruType; + +/* ־λ */ +typedef enum +{ + SPI_Flag_TB = 0x00000001, + SPI_Flag_RB = 0x00000002, + SPI_Flag_TE = 0x00000004, + SPI_Flag_RO = 0x00000008, + SPI_Flag_ID = 0x00000010, + SPI_Flag_NSSIF = 0x00000020, + SPI_Flag_TBWE = 0x00000040, + SPI_Flag_NSS = 0x00000080, + SPI_Flag_TBEF0 = 0x00000100, + SPI_Flag_TBEF1 = 0x00000200, + SPI_Flag_TBEF2 = 0x00000400, + SPI_Flag_TBEF3 = 0x00000800, + SPI_Flag_RBFF0 = 0x00001000, + SPI_Flag_RBFF1 = 0x00002000, + SPI_Flag_RBFF2 = 0x00004000, + SPI_Flag_RBFF3 = 0x00008000, + SPI_Flag_IDLE = 0x00010000, + SPI_Flag_TMS = 0x00020000, +}SPI_TYPE_FLAG; + +/* жģʽѡ */ +typedef enum +{ + SPI_IType_BYTE = 0x0 , + SPI_IType_HALFWORD = 0x1 , + SPI_IType_WORD = 0x2 , +}SPI_TYPE_TRBIM; + +/* SPIж */ +typedef enum +{ + SPI_IT_TB = 0x01 , + SPI_IT_RB = 0x02 , + SPI_IT_TE = 0x04 , + SPI_IT_RO = 0x08 , + SPI_IT_ID = 0x10 , + SPI_IT_NSS = 0x20 , + SPI_IT_TBWE = 0x40 , +}SPI_TYPE_IT; + +/* SPIжϱ־ */ +typedef enum +{ + SPI_Clr_TE = 0x04 , + SPI_Clr_RO = 0x08 , + SPI_Clr_ID = 0x10 , + SPI_Clr_NSS = 0x20 , + SPI_Clr_TBWE = 0x40 , +}SPI_CLR_IF; + +/************SPIģ궨***********/ + +/* SPIʹܿ */ +#define SPI_Enable() (SPI0->CON.EN = 1) +#define SPI_Disable() (SPI0->CON.EN = 0) + +/* SPIʹܿ */ +#define SPI_RecEnable() (SPI0->CON.REN = 1) +#define SPI_RecDisable() (SPI0->CON.REN = 0) + +/* SPIλ */ +#define SPI_Rst() (SPI0->CON.RST = 1) + +/* SPI */ +#define SPI_RX_CLR() (SPI0->CON.RXCLR = 1) +#define SPI_TX_CLR() (SPI0->CON.TXCLR = 1) + +/************SPIģ麯***********/ +void SPI_Init(SPI_InitStruType* SPI_InitStruct); +void SPI_ITConfig(SPI_TYPE_IT SPI_IE,TYPE_FUNCEN NewState); +void SPI_DataFormatConfig(SPI_TYPE_DFS Type); +void SPI_SendByte(uint8_t Temp); +void SPI_SendHalfWord(uint16_t Temp); +void SPI_SendWord(uint32_t Temp); +uint8_t SPI_RecByte(void); +uint16_t SPI_RecHalfWord(void); +uint32_t SPI_RecWord(void); +void SPI_TBIMConfig(SPI_TYPE_TRBIM Type); +void SPI_RBIMConfig(SPI_TYPE_TRBIM Type); +FlagStatus SPI_GetFlagStatus(SPI_TYPE_FLAG Flag); +ITStatus SPI_GetITStatus(SPI_TYPE_IT Flag); +void SPI_ClearITPendingBit(SPI_CLR_IF Flag); + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_timer.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..d5493c8e3a7af964e4ebb617a941f0448c3d4fad --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_timer.h @@ -0,0 +1,310 @@ +/****************************************************************************************** + * Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + * ļ: lib_timer.h + * : Liut + * : V1.00 + * : 2017/07/14 + * : 16λʱ/32λʱ/⺯ͷļ + * ע: ES8P508xϵоƬ + * ѧϰʾʹãûֱôķջеκηΡ + *******************************************************************************************/ +#ifndef __LIBTIMER_H__ +#define __LIBTIMER_H__ + +#include "ES8P508x.h" +#include "type.h" + +/* ʱԴѡ */ +typedef enum +{ + TIM_ClkS_PCLK = 0x0 , //ʱԴѡ:ڲPCLK + TIM_ClkS_CK0 = 0x1 , //ʱԴѡ:ⲿCK0ʱ + TIM_ClkS_CK1 = 0x2 , //ʱԴѡ:ⲿCK1ʱ +}TIM_TYPE_CLKS; + +/* ⲿʱӼѡ */ +typedef enum +{ + TIM_EDGE_Rise = 0x0 , //ⲿʱӼѡ: + TIM_EDGE_Fall = 0x1 , //ⲿʱӼѡ:½ + TIM_EDGE_All = 0x2 , //ⲿʱӼѡ: +}TIM_TYPE_EDGE; + + +/* ģʽѡ */ +typedef enum +{ + TIM_Mode_TC0 = 0x0 , //ģʽ:ʱģʽ + TIM_Mode_TC1 = 0x1 , //ģʽ:ʱģʽ + TIM_Mode_CAP = 0x2 , //ģʽ:׽ģʽ + TIM_Mode_PWM = 0x3 , //ģʽ:ģʽ +}TIM_TYPE_MODE; + +/* TIMʼýṹ嶨 */ +typedef struct +{ + TIM_TYPE_CLKS TIM_ClkS; //ʱԴѡ + TYPE_FUNCEN TIM_SYNC; //ⲿʱͬ + TIM_TYPE_EDGE TIM_EDGE; //ⲿʱӼѡ + TIM_TYPE_MODE TIM_Mode; //ģʽѡ +}TIM_BaseInitStruType; + +/* ƥĴֵƥĹģʽ */ +typedef enum +{ + TIM_Go_No = 0x0 , //ƥĴֵƥĹģʽ:ж + TIM_Hold_Int = 0x1 , //ƥĴֵƥĹģʽ:ּж + TIM_Clr_Int = 0x2 , //ƥĴֵƥĹģʽ:㲢¼ж + TIM_Go_Int = 0x3 , //ƥĴֵƥĹģʽ:ж +}TIM_TYPE_MATCON; + +/* ƥĴֵƥ˿ڵĹģʽ */ +typedef enum +{ + TIM_Out_Hold = 0x0 , //ƥĴֵƥ˿ڵĹģʽ + TIM_Out_Low = 0x1 , //ƥĴֵƥ˿ڵĹģʽ0 + TIM_Out_High = 0x2 , //ƥĴֵƥ˿ڵĹģʽ1 + TIM_Out_Switch = 0x3 , //ƥĴֵƥ˿ڵĹģʽȡ +}TIM_TYPE_MATOUT; + +/* ׽ */ +typedef enum +{ + TIM_CapTime_1 = 0x0 , //׽:1 + TIM_CapTime_2 = 0x1 , //׽:2 + TIM_CapTime_3 = 0x2 , //׽:3 + TIM_CapTime_4 = 0x3 , //׽:4 + TIM_CapTime_5 = 0x4 , //׽:5 + TIM_CapTime_6 = 0x5 , //׽:6 + TIM_CapTime_7 = 0x6 , //׽:7 + TIM_CapTime_8 = 0x7 , //׽:8 + TIM_CapTime_9 = 0x8 , //׽:9 + TIM_CapTime_10 = 0x9 , //׽:10 + TIM_CapTime_11 = 0xA , //׽:11 + TIM_CapTime_12 = 0xB , //׽:12 + TIM_CapTime_13 = 0xC , //׽:13 + TIM_CapTime_14 = 0xD , //׽:14 + TIM_CapTime_15 = 0xE , //׽:15 + TIM_CapTime_16 = 0xF , //׽:16 +}TIM_TYPE_CAPT; + +/* PWM */ +typedef enum +{ + POSITIVE = 0X00, // + NEGATIVE = 0X01, // +}T16Nx_PWMOUT_POLAR_Type; + +/* ƹܳʼṹ嶨 */ +typedef struct +{ + TYPE_FUNCEN T16Nx_MOE0; //˿0ʹ + TYPE_FUNCEN T16Nx_MOE1; //˿1ʹ + T16Nx_PWMOUT_POLAR_Type T16Nx_POL0; //T16NxOUT0ѡλ + T16Nx_PWMOUT_POLAR_Type T16Nx_POL1; //T16NxOUT1ѡλ +}T16Nx_PWMInitStruType; + +/* ׽ܳʼṹ嶨 */ +typedef struct +{ + TYPE_FUNCEN TIM_CapRise; //ز׽ʹ + TYPE_FUNCEN TIM_CapFall; //½ز׽ʹ + TYPE_FUNCEN TIM_CapIS0; //˿0ʹ + TYPE_FUNCEN TIM_CapIS1; //˿1ʹ + TIM_TYPE_CAPT TIM_CapTime; //׽ +}TIM_CapInitStruType; + +/* PWMɲƽ */ +typedef enum +{ + PWMBKOUT_Low = 0, + PWMBKOUT_High = 1, +}T16Nx_PWMBKOUT_LEVEl; + +/* PWMɲźżѡ */ +typedef enum +{ + PWMBKP_High = 0, + PWMBKP_Low = 1, +}T16Nx_PWMBKP_LEVEl; + +/*PWMɲźԴѡ*/ +typedef enum +{ + PWMBKPS_PINT0 = 0, + PWMBKPS_PINT1 = 1, + PWMBKPS_PINT2 = 2, + PWMBKPS_PINT3 = 3, + PWMBKPS_PINT4 = 4, + PWMBKPS_PINT5 = 5, + PWMBKPS_PINT6 = 6, + PWMBKPS_PINT7 = 7, +}T16Nx_PWMBKP_S; + +/*PWMɲ*/ +typedef struct +{ + + T16Nx_PWMBKOUT_LEVEl T16Nx_PWMBKL0; //PWMͨ0ɲƽѡ + T16Nx_PWMBKOUT_LEVEl T16Nx_PWMBKL1; //PWMͨ1ɲƽѡ + T16Nx_PWMBKP_S T16Nx_PWMBKS; //PWMͨźԴѡ + T16Nx_PWMBKP_LEVEl T16Nx_PWMBKPS; //PWMͨɲźżѡ + TYPE_FUNCEN T16Nx_PWMBKEN; //PWMɲʹ +}T16Nx_PWMBK_Type; + +/* ж */ +typedef enum +{ + TIM_IT_MAT0 = 0x01 , + TIM_IT_MAT1 = 0x02 , + TIM_IT_MAT2 = 0x04 , + TIM_IT_MAT3 = 0x08 , + TIM_IT_N = 0x10 , + TIM_IT_CAP0 = 0x20 , + TIM_IT_CAP1 = 0x40 , + TIM_IT_PBK = 0x80 , +}TIM_TYPE_IT; + +typedef enum +{ + TIM_IF_MAT0 = 0x01 , + TIM_IF_MAT1 = 0x02 , + TIM_IF_MAT2 = 0x04 , + TIM_IF_MAT3 = 0x08 , + TIM_IF_N = 0x10 , + TIM_IF_CAP0 = 0x20 , + TIM_IF_CAP1 = 0x40 , + TIM_IF_PBK = 0x80 , +}TIM_TYPE_IF; + +/* ƥĴ */ +typedef enum +{ + TIM_MAT0 = 0x00 , + TIM_MAT1 = 0x01 , + TIM_MAT2 = 0x02 , + TIM_MAT3 = 0x03 , +}TIM_TYPE_MATX; + +/*T16N ADCʹܿ*/ +typedef enum +{ + T16Nx_MAT0 = 0x02, //PWMͨ0ƥ0ʹ + T16Nx_MAT1 = 0x04, //PWMͨ0ƥ1ʹ + T16Nx_MAT2 = 0x20, //PWMͨ1ƥ2ʹ + T16Nx_MAT3 = 0x40, //PWMͨ1ƥ3ʹ +}T16Nx_PWMTRG_type; + +/*************TIMģ궨************/ + +/* TIMģʹܿ */ +#define T16N0_Enable() (T16N0->CON0.EN = 1) +#define T16N1_Enable() (T16N1->CON0.EN = 1) +#define T16N2_Enable() (T16N2->CON0.EN = 1) +#define T16N3_Enable() (T16N3->CON0.EN = 1) +#define T32N0_Enable() (T32N0->CON0.EN = 1) +#define T16N0_Disable() (T16N0->CON0.EN = 0) +#define T16N1_Disable() (T16N1->CON0.EN = 0) +#define T16N2_Disable() (T16N2->CON0.EN = 0) +#define T16N3_Disable() (T16N3->CON0.EN = 0) +#define T32N0_Disable() (T32N0->CON0.EN = 0) + +/* 첽дʹܿ */ +#define T16N0_ASYNCWR_Enable() (T16N0->CON0.ASYWEN = 1) +#define T16N1_ASYNCWR_Enable() (T16N1->CON0.ASYWEN = 1) +#define T16N2_ASYNCWR_Enable() (T16N2->CON0.ASYWEN = 1) +#define T16N3_ASYNCWR_Enable() (T16N3->CON0.ASYWEN = 1) +#define T32N0_ASYNCWR_Enable() (T32N0->CON0.ASYNCWREN = 1) +#define T16N0_ASYNCWR_Disable() (T16N0->CON0.ASYWEN= 0) +#define T16N1_ASYNCWR_Disable() (T16N1->CON0.ASYWEN = 0) +#define T16N2_ASYNCWR_Disable() (T16N2->CON0.ASYWEN = 0) +#define T16N3_ASYNCWR_Disable() (T16N3->CON0.ASYWEN = 0) +#define T32N0_ASYNCWR_Disable() (T32N0->CON0.ASYNCWREN = 0) + +/* PWMʹܿ */ +#define T16N0_PwmOut0_Enable() (T16N0->CON2.MOE0 = 1) +#define T16N1_PwmOut0_Enable() (T16N1->CON2.MOE0 = 1) +#define T16N2_PwmOut0_Enable() (T16N2->CON2.MOE0 = 1) +#define T16N3_PwmOut0_Enable() (T16N3->CON2.MOE0 = 1) +#define T32N0_PwmOut0_Enable() (T32N0->CON2.MOE0 = 1) +#define T16N0_PwmOut1_Enable() (T16N0->CON2.MOE1 = 1) +#define T16N1_PwmOut1_Enable() (T16N1->CON2.MOE1 = 1) +#define T16N2_PwmOut1_Enable() (T16N2->CON2.MOE1 = 1) +#define T16N3_PwmOut1_Enable() (T16N3->CON2.MOE1 = 1) +#define T32N0_PwmOut1_Enable() (T32N0->CON2.MOE1 = 1) +#define T16N0_PwmOut0_Disable() (T16N0->CON2.MOE0 = 0) +#define T16N1_PwmOut0_Disable() (T16N1->CON2.MOE0 = 0) +#define T16N2_PwmOut0_Disable() (T16N2->CON2.MOE0 = 0) +#define T16N3_PwmOut0_Disable() (T16N3->CON2.MOE0 = 0) +#define T32N0_PwmOut0_Disable() (T32N0->CON2.MOE0 = 0) +#define T16N0_PwmOut1_Disable() (T16N0->CON2.MOE1 = 0) +#define T16N1_PwmOut1_Disable() (T16N1->CON2.MOE1 = 0) +#define T16N2_PwmOut1_Disable() (T16N2->CON2.MOE1 = 0) +#define T16N3_PwmOut1_Disable() (T16N3->CON2.MOE1 = 0) +#define T32N0_PwmOut1_Disable() (T32N0->CON2.MOE1 = 0) + +/************T16ģ麯***********/ +void T16Nx_BaseInit(T16N_TypeDef* T16Nx,TIM_BaseInitStruType* TIM_BaseInitStruct); +void T16Nx_CapInit(T16N_TypeDef* T16Nx,TIM_CapInitStruType* TIM_CapInitStruct); +void T16Nx_MAT0ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type); +void T16Nx_MAT1ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type); +void T16Nx_MAT2ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type); +void T16Nx_MAT3ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type); +void T16Nx_MAT0Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type); +void T16Nx_MAT1Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type); +void T16Nx_MAT2Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type); +void T16Nx_MAT3Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type); +void T16Nx_ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState); +void T16Nx_PWMOutConfig(T16N_TypeDef* T16Nx,T16Nx_PWMInitStruType* T16Nx_PWMInitStruct); +void T16Nx_PWMBK_Config(T16N_TypeDef* T16Nx,T16Nx_PWMBK_Type* type); +void T16Nx_TRG_Config(T16N_TypeDef* T16Nx,T16Nx_PWMTRG_type Type,TYPE_FUNCEN NewState); +FlagStatus T16Nx_GetPWMBKF(T16N_TypeDef* T16Nx); +void T16Nx_ResetPWMBKF(T16N_TypeDef* T16Nx); +void T16Nx_SetCNT(T16N_TypeDef* T16Nx,uint16_t Value); +void T16Nx_SetPRECNT(T16N_TypeDef* T16Nx,uint8_t Value); +void T16Nx_SetPREMAT(T16N_TypeDef* T16Nx,uint8_t Value); +void T16Nx_SetMAT0(T16N_TypeDef* T16Nx,uint16_t Value); +void T16Nx_SetMAT1(T16N_TypeDef* T16Nx,uint16_t Value); +void T16Nx_SetMAT2(T16N_TypeDef* T16Nx,uint16_t Value); +void T16Nx_SetMAT3(T16N_TypeDef* T16Nx,uint16_t Value); +uint16_t T16Nx_GetMAT0(T16N_TypeDef* T16Nx); +uint16_t T16Nx_GetMAT1(T16N_TypeDef* T16Nx); +uint16_t T16Nx_GetMAT2(T16N_TypeDef* T16Nx); +uint16_t T16Nx_GetMAT3(T16N_TypeDef* T16Nx); +uint16_t T16Nx_GetCNT(T16N_TypeDef* T16Nx); +uint8_t T16Nx_GetPRECNT(T16N_TypeDef* T16Nx); +FlagStatus T16Nx_GetFlagStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag); +ITStatus T16Nx_GetITStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IT TIM_Flag); +void T16Nx_ClearIFPendingBit(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag); +/************************************T32ģ麯********************************************************/ +void T32Nx_BaseInit(T32N_TypeDef* T32Nx,TIM_BaseInitStruType* TIM_BaseInitStruct); +void T32Nx_CapInit(T32N_TypeDef* T32Nx,TIM_CapInitStruType* TIM_CapInitStruct); +void T32Nx_MAT0ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type); +void T32Nx_MAT1ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type); +void T32Nx_MAT2ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type); +void T32Nx_MAT3ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type); +void T32Nx_MAT0Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type); +void T32Nx_MAT1Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type); +void T32Nx_MAT2Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type); +void T32Nx_MAT3Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type); +void T32Nx_ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState); +void T32Nx_SetCNT(T32N_TypeDef* T16Nx,uint32_t Value); +void T32Nx_SetPRECNT(T32N_TypeDef* T32Nx,uint8_t Value); +void T32Nx_SetPREMAT(T32N_TypeDef* T32Nx,uint8_t Value); +void T32Nx_SetMAT0(T32N_TypeDef* T32Nx,uint32_t Value); +void T32Nx_SetMAT1(T32N_TypeDef* T32Nx,uint32_t Value); +void T32Nx_SetMAT2(T32N_TypeDef* T32Nx,uint32_t Value); +void T32Nx_SetMAT3(T32N_TypeDef* T32Nx,uint32_t Value); +uint32_t T32Nx_GetMAT0(T32N_TypeDef* T32Nx); +uint32_t T32Nx_GetMAT1(T32N_TypeDef* T32Nx); +uint32_t T32Nx_GetMAT2(T32N_TypeDef* T32Nx); +uint32_t T32Nx_GetMAT3(T32N_TypeDef* T32Nx); +uint32_t T32Nx_GetCNT(T32N_TypeDef* T32Nx); +uint8_t T32Nx_GetPRECNT(T32N_TypeDef* T32Nx); +FlagStatus T32Nx_GetFlagStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag); +ITStatus T32Nx_GetITStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IT TIM_Flag); +void T32Nx_ClearIFPendingBit(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag); + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_uart.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..7b0d0fe1df03e7785db3e9b54345f89aad0acd8b --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_uart.h @@ -0,0 +1,171 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ lib_uart.h + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * UARTģ⺯ͷļ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBUART_H__ +#define __LIBUART_H__ + +#include "ES8P508x.h" +#include "type.h" +#include "system_ES8P508x.h" + +/* ֹ֡ͣλѡ */ +typedef enum +{ + UART_StopBits_1 = 0x0 , //ֹ֡ͣλ1λ + UART_StopBits_2 = 0x1 , //ֹ֡ͣλ2λ +}UART_TYPE_TXFS; + +/* ݸʽ */ +typedef enum +{ + UART_DataMode_7 = 0x0 , //ݸʽ:7λ + UART_DataMode_8 = 0x1 , //ݸʽ:8λ + UART_DataMode_9 = 0x2 , //ݸʽ:9λ + UART_DataMode_7Odd = 0x4 , //ݸʽ:7λ+У + UART_DataMode_7Even = 0x5 , //ݸʽ:7λ+żУ + UART_DataMode_8Odd = 0x6 , //ݸʽ:8λ+У + UART_DataMode_8Even = 0x7 , //ݸʽ:8λ+żУ +}UART_TYPE_DATAMOD; + +/* ˿ڼ */ +typedef enum +{ + UART_Polar_Normal = 0x0 , //Ͷ˿ڼ: + UART_Polar_Opposite = 0x1 , //Ͷ˿ڼ: +}UART_TYPE_RTXP; + +/* ʷʱѡ */ +typedef enum +{ + UART_Clock_1 = 0x1 , //ʷʱ:PCLK + UART_Clock_2 = 0x2 , //ʷʱ:PCLK/2 + UART_Clock_4 = 0x3 , //ʷʱ:PCLK/4 + UART_Clock_8 = 0x4 , //ʷʱ:PCLK/8 + +}UART_TYPE_BCS; + +/* UARTʼýṹ嶨 */ +typedef struct +{ + UART_TYPE_TXFS UART_StopBits; //ֹ֡ͣλѡ + UART_TYPE_DATAMOD UART_TxMode; //֡ʽ + UART_TYPE_RTXP UART_TxPolar; //Ͷ˿ڼ + UART_TYPE_DATAMOD UART_RxMode; //֡ʽ + UART_TYPE_RTXP UART_RxPolar; //ն˿ڼ + uint32_t UART_BaudRate; //䲨 + UART_TYPE_BCS UART_ClockSet; //ʷʱѡ +}UART_InitStruType; + +/* жѡ */ +typedef enum +{ + UART_IT_TB = 0x0001 , + UART_IT_RB = 0x0002 , + UART_IT_RO = 0x0004 , + UART_IT_FE = 0x0008 , + UART_IT_PE = 0x0010 , + UART_IT_TBWE = 0x0020 , + UART_IT_TXIDLE = 0x1000 , + UART_IT_RXIDLE = 0x2000 , +}UART_TYPE_IT; + +/* ־λ */ +typedef enum +{ + UART_FLAG_TB = 0x0001 , + UART_FLAG_RB = 0x0002 , + UART_FLAG_RO = 0x0004 , + UART_FLAG_FE = 0x0008 , + UART_FLAG_PE = 0x0010 , + UART_FLAG_TBWE = 0x0020 , + UART_FLAG_TXIDLE = 0x1000 , + UART_FLAG_RXIDLE = 0x2000 , +}UART_TYPE_FLAG; + +/* жϱ־λ */ +typedef enum +{ + UART_Clr_RO = 0x0004 , + UART_Clr_FE = 0x0008 , + UART_Clr_PE = 0x0010 , + UART_Clr_TBWE = 0x0020 , +}UART_CLR_IF; + +/* ͡жģʽ */ +typedef enum +{ + UART_TRBIM_Byte = 0x0 , //ж:ֽ + UART_TRBIM_HalfWord = 0x1 , //ж: + UART_TRBIM_Word = 0x2 , //ж: +}UART_TYPE_TRBIM; + +/*************UARTģ궨************/ +/* ʹܿ */ +#define UART0_TxEnable() (UART0->CON.TXEN = 1) +#define UART1_TxEnable() (UART1->CON.TXEN = 1) +#define UART2_TxEnable() (UART2->CON.TXEN = 1) +#define UART3_TxEnable() (UART3->CON.TXEN = 1) +#define UART4_TxEnable() (UART4->CON.TXEN = 1) +#define UART5_TxEnable() (UART5->CON.TXEN = 1) +#define UART0_TxDisable() (UART0->CON.TXEN = 0) +#define UART1_TxDisable() (UART1->CON.TXEN = 0) +#define UART2_TxDisable() (UART2->CON.TXEN = 0) +#define UART3_TxDisable() (UART3->CON.TXEN = 0) +#define UART4_TxDisable() (UART4->CON.TXEN = 0) +#define UART5_TxDisable() (UART5->CON.TXEN = 0) + +/* ʹܿ */ +#define UART0_RxEnable() (UART0->CON.RXEN = 1) +#define UART1_RxEnable() (UART1->CON.RXEN = 1) +#define UART2_RxEnable() (UART2->CON.RXEN = 1) +#define UART3_RxEnable() (UART3->CON.RXEN = 1) +#define UART4_RxEnable() (UART4->CON.RXEN = 1) +#define UART5_RxEnable() (UART5->CON.RXEN = 1) +#define UART0_RxDisable() (UART0->CON.RXEN = 0) +#define UART1_RxDisable() (UART1->CON.RXEN = 0) +#define UART2_RxDisable() (UART2->CON.RXEN = 0) +#define UART3_RxDisable() (UART3->CON.RXEN = 0) +#define UART4_RxDisable() (UART4->CON.RXEN = 0) +#define UART5_RxDisable() (UART5->CON.RXEN = 0) + +/* λ */ +#define UART0_TxRst() (UART0->CON.TRST = 1) +#define UART1_TxRst() (UART1->CON.TRST = 1) +#define UART2_TxRst() (UART2->CON.TRST = 1) +#define UART3_TxRst() (UART3->CON.TRST = 1) +#define UART4_TxRst() (UART4->CON.TRST = 1) +#define UART5_TxRst() (UART5->CON.TRST = 1) + +/* λ */ +#define UART0_RxRst() (UART0->CON.RRST = 1) +#define UART1_RxRst() (UART1->CON.RRST = 1) +#define UART2_RxRst() (UART2->CON.RRST = 1) +#define UART3_RxRst() (UART3->CON.RRST = 1) +#define UART4_RxRst() (UART4->CON.RRST = 1) +#define UART5_RxRst() (UART5->CON.RRST = 1) + +/************UARTģ麯***********/ +void UART_Init(UART_TypeDef* UARTx,UART_InitStruType* UART_InitStruct); +void UART_ITConfig(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT,TYPE_FUNCEN NewState); +void UART_TBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type); +void UART_RBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type); +void UART_SendByte(UART_TypeDef* UARTx,uint8_t Temp08); +void UART_SendHalfWord(UART_TypeDef* UARTx,uint16_t Temp16); +void UART_SendWord(UART_TypeDef* UARTx,uint32_t Temp32); +uint8_t UART_RecByte(UART_TypeDef* UARTx); +uint16_t UART_RecHalfWord(UART_TypeDef* UARTx); +uint32_t UART_RecWord(UART_TypeDef* UARTx); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx,UART_TYPE_FLAG UART_Flag); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx,UART_TYPE_IT UART_Flag); +void UART_ClearITPendingBit(UART_TypeDef* UARTx,UART_CLR_IF UART_Flag); + +#endif + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_wdt.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..45ad9d4287f11fb2f37f953be51490ba812e97bf --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/lib_wdt.h @@ -0,0 +1,100 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_wdt.c + * ߣ Liut + * V1.00 + * ڣ 2017/02/04 + * Źģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#ifndef __LIBWDT_H__ +#define __LIBWDT_H__ + +#include "system_ES8P508x.h" +#include "ES8P508x.h" +#include "type.h" + +/* WDTʱѡ */ +typedef enum +{ + WDT_CLOCK_PCLK = 0x0, //PCLK + WDT_CLOCK_WDT = 0x1, //WDTʱԴ32kHz +} WDT_TYPE_CLKS; + +/* ʼṹ */ +typedef struct +{ + uint32_t WDT_Tms; //ʱʱ䣬λms + TYPE_FUNCEN WDT_IE; //жʹ + TYPE_FUNCEN WDT_Rst; //λʹ + WDT_TYPE_CLKS WDT_Clock;//ʱѡ +} IWDT_InitStruType; + +typedef enum +{ + WDT_WIN_25 = 0x0, //25%ڽֹιιλ + WDT_WIN_50 = 0x1, //50%ڽֹιιλ + WDT_WIN_75 = 0x2, //75%ڽֹιιλ + WDT_WIN_100 = 0x3, //ֹιιʹŹ +} WDT_TYPE_WIN; + +/* ʼṹ */ +typedef struct +{ + uint32_t WDT_Tms; //ʱʱ䣬λms + TYPE_FUNCEN WDT_IE; //жʹ + TYPE_FUNCEN WDT_Rst; //λʹ + WDT_TYPE_CLKS WDT_Clock;//ʱѡ + WDT_TYPE_WIN WDT_Win; //ֹι +} WWDT_InitStruType; + +#define IWDT_RegUnLock() (IWDT->LOCK.Word = 0x1ACCE551) +#define IWDT_RegLock() (IWDT->LOCK.Word = 0x0) + +#define IWDT_Enable() {IWDT_RegUnLock();IWDT->CON.EN = 1;IWDT_RegLock();} +#define IWDT_Disable() {IWDT_RegUnLock();IWDT->CON.EN = 0;IWDT_RegLock();} + +#define IWDT_Clear() {IWDT_RegUnLock();IWDT->INTCLR.INTCLR = 0;IWDT_RegLock();} + +#define IWDT_ITEnable() {IWDT_RegUnLock();IWDT->CON.IE = 1;IWDT_RegLock();} +#define IWDT_ITDisable() {IWDT_RegUnLock();IWDT->CON.IE = 0;IWDT_RegLock();} + +#define IWDT_RstEnable() {IWDT_RegUnLock();IWDT->CON.RSTEN = 1;IWDT_RegLock();} +#define IWDT_RstDisable() {IWDT_RegUnLock();IWDT->CON.RSTEN = 0;IWDT_RegLock();} + +#define IWDT_CLOCK_PCLK() {IWDT_RegUnLock();IWDT->CON.CLKS = 0;IWDT_RegLock();} +#define IWDT_CLOCK_WDT() {IWDT_RegUnLock();IWDT->CON.CLKS = 1;IWDT_RegLock();} + +#define WWDT_RegUnLock() (WWDT->LOCK.Word = 0x1ACCE551) +#define WWDT_RegLock() (WWDT->LOCK.Word = 0x0) + +#define WWDT_Enable() {WWDT_RegUnLock();WWDT->CON.EN = 1;WWDT_RegLock();} +#define WWDT_Disable() {WWDT_RegUnLock();WWDT->CON.EN = 0;WWDT_RegLock();} + +#define WWDT_Clear() {WWDT_RegUnLock();WWDT->INTCLR.INTCLR = 0;WWDT_RegLock();} + +#define WWDT_ITEnable() {WWDT_RegUnLock();WWDT->CON.IE = 1;WWDT_RegLock();} +#define WWDT_ITDisable() {WWDT_RegUnLock();WWDT->CON.IE = 0;WWDT_RegLock();} + +#define WWDT_RstEnable() {WWDT_RegUnLock();WWDT->CON.RSTEN = 1;WWDT_RegLock();} +#define WWDT_RstDisable() {WWDT_RegUnLock();WWDT->CON.RSTEN = 0;WWDT_RegLock();} + +#define WWDT_CLOCK_PCLK() {WWDT_RegUnLock();WWDT->CON.CLKS = 0;WWDT_RegLock();} +#define WWDT_CLOCK_WDT() {WWDT_RegUnLock();WWDT->CON.CLKS = 1;WWDT_RegLock();} + +void IWDT_Init(IWDT_InitStruType *IWDT_InitStruct); +void IWDT_SetReloadValue(uint32_t Value); +uint32_t IWDT_GetValue(void); +FlagStatus IWDT_GetFlagStatus(void); +FlagStatus IWDT_GetITStatus(void); +void WWDT_Init(WWDT_InitStruType *WDT_InitStruct); +void WWDT_SetReloadValue(uint32_t Value); +uint32_t WWDT_GetValue(void); +FlagStatus WWDT_GetFlagStatus(void); +FlagStatus WWDT_GetITStatus(void); + +#endif + +/*************************END OF FILE**********************/ + diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/type.h b/bsp/essemi/es8p508x/libraries/Library/Include/type.h new file mode 100644 index 0000000000000000000000000000000000000000..a23d72e8bd2dbd7705591b30a09982c7df3e150c --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Include/type.h @@ -0,0 +1,19 @@ +/********************************************************* + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ: type.h + * : Liut + * : V1.01 + * : 2017/11/01 + * : type define + * ע: HRSDK-GDB-8P508x + ѧϰʾʹãûֱôķջеκηΡ + **********************************************************/ +#ifndef __TYPE_H__ +#define __TYPE_H__ + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} TYPE_FUNCEN,FuncState,TYPE_PINTIE,TYPE_PINTMASK,TYPE_BUZZEN; +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, PinStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + + +#endif diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/irqhandler.c b/bsp/essemi/es8p508x/libraries/Library/Source/irqhandler.c new file mode 100644 index 0000000000000000000000000000000000000000..bd0d9b0f14f349b3798b80931924f476a942d8f6 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/irqhandler.c @@ -0,0 +1,27 @@ +#include "irqhandler.h" + +void NMI_IRQHandler(void) +{ + +} + +void HardFault_IRQHandler(void) +{ + while(1) + { + } +} + +void SVC_IRQHandler(void) +{ + +} + +void PendSV_IRQHandler(void) +{ + +} +void SysTick_Handler(void) +{ + systick_irq_cbk(); +} diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_adc.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..23aea8a229c5a0a9ceda968d502688cdbd73d72e --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_adc.c @@ -0,0 +1,301 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_timer.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ADCģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_adc.h" + +/*************************************************************** + ADC_Init + ʼADCģ + ֵʼýṹַ + ֵ + ֵ + ***************************************************************/ +void ADC_Init(ADC_InitStruType * ADC_InitStruct) +{ + ADC->VREFCON.VREF_EN = ENABLE; //ڲVREFPʹ + ADC->VREFCON.IREF_EN = ENABLE; //IREFʹλ + ADC->CON1.VCMBUF_EN = ENABLE; //ADCģѹVCM BUFʹ + ADC ->CON1.VCMBUF_HS = ENABLE; //ADCģѹVCM BUFģʽʹ + ADC->CON1.HSEN = ENABLE; //ADCתٶȣ + ADC->CHS.VDD5_FLAG_EN = DISABLE; //VDD + + ADC->CON1.CLKS = ADC_InitStruct->ADC_ClkS; //ADCCON1:bit3 ADCʱԴѡ + ADC->CON1.CLKDIV = ADC_InitStruct->ADC_ClkDiv; //ADCCON1:bit2-0 ADCʱԴԤƵ + ADC->CON1.VREFP = ADC_InitStruct->ADC_VrefP; //ADCCON1:bit9-8 ADCοѹѡ + ADC->CON1.SMPS = ADC_InitStruct->ADC_SampS; //ADCCON1:bit12 ADCģʽѡ + ADC->CHS.CHS = ADC_InitStruct->ADC_ChS; //ADCCHS:bit0-3 ADCģͨѡ + ADC->CON1.ST = ADC_InitStruct->ST; //ADCCON1:bit20-16 ADCʱѡ ST*2+1Tadclk + //ADC->VREFCON.VREF_SEL=ADC_InitStruct->VREF_SEL;//ڲοѹѡ + + ADC->CON1.VREFN = ADC_InitStruct->ADC_VREFN; //οѹʹλ + ADC->CON1.VRBUF_EN = ADC_InitStruct->ADC_VRBUF_EN; //VREF BUFʹλ +} + + +/*************************************************************** + ADC_Set_CH + ѡADCģͨ + ֵͨ + ֵ + ֵ + ***************************************************************/ +void ADC_Set_CH(ADC_TYPE_CHS AdcCH) +{ + ADC->CHS.CHS = AdcCH; +} + +/*************************************************************** + ADC_GetConvValue + ȡADCת + ֵ + ֵ + ֵתֵ + ***************************************************************/ +uint16_t ADC_GetConvValue(void) +{ + return ((uint16_t)ADC->DR.DR); +} + +/*************************************************************** + ADC_GetConvStatus + ȡADCת״̬ + ֵ + ֵ + ֵRESET()/SET(ת) + ***************************************************************/ +FlagStatus ADC_GetConvStatus(void) +{ + FlagStatus bitstatus = RESET; + + /* ת״̬Ĵ */ + if ((ADC->CON0.TRIG != (uint32_t)RESET)) + bitstatus = SET; //ת + else + bitstatus = RESET; //ת + + return bitstatus; +} + +/*************************************************************** + ADC_ACPConfig + ADC ԶȽϹܳʼ + ֵADC_ACP_InitStruct ԶȽϹܳʼṹ + ֵ + ֵSUCCESS ɹ + ERROR ʧ + ***************************************************************/ +ErrorStatus ADC_ACPConfig(ADC_ACP_TypeDef *ADC_ACP_InitStruct) +{ + if(ADC_ACP_InitStruct->ACPC_OVER_TIME > ADC_ACPC_OVFL_TIME_MAX + ||ADC_ACP_InitStruct->ACPC_TIMES > ADC_ACPC_TIMES_MAX + ||ADC_ACP_InitStruct->ACPC_MIN_TARGET > ADC_ACP_MIN_MAX + ||ADC_ACP_InitStruct->ACPC_MAX_TARGET > ADC_ACP_MAX_MAX) + { + return ERROR; + } + + if(ADC_ACP_InitStruct->ACP_EN == ENABLE) + { + if(ADC->CON1.CLKS == ADC_ClkS_PCLK) + { + ADC->ACPC.CLKS = ADC_ACPC_CLKS_PCLK; + } + else + { + ADC->ACPC.CLKS = ADC_ACPC_CLKS_LRC; + } + + ADC->ACPC.OVFL_TIME = ADC_ACP_InitStruct ->ACPC_OVER_TIME; + ADC->ACPC.TIMES = ADC_ACP_InitStruct->ACPC_TIMES; + ADC->IE.ACPOVIE = ENABLE; + + /* û߷ֵó0(Сֵ)ǿΪرոù */ + if(ADC_ACP_InitStruct ->ACPC_MAX_TARGET ==0x0) + { + ADC->IE.ACPMAXIE = DISABLE; + } + else + { + ADC->ACPCMP.CMP_MAX =ADC_ACP_InitStruct ->ACPC_MAX_TARGET; + ADC->IE.ACPMAXIE = ENABLE; + } + + /* ûͷֵó0xfff(ֵ)ǿΪرոù */ + if(ADC_ACP_InitStruct ->ACPC_MIN_TARGET == 0xfff) + { + ADC->IE.ACPMINIE = DISABLE; + } + else + { + ADC->ACPCMP.CMP_MIN =ADC_ACP_InitStruct ->ACPC_MIN_TARGET; + ADC->IE.ACPMINIE = ENABLE; + } + + ADC->CON0.ACP_EN = ENABLE; + + } + else + { + ADC->CON0.ACP_EN = DISABLE; + } + + return SUCCESS; +} + +/*************************************************************** + ADC_SampStart + ADC - + ֵ + ֵ + ֵSUCCESS ɹ + ERROR ʧ + ***************************************************************/ +ErrorStatus ADC_SoftStart(void) +{ + if(ADC->CON1.SMPS == ADC_SMPS_HARD) + return ERROR; + + ADC ->CON1.SMPON = SET; + return SUCCESS; +} + +/*************************************************************** + ADC_SampStop + ADC -ֹͣ + ֵ + ֵ + ֵSUCCESS ɹ + ERROR ʧ + ***************************************************************/ +ErrorStatus ADC_SoftStop(void) +{ + if(ADC->CON1.SMPS == ADC_SMPS_HARD) + return ERROR; + + ADC->CON1.SMPON = RESET; + return SUCCESS; +} + +/*************************************************************** + ADC_GetACPMeanValue + ADC õԶȽƽֵ + ֵ + ֵ + ֵ + ***************************************************************/ +uint16_t ADC_GetACPMeanValue(void) +{ + return ((uint16_t)ADC->ACPMEAN.MEAN_DATA); +} + +/*************************************************************** + ADC_GetACPMINValue + ADC õԶȽƽֵ + ֵ + ֵ + ֵ + ***************************************************************/ +uint16_t ADC_GetACPMinValue(void) +{ + return ((uint16_t)ADC->ACPCMP.CMP_MIN); +} + +/*************************************************************** + ADC_GetACPMAXValue + ADC õԶȽƽֵ + ֵ + ֵ + ֵ + ***************************************************************/ +uint16_t ADC_GetACPMaxValue(void) +{ + return ((uint16_t)ADC->ACPCMP.CMP_MAX); +} + +/*************************************************************** + ADC_GetFlagStatus + ȡADC־λ״̬ + ֵIFNameADCжϱ־ + ֵ + ֵSET/RESET + ***************************************************************/ +FlagStatus ADC_GetFlagStatus(ADC_TYPE_IF IFName) +{ + FlagStatus bitstatus = RESET; + + /* жϱ־λ */ + if (((ADC->IF.Word & IFName) != (uint32_t)RESET)) + bitstatus = SET; //ת + else + bitstatus = RESET; //ж + + return bitstatus; +} + +/*************************************************************** + ADC_GetITStatus + ȡADCж״̬δʹӦжʱ᷵SET + ֵ + ֵ + ֵSETжϣ/RESETжϣ + ***************************************************************/ +ITStatus ADC_GetITStatus(ADC_TYPE_IE IEName) +{ + ITStatus bitstatus = RESET; + + /* жϱ־λ */ + if (((ADC->IE.Word & IEName) != (uint32_t)RESET)) + bitstatus = SET; //תɣж + else + bitstatus = RESET; //ж + + return bitstatus; +} + +/*************************************************************** + ADC_ClearIFStatus + ADC ضж + ֵIFName жѡ + ADC_IF ADCж + ADC_IF_ACPMIN Զתͷֵж + ADC_IF_ACPMAX Զת߷ֵж + ADC_IF_ACPOVER Զתж + ֵ + ֵSUCCESS ɹ + ERROR ʧ + ***************************************************************/ +ErrorStatus ADC_ClearIFStatus(ADC_TYPE_IF IFName) +{ + ADC->IF.Word = (uint32_t)IFName; + + return SUCCESS; +} +/*************************************************************** + ADC_Reset + ADCλ + ֵ + ֵ + ֵ + ***************************************************************/ +void ADC_Reset(void) +{ + ADC->CON0.Word = 0x00000030; + ADC->CON1.Word = 0x00041000; + ADC->CHS.Word = 0x00000100; + ADC->IE.Word = 0x00000000; + ADC->IF.Word = 0x00000000; + ADC->ACPC.Word = 0x00000000; + ADC->ACPCMP.Word = 0x0FFF0000; + ADC->VREFCON.Word = 0x00000000; +} + +/*************************END OF FILE**********************/ + + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_aes.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_aes.c new file mode 100644 index 0000000000000000000000000000000000000000..e8f07e8bba521e2d09c1ca0360a612f0a57bfe5a --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_aes.c @@ -0,0 +1,222 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ + * : AE + * : V1.00 + * : 2017/07/14 + * + * ע ES8P508оƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_aes.h" + +/*************************************************************** +AES_Init + AESܳʼ +ֵAES_InitStruct ʼṹ +ֵ +ֵ +***************************************************************/ +void AES_Init(AES_InitStruType * AES_InitStruct) +{ + + + AES_Reset(); + + AES->CON.ENCRYPT = AES_InitStruct->MODE; + return; +} + +/*************************************************************** +AES_WriteKey + AESдԿ +ֵAES_KEY дԿ +ֵ +ֵ +***************************************************************/ +void AES_WriteKey(uint32_t *AES_KEY) +{ + uint32_t *address = AES_KEY; + + AES->KEY3.AES_KEY3 = *address; + address ++; + AES->KEY2.AES_KEY2 = *address; + address ++; + AES->KEY1.AES_KEY1 = *address; + address ++; + AES->KEY0.AES_KEY0 = *address; +} + +/*************************************************************** +AES_ReadKey + AESԿ +ֵ +ֵAES_DATAԿλ +ֵ +***************************************************************/ +void AES_ReadKey(uint32_t * AES_KEY) +{ + uint32_t *address = AES_KEY; + + *address = AES->KEY3.AES_KEY3; + address ++; + *address = AES->KEY2.AES_KEY2; + address ++; + *address = AES->KEY1.AES_KEY1; + address ++; + *address = AES->KEY0.AES_KEY0; + return; +} + +/*************************************************************** +AES_WriteData + AESдݺ +ֵAES_DATA д +ֵ +ֵ +***************************************************************/ +void AES_WriteData(uint32_t *AES_DATA) +{ + uint32_t *address = AES_DATA; + + AES->DATA3.AES_DATA3 = *address; + address ++; + AES->DATA2.AES_DATA2 = *address; + address ++; + AES->DATA1.AES_DATA1 = *address; + address ++; + AES->DATA0.AES_DATA0 = *address; +} + +/*************************************************************** +AES_WriteData + AESݺ +ֵ +ֵAES_DATAݴλ +ֵ +***************************************************************/ +void AES_ReadData(uint32_t * AES_DATA) +{ + uint32_t *address = AES_DATA; + + *address = AES->DATA3.AES_DATA3; + address ++; + *address = AES->DATA2.AES_DATA2; + address ++; + *address = AES->DATA1.AES_DATA1; + address ++; + *address = AES->DATA0.AES_DATA0; + return; +} + +/*************************************************************** +AES_ITConfig + AESжʹ +ֵAES_IE + NewState Enable/Disable +ֵ +ֵ +***************************************************************/ +void AES_ITConfig(AES_TYPE_IT AES_IE, TYPE_FUNCEN NewState) +{ + uint32_t Word = AES->CON.Word&0xffffff8e; + + if(AES->CON.GO_DONE == 1) + { + return; + } + + if (NewState == ENABLE) + Word |= (uint32_t)AES_IE; + else + + Word &= ~(uint32_t)AES_IE; + + AES->CON.Word = Word; + return; + +} + +/*************************************************************** +AES_GetFlagStatus + AESضжϱ־ +ֵIFName + AES_IF_IF ӽж +ֵ +ֵжϱ־ +***************************************************************/ +FlagStatus AES_GetFlagStatus(AES_TYPE_IF IFName) +{ + + if(AES->CON.Word & IFName) { + return SET; + } + return RESET; +} + +/*************************************************************** +AES_ClearITPendingBit + AESضжϱ־ +ֵIFName + AES_IF_DONE ӽж +ֵ +ֵ +***************************************************************/ +void AES_ClearITPendingBit(void) +{ + /* ǵIFGO_DONEͬһwordУIFֵܻһЩ + * GO_DONE1ʱȡֵGO_DONE0ֵԭ1ٶиֵ + * òҪв + */ + + if(AES->CON.GO_DONE == SET) + { + return; + } + + AES->CON.IF = SET; + + return; +} + +/*************************************************************** +AES_GetDoneStatus + AESǷ/ +ֵ +ֵ +ֵAES_DONE_NO δ + AES_DONE_YES δܻ߼Ѿ +***************************************************************/ +AES_TYPE_DONE AES_GetDoneStatus(void) +{ + if(AES->CON.GO_DONE == 1) + { + return AES_DONE_NO; + } + + return AES_DONE_YES; +} + +/*************************************************************** +AES_Reset + AESλ +ֵ +ֵ +ֵ +***************************************************************/ +void AES_Reset(void) +{ + AES->DATA0.Word = 0x00000000; + AES->DATA1.Word = 0x00000000; + AES->DATA2.Word = 0x00000000; + AES->DATA3.Word = 0x00000000; + + AES->KEY0.Word = 0x00000000; + AES->KEY1.Word = 0x00000000; + AES->KEY2.Word = 0x00000000; + AES->KEY3.Word = 0x00000000; + + AES->CON.Word = 0x00000000; +} + + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_crc.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..547d50fddf936f0eadb2e0463751cd42f5739a3a --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_crc.c @@ -0,0 +1,96 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ + * : Liut + * : V1.00 + * : 2017/07/14 + * + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_crc.h" + + /*************************************************************** + CRC_getTypeValue + òһCRC_CONò + ֵcon_value CRC_CON ֵṹ + ֵCRC_CONֵ + ***************************************************************/ +uint32_t CRC_getTypeValue(CRC_CONValueStruType con_value) +{ + uint32_t type =0; + type = (con_value.xorout | con_value.refout | con_value.refin |\ + con_value.mode|con_value.hs_type|con_value.init_data_type); + return type; +} + + /*************************************************************** + CRC_EmptayCheck + պ + ֵaddress: ׵ַ data_lenֽڳ + ֵ1ɹ0 ʧ + ***************************************************************/ +uint32_t CRC_EmptayCheck(void* address, uint32_t data_len) +{ + CRC_EM CRC_EmptayCheck = (CRC_EM)(*(uint32_t *)CRC_EmptayCheck_addr); + + uint32_t result; + __ASM("CPSID i"); + result = (*CRC_EmptayCheck)(address, data_len); + __ASM("CPSIE i"); + return result; +} + + /*************************************************************** + CRC_FlashVerify + FLASHУ麯 + ֵaddress: У׵ַ data_lenУֽڳȣ type:У鷽ʽ + ֵCRCУ + ***************************************************************/ +uint32_t CRC_FlashVerify(void* address, uint32_t data_len, uint32_t type) +{ + CRC_FL CRC_FlashVerify = (CRC_FL)(*(uint32_t *)CRC_FlashVerify_addr); + + uint32_t result; + __ASM("CPSID i"); + result = (*CRC_FlashVerify)(address, data_len, type); + __ASM("CPSIE i"); + return result; +} + + /*************************************************************** + CRC_UserCal + ûУ麯 + ֵaddress: ûУ׵ַ data_lenУֽڳȣ type:У鷽ʽ + ֵCRCУ + ***************************************************************/ +uint32_t CRC_UserCal(void* address, uint32_t data_len, uint32_t type) +{ + CRC_US CRC_UserCal = (CRC_US)(*(uint32_t *)CRC_UserCal_addr); + + uint32_t result; + __ASM("CPSID i"); + result = (*CRC_UserCal)(address, data_len, type); + __ASM("CPSIE i"); + return result; +} + + /*************************************************************** + CRC_CheckReset + CRCλѯ + ֵ + ֵλ־1иλ־0޸λ־ + ***************************************************************/ +uint32_t CRC_CheckReset(void) +{ + CRC_CH CRC_CheckReset = (CRC_CH)(*(uint32_t *)CRC_CheckReset_addr); + + uint32_t result; + __ASM("CPSID i"); + result = (*CRC_CheckReset)(); + __ASM("CPSIE i"); + return result; +} + +/************************END OF FILE**************************/ + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_flashiap.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_flashiap.c new file mode 100644 index 0000000000000000000000000000000000000000..599478b1647a2ea33cd38a02f882a3f74364267d --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_flashiap.c @@ -0,0 +1,355 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_flashiap.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * flashд⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_flashiap.h" + +/*************************************************************** + FlashIap_Close_WPROT + IAPرд + ֵPage:0-63,ÿpageӦ2Kֽ,64 ΪINFO + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_Close_WPROT(uint8_t Page) +{ + if(Page > 64) + return ERROR; + + if(Page == 64) + { + IAP->WPROT2.Word = 0x00000000; + return SUCCESS; + } + + if(Page < 32) + { + IAP->WPROT0.Word &=~ ((uint32_t)0x1 << Page); + } + else + { + Page -= 32; + IAP->WPROT1.Word &=~ ((uint32_t)0x1 << Page); + } + + return SUCCESS; +} + +/*************************************************************** + FlashIap_Open_WPROT + IAPд + ֵPage:0-63,ÿpageӦ2Kֽ,,64 ΪINFO + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_Open_WPROT(uint8_t Page) +{ + if(Page > 64) + return ERROR; + + if(Page == 64) + { + IAP->WPROT2.Word = 0x00000001; + return SUCCESS; + } + + if(Page < 32) + { + IAP->WPROT0.Word &=~ ((uint32_t)0x1 << Page); + IAP->WPROT0.Word |= ((uint32_t)0x1 << Page); + } + else + { + Page -= 32; + IAP->WPROT1.Word &=~ ((uint32_t)0x1 << Page); + IAP->WPROT1.Word |= ((uint32_t)0x1 << Page); + } + + return SUCCESS; +} + +/*************************************************************** + FlashIap_CloseAll_WPROT + IAPرд + ֵPage:0-63,ÿpageӦ2Kֽ + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_CloseAll_WPROT(void) +{ + IAP->WPROT0.Word = 0x00000000; + IAP->WPROT1.Word = 0x00000000; + IAP->WPROT2.Word = 0x00000000; + + return SUCCESS; +} +/*************************************************************** + FlashIap_OpenAll_WPROT + IAPд + ֵ + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_OpenAll_WPROT(void) +{ + IAP->WPROT0.Word = 0xFFFFFFFF; + IAP->WPROT1.Word = 0xFFFFFFFF; + IAP->WPROT2.Word = 0xFFFFFFFF; + + return SUCCESS; +} + +/*************************************************************** + FlashIap_Unlock + IAP + ֵ + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_Unlock(void) +{ + uint16_t Temp16; + + FlashIAP_RegUnLock(); // IAP + + FlashIAP_Enable(); //ʹIAP + + FlashIAP_REQ(); // + + for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++) //ȴFLASHӦź + { + if(IAP->CON.FLASH_ACK != 0) + break; + } + + if(Temp16 == 0xFFFF) + return ERROR; + else + return SUCCESS; +} + +/*************************************************************** + FlashIap_WriteEnd + IAPд + ֵ + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_WriteEnd(void) +{ + uint32_t Temp32; + + FlashIAP_RegUnLock(); //IAP + + IAP->CON.Word &= 0xFFFFFFEE; //IAPFLASH() + + for(Temp32 = 0; Temp32 < 0xFFFF; Temp32++) //ȴFLASHӦź() + { + if(IAP->CON.FLASH_ACK == 0) + break; + } + + if(Temp32 == 0xFFFF) + return ERROR; + else + return SUCCESS; +} + +/*************************************************************** + FlashIap_ErasePage + IAPҳ + ֵPage_Addrҳַ + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_ErasePage(uint8_t Page_Addr) +{ + uint16_t Temp16; + uint32_t temp; + + temp = __get_PRIMASK(); //ȡPRIMASKĴǰ״̬ + __disable_irq(); //ж + + if(FlashIap_Unlock() == ERROR) + { + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + return ERROR; + } + + if(FlashIap_CloseAll_WPROT() == ERROR) + { + __set_PRIMASK(temp); + return ERROR; + } + + IAP->ADDR.IAPPA = Page_Addr; //ҳַ + + IAP->TRIG.TRIG = 0x00005EA1; // + + for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++) + { //жIAP״̬ + if((IAP->STA.Word & (uint32_t)0x01) == (uint32_t)0x00) + break; + } + + if(Temp16 == 0xFFFF) + { + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + return ERROR; + } + + for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++) + { + if((IAP->STA.Word & (uint32_t)0x02) == (uint32_t)0x02) //жIAPҳ־ + break; + } + + if(Temp16 == 0xFFFF) + { + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + return ERROR; + } + + if(FlashIap_WriteEnd() == ERROR) + { + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + return ERROR; + } + + if(FlashIap_OpenAll_WPROT() == ERROR) + { + __set_PRIMASK(temp); + return ERROR; + } + + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + + return SUCCESS; +} + +/*************************************************************** + FlashIap_WriteCont + IAPд + ֵUnit_addrԪַ Page_addrҳַ Data32 + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_WriteCont(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32) +{ + uint16_t temp16; + + IAP->ADDR.IAPPA = Page_addr; //ַ + IAP->ADDR.IAPCA = Unit_addr; + + IAP->DATA.DATA = Data32; // + IAP->TRIG.TRIG = 0x00005DA2; // + + for(temp16 = 0; temp16 < 0xFFFF; temp16++) + { + if((IAP->STA.Word & (uint32_t)0x01) == (uint32_t)0x00) //жIAP״̬ + break; + } + + if(temp16 == 0xFFFF) + return ERROR; + + for(temp16 = 0; temp16 < 0xFFFF; temp16++) + { + if((IAP->STA.Word & 0x04)==0x04) //жIAP̽־ + break; + } + + if(temp16 == 0xFFFF) + return ERROR; + + return SUCCESS; +} + +/*************************************************************** + FlashIap_WriteWord + IAPдһ + ֵUnit_addrԪַ Page_addrҳַ Data32 + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus FlashIap_WriteWord(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32) +{ + uint32_t temp; + + temp = __get_PRIMASK(); //ȡPRIMASKĴǰ״̬ + __disable_irq(); //ж + + if(FlashIap_Unlock() == ERROR) + { + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + return ERROR; + } + + if(FlashIap_CloseAll_WPROT() == ERROR) + { + __set_PRIMASK(temp); //رд״̬ + return ERROR; + } + + if(FlashIap_WriteCont(Unit_addr, Page_addr, Data32) == ERROR) + { + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + return ERROR; + } + + if(FlashIap_WriteEnd() == ERROR) + { + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + return ERROR; + } + + if(FlashIap_OpenAll_WPROT() == ERROR) + { + __set_PRIMASK(temp); //д״̬ + return ERROR; + } + + __set_PRIMASK(temp); //ָPRIMASKĴ״̬ + + return SUCCESS; +} + +/*************************************************************** + Flash_Read + Flash + ֵRam_AddrݵĴŵַ Flash_AddrFlashַ0x00000000 ~ 0x0001FFFF Lenȡֳ + ֵ + ֵɹʧ + ***************************************************************/ +ErrorStatus Flash_Read(uint32_t * Ram_Addr, uint32_t Flash_Addr, uint8_t Len) +{ + uint8_t i; + uint32_t *ram_addr32; + const uint32_t *flash_addr32; + + ram_addr32 = (uint32_t *)Ram_Addr; + flash_addr32 = (const uint32_t *)Flash_Addr; + + if((Len == 0) & (Len>(0x20000 - Flash_Addr) / 4)) //ж϶ȡǷϷ + { + return ERROR; + } + + for(i=0; iGPIO_Signal == GPIO_Pin_Signal_Analog) { + GPIO_SetSingalTypeFromPin(GPIOx, PINx, GPIO_Pin_Signal_Analog); + GPIO_SetDirRegFromPin(GPIOx, PINx, GPIO_Dir_In); + GPIO_SetFuncxRegFromPin(GPIOx, PINx, GPIO_Func_0); + } + else { + GPIO_SetSingalTypeFromPin(GPIOx, PINx, GPIO_Pin_Signal_Digital); + GPIO_SetDirRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_Direction); + GPIO_SetFuncxRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_Func); + + if (GPIO_InitStruct->GPIO_Direction == GPIO_Dir_Out) { + GPIO_SetODERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_OD); + GPIO_SetDSRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_DS); + } + GPIO_SetPUERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_PUEN); + GPIO_SetPDERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_PDEN); + } +} + +/*************************************************************** + GPIO_SetFuncxRegFromPin + GPIOŵĹܸ + ֵPinĿ + Funcܸñ + ֵ + ֵ + ***************************************************************/ +void GPIO_SetFuncxRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_FUNC Func) +{ + uint32_t value; + + switch (Func) { + case GPIO_Func_0: + value = 0; + break; + case GPIO_Func_1: + value = 1; + break; + case GPIO_Func_2: + value = 2; + break; + case GPIO_Func_3: + value = 3; + break; + default: + value = 0; + break; + } + + /* Ź */ + if(GPIOx == GPIOB){ + switch (PINx) { + case GPIO_Pin_0: + GPIO->PBFUNC0.PB0 = value; + break; + case GPIO_Pin_1: + GPIO->PBFUNC0.PB1 = value; + break; + case GPIO_Pin_2: + GPIO->PBFUNC0.PB2 = value; + break; + case GPIO_Pin_3: + GPIO->PBFUNC0.PB3 = value; + break; + case GPIO_Pin_4: + GPIO->PBFUNC0.PB4 = value; + break; + case GPIO_Pin_5: + GPIO->PBFUNC0.PB5 = value; + break; + case GPIO_Pin_6: + GPIO->PBFUNC0.PB6 = value; + break; + case GPIO_Pin_7: + GPIO->PBFUNC0.PB7 = value; + break; + case GPIO_Pin_8: + GPIO->PBFUNC1.PB8 = value; + break; + case GPIO_Pin_9: + GPIO->PBFUNC1.PB9 = value; + break; + case GPIO_Pin_10: + GPIO->PBFUNC1.PB10 = value; + break; + case GPIO_Pin_11: + GPIO->PBFUNC1.PB11 = value; + break; + case GPIO_Pin_12: + GPIO->PBFUNC1.PB12 = value; + break; + case GPIO_Pin_13: + GPIO->PBFUNC1.PB13 = value; + break; + default: + break; + } + } + + else{ + switch (PINx) { + case GPIO_Pin_0: + GPIO->PAFUNC0.PA0 = value; + break; + case GPIO_Pin_1: + GPIO->PAFUNC0.PA1 = value; + break; + case GPIO_Pin_2: + GPIO->PAFUNC0.PA2 = value; + break; + case GPIO_Pin_3: + GPIO->PAFUNC0.PA3 = value; + break; + case GPIO_Pin_4: + GPIO->PAFUNC0.PA4 = value; + break; + case GPIO_Pin_5: + GPIO->PAFUNC0.PA5 = value; + break; + case GPIO_Pin_6: + GPIO->PAFUNC0.PA6 = value; + break; + case GPIO_Pin_7: + GPIO->PAFUNC0.PA7 = value; + break; + case GPIO_Pin_8: + GPIO->PAFUNC1.PA8 = value; + break; + case GPIO_Pin_9: + GPIO->PAFUNC1.PA9 = value; + break; + case GPIO_Pin_10: + GPIO->PAFUNC1.PA10 = value; + break; + case GPIO_Pin_11: + GPIO->PAFUNC1.PA11 = value; + break; + case GPIO_Pin_12: + GPIO->PAFUNC1.PA12 = value; + break; + case GPIO_Pin_13: + GPIO->PAFUNC1.PA13 = value; + break; + case GPIO_Pin_14: + GPIO->PAFUNC1.PA14 = value; + break; + case GPIO_Pin_15: + GPIO->PAFUNC1.PA15 = value; + break; + case GPIO_Pin_16: + GPIO->PAFUNC2.PA16 = value; + break; + case GPIO_Pin_17: + GPIO->PAFUNC2.PA17 = value; + break; + case GPIO_Pin_18: + GPIO->PAFUNC2.PA18 = value; + break; + case GPIO_Pin_19: + GPIO->PAFUNC2.PA19 = value; + break; + case GPIO_Pin_20: + GPIO->PAFUNC2.PA20 = value; + break; + case GPIO_Pin_21: + GPIO->PAFUNC2.PA21 = value; + break; + case GPIO_Pin_22: + GPIO->PAFUNC2.PA22 = value; + break; + case GPIO_Pin_23: + GPIO->PAFUNC2.PA23 = value; + break; + case GPIO_Pin_24: + GPIO->PAFUNC3.PA24 = value; + break; + case GPIO_Pin_25: + GPIO->PAFUNC3.PA25 = value; + break; + case GPIO_Pin_26: + GPIO->PAFUNC3.PA26 = value; + break; + case GPIO_Pin_27: + GPIO->PAFUNC3.PA27 = value; + break; + case GPIO_Pin_28: + GPIO->PAFUNC3.PA28 = value; + break; + case GPIO_Pin_29: + GPIO->PAFUNC3.PA29 = value; + break; + case GPIO_Pin_30: + GPIO->PAFUNC3.PA30 = value; + break; + case GPIO_Pin_31: + GPIO->PAFUNC3.PA31 = value; + break; + default: + break; + } + } + return; +} + +/*************************************************************** + GPIO_SetSingalTypeFromPin + ŵź + ֵPin: Ŀ + Signal: ŵź + ֵ + ֵ + ***************************************************************/ +void GPIO_SetSingalTypeFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_Pin_Signal GPIO_Signal) +{ + if(GPIOx == GPIOB) { + if (GPIO_Signal == GPIO_Pin_Signal_Digital) + GPIO->PBINEB.Word &= (~(1 << PINx)); + else + GPIO->PBINEB.Word |= (1 << PINx); + } + else{ + if (GPIO_Signal == GPIO_Pin_Signal_Digital) + GPIO->PAINEB.Word &= (~(1 << PINx)); + else + GPIO->PAINEB.Word |= (1 << PINx); + } + + return; +} + +/*************************************************************** + GPIO_SetDirRegFromPin + ŵ + ֵPin: Ŀ + Dirŷ + ֵ + ֵ + ***************************************************************/ +void GPIO_SetDirRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir) +{ + if (GPIOx == GPIOB) { + if (Dir == GPIO_Dir_In) + GPIO->PBDIRBSR.Word = (1 << PINx); + else + GPIO->PBDIRBCR.Word = (1 << PINx); + } + else { + if (Dir == GPIO_Dir_In) + GPIO->PADIRBSR.Word = (1 << PINx); + else + GPIO->PADIRBCR.Word = (1 << PINx); + } + + return; +} + +/*************************************************************** + GPIO_SetODERegFromPin + ŵ©ʽ + ֵPin: Ŀ +ODE: ©ʽ +ֵ +ֵ + ***************************************************************/ +void GPIO_SetODERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_ODE_Output ODE) +{ + if (GPIOx == GPIOB) { + if (ODE == GPIO_ODE_Output_Disable) + GPIO->PBODE.Word &= (~(1 << PINx)); + else + GPIO->PBODE.Word |= (1 << PINx); + } + else { + if (ODE == GPIO_ODE_Output_Disable) + GPIO->PAODE.Word &= (~(1 << PINx)); + else + GPIO->PAODE.Word |= (1 << PINx); + } + + return; +} + +/*************************************************************** + GPIO_SetDSRegFromPin + ŵ + ֵPin: Ŀ +DS: ʽ +ֵ +ֵ + ***************************************************************/ +void GPIO_SetDSRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DS DS) +{ + if (GPIOx == GPIOB) { + if (DS == GPIO_DS_Output_Normal) + GPIO->PBDS.Word &= (~(1 << PINx)); + else + GPIO->PBDS.Word |= (1 << PINx); + } + else { + if (DS == GPIO_DS_Output_Normal) + GPIO->PADS.Word &= (~(1 << PINx)); + else + GPIO->PADS.Word |= (1 << PINx); + } + + return; +} + +/*************************************************************** + GPIO_SetPUERegFromPin + ŵʽ + ֵPin: Ŀ +PUE: ʽ +ֵ +ֵ + ***************************************************************/ +void GPIO_SetPUERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PUE_Input PUE) +{ + if (GPIOx == GPIOB) { + if (PUE == GPIO_PUE_Input_Disable) + GPIO->PBPUE.Word &= (~(1 << PINx)); + else + GPIO->PBPUE.Word |= (1 << PINx); + } + else { + if (PUE == GPIO_PUE_Input_Disable) + GPIO->PAPUE.Word &= (~(1 << PINx)); + else + GPIO->PAPUE.Word |= (1 << PINx); + } +} + +/*************************************************************** + GPIO_SetPDERegFromPin + ŵʽ + ֵPin: Ŀ + PDEʽ + ֵ + ֵ + ***************************************************************/ +void GPIO_SetPDERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PDE_Input PDE) +{ + if (GPIOx == GPIOB) { + if (PDE == GPIO_PDE_Input_Disable) + GPIO->PBPDE.Word &= (~(1 << PINx)); + else + GPIO->PBPDE.Word |= (1 << PINx); + } + else { + if (PDE == GPIO_PDE_Input_Disable) + GPIO->PAPDE.Word &= (~(1 << PINx)); + else + GPIO->PAPDE.Word |= (1 << PINx); + } + + return; +} + +/*************************************************************** + GPIO_Write + GPIO˿д + ֵGPIOxGPIOA/GPIOB ValueҪдݡע⣺ЩڵţõֵӦλõ + ֵ + ֵ + ***************************************************************/ +void GPIO_Write(GPIO_TYPE GPIOx, uint32_t Value) +{ + if(GPIOx == GPIOA) + GPIO->PADATA.Word = Value; + else if(GPIOx == GPIOB) + GPIO->PBDATA.Word = Value; +} + +/*************************************************************** + GPIO_Read + GPIO˿ڶ + ֵGPIOxGPIOA/GPIOB + ֵ + ֵݡע⣺ЩڵţֵӦλЧ + ***************************************************************/ +uint32_t GPIO_Read(GPIO_TYPE GPIOx) +{ + if(GPIOx == GPIOA) + return GPIO->PAPORT.Word; + else if(GPIOx == GPIOB) + return GPIO->PBPORT.Word; + + return 0; +} + +/*************************************************************** + GPIO_ReadBit + GPIO˿ڶijλ + ֵGPIOxGPIOA/GPIOB PINx:GPIO_Pin_0 GPIO_Pin_31 + ֵ + ֵݡע⣺ЩڵţֵЧ + ***************************************************************/ +PinStatus GPIO_ReadBit(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx) +{ + PinStatus bitstatus = RESET; + + if(GPIOx == GPIOA) + { + if((GPIO->PAPORT.Word&((uint32_t)0x1<PBPORT.Word&((uint32_t)0x1<PADATABSR.Word = (uint32_t)0x1<PADATABCR.Word = (uint32_t)0x1<PADATABRR.Word = (uint32_t)0x1<PBDATABSR.Word = (uint32_t)0x1<PBDATABCR.Word = (uint32_t)0x1<PBDATABRR.Word = (uint32_t)0x1<PADIR.Word &=~((uint32_t)0x1 << PINx); + GPIO->PADIR.Word |= ((uint32_t)Dir_Type <PBDIR.Word &=~((uint32_t)0x1 << PINx); + GPIO->PBDIR.Word |= ((uint32_t)Dir_Type <BUZC.BUZ_LOAD = (SystemCoreClock/(freq*2)) - 1; + GPIO->BUZC.BUZEN = buzz_en; +} +/*************************************************************** + PINT_Config + PINT + ֵPINTxѡPINT0 PINT7 SELxѡ TRIGxѡ + ֵ + ֵ + ***************************************************************/ +void PINT_Config(PINT_TYPE PINTx, PINT_TYPE_SEL SELx, PINT_TYPE_TRIG TRIGx) +{ + GPIO->PINTSEL.Word &= ~((uint32_t)0x07<<(PINTx*4)); + GPIO->PINTSEL.Word |=((uint32_t)SELx << (PINTx*4)); //selѡ + + GPIO->PINTCFG.Word &= ~((uint32_t)0x07<<(PINTx*4)); + GPIO->PINTCFG.Word |=((uint32_t)TRIGx << (PINTx*4)); //ʽѡ +} + +/*************************************************************** + PINT_GetIFStatus + PINTȡжϱ־ + ֵPINTxPINT0-PINT7 + ֵ + ֵSET/RESET + ***************************************************************/ +FlagStatus PINT_GetIFStatus(PINT_TYPE_IT PINT_Flag) +{ + FlagStatus bitstatus = RESET; + + if((GPIO->PINTIF.Word & (uint32_t)PINT_Flag) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + PINT_GetITStatus + PINTȡжϱ־ + ֵPINTxPINT0-PINT7 + ֵ + ֵSET/RESET + ***************************************************************/ +FlagStatus PINT_GetITStatus(PINT_TYPE_IT PINT_Flag) +{ + FlagStatus bitstatus = RESET; + + if((GPIO->PINTIF.Word & (uint32_t)PINT_Flag) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + PINT_ClearITPendingBit + PINTжϱ־ + ֵPINTж + ֵ + ֵ + ***************************************************************/ +void PINT_ClearITPendingBit(PINT_TYPE_IT PINT_Flag) +{ + GPIO->PINTIF.Word = (uint32_t)PINT_Flag; +} + +/*************************END OF FILE**********************/ + + + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_iap.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_iap.c new file mode 100644 index 0000000000000000000000000000000000000000..9cd1bb4daf4d0b6a76424fbb1644d93c59172059 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_iap.c @@ -0,0 +1,97 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ + * : Liut + * : V1.00 + * : 2017/07/14 + * + * ע ES8P508оƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_iap.h" + +/************************************************* + * @brief IAP ҳ.ص̻ROMеij + * @param address: ҳ׵ַ + * @retval None + ***********************************************/ +ErrorStatus IAP_PageErase(uint32_t address) +{ + IAP_PE IAPPageErase = (IAP_PE)(*(uint32_t *)IAP_PageErase_addr); + + ErrorStatus result; + __ASM("CPSID i"); + result = (*IAPPageErase)(address); + __ASM("CPSIE i"); + return result; +} + +/************************************************* + * @brief IAP Ա.ص̻ROMеij + * @param address: ׵ַ + * @param data: + * @retval None + ************************************************/ +ErrorStatus IAP_WordProgram(uint32_t address, uint32_t data) +{ + IAP_WP IAPWordProgram = (IAP_WP)(*(uint32_t *)IAP_WordProgram_addr); + + ErrorStatus result; + __ASM("CPSID i"); + result = (*IAPWordProgram)( address, data); + __ASM("CPSIE i"); + return result; +} + +/************************************************ + * @brief IAP Ա.ص̻ROMеij + * @param address: ׵ַ + * @param data[]: + * @param length: ݳȣֽڣ + * @param address: ҳǷȲ + * @arg 0: + * @arg 1: + * @retval None + **********************************************/ +ErrorStatus IAP_PageProgram(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase) //@0x100001c5 +{ + IAP_PP IAPPageProgram = (IAP_PP)(*(uint32_t *)IAP_PageProgram_addr); + + ErrorStatus result; + __ASM("CPSID i"); + result = (*IAPPageProgram)(address,data,length,erase); + __ASM("CPSIE i"); + return result; +} +/************************************* + IARead + Flash + ֵڴַ--ȡݵĴŵַ + Flashַ + ȡݵijȣλΪ֣4ֽڣ + ֵɹ/ʧ + **************************************/ +ErrorStatus IAPRead(uint32_t *Ram_Addr, uint32_t Flash_Addr, uint8_t Len) +{ + uint8_t i; + uint32_t *ram_addr; + const uint32_t *flash_addr; + + ram_addr = Ram_Addr; + flash_addr = (const uint32_t *)Flash_Addr; + + if (Len == 0) + return ERROR; + + for (i = 0; i < Len; ++i) + { + *ram_addr = *flash_addr; + ++ram_addr; + ++flash_addr; + } + + return SUCCESS; +} + +/************************END OF FILE**************************/ + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_iic.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_iic.c new file mode 100644 index 0000000000000000000000000000000000000000..ab987843f170de78c7a96067e9b076a441eb0657 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_iic.c @@ -0,0 +1,311 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_iic.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * IICģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_iic.h" + +/*************************************************************** + I2C_Init + I2Cʼ + ֵI2C_InitStructʼýṹַ + ֵ + ֵ + ***************************************************************/ +void I2C_Init(I2C_InitStruType* I2C_InitStruct) +{ + uint32_t temp; + + if(I2C_InitStruct->I2C_Mode == I2C_Mode_Master) + { + if(I2C_InitStruct->I2C_16XSamp != DISABLE) + temp = SystemCoreClock/24/I2C_InitStruct->I2C_Clk - 1; + else + temp = SystemCoreClock/16/I2C_InitStruct->I2C_Clk - 1; + + if(temp > 254) + temp = 255; + + I2C0->CON.TJP = temp; //ʱʱ + + I2C0->CON.TJE = 0x1; //ʹʱʱ + } + + I2C0->CON.SDASE = I2C_InitStruct->I2C_16XSamp; //16 + I2C0->CON.SCKSE = I2C_InitStruct->I2C_16XSamp; + I2C0->CON.SCKOD = I2C_InitStruct->I2C_SclOd; //˿ڿ© + I2C0->CON.SDAOD = I2C_InitStruct->I2C_SdaOd; + I2C0->MOD.MS = I2C_InitStruct->I2C_Mode; //ģʽ + I2C0->MOD.SPAE = I2C_InitStruct->I2C_AutoStop; //Զֹͣ + I2C0->MOD.SRAE = I2C_InitStruct->I2C_AutoCall; //ԶѰ +} + +/*************************************************************** + I2C_ITConfig + I2Cж + ֵI2C_ITҪõж NewStateʹܻر + ֵ + ֵ + ***************************************************************/ +void I2C_ITConfig(I2C_TYPE_IT I2C_IT,TYPE_FUNCEN NewState) +{ + if (NewState != DISABLE) + I2C0->IE.Word |= (uint32_t)I2C_IT; + else + I2C0->IE.Word &= ~((uint32_t)I2C_IT); +} + +/*************************************************************** + I2C_SendAddress + I2Cʹӻַ + ֵI2C_Address7λӻַ 0x00~0xfe Modeд + ֵ + ֵ + ***************************************************************/ +void I2C_SendAddress(uint8_t I2C_Address,I2C_TYPE_RWMODE Mode) +{ + I2C0->CON.SA = I2C_Address>>1; + I2C0->CON.RW = Mode; +} + +/*************************************************************** + I2C_SetAddress + I2Cõַڴӻģʽ + ֵI2C_Address7λӻַ 0x00~0xfe + ֵ + ֵ + ***************************************************************/ +void I2C_SetAddress(uint8_t I2C_Address) +{ + I2C0->CON.SA = I2C_Address>>1; +} + +/*************************************************************** + I2C_RecModeConfig + I2Cýģʽ + ֵRecTypeģʽ + ֵ + ֵ + ***************************************************************/ +void I2C_RecModeConfig(I2C_TYPE_RECMODE RecType) +{ + I2C0->MOD.RDM = RecType; +} + +/*************************************************************** + I2C_TBIMConfig + I2Cͻжģʽѡ + ֵTypeжģʽ + ֵ + ֵ + ***************************************************************/ +void I2C_TBIMConfig(I2C_TYPE_TRBIM Type) +{ + I2C0->IE.TBIM = Type; +} + +/*************************************************************** + I2C_RBIMConfig + I2Cջжģʽѡ + ֵTypeжģʽ + ֵ + ֵ + ***************************************************************/ +void I2C_RBIMConfig(I2C_TYPE_TRBIM Type) +{ + I2C0->IE.RBIM = Type; +} + +/*************************************************************** + I2C_AckDelay + I2CӦʱ + ֵTypeʱʱ NewStatusʹܡʧ + ֵ + ֵ + ***************************************************************/ +void I2C_AckDelay(I2C_TYPE_ADLY Type,TYPE_FUNCEN NewStatus) +{ + I2C0->MOD.ADLY = Type; + I2C0->MOD.ADE = NewStatus; +} + +/*************************************************************** + I2C_TISConfig + I2C֡ + ֵTime + ֵ + ֵ + ***************************************************************/ +void I2C_TISConfig(I2C_TYPE_TIS Time) +{ + I2C0->MOD.TIS = Time; +} + +/*************************************************************** + I2C_SendByte + I2Cֽڷ + ֵByteֽ + ֵ + ֵ + ***************************************************************/ +void I2C_SendByte(uint8_t Byte) +{ + I2C0->TBW.Byte[0] = Byte; +} + +/*************************************************************** + I2C_SendHalfWord + I2Cַ + ֵHalfWord + ֵ + ֵ + ***************************************************************/ +void I2C_SendHalfWord(uint16_t HalfWord) +{ + I2C0->TBW.HalfWord[0] = HalfWord; +} + +/*************************************************************** + I2C_SendWord + I2Cַ + ֵWord + ֵ + ֵ + ***************************************************************/ +void I2C_SendWord(uint32_t Word) +{ + I2C0->TBW.Word = Word; +} + +/*************************************************************** + I2C_RecByte + I2C-ֽ + ֵ + ֵ + ֵյ + ***************************************************************/ +uint8_t I2C_RecByte(void) +{ + return I2C0->RBR.Byte[0] ; +} + +/*************************************************************** + I2C_RecHalfWord + I2C- + ֵ + ֵ + ֵյ + ***************************************************************/ +uint16_t I2C_RecHalfWord(void) +{ + return I2C0->RBR.HalfWord[0]; +} + +/*************************************************************** + I2C_RecWord + I2C- + ֵ + ֵ + ֵյ + ***************************************************************/ +uint32_t I2C_RecWord(void) +{ + return I2C0->RBR.Word ; +} + +/*************************************************************** + I2C_GetRWMode + I2Cд״̬ȡ + ֵ + ֵ + ֵ/д + ***************************************************************/ +I2C_TYPE_RWMODE I2C_GetRWMode(void) +{ + I2C_TYPE_RWMODE Status = I2C_Mode_Write; + + if(I2C0->CON.RW != 0) + Status = I2C_Mode_Read; + else + Status = I2C_Mode_Write; + + return Status; +} + +/*************************************************************** + I2C_GetTBStatus + I2CȡͻĴ״̬,TB0-TB3ȫ򷵻SET,򷵻RESET + ֵ + ֵ + ֵSET/RESET + ***************************************************************/ +FlagStatus I2C_GetTBStatus(void) +{ + FlagStatus bitstatus = RESET; + + if((I2C0->STA.Word&(uint32_t)0x0f00) != (uint32_t)0x0f00) + bitstatus = RESET; + else + bitstatus = SET; + + return bitstatus; +} + +/*************************************************************** + I2C_GetFlagStatus + I2Cȡ־λ״̬ + ֵI2C_FlagѡҪı־λ + ֵ + ֵSET/RESET + ***************************************************************/ +FlagStatus I2C_GetFlagStatus(I2C_TYPE_FLAG I2C_Flag) +{ + FlagStatus bitstatus = RESET; + + if ((I2C0->IF.Word & (uint32_t)I2C_Flag) != RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/************************************* + I2C_GetITStatus + ȡжʹ״̬ + ֵI2C_Flag жʹλ + ж + ֵSET/RESET + **************************************/ +FlagStatus I2C_GetITStatus( I2C_TYPE_IT I2C_Flag) +{ + FlagStatus status = RESET; + + if ((I2C0->IE.Word & (uint32_t)I2C_Flag) == RESET) + return status; + + if ((I2C0->IF.Word & (uint32_t)I2C_Flag) != RESET) + status = SET; + + return status; +} + +/*************************************************************** + I2C_ClearITPendingBit + I2Cжϱ־ + ֵI2C_IT־λ + ֵ + ֵ + ***************************************************************/ +void I2C_ClearITPendingBit(I2C_CLR_IF I2C_IT) +{ + I2C0->IF.Word = (uint32_t)I2C_IT; +} + +/*************************END OF FILE**********************/ + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_printf.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_printf.c new file mode 100644 index 0000000000000000000000000000000000000000..f2afdc314255d4f04442f74c10f4d788683aeadf --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_printf.c @@ -0,0 +1,283 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_printf.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ڴӡ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_printf.h" +#include + +/*************************************************************** + fputc + ضc⺯printfUART + ֵ + ֵ + ֵ + ***************************************************************/ +/*ʹprintf()Ҫ΢⣺Use MicroLIB*/ +int fputc(int ch, FILE *f) +{ + FlagStatus Status = RESET; + uint32_t Count=0; + +#if defined __PRINTF_USE_UART3__ + UART_SendByte(UART3, (unsigned char) ch); + do + { + Status = UART_GetFlagStatus(UART3,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + return (EOF); + +#elif defined __PRINTF_USE_UART2__ + UART_SendByte(UART2, (unsigned char) ch); + do + { + Status = UART_GetFlagStatus(UART2,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + return (EOF); + +#elif defined __PRINTF_USE_UART1__ + UART_SendByte(UART1, (unsigned char) ch); + do + { + Status = UART_GetFlagStatus(UART1,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + return (EOF); + +#else + UART_SendByte(UART0, (unsigned char) ch); + do + { + Status = UART_GetFlagStatus(UART0,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + return (EOF); + +#endif + return (ch); +} + +#ifdef __clang__ //ʹõidesignerʱ򲻵΢ +/*************************************************************** + תַ + ֵ -radix =10 ʾ10ƣΪ0 + * -value Ҫת + * -buf תַ + * -radix = 10 + ֵ + ***************************************************************/ +static char *itoa(int value, char *string, int radix) +{ + int i, d; + int flag = 0; + char *ptr = string; + + /* This implementation only works for decimal numbers. */ + if (radix != 10) + { + *ptr = 0; + return string; + } + + if (!value) + { + *ptr++ = 0x30; + *ptr = 0; + return string; + } + + /* if this is a negative value insert the minus sign. */ + if (value < 0) + { + *ptr++ = '-'; + + /* Make the value positive. */ + value *= -1; + } + + for (i = 10000; i > 0; i /= 10) + { + d = value / i; + + if (d || flag) + { + *ptr++ = (char)(d + 0x30); + value -= (d * i); + flag = 1; + } + } + + /* Null terminate the string. */ + *ptr = 0; + + return string; +} +/*************************************************************** + ʽCеprintfûõC + ֵ -UARTx ͨ + * -Data Ҫ͵ڵݵָ + * -... + ֵ + Ӧã UART_printf("\r\n this is a demo \r\n" ); + * UART1_printf("\r\n %d \r\n", i ); + * UART1_printf("\r\n %s \r\n", j ); + ***************************************************************/ +/* δCʱʹô˺Cеprintfprintfȫ + ֻ֧\r \n %d %s */ +ErrorStatus UART_printf(uint8_t *Data,...) +{ + UART_TypeDef *UARTx; + const char *s; + int d; + char buf[16]; + ErrorStatus RET = SUCCESS; + FlagStatus Status = RESET; + uint32_t Count=0; + va_list ap; + +/** + ** + **ʹú궨ѡʹһ + ** +***/ +#if defined __PRINTF_USE_UART3__ + + UARTx = UART3; + +#elif defined __PRINTF_USE_UART2__ + + UARTx = UART2; + +#elif defined __PRINTF_USE_UART1__ + + UARTx = UART1; + +#else + + UARTx = UART0; + +#endif + + va_start(ap, Data); + + while ( *Data != 0) // жǷ񵽴ַ + { + if ( *Data == 0x5c ) //'\' + { + switch ( *++Data ) + { + case 'r': //س + Count=0; + UART_SendByte(UARTx, 0x0d); + do + { + Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + RET = ERROR; + + Data ++; + break; + + case 'n': //з + Count=0; + UART_SendByte(UARTx, 0x0a); + do + { + Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + RET = ERROR; + + Data ++; + break; + + default: + Data ++; + break; + } + } + else if ( *Data == '%') + { + switch ( *++Data ) + { + case 's': //ַ + s = va_arg(ap, const char *); + for ( ; *s; s++) + { + Count=0; + UART_SendByte(UARTx,*s); + do + { + Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + RET = ERROR; + } + Data++; + break; + + case 'd': //ʮ + d = va_arg(ap, int); + itoa(d, buf, 10); + for (s = buf; *s; s++) + { + Count=0; + UART_SendByte(UARTx,*s); + do + { + Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + RET = ERROR; + } + Data++; + break; + default: + Data++; + break; + } + } /* end of else if */ + else + { + Count=0; + UART_SendByte(UARTx, *Data++); + do + { + Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); + Count++; + }while((Status == RESET)&&(Count != 0x1CE2)); + + if(Count == 0x1CE2) + RET = ERROR; + } + } + return RET; +} + +#endif +/*************************END OF FILE**********************/ + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_rtc.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..dfede6ca296fe232570b99c5afdbf6793f6a2cff --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_rtc.c @@ -0,0 +1,1906 @@ +/********************************************************* + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. + *ļ: lib_rtc.c + * : Liut + * : V1.00 + * : 2017/07/14 + * : RTCģ + * ע: HRSDK-GDB-ES8P508 V1.1 + ѧϰʾʹãûֱôķջеκηΡ + **********************************************************/ +#include "lib_rtc.h" +#include "lib_scu.h" + +/*************************************************************** + RTC_Init + ʵʱʱӳʼ + ֵCLKx:RTCʱԴѡHOURx12Сʱ/24Сʱѡ + ֵ + ֵ + ***************************************************************/ +void RTC_Init(RTC_TYPE_CLKS CLKx,RTC_TYPE_TIME HOURx) +{ + uint32_t flag; + + if(CLKx == RTC_LOSC ) + { + uint32_t Prot_Temp; + + Prot_Temp = SCU->PROT.PROT; + + if(Prot_Temp != 0) //д + SCU_RegUnLock(); // + + SCU_XTAL_Enable(); //ʹⲿ32kHZ + while(SCU_XTALReadyFlag() != SET); //ȴʱӿ + + if(Prot_Temp != 0) + SCU_RegLock(); //д + } + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + RTC->CON.PON = 0; // 㣬ʹRTC + RTC->CON.HSWI = HOURx; // 24Сʱģʽ + RTC->CON.CLKS = CLKx; // ʱԴѡ32768Hz + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; +} +/*************************************************************** + RTC_StartRead + ʵʱʱӶ + ֵ + ֵ + ֵ + ***************************************************************/ +void RTC_StartRead(void) +{ + RTC->CON.TMWR = 0; // Ƕ + RTC->CON.TMUP = 1; // + while (RTC->CON.TMUP == 1); //ȴ +} + +/*************************************************************** + RTC_ReadHourmode + ȡСʱģʽ + ֵ + ֵ + ֵǰСʱģʽ + ***************************************************************/ +uint32_t RTC_ReadHourmode(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + result = RTC->CON.HSWI; + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} +/*************************************************************** + RTC_ReadSecond + ȡ + ֵ + ֵ + ֵǰ + ***************************************************************/ +uint32_t RTC_ReadSecond(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->HMS.SEC & (uint32_t)0x01) * 1); + result += (((RTC->HMS.SEC >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->HMS.SEC >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->HMS.SEC >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->HMS.SEC >> 4) & (uint32_t)0x01) * 10); + result += (((RTC->HMS.SEC >> 5) & (uint32_t)0x01) * 20); + result += (((RTC->HMS.SEC >> 6) & (uint32_t)0x01) * 40); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_ReadMinute + ȡ + ֵ + ֵ + ֵǰķ + ***************************************************************/ +uint32_t RTC_ReadMinute(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->HMS.MIN & (uint32_t)0x01) * 1); + result += (((RTC->HMS.MIN >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->HMS.MIN >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->HMS.MIN >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->HMS.MIN >> 4) & (uint32_t)0x01) * 10); + result += (((RTC->HMS.MIN >> 5) & (uint32_t)0x01) * 20); + result += (((RTC->HMS.MIN >> 6) & (uint32_t)0x01) * 40); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_ReadHour + ȡСʱ + ֵ + ֵ + ֵǰСʱ + ***************************************************************/ +uint32_t RTC_ReadHour(uint32_t *meridiem) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->HMS.HOUR & (uint32_t)0x01) * 1); + result += (((RTC->HMS.HOUR >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->HMS.HOUR >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->HMS.HOUR >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->HMS.HOUR >> 4) & (uint32_t)0x01) * 10); + + if(RTC_ReadHourmode() == RTC_HOUR24) //24Сʱģʽ20Сʱ + { + result += (((RTC->HMS.HOUR >> 5) & (uint32_t)0x01) * 20); + } + else //12Сʱģʽ1 PM,0 AM + { + *meridiem = (((RTC->HMS.HOUR >> 5) & (uint32_t)0x01)); + } + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_ReadDay + ȡ + ֵ + ֵ + ֵǰ + ***************************************************************/ +uint32_t RTC_ReadDay(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->YMDW.DAY & (uint32_t)0x01) * 1); + result += (((RTC->YMDW.DAY >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->YMDW.DAY >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->YMDW.DAY >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->YMDW.DAY >> 4) & (uint32_t)0x01) * 10); + result += (((RTC->YMDW.DAY >> 5) & (uint32_t)0x01) * 20); + + /* RTCд */ + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return result; +} + +/*************************************************************** + RTC_ReadMonth + ȡ + ֵ + ֵ + ֵǰ + ***************************************************************/ +uint32_t RTC_ReadMonth(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->YMDW.MON & (uint32_t)0x01) * 1); + result += (((RTC->YMDW.MON >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->YMDW.MON >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->YMDW.MON >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->YMDW.MON >> 4) & (uint32_t)0x01) * 10); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_ReadYear + ȡ + ֵ + ֵ + ֵǰ + ***************************************************************/ +uint32_t RTC_ReadYear(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->YMDW.YEAR & (uint32_t)0x01) * 1); + result += (((RTC->YMDW.YEAR >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->YMDW.YEAR >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->YMDW.YEAR >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->YMDW.YEAR >> 4) & (uint32_t)0x01) * 10); + result += (((RTC->YMDW.YEAR >> 5) & (uint32_t)0x01) * 20); + result += (((RTC->YMDW.YEAR >> 6) & (uint32_t)0x01) * 40); + result += (((RTC->YMDW.YEAR >> 7) & (uint32_t)0x01) * 80); + result += 2000; + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} +/*************************************************************** + RTC_ReadWeek + ȡ + ֵ + ֵ + ֵǰ + ***************************************************************/ +uint32_t RTC_ReadWeek(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + switch(RTC->YMDW.WEEK) + { + case 0x00: result = 0;break; + case 0x01: result = 1;break; + case 0x02: result = 2;break; + case 0x03: result = 3;break; + case 0x04: result = 4;break; + case 0x05: result = 5;break; + case 0x06: result = 6;break; + default: result = 0;break; + } + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_StartRead + ʵʱʱд + ֵ + ֵ + ֵ + ***************************************************************/ +void RTC_StartWrite(void) +{ + /* д */ + RTC->CON.TMWR = 1; // д + RTC->CON.TMUP = 1; // д + while (RTC->CON.TMUP == 1); //ȴд +} + +/*************************************************************** + RTC_WriteSecond + ޸ + ֵsecond: + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteSecond(uint32_t second) +{ + uint32_t flag = 0; + uint32_t sec_buf = 0; + + /* */ + if (second >= 60) + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if (second >= 40) + { + sec_buf |= (uint32_t)1<<6; + second -= 40; + } + else + { + sec_buf &= ~(uint32_t)1<<6; + } + + if (second >= 20) + { + sec_buf |= (uint32_t)1<<5; + second -= 20; + } + else + { + sec_buf &= ~(uint32_t)1<<5; + } + + if (second >= 10) + { + sec_buf |= (uint32_t)1<<4; + second -= 10; + } + else + { + sec_buf &= ~(uint32_t)1<<4; + } + + if (second >= 8) + { + sec_buf |= (uint32_t)1<<3; + second -= 8; + } + else + { + sec_buf &= ~(uint32_t)1<<3; + } + + if (second >= 4) + { + sec_buf |= (uint32_t)1<<2; + second -= 4; + } + else + { + sec_buf &= ~(uint32_t)1<<2; + } + + if (second >= 2) + { + sec_buf |= (uint32_t)1<<1; + second -= 2; + } + else + { + sec_buf &= ~(uint32_t)1<<1; + } + + if (second >= 1) + { + sec_buf |= (uint32_t)1; + second -= 1; + } + else + { + sec_buf &= ~(uint32_t)1; + } + + RTC->HMS.SEC = sec_buf; + + /* д */ + RTC_StartWrite(); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + +/*************************************************************** + RTC_WriteMinute + ޸ + ֵminute: + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteMinute(uint32_t minute) +{ + uint32_t flag; + uint32_t min_buf = 0; + + /* */ + if (minute >= 60) + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if (minute >= 40) + { + min_buf |= (uint32_t)1<<6; + minute -= 40; + } + else + { + min_buf &= ~(uint32_t)1<<6; + } + + if (minute >= 20) + { + min_buf |= (uint32_t)1<<5; + minute -= 20; + } + else + { + min_buf &= ~(uint32_t)1<<5; + } + + if (minute >= 10) + { + min_buf |= (uint32_t)1<<4; + minute -= 10; + } + else + { + min_buf &= ~(uint32_t)1<<4; + } + + if (minute >= 8) + { + min_buf |= (uint32_t)1<<3; + minute -= 8; + } + else + { + min_buf &= ~(uint32_t)1<<3; + } + + if (minute >= 4) + { + min_buf |= (uint32_t)1<<2; + minute -= 4; + } + else + { + min_buf &= ~(uint32_t)1<<2; + } + + if (minute >= 2) + { + min_buf |= (uint32_t)1<<1; + minute -= 2; + } + else + { + min_buf &= ~(uint32_t)1<<1; + } + + if (minute >= 1) + { + min_buf |= (uint32_t)1; + minute -= 1; + } + else + { + min_buf &= ~(uint32_t)1; + } + + RTC->HMS.MIN = min_buf; + + /* д */ + RTC_StartWrite(); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + + +/*************************************************************** + RTC_WriteHour + ޸ʱ + ֵhour: ʱ + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteHour(uint32_t hour, uint32_t meridiem) +{ + uint32_t flag,mode; + uint32_t hour_buf = 0; + + /* */ + if (hour >= 24) + return ERROR; + + mode = RTC_ReadHourmode(); + + if(mode == RTC_HOUR12 && hour > 12) //12Сʱģʽɴ12Сʱ + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if(mode == RTC_HOUR24) + { + if (hour >= 20) + { + hour_buf |= (uint32_t)1<<5; + hour -= 20; + } + else + { + hour_buf &= ~((uint32_t)1<<5); + } + } + else + { + if(meridiem == 1) + hour_buf |= (uint32_t)1<<5; + else + hour_buf &= ~((uint32_t)1<<5); + } + + if (hour >= 10) + { + hour_buf |= (uint32_t)1<<4; + hour -= 10; + } + else + { + hour_buf &= ~((uint32_t)1<<4); + } + + if (hour >= 8) + { + hour_buf |= (uint32_t)1<<3; + hour -= 8; + } + else + { + hour_buf &= ~((uint32_t)1<<3); + } + + if (hour >= 4) + { + hour_buf |= (uint32_t)1<<2; + hour -= 4; + } + else + { + hour_buf &= ~((uint32_t)1<<2); + } + + if (hour >= 2) + { + hour_buf |= (uint32_t)1<<1; + hour -= 2; + } + else + { + hour_buf &= ~((uint32_t)1<<1); + } + + if (hour >= 1) + { + hour_buf |= (uint32_t)1; + hour -= 1; + } + else + { + hour_buf &= ~(uint32_t)1; + } + + RTC->HMS.HOUR = hour_buf; + + /* д */ + RTC_StartWrite(); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + +/*************************************************************** + RTC_WriteDay + ޸ + ֵday: + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteDay(uint32_t day) +{ + uint32_t flag; + uint32_t day_buf = 0; + + /* */ + if ((day == 0) || (day >= 32)) + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if (day >= 20) + { + day_buf |= (uint32_t)1<<5; + day -= 20; + } + else + { + day_buf &= ~((uint32_t)1<<5); + } + + if (day >= 10) + { + day_buf |= (uint32_t)1<<4; + day -= 10; + } + else + { + day_buf &= ~((uint32_t)1<<4); + } + + if (day >= 8) + { + day_buf |= (uint32_t)1<<3; + day -= 8; + } + else + { + day_buf &= ~((uint32_t)1<<3); + } + + if (day >= 4) + { + day_buf |= (uint32_t)1<<2; + day -= 4; + } + else + { + day_buf &= ~((uint32_t)1<<2); + } + + if (day >= 2) + { + day_buf |= (uint32_t)1<<1; + day -= 2; + } + else + { + day_buf &= ~((uint32_t)1<<1); + } + + if (day >= 1) + { + day_buf |= (uint32_t)1; + day -= 1; + } + else + { + day_buf &= ~(uint32_t)1; + } + + RTC->YMDW.DAY = day_buf; + + /* д */ + RTC_StartWrite(); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + + +/*************************************************************** + RTC_WriteMonth + ޸ + ֵmonth: + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteMonth(uint32_t month) +{ + uint32_t flag; + uint32_t month_buf = 0; + + /* */ + if ((month == 0) || (month >= 13)) + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if (month >= 10) + { + month_buf |= (uint32_t)1<<4; + month -= 10; + } + else + { + month_buf &= ~((uint32_t)1<<4); + } + + if (month >= 8) + { + month_buf |= (uint32_t)1<<3; + month -= 8; + } + else + { + month_buf &= ~((uint32_t)1<<3); + } + + if (month >= 4) + { + month_buf |= (uint32_t)1<<2; + month -= 4; + } + else + { + month_buf &= ~((uint32_t)1<<2); + } + + if (month >= 2) + { + month_buf |= (uint32_t)1<<1; + month -= 2; + } + else + { + month_buf &= ~((uint32_t)1<<1); + } + + if (month >= 1) + { + month_buf |= (uint32_t)1; + month -= 1; + } + else + { + month_buf &= ~(uint32_t)1; + } + + RTC->YMDW.MON = month_buf; + + /* д */ + RTC_StartWrite(); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + +/*************************************************************** + RTC_WriteYear + ޸ + ֵyear: + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteYear(uint32_t year) +{ + uint32_t flag; + uint32_t year_buf = 0; + + /* */ + if ((year < 2000) || (year > 2099)) + return ERROR; + + /* ת */ + year -= 2000; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if (year >= 80) + { + year_buf |= (uint32_t)1<<7; + year -= 80; + } + else + { + year_buf &= ~((uint32_t)1<<7); + } + + if (year >= 40) + { + year_buf |= (uint32_t)1<<6; + year -= 40; + } + else + { + year_buf &= ~((uint32_t)1<<6); + } + + if (year >= 20) + { + year_buf |= (uint32_t)1<<5; + year -= 20; + } + else + { + year_buf &= ~((uint32_t)1<<5); + } + + if (year >= 10) + { + year_buf |= (uint32_t)1<<4; + year -= 10; + } + else + { + year_buf &= ~((uint32_t)1<<4); + } + + if (year >= 8) + { + year_buf |= (uint32_t)1<<3; + year -= 8; + } + else + { + year_buf &= ~((uint32_t)1<<3); + } + + if (year >= 4) + { + year_buf |= (uint32_t)1<<2; + year -= 4; + } + else + { + year_buf &= ~((uint32_t)1<<2); + } + + if (year >= 2) + { + year_buf |= (uint32_t)1<<1; + year -= 2; + } + else + { + year_buf &= ~((uint32_t)1<<1); + } + + if (year >= 1) + { + year_buf |= (uint32_t)1; + year -= 1; + } + else + { + year_buf &= ~(uint32_t)1; + } + + RTC->YMDW.YEAR = year_buf; + + /* д */ + RTC_StartWrite(); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + +/*************************************************************** + RTC_WriteWeek + ޸ + ֵweek: ڣ0-6 + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteWeek(uint32_t week) +{ + uint32_t flag; + + /* */ + if (week > 6) + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + RTC->YMDW.WEEK = week; + + /* д */ + RTC->CON.TMWR = 1; // д + RTC->CON.TMUP = 1; // д + while (RTC->CON.TMUP == 1); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + +/*************************************************************** + RTC_ReadWeekAlarmMinute + ȡ + ֵ + ֵ + ֵǰķ + ***************************************************************/ +uint32_t RTC_ReadWeekAlarmMinute(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->WA.WM & (uint32_t)0x01) * 1); + result += (((RTC->WA.WM >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->WA.WM >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->WA.WM >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->WA.WM >> 4) & (uint32_t)0x01) * 10); + result += (((RTC->WA.WM >> 5) & (uint32_t)0x01) * 20); + result += (((RTC->WA.WM >> 6) & (uint32_t)0x01) * 40); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_ReadWeekAlarmHour + ȡСʱ + ֵ + ֵ + ֵǰСʱ + ***************************************************************/ +uint32_t RTC_ReadWeekAlarmHour(uint32_t *meridiem) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->WA.WH & (uint32_t)0x01) * 1); + result += (((RTC->WA.WH >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->WA.WH >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->WA.WH >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->WA.WH >> 4) & (uint32_t)0x01) * 10); + + if(RTC_ReadHourmode() == RTC_HOUR24) //24Сʱģʽ20Сʱ + { + result += (((RTC->WA.WH >> 5) & (uint32_t)0x01) * 20); + } + else //12Сʱģʽ1 PM,0 AM + { + *meridiem = (((RTC->WA.WH >> 5) & (uint32_t)0x01)); + } + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_ReadWeekAlarmWeek + ȡ + ֵ + ֵ + ֵǰ + ***************************************************************/ +uint32_t RTC_ReadWeekAlarmWeek(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + switch(RTC->WA.WW) + { + case 0x00: result = 0;break; + case 0x01: result = 1;break; + case 0x02: result = 2;break; + case 0x03: result = 3;break; + case 0x04: result = 4;break; + case 0x05: result = 5;break; + case 0x06: result = 6;break; + default: result = 0;break; + } + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + + +/*************************************************************** + RTC_ReadDayAlarmMinute + ȡ + ֵ + ֵ + ֵǰķ + ***************************************************************/ +uint32_t RTC_ReadDayAlarmMinute(void) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->DA.DM & (uint32_t)0x01) * 1); + result += (((RTC->DA.DM >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->DA.DM >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->DA.DM >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->DA.DM >> 4) & (uint32_t)0x01) * 10); + result += (((RTC->DA.DM >> 5) & (uint32_t)0x01) * 20); + result += (((RTC->DA.DM >> 6) & (uint32_t)0x01) * 40); + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_ReadDaykAlarmHour + ȡСʱ + ֵ + ֵ + ֵǰСʱ + ***************************************************************/ +uint32_t RTC_ReadDayAlarmHour(uint32_t *meridiem) +{ + uint32_t flag; + uint32_t result; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* */ + RTC_StartRead(); + + /* ʱ */ + result = ((RTC->DA.DH & (uint32_t)0x01) * 1); + result += (((RTC->DA.DH >> 1) & (uint32_t)0x01) * 2); + result += (((RTC->DA.DH >> 2) & (uint32_t)0x01) * 4); + result += (((RTC->DA.DH >> 3) & (uint32_t)0x01) * 8); + result += (((RTC->DA.DH >> 4) & (uint32_t)0x01) * 10); + + if(RTC_ReadHourmode() == RTC_HOUR24) //24Сʱģʽ20Сʱ + { + result += (((RTC->DA.DH >> 5) & (uint32_t)0x01) * 20); + } + else //12Сʱģʽ1 PM,0 AM + { + *meridiem = (((RTC->DA.DH >> 5) & (uint32_t)0x01)); + } + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + return result; +} + +/*************************************************************** + RTC_WriteWeekAlarmMinute + ޸ķ + ֵminute: + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteWeekAlarmMinute(uint32_t minute) +{ + uint32_t flag; + uint32_t minute_buf = 0; + + /* */ + if (minute >= 60) + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if (minute >= 40) + { + minute_buf |= (uint32_t)1<<6; + minute -= 40; + } + else + { + minute_buf &= ~(uint32_t)1<<6; + } + + if (minute >= 20) + { + minute_buf |= (uint32_t)1<<5; + minute -= 20; + } + else + { + minute_buf &= ~(uint32_t)1<<5; + } + + if (minute >= 10) + { + minute_buf |= (uint32_t)1<<4; + minute -= 10; + } + else + { + minute_buf &= ~(uint32_t)1<<4; + } + + if (minute >= 8) + { + minute_buf |= (uint32_t)1<<3; + minute -= 8; + } + else + { + minute_buf &= ~(uint32_t)1<<3; + } + + if (minute >= 4) + { + minute_buf |= (uint32_t)1<<2; + minute -= 4; + } + else + { + minute_buf &= ~(uint32_t)1<<2; + } + + if (minute >= 2) + { + minute_buf |= (uint32_t)1<<1; + minute -= 2; + } + else + { + minute_buf &= ~(uint32_t)1<<1; + } + + if (minute >= 1) + { + minute_buf |= (uint32_t)1; + minute -= 1; + } + else + { + minute_buf &= ~(uint32_t)1; + } + + RTC->WA.WM = minute_buf; + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + +/*************************************************************** + RTC_WriteWeekAlarmHour + ޸Сʱ + ֵhour: Сʱ + meridiem(12СʱģʽʱЧ) + 0 AM + 1 PM + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteWeekAlarmHour(uint32_t hour, uint32_t meridiem) +{ + uint32_t flag,mode; + uint32_t hour_buf = 0; + + /* */ + if (hour >= 24) + return ERROR; + + mode = RTC_ReadHourmode(); + + if(mode == RTC_HOUR12 && hour > 12) //12Сʱģʽɴ12Сʱ + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if(mode == RTC_HOUR24) + { + if (hour >= 20) + { + hour_buf |= (uint32_t)1<<5; + hour -= 20; + } + else + { + hour_buf &= ~((uint32_t)1<<5); + } + } + else + { + if(meridiem == 1) + hour_buf |= (uint32_t)1<<5; + else + hour_buf &= ~((uint32_t)1<<5); + } + + if (hour >= 10) + { + hour_buf |= (uint32_t)1<<4; + hour -= 10; + } + else + { + hour_buf &= ~((uint32_t)1<<4); + } + + if (hour >= 8) + { + hour_buf |= (uint32_t)1<<3; + hour -= 8; + } + else + { + hour_buf &= ~((uint32_t)1<<3); + } + + if (hour >= 4) + { + hour_buf |= (uint32_t)1<<2; + hour -= 4; + } + else + { + hour_buf &= ~((uint32_t)1<<2); + } + + if (hour >= 2) + { + hour_buf |= (uint32_t)1<<1; + hour -= 2; + } + else + { + hour_buf &= ~((uint32_t)1<<1); + } + + if (hour >= 1) + { + hour_buf |= (uint32_t)1; + hour -= 1; + } + else + { + hour_buf &= ~(uint32_t)1; + } + + RTC->WA.WH = hour_buf; + + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} +/*************************************************************** + RTC_WriteWeekAlarmWeek + ޸ + ֵweek: ڣ0-6 + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteWeekAlarmWeek(uint32_t week) +{ + uint32_t flag; + + /* */ + if (week > 6) + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + RTC->WA.WW = week; + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + +/*************************************************************** + RTC_WriteDayAlarmMinute + ޸ķ + ֵminute: + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteDayAlarmMinute(uint32_t minute) +{ + uint32_t flag,minute_buf; + + /* */ + if (minute >= 60) + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if (minute >= 40) + { + minute_buf |= (uint32_t)1<<6; + minute -= 40; + } + else + { + minute_buf &= ~(uint32_t)1<<6; + } + + if (minute >= 20) + { + minute_buf |= (uint32_t)1<<5; + minute -= 20; + } + else + { + minute_buf &= ~(uint32_t)1<<5; + } + + if (minute >= 10) + { + minute_buf |= (uint32_t)1<<4; + minute -= 10; + } + else + { + minute_buf &= ~(uint32_t)1<<4; + } + + if (minute >= 8) + { + minute_buf |= (uint32_t)1<<3; + minute -= 8; + } + else + { + minute_buf &= ~(uint32_t)1<<3; + } + + if (minute >= 4) + { + minute_buf |= (uint32_t)1<<2; + minute -= 4; + } + else + { + minute_buf &= ~(uint32_t)1<<2; + } + + if (minute >= 2) + { + minute_buf |= (uint32_t)1<<1; + minute -= 2; + } + else + { + minute_buf &= ~(uint32_t)1<<1; + } + + if (minute >= 1) + { + minute_buf |= (uint32_t)1; + minute -= 1; + } + else + { + minute_buf &= ~(uint32_t)1; + } + + RTC->DA.DM = minute_buf; + + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + +/*************************************************************** + RTC_WriteDayAlarmHour + ޸Сʱ + ֵhour: Сʱ + meridiem(12СʱģʽʱЧ) + 0 AM + 1 PM + ֵ + ֵ + ***************************************************************/ +ErrorStatus RTC_WriteDayAlarmHour(uint32_t hour, uint32_t meridiem) +{ + uint32_t flag,mode; + uint32_t hour_buf = 0; + + /* */ + if (hour >= 24) + return ERROR; + + mode = RTC_ReadHourmode(); + + if(mode == RTC_HOUR12 && hour > 12) //12Сʱģʽɴ12Сʱ + return ERROR; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + if(mode == RTC_HOUR24) + { + if (hour >= 20) + { + hour_buf |= (uint32_t)1<<5; + hour -= 20; + } + else + { + hour_buf &= ~((uint32_t)1<<5); + } + } + else + { + if(meridiem == 1) + hour_buf |= (uint32_t)1<<5; + else + hour_buf &= ~((uint32_t)1<<5); + } + + if (hour >= 10) + { + hour_buf |= (uint32_t)1<<4; + hour -= 10; + } + else + { + hour_buf &= ~((uint32_t)1<<4); + } + + if (hour >= 8) + { + hour_buf |= (uint32_t)1<<3; + hour -= 8; + } + else + { + hour_buf &= ~((uint32_t)1<<3); + } + + if (hour >= 4) + { + hour_buf |= (uint32_t)1<<2; + hour -= 4; + } + else + { + hour_buf &= ~((uint32_t)1<<2); + } + + if (hour >= 2) + { + hour_buf |= (uint32_t)1<<1; + hour -= 2; + } + else + { + hour_buf &= ~((uint32_t)1<<1); + } + + if (hour >= 1) + { + hour_buf |= (uint32_t)1; + hour -= 1; + } + else + { + hour_buf &= ~(uint32_t)1; + } + + RTC->DA.DH = hour_buf; + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return SUCCESS; +} + + +/*************************************************************** + RTC_InterruptEnable + ʹʵʱʱӵijЩж + ֵsrc: ʵʱʱӵжԴ + ֵ + ֵ + ***************************************************************/ +void RTC_InterruptEnable(RTC_Interrupt_Source src) +{ + uint32_t flag; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + switch (src) + { + case RTC_Interrupt_Source_Second: + RTC->IE.SCDIE = 1; + break; + case RTC_Interrupt_Source_Minute: + RTC->IE.MINIE = 1; + break; + case RTC_Interrupt_Source_Hour: + RTC->IE.HORIE = 1; + break; + case RTC_Interrupt_Source_Day: + RTC->IE.DAYIE = 1; + break; + case RTC_Interrupt_Source_Month: + RTC->IE.MONIE = 1; + break; + case RTC_Interrupt_Source_DayALE: + RTC->IE.DALE = 1; + break; + case RTC_Interrupt_Source_WeekALE: + RTC->IE.WALE = 1; + break; + default: + break; + } + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + + NVIC->ISER[0] |= (1 << 20); // ʹNVICж + return; +} + +/*************************************************************** + RTC_InterruptDisable + ʵʱʱӵijЩж + ֵsrc: ʵʱʱӵжԴ + ֵ + ֵ + ***************************************************************/ +void RTC_InterruptDisable(RTC_Interrupt_Source src) +{ + uint32_t flag; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + /* µֵ */ + switch (src) + { + case RTC_Interrupt_Source_Second: + RTC->IE.SCDIE = 0; + break; + case RTC_Interrupt_Source_Minute: + RTC->IE.MINIE = 0; + break; + case RTC_Interrupt_Source_Hour: + RTC->IE.HORIE = 0; + break; + case RTC_Interrupt_Source_Day: + RTC->IE.DAYIE = 0; + break; + case RTC_Interrupt_Source_Month: + RTC->IE.MONIE = 0; + break; + case RTC_Interrupt_Source_DayALE: + RTC->IE.DALE = 0; + break; + case RTC_Interrupt_Source_WeekALE: + RTC->IE.WALE = 0; + break; + default: + break; + } + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return; +} + +/*************************************************************** + RTC_GetITStatus + ȡʵʱʱӵijЩж״̬ + ֵsrc: ʵʱʱӵжԴ + ֵ + ֵжϱ־ + ***************************************************************/ +ITStatus RTC_GetITStatus(RTC_Interrupt_Source src) +{ + ITStatus result = RESET; + + switch (src) + { + case RTC_Interrupt_Source_Second: + if(RTC->IE.SCDIE) + result = SET; + break; + case RTC_Interrupt_Source_Minute: + if(RTC->IE.MINIE) + result = SET; + break; + case RTC_Interrupt_Source_Hour: + if(RTC->IE.HORIE) + result = SET; + break; + case RTC_Interrupt_Source_Day: + if(RTC->IE.DAYIE) + result = SET; + break; + case RTC_Interrupt_Source_Month: + if(RTC->IE.MONIE) + result = SET; + break; + case RTC_Interrupt_Source_DayALE: + if(RTC->IE.DALE) + result = SET; + break; + case RTC_Interrupt_Source_WeekALE: + if(RTC->IE.WALE) + result = SET; + break; + default: + result = RESET; + break; + } + + return result; +} + +/*************************************************************** + RTC_GetFlagStatus + ȡʵʱʱӵijЩжϱ־ + ֵsrc: ʵʱʱӵжԴ + ֵ + ֵжϱ־ + ***************************************************************/ +FlagStatus RTC_GetFlagStatus(RTC_Interrupt_Source src) +{ + FlagStatus result = RESET; + + switch (src) + { + case RTC_Interrupt_Source_Second: + if(RTC->IF.SCDIF) + result = SET; + break; + case RTC_Interrupt_Source_Minute: + if(RTC->IF.MINIF) + result = SET; + break; + case RTC_Interrupt_Source_Hour: + if(RTC->IF.HORIF) + result = SET; + break; + case RTC_Interrupt_Source_Day: + if(RTC->IF.DAYIF) + result = SET; + break; + case RTC_Interrupt_Source_Month: + if(RTC->IF.MONIF) + result = SET; + break; + case RTC_Interrupt_Source_DayALE: + if(RTC->IF.DAFG) + result = SET; + break; + case RTC_Interrupt_Source_WeekALE: + if(RTC->IF.WAFG) + result = SET; + break; + default: + result = RESET; + break; + } + + return result; +} + +/*************************************************************** + RTC_ClearITPendingBit + ָжϱ־λ + ֵsrc: ʵʱʱӵжԴ + ֵ + ֵ + ***************************************************************/ +void RTC_ClearITPendingBit(RTC_Interrupt_Source src) +{ + uint32_t flag; + + /* RTCд */ + flag = RTC->WP.WP; + if (flag == 0x00000000) + RTC->WP.WP = 0x55AAAA55; + + switch (src) + { + case RTC_Interrupt_Source_Second: + RTC->IF.Word = RTC_Interrupt_Source_Second; + break; + case RTC_Interrupt_Source_Minute: + RTC->IF.Word = RTC_Interrupt_Source_Minute; + break; + case RTC_Interrupt_Source_Hour: + RTC->IF.Word = RTC_Interrupt_Source_Hour; + break; + case RTC_Interrupt_Source_Day: + RTC->IF.Word = RTC_Interrupt_Source_Day; + break; + case RTC_Interrupt_Source_Month: + RTC->IF.Word = RTC_Interrupt_Source_Month; + break; + case RTC_Interrupt_Source_DayALE: + RTC->IF.Word = RTC_Interrupt_Source_DayALE; + break; + case RTC_Interrupt_Source_WeekALE: + RTC->IF.Word = RTC_Interrupt_Source_WeekALE; + break; + default: + + break; + } + + /* RTCд */ + if (flag == 0x00000000) + RTC->WP.WP = 0x00000000; + return; +} + +/*************************END OF FILE**********************/ + + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_scs.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_scs.c new file mode 100644 index 0000000000000000000000000000000000000000..6579ddaee1a042bab0a66418b2db81e262245849 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_scs.c @@ -0,0 +1,97 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_scs.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ںģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_scs.h" + +/*************************************************************** + NVIC_Init + NVICʼ + ֵChannelжͨ Priorityжȼ Cmdʧܻʹ + ֵ + ֵ + ***************************************************************/ +void NVIC_Init(NVIC_IRQChannel Channel,NVIC_IRQPriority Priority,TYPE_FUNCEN Cmd) +{ + uint32_t tmppriority = 0x00; + + if (Cmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority */ + tmppriority = NVIC->IP[Channel >> 0x02]; + tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((Channel & 0x03) * 8))); + tmppriority |= (uint32_t)((((uint32_t)Priority << 6) & 0xFF) << ((Channel & 0x03) * 8)); + + NVIC->IP[Channel >> 0x02] = tmppriority; + + /* Enable the Selected IRQ Channels */ + NVIC->ISER[0] = (uint32_t)0x01 << (Channel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels */ + NVIC->ICER[0] = (uint32_t)0x01 << (Channel & (uint8_t)0x1F); + } +} + +/*************************************************************** + SCB_SystemLPConfig + ϵͳģʽ + ֵLowPowerModeģʽ NewStateʹܡʹ + ֵ + ֵ + ***************************************************************/ +void SCB_SystemLPConfig(SCB_TYPE_SCR LowPowerMode, TYPE_FUNCEN NewState) +{ + if (NewState != DISABLE) + SCB->SCR |= LowPowerMode; + else + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); +} + +/*************************************************************** + SCB_GetCpuID + ȡCPUID + ֵ + ֵ + ֵ32λIDֵ + ***************************************************************/ +uint32_t SCB_GetCpuID(void) +{ + return (SCB->CPUID); +} + +/*************************************************************** + SysTick_Init + SysTickʼ + ֵʼýṹַ + ֵ + ֵ + ***************************************************************/ +void SysTick_Init(SYSTICK_InitStruType* SysT_InitStruct) +{ + uint32_t temp32 = 0; + + SysTick->LOAD = SysT_InitStruct->SysTick_Value; + SysTick->VAL = (uint32_t)0; + + if(SysT_InitStruct->SysTick_ClkSource != SysTick_ClkS_Base) + temp32 |= 0x00000004; + else + temp32 &= 0xFFFFFFFB; + + if(SysT_InitStruct->SysTick_ITEnable != DISABLE) + temp32 |= 0x00000002; + else + temp32 &= 0xFFFFFFFD; + + SysTick->CTRL = temp32; +} + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_scu.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_scu.c new file mode 100644 index 0000000000000000000000000000000000000000..48a3b51ac97cc755fec4078c36385582d214a0c4 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_scu.c @@ -0,0 +1,387 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_scu.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ϵͳģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_scu.h" + +/*************************************************************** + SCU_OpenXTAL + : ⲿʱ + ֵ + ֵ + ֵϵͳʱԴ + ***************************************************************/ +void SCU_OpenXTAL(void) +{ + SCU_RegUnLock(); + SCU->SCLKEN1.XTAL_EN = 1; + SCU->SCLKEN0.XTAL_LP = 0; + while(SCU->SCLKEN1.XTAL_RDY == 0); //ȴⲿʱȶ + SCU_RegLock() ; +} + +/*************************************************************** + SCU_NMISelect + NMIж + ֵж + ֵ + ֵ + ***************************************************************/ +void SCU_NMISelect(SCU_TYPE_NMICS NMI_Type) +{ + SCU_RegUnLock(); + SCU->NMICON.NMICS = NMI_Type; + SCU_RegLock() ; +} + +/*************************************************************** + SCU_GetPWRCFlagStatus + ȡPWRCλ״̬Ĵ־λ״̬ + ֵPWRCĴ־λ + ֵ + ֵRESET/SET + ***************************************************************/ +FlagStatus SCU_GetPWRCFlagStatus(SCU_TYPE_PWRC PWRC_Flag) +{ + FlagStatus bitstatus = RESET; + if((SCU->PWRC.Word & (uint32_t)PWRC_Flag) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + SCU_ClearPWRCFlagBit + PWRCλ״̬Ĵ־λ + ֵPWRCĴ־λ + ֵ + ֵ + ***************************************************************/ +void SCU_ClearPWRCFlagBit(SCU_TYPE_PWRC PWRC_Flag) +{ + SCU_RegUnLock() ; + SCU->PWRC.Word &= ~((uint32_t)PWRC_Flag); + SCU_RegLock() ; +} + +/*************************************************************** + SCU_GetLVDFlagStatus + ȡLVDDĴ־λ״̬ + ֵLVDĴ־λ + ֵ + ֵRESET/SET + ***************************************************************/ +FlagStatus SCU_GetLVDFlagStatus(SCU_TYPE_LVD0CON LVD_Flag) +{ + FlagStatus bitstatus = RESET; + + if((SCU->LVDCON.Word & (uint32_t)LVD_Flag) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + SCU_SysClkSelect + ѡϵͳʱ + ֵʱԴ + ֵ + ֵ + ***************************************************************/ +void SCU_SysClkSelect(SCU_TYPE_SYSCLK Sysclk) +{ + SCU_RegUnLock() ; + SCU->SCLKEN0.CLK_SEL = Sysclk; + SCU_RegLock() ; +} + +/*************************************************************** + SCU_GetSysClk + ȡϵͳʱԴ + ֵ + ֵ + ֵϵͳʱԴ + ***************************************************************/ +SCU_TYPE_SYSCLK SCU_GetSysClk(void) +{ + return (SCU_TYPE_SYSCLK)(SCU->SCLKEN0.CLK_SEL); +} + +/*************************************************************** + SCU_HRCReadyFlag + ȡHRCȶ־λ + ֵ + ֵ + ֵRESETȶ/SETȶ + ***************************************************************/ +FlagStatus SCU_HRCReadyFlag(void) +{ + FlagStatus bitstatus = RESET; + + if((SCU->SCLKEN1.HRC_RDY) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + SCU_XTALReadyFlag + ȡXTALȶ־λ + ֵ + ֵ + ֵRESETȶ/SETȶ + ***************************************************************/ +FlagStatus SCU_XTALReadyFlag(void) +{ + FlagStatus bitstatus = RESET; + + if((SCU->SCLKEN1.XTAL_RDY) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + SCU_LOSCReadyFlag + ȡLOSCȶ־λ + ֵ + ֵ + ֵRESETȶ/SETȶ + ***************************************************************/ +FlagStatus SCU_PLLReadyFlag(void) +{ + FlagStatus bitstatus = RESET; + + if((SCU->SCLKEN1.PLL_RDY) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + SystemClockConfig + ϵͳʱãڲʱӣ20MHZʱ + ֵ + ֵ + ֵ +***************************************************************/ +void SystemClockConfig(void) +{ + uint32_t Prot_Temp; + + Prot_Temp = SCU->PROT.PROT; + + if(Prot_Temp != 0) //д + SCU_RegUnLock(); // + + SCU_HRC_Enable(); //ʹڲ20MHZ + while(SCU_HRCReadyFlag() != SET); //ȴʱӿ + SCU_SysClkSelect(SCU_SysClk_HRC); //ѡڲ20MHZΪϵͳʱ + + SCU_SysClk_Div1(); //ϵͳʱӺƵ1:1 + + SystemCoreClock = 20000000; + + if(Prot_Temp != 0) //д + SCU_RegLock(); //д +} + +/*************************************************************** + DeviceClockAllEnable + ʱ + ֵ + ֵ + ֵ + ***************************************************************/ +void DeviceClockAllEnable(void) +{ + uint32_t Prot_Temp; + + Prot_Temp = SCU->PROT.PROT; + if(Prot_Temp != 0) //д + SCU_RegUnLock(); // + + SCU->PCLKEN0.Word = 0xFFFFFFFF; + SCU->PCLKEN1.Word = 0xFFFFFFFF; //ʱ + + if(Prot_Temp != 0) //д + SCU_RegLock(); //д +} + +/*************************************************************** + DeviceClockAllDisable + رʱ + ֵ + ֵ + ֵ + ***************************************************************/ +void DeviceClockAllDisable(void) +{ + uint32_t Prot_Temp; + + Prot_Temp = SCU->PROT.PROT; + if(Prot_Temp != 0) //д + SCU_RegUnLock(); // + + SCU->PCLKEN0.Word = 0x00000000; //رʱӣscu޷ر + SCU->PCLKEN1.Word = 0x00000000; + + if(Prot_Temp != 0) //д + SCU_RegLock(); //д +} + +/*************************************************************** + SystemClockConfig + ϵͳʱѡ + ֵCLKx ϵͳʱԴѡ + ֵ + ֵ + ***************************************************************/ +void SystemClockSelect(SCU_TYPE_SYSCLK SYSCLKx , SCU_TYPE_CLK_SEL CLK_SEL) +{ + SCU_RegUnLock(); // + + switch(SYSCLKx) + { + case 0: + SCU_HRC_Enable(); + while(SCU_HRCReadyFlag() != SET); + break; + case 1: + SCU_XTAL_Enable(); + while(SCU_XTALReadyFlag() != SET); + break; + case 2: + SCU_PLL_Enable(); + while(SCU_PLLReadyFlag() != SET); + break; + default:break; + } + + SCU->SCLKEN0.SYSCLK_DIV = 0; + SCU->SCLKEN0.CLK_SEL = CLK_SEL; + + SCU_RegLock(); +} + + +/*************************************************************** + PLLClock_Config + PLLʱ,PLLʱΪϵͳʱ + ֵpll_en:ǷPLLpll_originpllʱԴѡpll_outpllƵѡsys_pllϵͳʱǷʹPLLʱ + ֵ + ֵ + ***************************************************************/ +void PLLClock_Config(TYPE_FUNCEN pll_en , SCU_PLL_Origin pll_origin ,SCU_PLL_Out pll_out,TYPE_FUNCEN sys_pll) +{ + SCU_RegUnLock(); + + if(pll_en == DISABLE) //PLLΪֱֹӽֹPLL + { + SCU->SCLKEN0.PLL_MUX = 0; + SCU->SCLKEN1.PLL_BYLOCK = 0; + SCU->SCLKEN0.CLKFLT_BY = 0x00; + SCU->SCLKEN1.PLL_EN = 0; + return; + } + + if((pll_origin == SCU_PLL_HRC)) //ʹڲʱӣ迪ڲʱ + { + if(SCU->SCLKEN1.HRC_RDY == 0) + { + SCU->SCLKEN1.HRC_EN = 1; + while(SCU->SCLKEN1.HRC_RDY == 0); //ȴHRC + } + } + + if((pll_origin == SCU_PLL_XTAL_32K) + || (pll_origin == SCU_PLL_XTAL_4M) + ||(pll_origin == SCU_PLL_XTAL_8M) + || (pll_origin == SCU_PLL_XTAL_16M) + || (pll_origin == SCU_PLL_XTAL_20M)) //ʹⲿʱӣ迪ⲿʱ + { + if(SCU->SCLKEN1.XTAL_RDY == 0) + { + SCU->SCLKEN1.XTAL_EN = 1; + SCU->SCLKEN0.XTAL_LP = 0; + while(SCU->SCLKEN1.XTAL_RDY == 0); //ȴXTAL + } + } + + switch(pll_origin) + { + case SCU_PLL_HRC: + SCU->SCLKEN1.PLL_REF_SEL = 0x00; + break; + case SCU_PLL_LRC: + SCU->SCLKEN1.PLL_REF_SEL = 0x02; + break; + case SCU_PLL_XTAL_32K: + SCU->SCLKEN1.PLL_REF_SEL = 0x03; + break; + case SCU_PLL_XTAL_4M: + SCU->SCLKEN1.PLL_REF_SEL = 0x04; + break; + case SCU_PLL_XTAL_8M: + SCU->SCLKEN1.PLL_REF_SEL = 0x05; + break; + case SCU_PLL_XTAL_16M: + SCU->SCLKEN1.PLL_REF_SEL = 0x06; + break; + case SCU_PLL_XTAL_20M: + SCU->SCLKEN1.PLL_REF_SEL = 0x07; + break; + default: + break; + } + + SCU->SCLKEN1.PLL_48M_SEL = pll_out; //PLLΪ3248Mhz + + SCU->SCLKEN1.PLL_EN = 1; + while(SCU->SCLKEN1.PLL_RDY == 0); + + + if(sys_pll == ENABLE) + { + + if(pll_out == SCU_PLL_32M) + { + SCU->SCLKEN0.CLKFLT_BY = 0; + } + else + { + SCU->SCLKEN0.CLKFLT_BY = 0x55; //48M ʱ˲· + } + SCU->SCLKEN1.PLL_BYLOCK = 1; + SCU->SCLKEN0.PLL_MUX = 1; + } + else + { + SCU->SCLKEN0.PLL_MUX = 0; + SCU->SCLKEN1.PLL_BYLOCK = 0; + SCU->SCLKEN0.CLKFLT_BY = 0x00; + } + + SCU_RegLock(); +} + +/*************************END OF FILE**********************/ + + + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_spi.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..666c142dcf6a871432579a2dbed858d9aed00d61 --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_spi.c @@ -0,0 +1,233 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_spi.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * SPIģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_spi.h" + +/*************************************************************** + SPI0_Init + SPIʼ + ֵʼýṹַ + ֵ + ֵ + ***************************************************************/ +void SPI_Init(SPI_InitStruType* SPI_InitStruct) +{ + uint32_t Temp = 0; + + Temp = SystemCoreClock / (SPI_InitStruct->SPI_Freq * 2); + if(Temp > 254) + Temp = 255; + + SPI0->CKS.CKS = Temp; + + SPI0->CON.DFS = SPI_InitStruct->SPI_Df; + SPI0->CON.MS = SPI_InitStruct->SPI_Mode; + SPI0->CON.DW = SPI_InitStruct->SPI_DW; + SPI0->CON.DRE = SPI_InitStruct->SPI_DelayRec; + SPI0->CON.TME = SPI_InitStruct->SPI_DelaySend; + + Temp = (uint32_t)SPI_InitStruct->SPI_SendDelayPeroid - 1; + if(Temp > 62) + Temp = 63; + + SPI0->CON.TMP = Temp; +} + +/*************************************************************** + SPI0_ITConfig + SPIж + ֵSPI_IEж NewStateʹܡʧ + ֵ + ֵ + ***************************************************************/ +void SPI_ITConfig(SPI_TYPE_IT SPI_IE,TYPE_FUNCEN NewState) +{ + if(NewState != DISABLE) + SPI0->IE.Word |= (uint32_t)SPI_IE; + else + SPI0->IE.Word &= ~((uint32_t)SPI_IE); +} + +/*************************************************************** + SPI0_DataFormatConfig + SPIݸʽ + ֵݸʽ + ֵ + ֵ + ***************************************************************/ +void SPI_DataFormatConfig(SPI_TYPE_DFS Type) +{ + SPI0->CON.DFS = Type; +} + +/*************************************************************** + SPI0_SendByte + SPIһֽڣ8λ + ֵҪ͵ + ֵ + ֵ + ***************************************************************/ +void SPI_SendByte(uint8_t Temp) +{ + SPI0->TBW.Byte[0] = Temp; +} + +/*************************************************************** + SPI0_SendHalfWord + SPIһ֣16λ + ֵҪ͵ + ֵ + ֵ + ***************************************************************/ +void SPI_SendHalfWord(uint16_t Temp) +{ + SPI0->TBW.HalfWord[0] = Temp; +} + +/*************************************************************** + SPI0_SendWord + SPIһ֣32λ + ֵҪ͵ + ֵ + ֵ + ***************************************************************/ +void SPI_SendWord(uint32_t Temp) +{ + SPI0->TBW.Word = Temp; +} + +/*************************************************************** + SPI0_RecByte + SPIһֽ + ֵ + ֵ + ֵյ + ***************************************************************/ +uint8_t SPI_RecByte(void) +{ + return SPI0->RBR.Byte[0]; +} + +/*************************************************************** + SPI0_RecHalfWord + SPIһ + ֵ + ֵ + ֵյ + ***************************************************************/ +uint16_t SPI_RecHalfWord(void) +{ + return SPI0->RBR.HalfWord[0]; +} + +/*************************************************************** + SPI0_RecWord + SPIһ + ֵ + ֵ + ֵյ + ***************************************************************/ +uint32_t SPI_RecWord(void) +{ + return SPI0->RBR.Word; +} + +/*************************************************************** + SPI0_TBIMConfig + SPIͻжģʽѡ + ֵжģʽ + ֵ + ֵ + ***************************************************************/ +void SPI_TBIMConfig(SPI_TYPE_TRBIM Type) +{ + SPI0->IE.TBIM = Type; +} + +/*************************************************************** + SPI0_RBIMConfig + SPIջжģʽѡ + ֵжģʽ + ֵ + ֵ + ***************************************************************/ +void SPI_RBIMConfig(SPI_TYPE_TRBIM Type) +{ + SPI0->IE.RBIM = Type; +} + +/*************************************************************** + SPI0_GetFlagStatus + SPI־λ״̬ + ֵ־λ + ֵ + ֵSET/RESET + ***************************************************************/ +FlagStatus SPI_GetFlagStatus(SPI_TYPE_FLAG Flag) +{ + FlagStatus bitstatus = RESET; + + /* ȡĴ */ + if((uint32_t)Flag <= 0x00000040) + { + if ((SPI0->IF.Word & Flag) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + } + + else + { + if ((SPI0->STA.Word & Flag) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + } + + return bitstatus; +} + +/*************************************************************** + SPI0_GetITStatus + SPIж״̬,δʹӦжʱ᷵SET + ֵжϱ־λ + ֵ + ֵSET/RESET + ***************************************************************/ +ITStatus SPI_GetITStatus(SPI_TYPE_IT Flag) +{ + FlagStatus bitstatus = RESET; + uint32_t itstatus = 0x0, itenable = 0x0; + + itstatus = SPI0->IF.Word & (uint32_t)Flag; + itenable = SPI0->IE.Word & (uint32_t)Flag; + + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + SPI0_ClearITPendingBit + SPIжϱ־ + ֵ־λ + ֵ + ֵ + ***************************************************************/ +void SPI_ClearITPendingBit(SPI_CLR_IF Flag) +{ + SPI0->IF.Word = (uint32_t)Flag; +} + +/*************************END OF FILE**********************/ + diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_timer.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..495e53b4cf42ba317024912454f7e4e2e55a545b --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_timer.c @@ -0,0 +1,569 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_timer.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * ʱģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_timer.h" + +/*************************************************************** + T16Nx_BaseInit + T16Nxʼ + ֵT16NxT16N0/1/2/3 TIM_BaseInitStructʼýṹַ + ֵ + ֵ + ***************************************************************/ +void T16Nx_BaseInit(T16N_TypeDef* T16Nx,TIM_BaseInitStruType* TIM_BaseInitStruct) +{ + T16Nx->CON0.CS = TIM_BaseInitStruct->TIM_ClkS; + T16Nx->CON0.SYNC = TIM_BaseInitStruct->TIM_SYNC; + T16Nx->CON0.EDGE = TIM_BaseInitStruct->TIM_EDGE; + T16Nx->CON0.MOD = TIM_BaseInitStruct->TIM_Mode; +} +/*************************************************************** + T32Nx_BaseInit + T32Nxʼ + ֵT32NxT32N0 TIM_BaseInitStructʼýṹַ + ֵ + ֵ + ***************************************************************/ +void T32Nx_BaseInit(T32N_TypeDef* T32Nx,TIM_BaseInitStruType* TIM_BaseInitStruct) +{ + T32Nx->CON0.CS = TIM_BaseInitStruct->TIM_ClkS; + T32Nx->CON0.SYNC = TIM_BaseInitStruct->TIM_SYNC; + T32Nx->CON0.EDGE = TIM_BaseInitStruct->TIM_EDGE; + T32Nx->CON0.MOD = TIM_BaseInitStruct->TIM_Mode; +} +/*************************************************************** + T16Nx_CapInit + T16Nx׽ʼ + ֵT16NxT16N0/1/2/3 TIM_CapInitStructʼýṹַ + ֵ + ֵ + ***************************************************************/ +void T16Nx_CapInit(T16N_TypeDef* T16Nx,TIM_CapInitStruType* TIM_CapInitStruct) +{ + T16Nx->CON1.CAPPE = TIM_CapInitStruct->TIM_CapRise; + T16Nx->CON1.CAPNE = TIM_CapInitStruct->TIM_CapFall; + T16Nx->CON1.CAPIS0 = TIM_CapInitStruct->TIM_CapIS0; + T16Nx->CON1.CAPIS1 = TIM_CapInitStruct->TIM_CapIS1; + T16Nx->CON1.CAPT = TIM_CapInitStruct->TIM_CapTime; +} +/*************************************************************** + T32Nx_CapInit + T32Nx׽ʼ + ֵT32NxT32N0 TIM_CapInitStructʼýṹַ + ֵ + ֵ + ***************************************************************/ +void T32Nx_CapInit(T32N_TypeDef* T32Nx,TIM_CapInitStruType* TIM_CapInitStruct) +{ + T32Nx->CON1.CAPPE = TIM_CapInitStruct->TIM_CapRise; + T32Nx->CON1.CAPNE = TIM_CapInitStruct->TIM_CapFall; + T32Nx->CON1.CAPIS0 = TIM_CapInitStruct->TIM_CapIS0; + T32Nx->CON1.CAPIS1 = TIM_CapInitStruct->TIM_CapIS1; + T32Nx->CON1.CAPT = TIM_CapInitStruct->TIM_CapTime; +} +/*************************************************************** + T16Nx_MATxITConfig + T16NxƥĹģʽ + ֵT16NxT16N0/1/2/3 TypeƥĹģʽ + ֵ + ֵ + ***************************************************************/ +void T16Nx_MAT0ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type) +{ + T16Nx->CON0.MAT0S = Type; +} +void T16Nx_MAT1ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type) +{ + T16Nx->CON0.MAT1S = Type; +} +void T16Nx_MAT2ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type) +{ + T16Nx->CON0.MAT2S = Type; +} +void T16Nx_MAT3ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type) +{ + T16Nx->CON0.MAT3S = Type; +} +/*************************************************************** + T32Nx_MATxITConfig + T32NxƥĹģʽ + ֵT32NxT32N0 TypeƥĹģʽ + ֵ + ֵ + ***************************************************************/ +void T32Nx_MAT0ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type) +{ + T32Nx->CON0.MAT0S = Type; +} +void T32Nx_MAT1ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type) +{ + T32Nx->CON0.MAT1S = Type; +} +void T32Nx_MAT2ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type) +{ + T32Nx->CON0.MAT2S = Type; +} +void T32Nx_MAT3ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type) +{ + T32Nx->CON0.MAT3S = Type; +} +/*************************************************************** + T16Nx_MATxOutxConfig + T16Nxƥ˿ڵģʽ + ֵT16NxT16N0/1/2/3 Typeƥ˿ڵĹģʽ + ֵ + ֵ + ***************************************************************/ +void T16Nx_MAT0Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type) +{ + T16Nx->CON2.MOM0 = Type; +} +void T16Nx_MAT1Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type) +{ + T16Nx->CON2.MOM1 = Type; +} +void T16Nx_MAT2Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type) +{ + T16Nx->CON2.MOM2 = Type; +} +void T16Nx_MAT3Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type) +{ + T16Nx->CON2.MOM3 = Type; +} +/*************************************************************** + T32Nx_MATxOutxConfig + T32Nxƥ˿ڵģʽ + ֵT32NxT32N0 Typeƥ˿ڵĹģʽ + ֵ + ֵ + ***************************************************************/ +void T32Nx_MAT0Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type) +{ + T32Nx->CON2.MOM0 = Type; +} +void T32Nx_MAT1Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type) +{ + T32Nx->CON2.MOM1 = Type; +} +void T32Nx_MAT2Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type) +{ + T32Nx->CON2.MOM2 = Type; +} +void T32Nx_MAT3Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type) +{ + T32Nx->CON2.MOM3 = Type; +} +/*************************************************************** + T16Nx_ITConfig + T16Nж + ֵT16NxT16N0/1/2/3 Typeж NewStateʹ/ʧ + ֵ + ֵ + ***************************************************************/ +void T16Nx_ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState) +{ + if (NewState != DISABLE) + T16Nx->IE.Word |= (uint32_t)Type; + else + T16Nx->IE.Word &= (~(uint32_t)Type); +} +/*************************************************************** + T32Nx_ITConfig + T32Nж + ֵT32NxT32N0 Typeж NewStateʹ/ʧ + ֵ + ֵ + ***************************************************************/ +void T32Nx_ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState) +{ + if (NewState != DISABLE) + T32Nx->IE.Word|= (uint32_t)Type; + else + T32Nx->IE.Word &= (~(uint32_t)Type); +} +/*************************************************************** + T16Nx_PWMOutConfig + T16N0OUT0,T16N1OUT0T16N2OUT0T16N3OUT0 áԭΪʹuartƣ˲uartͬʱʹá + ֵ + ֵ + ֵ + ***************************************************************/ +void T16Nx_PWMOutConfig(T16N_TypeDef* T16Nx,T16Nx_PWMInitStruType* T16Nx_PWMInitStruct) +{ + T16Nx->CON2.MOE0 = T16Nx_PWMInitStruct->T16Nx_MOE0; //˿0Ƿʹ + T16Nx->CON2.MOE1 = T16Nx_PWMInitStruct->T16Nx_MOE1; //˿1Ƿʹ + T16Nx->CON2.POL0 = T16Nx_PWMInitStruct->T16Nx_POL0; //T16NxOut0 + T16Nx->CON2.POL1 = T16Nx_PWMInitStruct->T16Nx_POL1; //T16NxOut1 +} +/*************************************************************** + T16Nx_PWMBK_Config + PWMɲ + ֵT16NxT16N0/1/2/3 ,Type PWMɲṹ + ֵ + ֵ + ***************************************************************/ +void T16Nx_PWMBK_Config(T16N_TypeDef* T16Nx,T16Nx_PWMBK_Type* type) +{ + T16Nx->CON2.PBKL0 = type->T16Nx_PWMBKL0; //PWMͨ0ɲƽѡ + T16Nx->CON2.PBKL1 = type->T16Nx_PWMBKL1; //PWMͨ1ɲƽѡ + T16Nx->CON2.PBKS = type->T16Nx_PWMBKS; //PWMźԴѡ + T16Nx->CON2.PBKPS = type->T16Nx_PWMBKPS; //PWMͨɲźżѡ + T16Nx->CON2.PBKEN = type->T16Nx_PWMBKEN; //PWMͨɲʹ +} +/*************************************************************** + T16Nx_TRG_Config + : T16N ADCʹ + ֵT16NxT16N0/1/2/3 + ֵ + ֵ + ***************************************************************/ +void T16Nx_TRG_Config(T16N_TypeDef* T16Nx,T16Nx_PWMTRG_type Type,TYPE_FUNCEN NewState) +{ + if(Type == T16Nx_MAT0) + T16Nx->TRG.MAT0TAR = 1; + else if(Type == T16Nx_MAT1) + T16Nx->TRG.MAT1TAR = 1; + else if(Type == T16Nx_MAT2) + T16Nx->TRG.MAT2TAR = 1; + else if(Type == T16Nx_MAT3) + T16Nx->TRG.MAT3TAR = 1; + + T16Nx->TRG.OVTAR = NewState; +} +/*************************************************************** + T16Nx_GetPWMBKF + ȡPWMBKFɲ־λ + ֵT16NxT16N0/1/2/3 + ֵPWMBKF־λֵSETɲ¼RESETδɲ¼ + ֵ + ***************************************************************/ +FlagStatus T16Nx_GetPWMBKF(T16N_TypeDef* T16Nx) +{ + if(T16Nx->CON2.PBKF == 1) + return SET; + else + return RESET; +} +/*************************************************************** + T16Nx_ResetPWMBKF + : PWMBKF־־PWM˿ڻָshuc + ֵT16NxT16N0/1/2/3 + ֵ + ֵ + ***************************************************************/ +void T16Nx_ResetPWMBKF(T16N_TypeDef* T16Nx) +{ + T16Nx->CON2.PBKF = 1; +} +/*************************************************************** + T16Nx_SetCNT + üֵ + ֵT16NxT16N0/1/2/3 Value16λֵ + ֵ + ֵ + ***************************************************************/ +void T16Nx_SetCNT(T16N_TypeDef* T16Nx,uint16_t Value) +{ + T16Nx->CNT.CNT = Value; +} +/*************************************************************** + T32Nx_SetCNT + üֵ + ֵT32NxT32N0 Value32λֵ16λʱҶ룩 + ֵ + ֵ + ***************************************************************/ +void T32Nx_SetCNT(T32N_TypeDef* T32Nx,uint32_t Value) +{ + T32Nx->CNT.CNT = Value; +} +/*************************************************************** + T16Nx_SetPRECNT + ԤƵĴֵ + ֵT16NxT16N0/1/2/3 Value8λֵ + ֵ + ֵ + ***************************************************************/ +void T16Nx_SetPRECNT(T16N_TypeDef* T16Nx,uint8_t Value) +{ + T16Nx->PRECNT.PRECNT = Value; +} +/*************************************************************** + T32Nx_SetPRECNT + ԤƵĴֵ + ֵT32NxT32N0 Value8λֵ + ֵ + ֵ + ***************************************************************/ +void T32Nx_SetPRECNT(T32N_TypeDef* T32Nx,uint8_t Value) +{ + T32Nx->PRECNT.PRECNT = Value - 1; +} +/*************************************************************** + T16Nx_SetPREMAT + ԤƵƥĴֵ + ֵT16NxT16N0/1/2/3 Value8λֵ + ֵ + ֵ + ***************************************************************/ +void T16Nx_SetPREMAT(T16N_TypeDef* T16Nx,uint8_t Value) +{ + T16Nx->PREMAT.PREMAT = Value - 1; +} +/*************************************************************** + T32Nx_SetPREMAT + ԤƵƥĴֵ + ֵT32NxT32N0 Value8λֵ + ֵ + ֵ + ***************************************************************/ +void T32Nx_SetPREMAT(T32N_TypeDef* T32Nx,uint8_t Value) +{ + T32Nx->PREMAT.PREMAT = Value - 1; +} +/*************************************************************** + T16Nx_SetMATx + ƥĴ + ֵT16NxT16N0/1/2/3 MATxTIM_MAT0/1/2/3 Value16λֵ + ֵ + ֵ + ***************************************************************/ +void T16Nx_SetMAT0(T16N_TypeDef* T16Nx,uint16_t Value) +{ + T16Nx->MAT0.MAT0 = Value; +} +void T16Nx_SetMAT1(T16N_TypeDef* T16Nx,uint16_t Value) +{ + T16Nx->MAT1.MAT1 = Value; +} +void T16Nx_SetMAT2(T16N_TypeDef* T16Nx,uint16_t Value) +{ + T16Nx->MAT2.MAT2 = Value; +} +void T16Nx_SetMAT3(T16N_TypeDef* T16Nx,uint16_t Value) +{ + T16Nx->MAT3.MAT3 = Value; +} +/*************************************************************** + T32Nx_SetMATx + ƥĴ + ֵT32NxT32N0 MATxTIM_MAT0/1/2/3 Value32λֵ + ֵ + ֵ + ***************************************************************/ +void T32Nx_SetMAT0(T32N_TypeDef* T32Nx,uint32_t Value) +{ + T32Nx->MAT0.MAT0 = Value; +} +void T32Nx_SetMAT1(T32N_TypeDef* T32Nx,uint32_t Value) +{ + T32Nx->MAT1.MAT1 = Value; +} +void T32Nx_SetMAT2(T32N_TypeDef* T32Nx,uint32_t Value) +{ + T32Nx->MAT2.MAT2 = Value; +} +void T32Nx_SetMAT3(T32N_TypeDef* T32Nx,uint32_t Value) +{ + T32Nx->MAT3.MAT3 = Value; +} +/*************************************************************** + T16Nx_GetMATx + ȡƥĴֵ + ֵT16NxT16N0/1/2/3 + ֵ + ֵ16λֵ + ***************************************************************/ +uint16_t T16Nx_GetMAT0(T16N_TypeDef* T16Nx) +{ + return (T16Nx->MAT0.MAT0); +} +uint16_t T16Nx_GetMAT1(T16N_TypeDef* T16Nx) +{ + return (T16Nx->MAT1.MAT1); +} +uint16_t T16Nx_GetMAT2(T16N_TypeDef* T16Nx) +{ + return (T16Nx->MAT2.MAT2); +} +uint16_t T16Nx_GetMAT3(T16N_TypeDef* T16Nx) +{ + return (T16Nx->MAT3.MAT3); +} +/*************************************************************** + T32Nx_GetMATx + ȡƥĴֵ + ֵT32NxT32N0/3 MATxTIM_MAT0/1/2/3 + ֵ + ֵ32λֵ + ***************************************************************/ +uint32_t T32Nx_GetMAT0(T32N_TypeDef* T32Nx) +{ + return (T32Nx->MAT0.MAT0); +} +uint32_t T32Nx_GetMAT1(T32N_TypeDef* T32Nx) +{ + return (T32Nx->MAT1.MAT1); +} +uint32_t T32Nx_GetMAT2(T32N_TypeDef* T32Nx) +{ + return (T32Nx->MAT2.MAT2); +} +uint32_t T32Nx_GetMAT3(T32N_TypeDef* T32Nx) +{ + return (T32Nx->MAT3.MAT3); +} +/*************************************************************** + T16Nx_GetCNT + ȡĴֵ + ֵT16NxT16N0/1/2/3 + ֵ16λֵ + ***************************************************************/ +uint16_t T16Nx_GetCNT(T16N_TypeDef* T16Nx) +{ + return (T16Nx->CNT.CNT); +} +/*************************************************************** + T32Nx_GetCNT + ȡĴֵ + ֵT32NxT32N0/3 + ֵ16/32λֵ + ***************************************************************/ +uint32_t T32Nx_GetCNT(T32N_TypeDef* T32Nx) +{ + return (T32Nx->CNT.CNT); +} +/*************************************************************** + T16Nx_GetPRECNT + ȡԤƵĴֵ + ֵT16NxT16N0/1/2/3 + ֵ + ֵ8λֵ + ***************************************************************/ +uint8_t T16Nx_GetPRECNT(T16N_TypeDef* T16Nx) +{ + return (uint8_t)(T16Nx->PRECNT.PRECNT); +} +/*************************************************************** + T32Nx_GetPRECNT + ȡԤƵĴֵ + ֵT32NxT32N0 + ֵ + ֵ8λֵ + ***************************************************************/ +uint8_t T32Nx_GetPRECNT(T32N_TypeDef* T32Nx) +{ + return (uint8_t)(T32Nx->PRECNT.PRECNT); +} +/*************************************************************** + T16Nx_GetFlagStatus + ȡָ־λ + ֵT16NxT16N0/1/2/3 TIM_Flagжϱ־λ + ֵ + ֵRESET/SET + ***************************************************************/ +FlagStatus T16Nx_GetFlagStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag) +{ + FlagStatus bitstatus = RESET; + + if((T16Nx->IF.Word & (uint32_t)TIM_Flag) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} +/*************************************************************** + T32Nx_GetFlagStatus + ȡָ־λ + ֵT32NxT32N0 TIM_Flagжϱ־λ + ֵ + ֵRESET/SET + ***************************************************************/ +FlagStatus T32Nx_GetFlagStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag) +{ + FlagStatus bitstatus = RESET; + + if((T32Nx->IF.Word & (uint32_t)TIM_Flag) != (uint32_t)RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + T16Nx_GetITStatus + ȡָжϱ־λ,δʹӦжʱ᷵SET + ֵT16NxT16N0/1/2/3 TIM_Flagжϱ־λ + ֵ + ֵRESET/SET + ***************************************************************/ +ITStatus T16Nx_GetITStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IT TIM_Flag) +{ + ITStatus bitstatus = RESET; + uint32_t itstatus = 0x0, itenable = 0x0; + + itstatus = T16Nx->IF.Word & (uint32_t)TIM_Flag; + itenable = T16Nx->IE.Word & (uint32_t)TIM_Flag; + + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} +/*************************************************************** + T32Nx_GetITStatus + ȡָжϱ־λ,δʹӦжʱ᷵SET + ֵT32NxT32N0 TIM_Flagжϱ־λ + ֵ + ֵRESET/SET + ***************************************************************/ +ITStatus T32Nx_GetITStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IT TIM_Flag) +{ + ITStatus bitstatus = RESET; + uint32_t itstatus = 0x0, itenable = 0x0; + + itstatus = T32Nx->IF.Word & (uint32_t)TIM_Flag; + itenable = T32Nx->IE.Word & (uint32_t)TIM_Flag; + + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} +/*************************************************************** + T16Nx_ClearIFPendingBit + ָжϱ־λ + ֵT16NxT16N0/1/2/3 TIM_Flagжϱ־λ + ֵ + ֵ + ***************************************************************/ +void T16Nx_ClearIFPendingBit(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag) +{ + T16Nx->IF.Word = (uint32_t)TIM_Flag; +} +/*************************************************************** + T32Nx_ClearIFPendingBit + ָжϱ־λ + ֵT32NxT32N0 TIM_Flagжϱ־λ + ֵ + ֵ + ***************************************************************/ +void T32Nx_ClearIFPendingBit(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag) +{ + T32Nx->IF.Word = (uint32_t)TIM_Flag; +} + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_uart.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..0314562ff09b0188e46424a2ef2d007c3e56a08b --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_uart.c @@ -0,0 +1,198 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_uart.c + * ߣ Liut + * V1.00 + * ڣ 2017/07/14 + * UARTģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_uart.h" + +/*************************************************************** + UART_Init + UARTʼ + ֵUARTxUART0/1/2/3/4/5 UART_InitStructʼýṹַ + ֵ + ֵ + ***************************************************************/ +void UART_Init(UART_TypeDef* UARTx,UART_InitStruType* UART_InitStruct) +{ + uint32_t BaudClockTemp = 0, BaudTemp = 0; + + if(UART_InitStruct->UART_ClockSet == UART_Clock_1) + { + BaudClockTemp = (SystemCoreClock/16)%UART_InitStruct->UART_BaudRate; + if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp)) + { + BaudTemp = (SystemCoreClock/16/UART_InitStruct->UART_BaudRate)-1; + } + else + { + BaudTemp = SystemCoreClock/16/UART_InitStruct->UART_BaudRate; + } + } + else if(UART_InitStruct->UART_ClockSet == UART_Clock_2) + { + BaudClockTemp = (SystemCoreClock/32)%UART_InitStruct->UART_BaudRate; + if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp)) + { + BaudTemp = (SystemCoreClock/32/UART_InitStruct->UART_BaudRate)-1; + } + else + { + BaudTemp = SystemCoreClock/32/UART_InitStruct->UART_BaudRate; + } + } + else if(UART_InitStruct->UART_ClockSet == UART_Clock_4) + { + BaudClockTemp = (SystemCoreClock/64)%UART_InitStruct->UART_BaudRate; + if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp)) + { + BaudTemp = (SystemCoreClock/64/UART_InitStruct->UART_BaudRate)-1; + } + else + { + BaudTemp = SystemCoreClock/64/UART_InitStruct->UART_BaudRate; + } + } + + if(BaudTemp > 2046) + { + BaudTemp = 2047; + } + + UARTx->CON.BCS = UART_InitStruct->UART_ClockSet; + UARTx->BRR.BRR = BaudTemp ; + + UARTx->CON.TXFS = UART_InitStruct->UART_StopBits; + UARTx->CON.TXMOD = UART_InitStruct->UART_TxMode; + UARTx->CON.TXP = UART_InitStruct->UART_TxPolar; + UARTx->CON.RXMOD = UART_InitStruct->UART_RxMode; + UARTx->CON.RXP = UART_InitStruct->UART_RxPolar; +} +/*************************************************************** + UART_ITConfig + UARTж + ֵUARTxUART0/1/2/3/4/5 UART_ITж NewStateʹ/ʧ + ֵ + ֵ + ***************************************************************/ +void UART_ITConfig(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT,TYPE_FUNCEN NewState) +{ + if (NewState != DISABLE) + UARTx->IE.Word = (UARTx->IE.Word & (uint32_t)0x0000FFFF) | (uint32_t) UART_IT; + else + UARTx->IE.Word = (UARTx->IE.Word & (uint32_t)0x0000FFFF) & (~((uint32_t) UART_IT)); +} +/*************************************************************** + UART_TBIMConfig + UARTͻжģʽѡ + ֵUARTxUART0/1/2/3/4/5 Typeжģʽ + ֵ + ֵ + ***************************************************************/ +void UART_TBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type) +{ + UARTx->IE.TBIM = Type; +} +/*************************************************************** + UART_RBIMConfig + UARTջжģʽѡ + ֵUARTxUART0/1/2/3 Typeжģʽ + ֵ + ֵ + ***************************************************************/ +void UART_RBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type) +{ + UARTx->IE.RBIM = Type; +} +/*************************************************************** + UART_Sendxxxx + UARTֽڡ֡ + ֵUARTxUART0/1/2/3/4/5 + ֵ + ֵ + ***************************************************************/ +void UART_SendByte(UART_TypeDef* UARTx,uint8_t Temp08) +{ + UARTx->TBW.Byte[0] = Temp08; +} +void UART_SendHalfWord(UART_TypeDef* UARTx,uint16_t Temp16) +{ + UARTx->TBW.HalfWord[0] = Temp16; +} +void UART_SendWord(UART_TypeDef* UARTx,uint32_t Temp32) +{ + UARTx->TBW.Word = Temp32; +} +/*************************************************************** + UART_Recxxxx + UARTֽڡ֡ + ֵUARTxUART0/1/2/3/4/5 + ֵ + ֵ + ***************************************************************/ +uint8_t UART_RecByte(UART_TypeDef* UARTx) +{ + return UARTx->RBR.Byte[0]; +} +uint16_t UART_RecHalfWord(UART_TypeDef* UARTx) +{ + return UARTx->RBR.HalfWord[0]; +} +uint32_t UART_RecWord(UART_TypeDef* UARTx) +{ + return UARTx->RBR.Word; +} +/*************************************************************** + UART_GetFlagStatus + UARTȡ־λ״̬ + ֵUARTxUART0/1/2/3/4/5 UART_Flag־λ + ֵ + ֵSET/RESET + ***************************************************************/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx,UART_TYPE_FLAG UART_Flag) +{ + FlagStatus bitstatus = RESET; + + if ((UARTx->IF.Word & ((uint32_t)UART_Flag)) != RESET) + bitstatus = SET; + else + bitstatus = RESET; + + return bitstatus; +} + +/*************************************************************** + UART_GetITStatus + UARTȡж״̬ + ֵUARTxUART0/1/2/3/4/5 UART_Flag־λ + ֵ + ֵSET/RESET + ***************************************************************/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT) +{ + FlagStatus bitstatus = RESET; + + if((UARTx->IE.Word & ((uint32_t)UART_IT)) == 0) + bitstatus = RESET; + else + bitstatus = SET; + + return bitstatus; +} +/*************************************************************** + UART_ClearIFPendingBit + UART־λ + ֵUARTxUART0/1/2/3/4/5 UART_Flag־λ + ֵ + ֵ + ***************************************************************/ +void UART_ClearIFPendingBit(UART_TypeDef* UARTx,UART_CLR_IF UART_Flag) +{ + UARTx->IF.Word = (uint32_t)UART_Flag; +} + +/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_wdt.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..2218a204a97edd9829a8fc753e50c2d5acdef90a --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/Library/Source/lib_wdt.c @@ -0,0 +1,172 @@ +/*************************************************************** + *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd + *ļ lib_wdt.c + * ߣ Liut + * V1.00 + * ڣ 2017/02/04 + * Źģ⺯ + * ע ES8P508xоƬ + ѧϰʾʹãûֱôķջеκηΡ + ***************************************************************/ +#include "lib_wdt.h" + +/************************************* + IWDT_Init + IWDTʼ + ֵʼṹ + ֵ + **************************************/ +void IWDT_Init(IWDT_InitStruType *WDT_InitStruct) +{ + uint32_t tmp; + + if (WDT_InitStruct->WDT_Clock != WDT_CLOCK_PCLK) + tmp = (uint32_t)(32 * WDT_InitStruct->WDT_Tms); + else + tmp = SystemCoreClock / 1000 * WDT_InitStruct->WDT_Tms; + + IWDT->LOAD.LOAD = tmp; + IWDT->CON.CLKS = WDT_InitStruct->WDT_Clock; + IWDT->CON.IE = WDT_InitStruct->WDT_IE; + IWDT->CON.RSTEN = WDT_InitStruct->WDT_Rst; + + return; +} + +/************************************* + IWDT_SetReloadValue + WDTصijֵ + ֵʼֵ32-bit޷ + ֵ + **************************************/ +void IWDT_SetReloadValue(uint32_t Value) +{ + IWDT->LOAD.LOAD = Value; + return; +} + +/************************************* + IWDT_GetValue + ȡWDTǰֵ + ֵ + ֵǰֵ + **************************************/ +uint32_t IWDT_GetValue(void) +{ + return (uint32_t)IWDT->VALUE.VALUE; +} + +/************************************* + IWDT_GetFlagStatus + ȡWDTж״̬ + ֵ + ֵSET/RESET + **************************************/ +FlagStatus IWDT_GetFlagStatus(void) +{ + FlagStatus bitstatus = RESET; + + if (IWDT->RIS.WDTIF != RESET) + bitstatus = SET; + + return bitstatus; +} + +/************************************* + IWDT_GetITStatus + ȡWDTʹж״̬ + ֵ + ֵSET/RESET + **************************************/ +FlagStatus IWDT_GetITStatus(void) +{ + FlagStatus bitstatus = RESET; + + if (IWDT->CON.IE != RESET) + bitstatus = SET; + + return bitstatus; +} + +/************************************* + WWDT_Init + WWDTʼ + ֵʼṹ + ֵ + **************************************/ +void WWDT_Init(WWDT_InitStruType *WDT_InitStruct) +{ + uint32_t tmp; + + if (WDT_InitStruct->WDT_Clock != WDT_CLOCK_PCLK) + tmp = (uint32_t)(32 * WDT_InitStruct->WDT_Tms); + else + tmp = SystemCoreClock / 1000 * WDT_InitStruct->WDT_Tms; + + WWDT->LOAD.LOAD = tmp; + WWDT->CON.CLKS = WDT_InitStruct->WDT_Clock; + WWDT->CON.IE = WDT_InitStruct->WDT_IE; + WWDT->CON.RSTEN = WDT_InitStruct->WDT_Rst; + WWDT->CON.WWDTWIN = WDT_InitStruct->WDT_Win; + + return; +} + +/************************************* + WWDT_SetReloadValue + WDTصijֵ + ֵʼֵ32-bit޷ + ֵ + **************************************/ +void WWDT_SetReloadValue(uint32_t Value) +{ + WWDT->LOAD.LOAD = Value; + return; +} + +/************************************* + WWDT_GetValue + ȡWDTǰֵ + ֵ + ֵǰֵ + **************************************/ +uint32_t WWDT_GetValue(void) +{ + return (uint32_t)WWDT->VALUE.VALUE; +} + +/************************************* + WWDT_GetFlagStatus + ȡWDTж״̬ + ֵ + ֵSET/RESET + **************************************/ +FlagStatus WWDT_GetFlagStatus(void) +{ + FlagStatus bitstatus = RESET; + + if (WWDT->RIS.WWDTIF != RESET) + bitstatus = SET; + + return bitstatus; +} + +/************************************* + WWDT_GetIEStatus + ȡWDTжʹ״̬ + ֵ + ֵSET/RESET + **************************************/ +FlagStatus WWDT_GetITStatus(void) +{ + FlagStatus bitstatus = RESET; + + if (WWDT->CON.IE != RESET) + bitstatus = SET; + + return bitstatus; +} + +/*************************END OF FILE**********************/ + + diff --git a/bsp/essemi/es8p508x/libraries/SConscript b/bsp/essemi/es8p508x/libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e67dc9e4e3e43aa8e507a81927af651b5a6eeebb --- /dev/null +++ b/bsp/essemi/es8p508x/libraries/SConscript @@ -0,0 +1,27 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = [] + +src += Glob('Library/Source/*.c') +src += ['CMSIS/system_ES8P508x.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/startup_ES8P508x.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + +path = [cwd + '/CMSIS', + cwd + '/Library/Include',] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/essemi/es8p508x/project.uvopt b/bsp/essemi/es8p508x/project.uvopt new file mode 100644 index 0000000000000000000000000000000000000000..26bbe6a024fc45d34456d98d2d20e50d74a2cf69 --- /dev/null +++ b/bsp/essemi/es8p508x/project.uvopt @@ -0,0 +1,174 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 20000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U12345678 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0ES8P508x -FS00 -FL020000 + + + 0 + CMSIS_AGDI + -X"essemi CMSIS-DAP" -U0001A000000A -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00 -FL020000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00000000 -FL020000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/essemi/es8p508x/project.uvproj b/bsp/essemi/es8p508x/project.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..26dac69d04bb891a3e2d7bd28bb39d1e633f4526 --- /dev/null +++ b/bsp/essemi/es8p508x/project.uvproj @@ -0,0 +1,790 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + + + ES8P508xFLXX + ES + IRAM(0x20000000-0x20005FFF) IROM(0x00000000-0x0001FFFF) CLOCK(20000000) CPUTYPE("Cortex-M0") + + "STARTUP\HR\startup_ES8P508x.s" ("ES8P508x Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00000000 -FL020000) + 0 + ES8P508x.h + + + + + + + + + + SFD\HR\ES8P508x.SFR + 0 + 0 + + + + HR\ + HR\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + fromelf --text -c ".\build\keil\@L.axf" --output ".\build\keil\@L.txt" + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 13 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 1 + 0x0 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --c99 + + + .;..\..\..\include;applications;.;drivers;libraries\CMSIS;libraries\Library\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + Libraries + + + irqhandler.c + 1 + libraries\Library\Source\irqhandler.c + + + + + lib_adc.c + 1 + libraries\Library\Source\lib_adc.c + + + + + lib_aes.c + 1 + libraries\Library\Source\lib_aes.c + + + + + lib_crc.c + 1 + libraries\Library\Source\lib_crc.c + + + + + lib_flashiap.c + 1 + libraries\Library\Source\lib_flashiap.c + + + + + lib_gpio.c + 1 + libraries\Library\Source\lib_gpio.c + + + + + lib_iap.c + 1 + libraries\Library\Source\lib_iap.c + + + + + lib_iic.c + 1 + libraries\Library\Source\lib_iic.c + + + + + lib_printf.c + 1 + libraries\Library\Source\lib_printf.c + + + + + lib_rtc.c + 1 + libraries\Library\Source\lib_rtc.c + + + + + lib_scs.c + 1 + libraries\Library\Source\lib_scs.c + + + + + lib_scu.c + 1 + libraries\Library\Source\lib_scu.c + + + + + lib_spi.c + 1 + libraries\Library\Source\lib_spi.c + + + + + lib_timer.c + 1 + libraries\Library\Source\lib_timer.c + + + + + lib_uart.c + 1 + libraries\Library\Source\lib_uart.c + + + + + lib_wdt.c + 1 + libraries\Library\Source\lib_wdt.c + + + + + system_ES8P508x.c + 1 + libraries\CMSIS\system_ES8P508x.c + + + + + startup_ES8P508x.s + 2 + libraries\CMSIS\startup_ES8P508x.s + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + + + diff --git a/bsp/essemi/es8p508x/rtconfig.h b/bsp/essemi/es8p508x/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..034174f9ec17f35573a1cef75ba3ac48017833c9 --- /dev/null +++ b/bsp/essemi/es8p508x/rtconfig.h @@ -0,0 +1,162 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart5" +#define RT_VER_NUM 0x40002 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 2048 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_ES8P508x + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART5 + +/* Onboard Peripheral Drivers */ + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/essemi/es8p508x/rtconfig.py b/bsp/essemi/es8p508x/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..eb371bf3a7199a3b5530611d6fb7f0dc26bf5600 --- /dev/null +++ b/bsp/essemi/es8p508x/rtconfig.py @@ -0,0 +1,135 @@ +import os +import sys + +# toolchains options +CROSS_TOOL = 'keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# device options +ARCH = 'arm' +CPU = 'cortex-m0' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': # not support gcc yet + PLATFORM = 'gcc' + EXEC_PATH = 'C:/GCC' + +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' + +elif CROSS_TOOL == 'iar': # not support iar yet + PLATFORM = 'iar' + EXEC_PATH = 'C:/IAR' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + LFLAGS = ' --config "drivers\linker_scripts\link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS += ' --entry __iar_program_start' + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/essemi/es8p508x/template.uvopt b/bsp/essemi/es8p508x/template.uvopt new file mode 100644 index 0000000000000000000000000000000000000000..26bbe6a024fc45d34456d98d2d20e50d74a2cf69 --- /dev/null +++ b/bsp/essemi/es8p508x/template.uvopt @@ -0,0 +1,174 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 20000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U12345678 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0ES8P508x -FS00 -FL020000 + + + 0 + CMSIS_AGDI + -X"essemi CMSIS-DAP" -U0001A000000A -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00 -FL020000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00000000 -FL020000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/essemi/es8p508x/template.uvproj b/bsp/essemi/es8p508x/template.uvproj new file mode 100644 index 0000000000000000000000000000000000000000..fe2d881412443abba9e2a4edeffa0f16c692e4d3 --- /dev/null +++ b/bsp/essemi/es8p508x/template.uvproj @@ -0,0 +1,400 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + + + ES8P508xFLXX + ES + IRAM(0x20000000-0x20005FFF) IROM(0x00000000-0x0001FFFF) CLOCK(20000000) CPUTYPE("Cortex-M0") + + "STARTUP\HR\startup_ES8P508x.s" ("ES8P508x Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00000000 -FL020000) + 0 + ES8P508x.h + + + + + + + + + + SFD\HR\ES8P508x.SFR + 0 + 0 + + + + HR\ + HR\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + fromelf --text -c ".\build\keil\@L.axf" --output ".\build\keil\@L.txt" + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 13 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 1 + 0x0 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --c99 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + --map --first='startup_M451Series.o(RESET)' --datacompressor=off --info=inline --entry Reset_Handler + + + + + + + + +