diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
index 148a03f45b31df6c945badaa8d2e0bc54b5ae2f2..ecac596d38e29eaf6053228c07e4b088787f397d 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2018-11-19     SummerGift   first version
  * 2018-12-25     zylx         fix some bugs
+ * 2019-06-10     SummerGift   optimize PHY state detection process 
  */
 
 #include "board.h"
@@ -382,7 +383,7 @@ void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
     rt_err_t result;
     result = eth_device_ready(&(stm32_eth_device.parent));
     if (result != RT_EOK)
-        LOG_E("RX err = %d", result);
+        LOG_I("RxCpltCallback err = %d", result);
 }
 
 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
@@ -468,34 +469,50 @@ static void phy_monitor_thread_entry(void *parameter)
 
     while (1)
     {
-        HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
-        LOG_D("PHY BASIC STATUS REG:0x%04X", status);
-
         phy_speed_new = 0;
 
-        if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
+        if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status) == HAL_OK)
         {
-            rt_uint32_t SR;
-
-            phy_speed_new = PHY_LINK_MASK;
-
-            SR = HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
-            LOG_D("PHY Control/Status REG:0x%04X ", SR);
-
-            if (SR & PHY_100M_MASK)
+            LOG_D("PHY BASIC STATUS REG:0x%04X", status);
+            
+            if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
             {
-                phy_speed_new |= PHY_100M_MASK;
-            }
-            else if (SR & PHY_10M_MASK)
-            {
-                phy_speed_new |= PHY_10M_MASK;
-            }
+                rt_uint32_t SR;
 
-            if (SR & PHY_FULL_DUPLEX_MASK)
-            {
-                phy_speed_new |= PHY_FULL_DUPLEX_MASK;
+                phy_speed_new = PHY_LINK_MASK;
+
+                if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR) == HAL_OK)
+                {
+                    LOG_D("PHY Control/Status REG:0x%04X ", SR); 
+
+                    if (SR & PHY_100M_MASK)
+                    {
+                        phy_speed_new |= PHY_100M_MASK;
+                    }
+                    else if (SR & PHY_10M_MASK)
+                    {
+                        phy_speed_new |= PHY_10M_MASK;
+                    }
+
+                    if (SR & PHY_FULL_DUPLEX_MASK)
+                    {
+                        phy_speed_new |= PHY_FULL_DUPLEX_MASK;
+                    }
+                }
+                else
+                {
+                    LOG_D("PHY PHY_Status_REG read error."); 
+                    rt_thread_mdelay(100);
+                    continue;
+                }
             }
         }
+        else
+        {
+            LOG_D("PHY_BASIC_STATUS_REG read error."); 
+            rt_thread_mdelay(100);
+            continue;
+        }
 
         /* linkchange */
         if (phy_speed_new != phy_speed)