diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript b/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript
index f40bfe3561cdf31c1bcd3be6cd2c133532d27fed..77ca10652bdd90bb4974e8c0eff168970fd81d98 100644
--- a/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript
+++ b/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript
@@ -22,6 +22,10 @@ if  GetDepend('SOC_RISCV_FAMILY_CH32'):
     if GetDepend(['BSP_USING_DAC']):
         src += ['drv_dac.c'] 
 
+    if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+        if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'):
+            src += ['drv_soft_i2c.c']
+
 path =  [cwd]
 
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_adc.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_adc.c
index 6ada83c8cfd2350572214d83a39ea03456d3d821..074d0be182982e6d38fa9232553111b41398155c 100644
--- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_adc.c
+++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_adc.c
@@ -148,9 +148,11 @@ static rt_uint32_t ch32_adc_get_channel(rt_uint32_t channel)
         ch32_channel = ADC_Channel_17;
         break;
 #endif /* ADC_CHANNEL_17 */
+#ifdef ADC_CHANNEL_18
     case 18:
         ch32_channel = ADC_Channel_18;
         break;
+#endif /* ADC_CHANNEL_18 */
 #ifdef ADC_CHANNEL_19
     case 19:
         ch32_channel = ADC_Channel_19;
diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_i2c.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..a6de7a5374b06f7ebd5c70f3c224200691dfd01e
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_i2c.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-09-19     hg0720       the first version which add from wch
+ */
+
+#include <board.h>
+#include "drv_soft_i2c.h"
+
+#ifdef RT_USING_I2C
+
+//#define DRV_DEBUG
+#define LOG_TAG              "drv.i2c"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2)
+#error "Please define at least one BSP_USING_I2Cx"
+/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+static const struct ch32_soft_i2c_config soft_i2c_config[] =
+{
+#ifdef BSP_USING_I2C1
+    I2C1_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_I2C2
+    I2C2_BUS_CONFIG,
+#endif
+};
+
+static struct ch32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
+
+/*
+ * This function initializes the i2c pin.
+ *
+ * @param ch32 i2c dirver class.
+ */
+static void ch32_i2c_gpio_init(struct ch32_i2c *i2c)
+{
+    struct ch32_soft_i2c_config* cfg = (struct ch32_soft_i2c_config*)i2c->ops.data;
+
+    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+
+    rt_pin_write(cfg->scl, PIN_HIGH);
+    rt_pin_write(cfg->sda, PIN_HIGH);
+}
+
+/*
+ * This function sets the sda pin.
+ *
+ * @param Ch32 config class.
+ * @param The sda pin state.
+ */
+static void ch32_set_sda(void *data, rt_int32_t state)
+{
+    struct ch32_soft_i2c_config* cfg = (struct ch32_soft_i2c_config*)data;
+    if (state)
+    {
+        rt_pin_write(cfg->sda, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->sda, PIN_LOW);
+    }
+}
+
+/*
+ * This function sets the scl pin.
+ *
+ * @param Ch32 config class.
+ * @param The scl pin state.
+ */
+static void ch32_set_scl(void *data, rt_int32_t state)
+{
+    struct ch32_soft_i2c_config* cfg = (struct ch32_soft_i2c_config*)data;
+    if (state)
+    {
+        rt_pin_write(cfg->scl, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->scl, PIN_LOW);
+    }
+}
+
+/*
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t ch32_get_sda(void *data)
+{
+    struct ch32_soft_i2c_config* cfg = (struct ch32_soft_i2c_config*)data;
+    return rt_pin_read(cfg->sda);
+}
+
+/*
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t ch32_get_scl(void *data)
+{
+    struct ch32_soft_i2c_config* cfg = (struct ch32_soft_i2c_config*)data;
+    return rt_pin_read(cfg->scl);
+}
+
+/*
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+static void ch32_udelay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->CMP;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->CNT;
+    while (1)
+    {
+        tnow = SysTick->CNT;
+        if (tnow != told)
+        {
+            if (tnow > told)
+            {
+                tcnt += tnow - told;
+            }
+            else
+            {
+                tcnt += reload - told + tnow;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+static const struct rt_i2c_bit_ops ch32_bit_ops_default =
+{
+    .data     = RT_NULL,
+    .set_sda  = ch32_set_sda,
+    .set_scl  = ch32_set_scl,
+    .get_sda  = ch32_get_sda,
+    .get_scl  = ch32_get_scl,
+    .udelay   = ch32_udelay,
+    .delay_us = 1,
+    .timeout  = 100
+};
+
+/*
+ * if i2c is locked, this function will unlock it
+ *
+ * @param ch32 config class
+ *
+ * @return RT_EOK indicates successful unlock.
+ */
+static rt_err_t ch32_i2c_bus_unlock(const struct ch32_soft_i2c_config *cfg)
+{
+    rt_int32_t i = 0;
+
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        while (i++ < 9)
+        {
+            rt_pin_write(cfg->scl, PIN_HIGH);
+            ch32_udelay(100);
+            rt_pin_write(cfg->scl, PIN_LOW);
+            ch32_udelay(100);
+        }
+    }
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/* I2C initialization function */
+int rt_hw_i2c_init(void)
+{
+    rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ch32_i2c);
+    rt_err_t result;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        i2c_obj[i].ops = ch32_bit_ops_default;
+        i2c_obj[i].ops.data = (void*)&soft_i2c_config[i];
+        i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
+        ch32_i2c_gpio_init(&i2c_obj[i]);
+        result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
+        RT_ASSERT(result == RT_EOK);
+        ch32_i2c_bus_unlock(&soft_i2c_config[i]);
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+        soft_i2c_config[i].bus_name,
+        soft_i2c_config[i].scl,
+        soft_i2c_config[i].sda);
+    }
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
+
+#endif /* RT_USING_I2C */
diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_i2c.h b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_i2c.h
new file mode 100644
index 0000000000000000000000000000000000000000..e775c7ca0a18b55dd628cade839a2be33b80fac2
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_i2c.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-09-19     hg0720       the first version which add from wch
+ */
+
+#ifndef __DRV_I2C__
+#define __DRV_I2C__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+/* ch32 config class */
+struct ch32_soft_i2c_config
+{
+    rt_uint8_t scl;
+    rt_uint8_t sda;
+    const char *bus_name;
+};
+
+/* ch32 i2c dirver class */
+struct ch32_i2c
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device i2c2_bus;
+};
+
+#ifdef BSP_USING_I2C1
+#define I2C1_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C1_SCL_PIN,                         \
+        .sda = BSP_I2C1_SDA_PIN,                         \
+        .bus_name = "i2c1",                              \
+    }
+#endif
+
+#ifdef BSP_USING_I2C2
+#define I2C2_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C2_SCL_PIN,                         \
+        .sda = BSP_I2C2_SDA_PIN,                         \
+        .bus_name = "i2c2",                              \
+    }
+#endif
+
+int rt_hw_i2c_init(void);
+
+#endif
diff --git a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig
index 292e0f2ad011b22d4e3e9aaf4dd9ec9279053f9e..a14488992a37c53ea4ae22db2fb3dc74b1d9dd48 100644
--- a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig
+++ b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig
@@ -84,6 +84,44 @@ menu "On-chip Peripheral Drivers"
                 default n  
         endif 
 
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C Bus"
+        default n
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN
+        if BSP_USING_I2C
+            config BSP_USING_I2C1
+                bool "Enable I2C1 Bus"
+                default n
+                if BSP_USING_I2C1
+                    comment "Notice: PC7 --> 39; PC6 --> 38"
+                    config BSP_I2C1_SCL_PIN
+                        int "i2c1 SCL pin number"
+                        range 0 79
+                        default 38
+                    config BSP_I2C1_SDA_PIN
+                        int "i2c1 SDA pin number"
+                        range 0 79
+                        default 39
+                endif
+
+            config BSP_USING_I2C2
+                bool "Enable I2C2 Bus"
+                default n
+                if BSP_USING_I2C2
+                    comment "Notice: PC1 --> 33; PC0 --> 32"
+                    config BSP_I2C2_SCL_PIN
+                        int "i2c2 SCL pin number"
+                        range 0 79
+                        default 32
+                    config BSP_I2C2_SDA_PIN
+                        int "i2c2 SDA pin number"
+                        range 0 79
+                        default 33
+                endif
+        endif
+
 endmenu
 
 menu "Onboard Peripheral Drivers"