diff --git a/bsp/zynq7000/README.txt b/bsp/zynq7000/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..f84aaa81e7663bce8116816b816da75bc1dfff3f --- /dev/null +++ b/bsp/zynq7000/README.txt @@ -0,0 +1,5 @@ +Place the rtthread.bin in the SD card and run: + + mmcinfo; fatload mmc 0 0x1ff00000 rtthread.bin; go 0x1ff00000 + +in the uboot console. diff --git a/bsp/zynq7000/SConscript b/bsp/zynq7000/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..fe0ae941ae9a759ae478de901caec1c961e56af8 --- /dev/null +++ b/bsp/zynq7000/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/zynq7000/SConstruct b/bsp/zynq7000/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..9d9b35277a981d5a31340c568cf1bf8c63c8c20d --- /dev/null +++ b/bsp/zynq7000/SConstruct @@ -0,0 +1,34 @@ +import os +import sys +import rtconfig + +if os.path.isdir('./rt-thread'): + RTT_ROOT = os.path.normpath(os.path.join(os.getcwd(), 'rt-thread/')) +elif os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-zynq7000.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# if the linker script changed, relink the target +Depends(TARGET, rtconfig.LINK_SCRIPT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/zynq7000/applications/SConscript b/bsp/zynq7000/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..01eb940dfb35f92c503a78b0b49a4354590f9f3a --- /dev/null +++ b/bsp/zynq7000/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/zynq7000/applications/application.c b/bsp/zynq7000/applications/application.c new file mode 100644 index 0000000000000000000000000000000000000000..ad89c80751f085236387110a33fcf5847c9c96a6 --- /dev/null +++ b/bsp/zynq7000/applications/application.c @@ -0,0 +1,49 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#ifdef RT_USING_COMPONENTS_INIT +#include +#endif +#include + +/* thread phase init */ +static void rt_init_thread_entry(void *parameter) +{ + /* do component initialization */ + rt_components_init(); + rt_kprintf("running on cpu %d\n", + rt_cpu_get_smp_id() & 0x0f); + + /* add your initialization here */ +} + +int rt_application_init() +{ + rt_thread_t tid; + + tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048, + RT_THREAD_PRIORITY_MAX/3, 20); + if (tid != RT_NULL) + rt_thread_startup(tid); + + return 0; +} + diff --git a/bsp/zynq7000/applications/startup.c b/bsp/zynq7000/applications/startup.c new file mode 100644 index 0000000000000000000000000000000000000000..d2958a2c589d2d1c3a6203ae7c02b594f40a3bf2 --- /dev/null +++ b/bsp/zynq7000/applications/startup.c @@ -0,0 +1,81 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include + +#include + +extern int rt_application_init(void); + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + rt_hw_mmu_init(); + + /* initialzie hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize board */ + rt_hw_board_init(); + + /* show RT-Thread version */ + rt_show_version(); + + /* initialize memory system */ +#ifdef RT_USING_HEAP + rt_system_heap_init(HEAP_BEGIN, HEAP_END); +#endif + + /* initialize scheduler system */ + rt_system_scheduler_init(); + + /* initialize system timer */ + rt_system_timer_init(); + + /* initialize soft timer thread */ + rt_system_timer_thread_init(); + + /* initialize application */ + rt_application_init(); + + /* initialize idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* invoke rtthread_startup */ + rtthread_startup(); + + return 0; +} + diff --git a/bsp/zynq7000/drivers/SConscript b/bsp/zynq7000/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..a630c8a7c407f13071e80ddbae48db5b12a32046 --- /dev/null +++ b/bsp/zynq7000/drivers/SConscript @@ -0,0 +1,22 @@ +import copy +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +# remove no need file. +if GetDepend('RT_USING_LWIP') == False: + src_need_remove = ['dm9000.c'] # need remove file list. + SrcRemove(src, src_need_remove) + +if GetDepend('RT_USING_DFS') == False: + src_need_remove = ['sd.c'] # need remove file list. + SrcRemove(src, src_need_remove) + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/zynq7000/drivers/board.c b/bsp/zynq7000/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..1df6199b6097fe960c03d59488313d835f66b704 --- /dev/null +++ b/bsp/zynq7000/drivers/board.c @@ -0,0 +1,88 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include + +#include "board.h" + +typedef struct +{ + volatile rt_uint32_t LOAD; + volatile rt_uint32_t COUNTER; + volatile rt_uint32_t CONTROL; + volatile rt_uint32_t ISR; +} ptimer_reg_t; + +/* Values for control register */ +#define PRIVATE_TIMER_CONTROL_PRESCALER_MASK 0x0000FF00 +#define PRIVATE_TIMER_CONTROL_PRESCALER_SHIFT 8 +#define PRIVATE_TIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004 +#define PRIVATE_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 +#define PRIVATE_TIMER_CONTROL_ENABLE_MASK 0x00000001 + +/* Values for ISR register */ +#define PRIVATE_TIMER_ISR_EVENT_FLAG_MASK 0x00000001 + + +#define PRIVATE_TIMER_BASE 0xF8F00600 +#define PRIVATE_TIMER ((ptimer_reg_t*)PRIVATE_TIMER_BASE) + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + /* clear interrupt */ + PRIVATE_TIMER->ISR = PRIVATE_TIMER_ISR_EVENT_FLAG_MASK; +} + +int rt_hw_timer_init(void) +{ + PRIVATE_TIMER->CONTROL &= ~PRIVATE_TIMER_CONTROL_ENABLE_MASK; + { + /* Clear the prescaler. */ + rt_uint32_t ctrl = PRIVATE_TIMER->CONTROL; + ctrl &= ~PRIVATE_TIMER_CONTROL_PRESCALER_MASK; + PRIVATE_TIMER->CONTROL = ctrl; + } + /* The processor timer is always clocked at 1/2 CPU frequency(CPU_3x2x). */ + PRIVATE_TIMER->COUNTER = APU_FREQ/2/RT_TICK_PER_SECOND; + /* Set reload value. */ + PRIVATE_TIMER->LOAD = APU_FREQ/2/RT_TICK_PER_SECOND; + PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_AUTO_RELOAD_MASK; + + PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_IRQ_ENABLE_MASK; + PRIVATE_TIMER->ISR = PRIVATE_TIMER_ISR_EVENT_FLAG_MASK; + + rt_hw_interrupt_install(IRQ_Zynq7000_PTIMER, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_Zynq7000_PTIMER); + + PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_ENABLE_MASK; + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); + +void rt_hw_board_init() +{ + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + diff --git a/bsp/zynq7000/drivers/board.h b/bsp/zynq7000/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..cfd617f8249e59e83860bc93e1b03959911e920d --- /dev/null +++ b/bsp/zynq7000/drivers/board.h @@ -0,0 +1,64 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +/* Freq of all peripherals */ +#define APU_FREQ 666666667 +#define DDR_FREQ 533333313 +#define DCI_FREQ 10159000 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 100000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 125000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 166666666 +#define I2C_FREQ 25000000 +#define WDT_FREQ 133333333 +#define TTC_FREQ 50000000 +#define CAN_FREQ 100000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 0 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 200000000 +#define FPGA2_FREQ 200000000 +#define FPGA3_FREQ 80000000 + +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) +#endif + +#define HEAP_END (void*)(0x20000000) + +void rt_hw_board_init(); + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/zynq7000/drivers/uart.c b/bsp/zynq7000/drivers/uart.c new file mode 100644 index 0000000000000000000000000000000000000000..f10c48d3300af0d32730beac9c35ea3b680803e0 --- /dev/null +++ b/bsp/zynq7000/drivers/uart.c @@ -0,0 +1,304 @@ +/* + * serial.c UART driver + * + * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#include +#include + +#include "board.h" + +#include "gic.h" +#include "cp15.h" + +#include "uart_hw.h" + +#define Zynq7000_UART_INT_DISABLE(UART) \ + (UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL)) +#define Zynq7000_UART_INT_ENABLE(UART) \ + (UART->IER |= (UART_IXR_RXOVR | UART_IXR_RXFULL)) + +#define Zynq7000_UART_SENDCHAR(UART, ch) \ + do { \ + while ((UART->SR) & UART_SR_TXFULL); \ + UART->FIFO = ch; \ + } while(0) + +#define Zynq7000_UART_GETCHAR(UART, ch) \ + do { \ + if (UART->ISR & UART_SR_RXOVR) \ + { \ + ch = UART->FIFO & 0xff; \ + UART->ISR = (UART_IXR_RXOVR | UART_IXR_RXFULL); \ + } \ + } while(0) + +static void UartEnable(UART_Registers* uart) +{ + uint32_t tmp = uart->CR; + tmp &= ~UART_CR_EN_DIS_MASK; + tmp |= (UART_CR_TX_EN | UART_CR_RX_EN); + + uart->CR = tmp; +} + +static void UartDisable(UART_Registers* uart) +{ + uint32_t tmp = uart->CR; + tmp &= ~UART_CR_EN_DIS_MASK; + tmp |= (UART_CR_TX_DIS | UART_CR_RX_DIS); + uart->CR = tmp; +} + +static void UartResetTXRXLogic(UART_Registers* uart) +{ + uart->CR |= 0x03; + while (uart->CR & 0x03) + ; +} + +/* PULLUP | LVCMOS18 | Fast CMOS | UART */ +#define RX_MIO_PIN_MODE ((0x1UL << 12) | (0x1UL << 9) | (0x01UL << 8) | (0x7UL << 5)) +#define TX_MIO_PIN_MODE ( (0x1UL << 9) | (0x01UL << 8) | (0x7UL << 5)) + +struct hw_uart_device +{ + UART_Registers * uart; + rt_uint32_t irqno; + + /* MIO pin mode address */ + rt_uint32_t *rxmio; + rt_uint32_t *txmio; +}; + +/* RT-Thread UART interface */ + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + rt_hw_serial_isr(serial); +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + uint32_t mr; + struct hw_uart_device *pdev = serial->parent.user_data; + UART_Registers *uart = pdev->uart; + + /* unlock SLCR */ + __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UNLOCK) = 0xDF0D; + + /* no loopback */ + __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_MIO_LOOPBACK) &= ~(1 << 1); + + if (uart == (void*)Zynq7000_UART0_BASE) + { + /* enable the coresponding AMBA Peripheral Clock */ + __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_APER_CLK_CTRL) |= 1 << 20; + /* enable uart clock. Divider 0x14 gives 50MHZ ref clock on IO PLL input. */ + __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_CLK_CTRL) |= (0x14 << 8) | 0x01; + /* deassert the AMBA clock and software reset */ + __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_RST_CTRL) &= ~((0x01 << 2)|(0x01 << 0)); + } + else if (uart == (void*)Zynq7000_UART1_BASE) + { + __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_APER_CLK_CTRL) |= 1 << 21; + __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_CLK_CTRL) |= (0x14 << 8) | 0x02; + __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_RST_CTRL) &= ~((0x01 << 3)|(0x01 << 1)); + } + else + return -RT_ERROR; + + UartDisable(uart); + UartResetTXRXLogic(uart); + UartEnable(uart); + + mr = uart->MR & ~(UART_MR_CHARLEN_MASK | + UART_MR_STOPMODE_MASK | + UART_MR_PARITY_MASK); + + if (cfg->stop_bits == STOP_BITS_2) + mr |= UART_MR_STOPMODE_2_BIT; + else if (cfg->stop_bits == STOP_BITS_1) + mr |= UART_MR_STOPMODE_1_BIT; + else + return -RT_ERROR; + + if (cfg->parity == PARITY_EVEN) + mr |= UART_MR_PARITY_EVEN; + else if (cfg->parity == PARITY_ODD) + mr |= UART_MR_PARITY_ODD; + else if (cfg->parity == PARITY_NONE) + mr |= UART_MR_PARITY_NONE; + else + return -1; + + if (cfg->data_bits == DATA_BITS_8) + mr |= UART_MR_CHARLEN_8_BIT; + else if (cfg->data_bits == DATA_BITS_7) + mr |= UART_MR_CHARLEN_7_BIT; + else if (cfg->data_bits == DATA_BITS_6) + mr |= UART_MR_CHARLEN_6_BIT; + else + return -RT_ERROR; + + uart->MR = mr; + + uart->TXWM = 8; + uart->RXWM = 1; + + if (cfg->baud_rate == BAUD_RATE_115200) + { + uart->BAUDGEN = UART_BAUDGEN_115200; + uart->BAUDDIV = UART_BAUDDIV_115200; + } + else + { + rt_kprintf("baudrate %d not implemented yet\n", cfg->baud_rate); + } + + /* disable all interrupts */ + uart->IDR = UART_IXR_MASK; + + /* configure the pin */ + *(pdev->txmio) = TX_MIO_PIN_MODE; + *(pdev->rxmio) = RX_MIO_PIN_MODE; + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *pdev; + + RT_ASSERT(serial != RT_NULL); + + pdev = serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + Zynq7000_UART_INT_DISABLE(pdev->uart); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + Zynq7000_UART_INT_ENABLE(pdev->uart); + rt_hw_interrupt_install(pdev->irqno, rt_hw_uart_isr, serial, "uart"); + /* set the interrupt to this cpu */ + arm_gic_set_cpu(0, pdev->irqno, 1 << rt_cpu_get_smp_id()); + rt_hw_interrupt_umask(pdev->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *dev; + + RT_ASSERT(serial != RT_NULL); + dev = (struct hw_uart_device *)serial->parent.user_data; + + Zynq7000_UART_SENDCHAR(dev->uart, c); + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct hw_uart_device *dev; + + RT_ASSERT(serial != RT_NULL); + dev = (struct hw_uart_device *)serial->parent.user_data; + + ch = -1; + Zynq7000_UART_GETCHAR(dev->uart, ch); + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +/* UART device driver structure */ +static struct hw_uart_device _uart_device0 = +{ + .uart = (UART_Registers*)Zynq7000_UART0_BASE, + .irqno = IRQ_Zynq7000_UART0, + .rxmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x0728), /* MIO10 */ + .txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x072C), /* MIO11 */ +}; +static struct hw_uart_device _uart_device1 = +{ + .uart = (UART_Registers*)Zynq7000_UART1_BASE, + .irqno = IRQ_Zynq7000_UART1, + .rxmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C4), /* MIO49 */ + .txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C0), /* MIO48 */ +}; + +static struct serial_ringbuffer _uart_int_rx0; +static struct rt_serial_device _serial0; +static struct serial_ringbuffer _uart_int_rx1; +static struct rt_serial_device _serial1; + +int rt_hw_uart_init(void) +{ + struct serial_configure config; + + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + + _serial0.ops = &_uart_ops; + _serial0.int_rx = &_uart_int_rx0; + _serial0.config = config; + + _serial1.ops = &_uart_ops; + _serial1.int_rx = &_uart_int_rx1; + _serial1.config = config; + + /* register uart device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &_uart_device0); + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &_uart_device1); + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + diff --git a/bsp/zynq7000/drivers/uart_hw.h b/bsp/zynq7000/drivers/uart_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..75e3937559bacf90e193accd4c36ce8c83a44701 --- /dev/null +++ b/bsp/zynq7000/drivers/uart_hw.h @@ -0,0 +1,307 @@ +#ifndef _UART_HW_H_ +#define _UART_HW_H_ + +#include + +/** @name Register Map + * + * Registers of the UART. + * @{ + */ +typedef struct +{ + volatile uint32_t CR; /**< Control Register */ + volatile uint32_t MR; /**< Mode Register */ + volatile uint32_t IER; /**< Interrupt Enable */ + volatile uint32_t IDR; /**< Interrupt Disable */ + volatile uint32_t IMR; /**< Interrupt Mask */ + volatile uint32_t ISR; /**< Interrupt Status */ + volatile uint32_t BAUDGEN; /**< Baud Rate Generator */ + volatile uint32_t RXTOUT; /**< RX Timeout */ + volatile uint32_t RXWM; /**< RX FIFO Trigger Level */ + volatile uint32_t MODEMCR; /**< Modem Control */ + volatile uint32_t MODEMSR; /**< Modem Status */ + volatile uint32_t SR; /**< Channel Status */ + volatile uint32_t FIFO; /**< FIFO */ + volatile uint32_t BAUDDIV; /**< Baud Rate Divider */ + volatile uint32_t FLOWDEL; /**< Flow Delay */ + volatile uint32_t RESERVED1; + volatile uint32_t RESERVED2; + volatile uint32_t TXWM; /* TX FIFO Trigger Level */ +} UART_Registers; +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ +#define UART_CR_STOPBRK 0x00000100 /**< Stop transmission of break */ +#define UART_CR_STARTBRK 0x00000080 /**< Set break */ +#define UART_CR_TORST 0x00000040 /**< RX timeout counter restart */ +#define UART_CR_TX_DIS 0x00000020 /**< TX disabled. */ +#define UART_CR_TX_EN 0x00000010 /**< TX enabled */ +#define UART_CR_RX_DIS 0x00000008 /**< RX disabled. */ +#define UART_CR_RX_EN 0x00000004 /**< RX enabled */ +#define UART_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */ +#define UART_CR_TXRST 0x00000002 /**< TX logic reset */ +#define UART_CR_RXRST 0x00000001 /**< RX logic reset */ +/* @}*/ + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ +#define UART_MR_CCLK 0x00000400 /**< Input clock selection */ +#define UART_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */ +#define UART_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */ +#define UART_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */ +#define UART_MR_CHMODE_NORM 0x00000000 /**< Normal mode */ +#define UART_MR_CHMODE_SHIFT 8 /**< Mode shift */ +#define UART_MR_CHMODE_MASK 0x00000300 /**< Mode mask */ +#define UART_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */ +#define UART_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */ +#define UART_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */ +#define UART_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */ +#define UART_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */ +#define UART_MR_PARITY_NONE 0x00000020 /**< No parity mode */ +#define UART_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */ +#define UART_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */ +#define UART_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */ +#define UART_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */ +#define UART_MR_PARITY_SHIFT 3 /**< Parity setting shift */ +#define UART_MR_PARITY_MASK 0x00000038 /**< Parity mask */ +#define UART_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */ +#define UART_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */ +#define UART_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */ +#define UART_MR_CHARLEN_SHIFT 1 /**< Data Length shift */ +#define UART_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */ +#define UART_MR_CLKSEL 0x00000001 /**< Input clock selection */ +/* @} */ + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ +#define UART_IXR_DMS 0x00000200 /**< Modem status change interrupt */ +#define UART_IXR_TOUT 0x00000100 /**< Timeout error interrupt */ +#define UART_IXR_PARITY 0x00000080 /**< Parity error interrupt */ +#define UART_IXR_FRAMING 0x00000040 /**< Framing error interrupt */ +#define UART_IXR_OVER 0x00000020 /**< Overrun error interrupt */ +#define UART_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */ +#define UART_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */ +#define UART_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */ +#define UART_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */ +#define UART_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */ +#define UART_IXR_MASK 0x000003FF /**< Valid bit mask */ +/* @} */ + +/** @name Baud Rate Generator Register + * + * The baud rate generator control register (BRGR) is a 16 bit register that + * controls the receiver bit sample clock and baud rate. + * Valid values are 1 - 65535. + * + * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit + * in the MR register. + * @{ + */ +#define UART_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */ +#define UART_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */ +/* @} */ + +/** @name Baud Divisor Rate register + * + * The baud rate divider register (BDIV) controls how much the bit sample + * rate is divided by. It sets the baud rate. + * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. + * + * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by + * the MR_CCLK bit in the MR register. + * @{ + */ +#define UART_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */ +/* @} */ + +/* + Page 496 + Simplifyed Table 19-1 UART Parameter Value Examples + Parameter Value Examples + Clock Baud BRGR-CD BDIV-CD Actual Baud Rate + UART Ref clock 600 10417 7 + UART Ref clock 9,600 651 7 + UART Ref clock 28,800 347 4 + UART Ref clock 115,200 62 6 + UART Ref clock 230,400 31 6 +*/ + +/*Baudrates assuming input clock speed is 3125000L */ +/*Baud_rate_gen_reg0*/ +#define UART_BAUDGEN_115200 62 /*Baud Rate Clock Divisor*/ + +/*Register Baud_rate_divider_reg0 Details*/ +#define UART_BAUDDIV_115200 6 /*Baud Rate Clock Divisor*/ + +/** @name Receiver Timeout Register + * + * Use the receiver timeout register (RTR) to detect an idle condition on + * the receiver data line. + * + * @{ + */ +#define UART_RXTOUT_DISABLE 0x00000000 /**< Disable time out */ +#define UART_RXTOUT_MASK 0x000000FF /**< Valid bits mask */ +/* @} */ + +/** @name Receiver FIFO Trigger Level Register + * + * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at + * which the RX FIFO triggers an interrupt event. + * @{ + */ +#define UART_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */ +#define UART_RXWM_MASK 0x0000003F /**< Valid bits mask */ +/* @} */ + +/** @name Modem Control Register + * + * This register (MODEMCR) controls the interface with the modem or data set, + * or a peripheral device emulating a modem. + * + * @{ + */ +#define UART_MODEMCR_FCM 0x00000010 /**< Flow control mode */ +#define UART_MODEMCR_RTS 0x00000002 /**< Request to send */ +#define UART_MODEMCR_DTR 0x00000001 /**< Data terminal ready */ +/* @} */ + +/** @name Modem Status Register + * + * This register (MODEMSR) indicates the current state of the control lines + * from a modem, or another peripheral device, to the CPU. In addition, four + * bits of the modem status register provide change information. These bits + * are set to a logic 1 whenever a control input from the modem changes state. + * + * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem + * status interrupt is generated and this is reflected in the modem status + * register. + * + * @{ + */ +#define UART_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */ +#define UART_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */ +#define UART_MODEMSR_RI 0x00000040 /**< Complement of RI input */ +#define UART_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */ +#define UART_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */ +#define UART_MEDEMSR_DCDX 0x00000008 /**< Delta DCD indicator */ +#define UART_MEDEMSR_RIX 0x00000004 /**< Change of RI */ +#define UART_MEDEMSR_DSRX 0x00000002 /**< Change of DSR */ +#define UART_MEDEMSR_CTSX 0x00000001 /**< Change of CTS */ +/* @} */ + +/** @name Channel Status Register + * + * The channel status register (CSR) is provided to enable the control logic + * to monitor the status of bits in the channel interrupt status register, + * even if these are masked out by the interrupt mask register. + * + * @{ + */ +#define UART_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */ +#define UART_SR_TACTIVE 0x00000800 /**< TX active */ +#define UART_SR_RACTIVE 0x00000400 /**< RX active */ +#define UART_SR_DMS 0x00000200 /**< Delta modem status change */ +#define UART_SR_TOUT 0x00000100 /**< RX timeout */ +#define UART_SR_PARITY 0x00000080 /**< RX parity error */ +#define UART_SR_FRAME 0x00000040 /**< RX frame error */ +#define UART_SR_OVER 0x00000020 /**< RX overflow error */ +#define UART_SR_TXFULL 0x00000010 /**< TX FIFO full */ +#define UART_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */ +#define UART_SR_RXFULL 0x00000004 /**< RX FIFO full */ +#define UART_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */ +#define UART_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */ +/* @} */ + +/** @name Flow Delay Register + * + * Operation of the flow delay register (FLOWDEL) is very similar to the + * receive FIFO trigger register. An internal trigger signal activates when the + * FIFO is filled to the level set by this register. This trigger will not + * cause an interrupt, although it can be read through the channel status + * register. In hardware flow control mode, RTS is deactivated when the trigger + * becomes active. RTS only resets when the FIFO level is four less than the + * level of the flow delay trigger and the flow delay trigger is not activated. + * A value less than 4 disables the flow delay. + * @{ + */ +#define UART_FLOWDEL_MASK UART_RXWM_MASK /**< Valid bit mask */ +/* @} */ + + +/** @name Base Address of UART0 + * + * The base address of UART0 + */ +#define UART0_BASE 0xE0000000 + +/** @name Base Address of UART1 + * + * The base address of UART1 + */ +#define UART1_BASE 0xE0001000 + + +#define UART0 ((UART_Registers*)UART0_BASE) +#define UART1 ((UART_Registers*)UART1_BASE) + +/****************************************************************************/ +/** +* Determine if there is receive data in the receiver and/or FIFO. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if there is receive data, FALSE otherwise. +* +* @note C-Style signature: +* uint32_t UartDataReceived(uint32_t BaseAddress) +* +******************************************************************************/ +#define UartDataReceived(BaseAddress) \ + !((io_in32((BaseAddress) + UART_SR_OFFSET) & \ + UART_SR_RXEMPTY) == UART_SR_RXEMPTY) + +/****************************************************************************/ +/** +* Determine if a byte of data can be sent with the transmitter. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the +* FIFO. +* +* @note C-Style signature: +* uint32_t UartTXFIFOFull(uint32_t BaseAddress) +* +******************************************************************************/ +#define UartTXFIFOFull(BaseAddress) \ + ((io_in32((BaseAddress) + UART_SR_OFFSET) & \ + UART_SR_TXFULL) == UART_SR_TXFULL) + +#endif + diff --git a/bsp/zynq7000/drivers/zynq7000.h b/bsp/zynq7000/drivers/zynq7000.h new file mode 100644 index 0000000000000000000000000000000000000000..fb3d349b045e3aac155a2a680970984817f9d0d6 --- /dev/null +++ b/bsp/zynq7000/drivers/zynq7000.h @@ -0,0 +1,59 @@ +#ifndef __AM33XX_H__ +#define __AM33XX_H__ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "armv7.h" + +#define __REG32(x) (*((volatile unsigned int *)(x))) +#define __REG16(x) (*((volatile unsigned short *)(x))) + +#define Zynq7000_UART0_BASE 0xE0000000 +#define Zynq7000_UART1_BASE 0xE0001000 + +#define Zynq7000_SLCR_BASE 0xF8000000 +#define Zynq7000_SLCR_LOCK 0x004 +#define Zynq7000_SLCR_UNLOCK 0x008 +#define Zynq7000_SLCR_APER_CLK_CTRL 0x12C +#define Zynq7000_SLCR_UART_CLK_CTRL 0x154 +#define Zynq7000_SLCR_UART_RST_CTRL 0x228 +#define Zynq7000_SLCR_MIO_LOOPBACK 0x804 +#define Zynq7000_SLCR_MIO_MST_TRI0 0x80C +#define Zynq7000_SLCR_MIO_MST_TRI1 0x810 + +#define Zynq7000_SCTL_BASE 0xF8F00000 /* System Controller */ +#define Zynq7000_TIMER_GLOBAL_BASE 0xF8F00200 /* Global 64bit timer */ + +#define Zynq7000_GIC_CPU_BASE 0xF8F00100 /* Generic interrupt controller CPU interface */ +#define Zynq7000_GIC_DIST_BASE 0xF8F01000 /* Generic interrupt controller distributor */ + +/* zynq on-board gic irq sources */ +#define IRQ_Zynq7000_GTIMER 27 +#define IRQ_Zynq7000_PTIMER 29 +#define IRQ_Zynq7000_AWDT 30 +#define IRQ_Zynq7000_UART0 59 +#define IRQ_Zynq7000_UART1 82 +#define IRQ_Zynq7000_MAXNR 94 + +#define ARM_GIC_NR_IRQS IRQ_Zynq7000_MAXNR +/* only one GIC available */ +#define ARM_GIC_MAX_NR 1 + +#endif diff --git a/bsp/zynq7000/rtconfig.h b/bsp/zynq7000/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..bc015321d0dd11b38dd15033438396702df61eea --- /dev/null +++ b/bsp/zynq7000/rtconfig.h @@ -0,0 +1,143 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// + +// +#define RT_NAME_MAX 6 +// +#define RT_ALIGN_SIZE 4 +// +// 8 +// 32 +// 256 +// +#define RT_THREAD_PRIORITY_MAX 32 +// +#define RT_TICK_PER_SECOND 1000 +// +#define IDLE_THREAD_STACK_SIZE 512 +//
+#define RT_DEBUG +// +// #define RT_THREAD_DEBUG +// +#define RT_USING_OVERFLOW_CHECK +//
+ +// +#define RT_USING_HOOK +//
+// #define RT_USING_TIMER_SOFT +// +#define RT_TIMER_THREAD_PRIO 4 +// +#define RT_TIMER_THREAD_STACK_SIZE 512 +// +#define RT_TIMER_TICK_PER_SECOND 10 +//
+ +//
+// +#define RT_USING_SEMAPHORE +// +#define RT_USING_MUTEX +// +#define RT_USING_EVENT +// +#define RT_USING_MAILBOX +// +#define RT_USING_MESSAGEQUEUE +//
+ +//
+// +#define RT_USING_MEMPOOL +// +// #define RT_USING_MEMHEAP +// +#define RT_USING_HEAP +// +// #define RT_USING_MEMHEAP_AS_HEAP +// +#define RT_USING_SMALL_MEM +// +// #define RT_USING_SLAB +//
+ +//
+#define RT_USING_DEVICE +// +#define RT_USING_DEVICE_IPC +// +#define RT_USING_SERIAL +// +#define RT_UART_RX_BUFFER_SIZE 64 +// +#define RT_USING_INTERRUPT_INFO +//
+ +//
+#define RT_USING_CONSOLE +// +#define RT_CONSOLEBUF_SIZE 128 +// +#define RT_CONSOLE_DEVICE_NAME "uart0" +//
+ +// +#define RT_USING_COMPONENTS_INIT +//
+#define RT_USING_FINSH +// +#define FINSH_USING_MSH +// +#define FINSH_USING_MSH_DEFAULT +// +#define FINSH_USING_SYMTAB +// +#define FINSH_USING_DESCRIPTION +// +#define FINSH_THREAD_STACK_SIZE 4096 +//
+ +//
+// +#define RT_USING_NEWLIB +// +#define RT_USING_PTHREADS +//
+ +//
+// #define RT_USING_DFS +// +// #define DFS_USING_WORKDIR +// +#define DFS_FILESYSTEMS_MAX 2 +// +#define DFS_FD_MAX 4 +// +#define RT_USING_DFS_ELMFAT +// +// 1 +// 2 +// +#define RT_DFS_ELM_USE_LFN 1 +// +#define RT_DFS_ELM_MAX_LFN 64 +// +// #define RT_USING_DFS_YAFFS2 +// +// #define RT_USING_DFS_UFFS +// +// #define RT_USING_DFS_DEVFS +// +// #define RT_USING_DFS_NFS +// +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +//
+// + + +#endif diff --git a/bsp/zynq7000/rtconfig.py b/bsp/zynq7000/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..45889fb7a5bf221b4dd4e0af17b066aef1346811 --- /dev/null +++ b/bsp/zynq7000/rtconfig.py @@ -0,0 +1,84 @@ +import os + +# toolchains options +ARCH='arm' +CPU='zynq7000' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/home/grissiom/' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' +elif CROSS_TOOL == 'iar': + print '================ERROR============================' + print 'Not support IAR yet!' + print '=================================================' + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + #ARCH = -mcpu=cortex-a9 -mfpu=vfpv3 + DEVICE = ' -Wall -mcpu=cortex-a9 -mfpu=vfpv3 -ftree-vectorize -ffast-math -mfloat-abi=softfp' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LINK_SCRIPT = 'zynq7000.ld' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=zynq7000.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMP' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-zynq7000.map --scatter zynq7000.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' diff --git a/bsp/zynq7000/zynq7000.ld b/bsp/zynq7000/zynq7000.ld new file mode 100644 index 0000000000000000000000000000000000000000..ae9b8ea38d704e725dfb38ce4ef55d5177c1c9c9 --- /dev/null +++ b/bsp/zynq7000/zynq7000.ld @@ -0,0 +1,116 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + . = 0x1ff00000; + __text_start = .; + .text : + { + *(.vectors) + /* make the ISRs close to vectors may be more cache-friendly */ + *(.text.isr) + + *(.text) + *(.text.*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + __data_start = .; + . = ALIGN(4); + .data : + { + KEEP(*(.resource_table)) + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(4); + __bss_start = __data_end; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..2ad51b573e9fb738f85c3c91aebd2e9319d2d60d --- /dev/null +++ b/libcpu/arm/zynq7000/SConscript @@ -0,0 +1,17 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') +elif rtconfig.PLATFORM == 'gcc': + src += Glob('*_gcc.S') +elif rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +group = DefineGroup('AM1808', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/zynq7000/armv7.h b/libcpu/arm/zynq7000/armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..65f6c278608f9ef023bdc8d9895b4787de362c07 --- /dev/null +++ b/libcpu/arm/zynq7000/armv7.h @@ -0,0 +1,65 @@ +#ifndef __ARMV7_H__ +#define __ARMV7_H__ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +void rt_hw_mmu_init(void); + +#endif diff --git a/libcpu/arm/zynq7000/context_gcc.S b/libcpu/arm/zynq7000/context_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..3dbf3c861dad162330d847b556e2f3e0467a9196 --- /dev/null +++ b/libcpu/arm/zynq7000/context_gcc.S @@ -0,0 +1,102 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define NOINT 0xc0 + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mrs r0, cpsr + orr r1, r0, #NOINT + msr cpsr_c, r1 + bx lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + msr cpsr, r0 + bx lr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file + + mrs r4, cpsr + tst lr, #0x01 + beq _ARM_MODE + orr r4, r4, #0x20 @ it's thumb code + +_ARM_MODE: + stmfd sp!, {r4} @ push cpsr + + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + ldr sp, [r0] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + + bic r4, r4, #0x20 @ must be ARM mode + msr cpsr_cxsf, r4 + + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r3, [r2] + ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + str r0, [r2] +_reswitch: + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + bx lr diff --git a/libcpu/arm/zynq7000/cp15.h b/libcpu/arm/zynq7000/cp15.h new file mode 100644 index 0000000000000000000000000000000000000000..bd6a23f1b24520240ac07895521fbb497aeabe15 --- /dev/null +++ b/libcpu/arm/zynq7000/cp15.h @@ -0,0 +1,31 @@ +#ifndef __CP15_H__ +#define __CP15_H__ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_vector_set_base(unsigned int addr); + +#endif diff --git a/libcpu/arm/zynq7000/cp15_gcc.S b/libcpu/arm/zynq7000/cp15_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..f1ed6492aad55f8f0deb769583e738dc79a8a6f2 --- /dev/null +++ b/libcpu/arm/zynq7000/cp15_gcc.S @@ -0,0 +1,140 @@ +/* + * File : cp15_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * http://www.rt-thread.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.globl rt_cpu_get_smp_id +rt_cpu_get_smp_id: + mrc p15, #0, r0, c0, c0, #5 + bx lr + +.globl rt_cpu_vector_set_base +rt_cpu_vector_set_base: + mcr p15, #0, r0, c12, c0, #0 + dsb + bx lr + +.globl rt_hw_cpu_dcache_enable +rt_hw_cpu_dcache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_hw_cpu_icache_enable +rt_hw_cpu_icache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +_FLD_MAX_WAY: + .word 0x3ff +_FLD_MAX_IDX: + .word 0x7ff + +.globl rt_cpu_dcache_clean_flush +rt_cpu_dcache_clean_flush: + push {r4-r11} + dmb + mrc p15, #1, r0, c0, c0, #1 @ read clid register + ands r3, r0, #0x7000000 @ get level of coherency + mov r3, r3, lsr #23 + beq finished + mov r10, #0 +loop1: + add r2, r10, r10, lsr #1 + mov r1, r0, lsr r2 + and r1, r1, #7 + cmp r1, #2 + blt skip + mcr p15, #2, r10, c0, c0, #0 + isb + mrc p15, #1, r1, c0, c0, #0 + and r2, r1, #7 + add r2, r2, #4 + ldr r4, _FLD_MAX_WAY + ands r4, r4, r1, lsr #3 + clz r5, r4 + ldr r7, _FLD_MAX_IDX + ands r7, r7, r1, lsr #13 +loop2: + mov r9, r4 +loop3: + orr r11, r10, r9, lsl r5 + orr r11, r11, r7, lsl r2 + mcr p15, #0, r11, c7, c14, #2 + subs r9, r9, #1 + bge loop3 + subs r7, r7, #1 + bge loop2 +skip: + add r10, r10, #2 + cmp r3, r10 + bgt loop1 + +finished: + dsb + isb + pop {r4-r11} + bx lr + +.globl rt_hw_cpu_dcache_disable +rt_hw_cpu_dcache_disable: + push {r4-r11, lr} + bl rt_cpu_dcache_clean_flush + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + pop {r4-r11, lr} + bx lr + +.globl rt_hw_cpu_icache_disable +rt_hw_cpu_icache_disable: + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_cpu_mmu_disable +rt_cpu_mmu_disable: + mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit + dsb + bx lr + +.globl rt_cpu_mmu_enable +rt_cpu_mmu_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x001 + mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit + dsb + bx lr + +.globl rt_cpu_tlb_set +rt_cpu_tlb_set: + mcr p15, #0, r0, c2, c0, #0 + dmb + bx lr diff --git a/libcpu/arm/zynq7000/cpu.c b/libcpu/arm/zynq7000/cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..9853effe3ccb719e654ee46f5c9aab890ef0da1e --- /dev/null +++ b/libcpu/arm/zynq7000/cpu.c @@ -0,0 +1,45 @@ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#include +#include +#include "zynq7000.h" + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + while (1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c new file mode 100644 index 0000000000000000000000000000000000000000..498446db43934cbcbb5ba54d738431d9a8f05a55 --- /dev/null +++ b/libcpu/arm/zynq7000/gic.c @@ -0,0 +1,239 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include + +#include "gic.h" +#include "cp15.h" + +struct arm_gic +{ + rt_uint32_t offset; + + rt_uint32_t dist_hw_base; + rt_uint32_t cpu_hw_base; +}; +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; + +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) + +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + (n/32) * 4) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280) +#define GIC_DIST_ACTIVE_BIT(hw_base) __REG32((hw_base) + 0x300) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + (n/16) * 4) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + (n/4) * 4) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) + +static unsigned int _gic_max_irq; + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); + old_tgt |= cpumask << ((irq % 4)*8); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1 << 10) ? "has" : "no", + gic_type); +} + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint32_t cpumask = 1 << 0; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020) + _gic_max_irq = 1020; + if (_gic_max_irq > ARM_GIC_NR_IRQS) + _gic_max_irq = ARM_GIC_NR_IRQS; + + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + + GIC_DIST_CTRL(dist_base) = 0x0; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32; i < _gic_max_irq; i += 16) + GIC_DIST_CONFIG(dist_base, i) = 0x0; + + /* Set all global interrupts to this CPU only. */ + for (i = 32; i < _gic_max_irq; i += 4) + GIC_DIST_TARGET(dist_base, i) = cpumask; + + /* Set priority on all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 4) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + + /* Disable all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + + /* Set the FIQEn bit, signal FIQ for IGROUP0. */ + GIC_DIST_CTRL(dist_base) = 0x01; + + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].cpu_hw_base = cpu_base; + + GIC_CPU_PRIMASK(cpu_base) = 0xf0; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01; + + return 0; +} + +void arm_gic_set_group(rt_uint32_t index, int vector, int group) +{ + /* As for GICv2, there are only group0 and group1. */ + RT_ASSERT(group <= 1); + RT_ASSERT(vector < _gic_max_irq); + + if (group == 0) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) &= ~(1 << (vector % 32)); + } + else if (group == 1) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) |= (1 << (vector % 32)); + } +} + +void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) +{ + unsigned int reg; + + RT_ASSERT(irq <= 15); + RT_ASSERT(target_cpu <= 255); + + reg = (target_cpu << 16) | irq; + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; +} + +void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) +{ + RT_ASSERT(irq <= 15); + RT_ASSERT(target_cpu <= 255); + + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4); +} diff --git a/libcpu/arm/zynq7000/gic.h b/libcpu/arm/zynq7000/gic.h new file mode 100644 index 0000000000000000000000000000000000000000..4b89538948c97fba46424330e8e17b7b35558603 --- /dev/null +++ b/libcpu/arm/zynq7000/gic.h @@ -0,0 +1,41 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __GIC_H__ +#define __GIC_H__ + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +void arm_gic_set_group(rt_uint32_t index, int vector, int group); + +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq); +void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq); + +void arm_gic_dump_type(rt_uint32_t index); + +#endif + diff --git a/libcpu/arm/zynq7000/interrupt.c b/libcpu/arm/zynq7000/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..ce3fbc8dfbd32b9d96880d89d5b0b1f093979d1c --- /dev/null +++ b/libcpu/arm/zynq7000/interrupt.c @@ -0,0 +1,143 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include "zynq7000.h" +#include "cp15.h" +#include "gic.h" + +#define MAX_HANDLERS IRQ_Zynq7000_MAXNR + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +static void rt_hw_interrupt_handle(int vector, void *param) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +const unsigned int VECTOR_BASE = 0x00; +extern int system_vectors; + +static void rt_hw_vector_init(void) +{ + int sctrl; + unsigned int *src = (unsigned int *)&system_vectors; + + /* C12-C0 is only active when SCTLR.V = 0 */ + asm volatile ("mrc p15, #0, %0, c1, c0, #0" + :"=r" (sctrl)); + sctrl &= ~(1 << 13); + asm volatile ("mcr p15, #0, %0, c1, c0, #0" + : + :"r" (sctrl)); + + asm volatile ("mcr p15, #0, %0, c12, c0, #0" + : + :"r" (src)); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + register rt_uint32_t idx; + + /* set vector table */ + rt_hw_vector_init(); + + /* init exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + for (idx = 0; idx < MAX_HANDLERS; idx++) + { + isr_table[idx].handler = rt_hw_interrupt_handle; + } + + /* initialize ARM GIC */ + arm_gic_dist_init(0, Zynq7000_GIC_DIST_BASE, 0); + arm_gic_cpu_init(0, Zynq7000_GIC_CPU_BASE); + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + arm_gic_mask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + arm_gic_umask(0, vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + /* set the interrupt to this cpu */ + arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); + } + + return old_handler; +} + +void rt_hw_interrupt_clear(int vector) +{ + /* SGI will be cleared automatically. */ + if (vector < 16) + return; +} diff --git a/libcpu/arm/zynq7000/interrupt.h b/libcpu/arm/zynq7000/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..07eafc84e56daceb37d2c374fe30937ab2f8cbf8 --- /dev/null +++ b/libcpu/arm/zynq7000/interrupt.h @@ -0,0 +1,26 @@ +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +void rt_hw_interrupt_clear(int vector); + +#endif /* end of include guard: __INTERRUPT_H__ */ + diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..2a58fabe4fa007386153cc00824cbb592e4a9c38 --- /dev/null +++ b/libcpu/arm/zynq7000/mmu.c @@ -0,0 +1,182 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include + +#include "cp15.h" + +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO +#define XN (1<<4) //eXecute Never + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* Read/Write, cache, write back */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +/* Read/Write, cache, write through */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +/* Read/Write, device type */ +#define RW_NCB (AP_RW|DOMAIN0|NCB|DESC_SEC) +/* Read/Write strongly ordered type */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +/* Read/Write without cache and write buffer, no execute */ +#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) +/* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +/* MMUTable is the name used by codes of Xilinx */ +volatile unsigned long MMUTable[4*1024] SECTION("mmu_tbl") __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_mmu_init(void) +{ + extern rt_uint32_t __text_start; + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /* set page table */ + /* no access to the memory below .text */ + /* 128M cached DDR memory */ + rt_hw_mmu_setmtt((rt_uint32_t)&__text_start, 0x20000000-1, + 0x1ff00000, RW_CB); + /* PL region */ + rt_hw_mmu_setmtt(0x40000000, 0xBFFFFFFF, 0x40000000, RW_NCNBXN); + /* IOP registers */ + rt_hw_mmu_setmtt(0xE0000000, 0xE02FFFFF, 0xE0000000, RW_NCNBXN); + /* no access to the SMC memory(enable it if you want) */ + /* SLCR, PS and CPU private registers, note we map more memory space as the + * entry is 1MB in size. */ + rt_hw_mmu_setmtt(0xF8000000, 0xF8FFFFFF, 0xF8000000, RW_NCNBXN); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + + /* become clients for all domains */ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + diff --git a/libcpu/arm/zynq7000/stack.c b/libcpu/arm/zynq7000/stack.c new file mode 100644 index 0000000000000000000000000000000000000000..8e1b86432e7c98d43331f59480385aff424df7af --- /dev/null +++ b/libcpu/arm/zynq7000/stack.c @@ -0,0 +1,60 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + * 2013-07-15 Bernard add Cortex-A8 support. + */ +#include +#include "zynq7000.h" + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + diff --git a/libcpu/arm/zynq7000/start_gcc.S b/libcpu/arm/zynq7000/start_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..41a7906b00db6ab71e9b6e5de6f37e86f1d0ccb2 --- /dev/null +++ b/libcpu/arm/zynq7000/start_gcc.S @@ -0,0 +1,254 @@ +/* + * File : start_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000000 +.equ ABT_Stack_Size, 0x00000000 +.equ FIQ_Stack_Size, 0x00000100 +.equ IRQ_Stack_Size, 0x00000100 +.equ USR_Stack_Size, 0x00000000 + +#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + +/* stack */ +.globl stack_start +.globl stack_top + +.bss +stack_start: +.rept ISR_Stack_Size +.long 0 +.endr +stack_top: + +.text +/* reset entry */ +.globl _reset +_reset: + /* invalidate SCU */ + ldr r7, =0xF8F0000C + ldr r6, =0xFFFF + str r6, [r7] + + /* disable MMU */ + mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ + bic r0, r0, #0x1 /* clear bit 0 */ + mcr p15, 0, r0, c1, c0, 0 /* write value back */ + + /* set the cpu to SVC32 mode and disable interrupt */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0x13 + msr cpsr_c, r0 + + /* setup stack */ + bl stack_setup + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + + /* start RT-Thread Kernel */ + ldr pc, _rtthread_startup + +_rtthread_startup: + .word rtthread_startup + +stack_setup: + ldr r0, =stack_top + + @ Set the startup stack for svc + mov sp, r0 + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + + @ Switch back to SVC + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + + bx lr + +.section .text.isr, "ax" +/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ + .align 5 +.globl vector_fiq +vector_fiq: + stmfd sp!,{r0-r7,lr} + bl rt_hw_trap_fiq + ldmfd sp!,{r0-r7,lr} + subs pc,lr,#4 + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + + .align 5 +.globl vector_irq +vector_irq: + stmfd sp!, {r0-r12,lr} + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do + + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 + +rt_hw_context_switch_interrupt_do: + mov r1, #0 @ clear flag + str r1, [r0] + + mov r1, sp @ r1 point to {r0-r3} in stack + add sp, sp, #4*4 + ldmfd sp!, {r4-r12,lr}@ reload saved registers + mrs r0, spsr @ get cpsr of interrupt thread + sub r2, lr, #4 @ save old task's pc to r2 + + @ Switch to SVC mode with no interrupt. + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + + stmfd sp!, {r2} @ push old task's pc + stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 + ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread + stmfd sp!, {r1-r4} @ push old task's r0-r3 + stmfd sp!, {r0} @ push old task's cpsr + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] @ store sp in preempted tasks's TCB + + ldr r6, =rt_interrupt_to_thread + ldr r7, [r6] + ldr sp, [r7] @ get new task's stack pointer + + ldmfd sp!, {r4} @ pop new task's cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + + +.macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ +.endm + + .align 5 + .globl vector_swi +vector_swi: + push_svc_reg + bl rt_hw_trap_swi + b . + + .align 5 + .globl vector_undef +vector_undef: + push_svc_reg + bl rt_hw_trap_undef + b . + + .align 5 + .globl vector_pabt +vector_pabt: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .align 5 + .globl vector_dabt +vector_dabt: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .align 5 + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . diff --git a/libcpu/arm/zynq7000/trap.c b/libcpu/arm/zynq7000/trap.c new file mode 100644 index 0000000000000000000000000000000000000000..9bf58f916c930a51fc8acf1197394e5f3c7d37e8 --- /dev/null +++ b/libcpu/arm/zynq7000/trap.c @@ -0,0 +1,185 @@ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include + +#include "zynq7000.h" +#include "gic.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register (struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("data abort:"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +#define GIC_ACK_INTID_MASK 0x000003ff + +void rt_hw_trap_irq() +{ + void *param; + unsigned long ir; + unsigned long fullir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + fullir = arm_gic_get_active_irq(0); + ir = fullir & GIC_ACK_INTID_MASK; + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + if (isr_func) + { + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + arm_gic_ack(0, fullir); +} + +void rt_hw_trap_fiq() +{ + void *param; + unsigned long ir; + unsigned long fullir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + fullir = arm_gic_get_active_irq(0); + ir = fullir & GIC_ACK_INTID_MASK; + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + param = isr_table[ir].param; + + /* turn to interrupt service routine */ + isr_func(ir, param); + + /* end of interrupt */ + arm_gic_ack(0, fullir); +} + diff --git a/libcpu/arm/zynq7000/vector_gcc.S b/libcpu/arm/zynq7000/vector_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..4a44a7395cbbf15e4fe45d39183c3bdc1fe3b072 --- /dev/null +++ b/libcpu/arm/zynq7000/vector_gcc.S @@ -0,0 +1,65 @@ +/* + * File : vector_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .vectors, "ax" +.code 32 + +.globl system_vectors +system_vectors: + ldr pc, _vector_reset + ldr pc, _vector_undef + ldr pc, _vector_swi + ldr pc, _vector_pabt + ldr pc, _vector_dabt + ldr pc, _vector_resv + ldr pc, _vector_irq + ldr pc, _vector_fiq + +.globl _reset +.globl vector_undef +.globl vector_swi +.globl vector_pabt +.globl vector_dabt +.globl vector_resv +.globl vector_irq +.globl vector_fiq + +_vector_reset: + .word _reset +_vector_undef: + .word vector_undef +_vector_swi: + .word vector_swi +_vector_pabt: + .word vector_pabt +_vector_dabt: + .word vector_dabt +_vector_resv: + .word vector_resv +_vector_irq: + .word vector_irq +_vector_fiq: + .word vector_fiq + +.balignl 16,0xdeadbeef