/** @addtogroup STM32F1xx_HAL_Driver
* @{
@@ -54,7 +53,6 @@ extern "C" {
* @{
*/
-/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
@@ -74,6 +72,9 @@ typedef enum
/**
* @}
*/
+/* Exported types ------------------------------------------------------------*/
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h
index 309df36a89a40ade653510ac5a6a28076220684e..923b53eb614bd85c7777f49cfc14f7dbf3fb832c 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -34,15 +34,12 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CAN_H
-#define __STM32F1xx_HAL_CAN_H
+#ifndef STM32F1xx_HAL_CAN_H
+#define STM32F1xx_HAL_CAN_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
- defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
@@ -51,6 +48,7 @@
* @{
*/
+#if defined (CAN1)
/** @addtogroup CAN
* @{
*/
@@ -59,7 +57,6 @@
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
-
/**
* @brief HAL State structures definition
*/
@@ -67,144 +64,183 @@ typedef enum
{
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
- HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
+ HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
+ HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
+ HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
+ HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
-}HAL_CAN_StateTypeDef;
+} HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
+ is allowed to lengthen or shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
- uint32_t Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
- uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
- uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
- uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set to ENABLE or DISABLE. */
+ uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
+ For single CAN instance(14 dedicated filter banks),
+ this parameter must be a number between Min_Data = 0 and Max_Data = 13.
+ For dual CAN instances(28 filter banks shared),
+ this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
- uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set to ENABLE or DISABLE */
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set to ENABLE or DISABLE */
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
- uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE */
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be a value of @ref CAN_filter_activation */
- uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
- This parameter can be set to ENABLE or DISABLE */
+ uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
+ For single CAN instances, this parameter is meaningless.
+ For dual CAN instances, all filter banks with lower index are assigned to master
+ CAN instance, whereas all filter banks with greater index are assigned to slave
+ CAN instance.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
- uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
+} CAN_FilterTypeDef;
-/**
- * @brief CAN Tx message structure definition
+/**
+ * @brief CAN Tx message header structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_Identifier_Type */
+ This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
- uint8_t Data[8]; /*!< Contains the data to be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
+ of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
+ @note: Time Triggered Communication Mode must be enabled.
+ @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
+ This parameter can be set to ENABLE or DISABLE. */
-}CanTxMsgTypeDef;
+} CAN_TxHeaderTypeDef;
/**
- * @brief CAN Rx message structure definition
+ * @brief CAN Rx message header structure definition
*/
typedef struct
{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_Identifier_Type */
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
- uint32_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of @ref CAN_remote_transmission_request */
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
- uint32_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
- uint8_t Data[8]; /*!< Contains the data to be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
- uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
+ @note: Time Triggered Communication Mode must be enabled.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
- This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+ uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-}CanRxMsgTypeDef;
+} CAN_RxHeaderTypeDef;
/**
* @brief CAN handle Structure definition
*/
-typedef struct
+typedef struct __CAN_HandleTypeDef
{
- CAN_TypeDef *Instance; /*!< Register base address */
-
- CAN_InitTypeDef Init; /*!< CAN required parameters */
-
- CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
-
- CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
-
- CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
+ CAN_TypeDef *Instance; /*!< Register base address */
- __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
- HAL_LockTypeDef Lock; /*!< CAN locking object */
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
- __IO uint32_t ErrorCode; /*!< CAN Error code */
+ __IO uint32_t ErrorCode; /*!< CAN Error code.
+ This parameter can be a value of @ref CAN_Error_Code */
-}CAN_HandleTypeDef;
+} CAN_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
@@ -212,28 +248,41 @@ typedef struct
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
-#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
-#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
-#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
-#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
-#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
-#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
-#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
-#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
-#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
-#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
+#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
+#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
+#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
+#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
+#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
+#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
+#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
+#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
+#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
+#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
+#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
+#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
+#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
+#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
+
+#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
+
/**
* @}
*/
-/** @defgroup CAN_InitStatus CAN initialization Status
+/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
-#define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */
+#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
/**
* @}
*/
@@ -241,7 +290,7 @@ typedef struct
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
-#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
+#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
@@ -249,10 +298,11 @@ typedef struct
* @}
*/
+
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
-#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
@@ -263,7 +313,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
-#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@@ -283,10 +333,10 @@ typedef struct
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
-#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@@ -298,11 +348,11 @@ typedef struct
* @}
*/
-/** @defgroup CAN_filter_mode CAN Filter Mode
+/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
-#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
/**
* @}
*/
@@ -310,8 +360,17 @@ typedef struct
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
-#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_activation CAN Filter Activation
+ * @{
+ */
+#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
+#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
/**
* @}
*/
@@ -319,17 +378,17 @@ typedef struct
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
-#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
-/** @defgroup CAN_Identifier_Type CAN Identifier Type
+/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
-#define CAN_ID_STD 0x00000000U /*!< Standard Id */
-#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
+#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
+#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/**
* @}
*/
@@ -337,25 +396,27 @@ typedef struct
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
-#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
-#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
+#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
+#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/**
* @}
*/
-/** @defgroup CAN_transmit_constants CAN Transmit Constants
+/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
* @{
*/
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
+#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
/**
* @}
*/
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
+/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
* @{
*/
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
+#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
+#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
/**
* @}
*/
@@ -363,69 +424,72 @@ typedef struct
/** @defgroup CAN_flags CAN Flags
* @{
*/
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
-#define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK2_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
+#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
+#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
+#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
+#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
+#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
+#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
+#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
+#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
+#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
+#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
+#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
+#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
+#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
+#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
+#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
+#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
/* Receive Flags */
-#define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
-#define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
-#define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
+#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
+#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
-#define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
-#define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
-
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
+#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
+#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
+#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
-#define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
-#define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
-
+#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
+#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
+#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/**
* @}
*/
+
/** @defgroup CAN_Interrupts CAN Interrupts
* @{
*/
-#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+/* Transmit Interrupt */
+#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
-#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
-#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
-#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
-#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
-#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
-#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
-#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
@@ -434,313 +498,228 @@ typedef struct
* @}
*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
- * @{
- */
-
-/* CAN intermediate shift values used for CAN flags */
-#define TSR_REGISTER_INDEX 0x5U
-#define RF0R_REGISTER_INDEX 0x2U
-#define RF1R_REGISTER_INDEX 0x4U
-#define MSR_REGISTER_INDEX 0x1U
-#define ESR_REGISTER_INDEX 0x3U
-
-/* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
-/* Transmit Flags */
-#define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
-#define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
-#define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
-#define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
-#define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
-#define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
-#define CAN_TSR_TME0_BIT_POSITION 0x0000001AU
-#define CAN_TSR_TME1_BIT_POSITION 0x0000001BU
-#define CAN_TSR_TME2_BIT_POSITION 0x0000001CU
-
-/* Receive Flags */
-#define CAN_RF0R_FF0_BIT_POSITION 0x00000003U
-#define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
-
-#define CAN_RF1R_FF1_BIT_POSITION 0x00000003U
-#define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
-
-/* Operating Mode Flags */
-#define CAN_MSR_WKU_BIT_POSITION 0x00000003U
-#define CAN_MSR_SLAK_BIT_POSITION 0x00000001U
-#define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
-
-/* Error Flags */
-#define CAN_ESR_EWG_BIT_POSITION 0x00000000U
-#define CAN_ESR_EPV_BIT_POSITION 0x00000001U
-#define CAN_ESR_BOF_BIT_POSITION 0x00000002U
-
-/* Mask used by macro to get/clear CAN flags*/
-#define CAN_FLAG_MASK 0x000000FFU
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-/**
- * @}
- */
-
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
/** @brief Reset CAN handle state
- * @param __HANDLE__: CAN handle.
+ * @param __HANDLE__ CAN handle.
* @retval None
*/
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
- * @brief Enable the specified CAN interrupts
- * @param __HANDLE__: CAN handle.
- * @param __INTERRUPT__: CAN Interrupt.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
- * @arg CAN_IT_FF0 : FIFO 0 full interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
- * @arg CAN_IT_FF1 : FIFO 1 full interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
- * @arg CAN_IT_WKU : Wake-up interrupt
- * @arg CAN_IT_SLK : Sleep acknowledge interrupt
- * @arg CAN_IT_EWG : Error warning interrupt
- * @arg CAN_IT_EPV : Error passive interrupt
- * @arg CAN_IT_BOF : Bus-off interrupt
- * @arg CAN_IT_LEC : Last error code interrupt
- * @arg CAN_IT_ERR : Error Interrupt
- * @retval None.
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to enable.
+ * This parameter can be any combination of @arg CAN_Interrupts
+ * @retval None
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
- * @brief Disable the specified CAN interrupts
- * @param __HANDLE__: CAN handle.
- * @param __INTERRUPT__: CAN Interrupt.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
- * @arg CAN_IT_FF0 : FIFO 0 full interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
- * @arg CAN_IT_FF1 : FIFO 1 full interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
- * @arg CAN_IT_WKU : Wake-up interrupt
- * @arg CAN_IT_SLK : Sleep acknowledge interrupt
- * @arg CAN_IT_EWG : Error warning interrupt
- * @arg CAN_IT_EPV : Error passive interrupt
- * @arg CAN_IT_BOF : Bus-off interrupt
- * @arg CAN_IT_LEC : Last error code interrupt
- * @arg CAN_IT_ERR : Error Interrupt
- * @retval None.
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to disable.
+ * This parameter can be any combination of @arg CAN_Interrupts
+ * @retval None
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-/**
- * @brief Return the number of pending received messages.
- * @param __HANDLE__: CAN handle.
- * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval The number of pending message.
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be a value of @arg CAN_Interrupts
+ * @retval The state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
/** @brief Check whether the specified CAN flag is set or not.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of @arg CAN_flags
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+ ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Clear the specified CAN pending flag.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
-
-/** @brief Check if the specified CAN interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __INTERRUPT__: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
- * @arg CAN_IT_FF0 : FIFO 0 full interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
- * @arg CAN_IT_FF1 : FIFO 1 full interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
- * @arg CAN_IT_WKU : Wake-up interrupt
- * @arg CAN_IT_SLK : Sleep acknowledge interrupt
- * @arg CAN_IT_EWG : Error warning interrupt
- * @arg CAN_IT_EPV : Error passive interrupt
- * @arg CAN_IT_BOF : Bus-off interrupt
- * @arg CAN_IT_LEC : Last error code interrupt
- * @arg CAN_IT_ERR : Error Interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Check the transmission status of a CAN Frame.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
- * @retval The new status of transmission (TRUE or FALSE).
- */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
-
-/**
- * @brief Release the specified receive FIFO.
- * @param __HANDLE__: CAN handle.
- * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval None.
- */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
-
-/**
- * @brief Cancel a transmit request.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
- * @retval None.
- */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
-
-/**
- * @brief Enable or disables the DBG Freeze for CAN.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __NEWSTATE__: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
+ * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
+ * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
+ * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
+ * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
+ * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
+ * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
+ * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
+ * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
+ * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
+ * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
* @retval None
*/
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/**
- * @}
- */
-
-/* Include CAN HAL Extension module */
-#include "stm32f1xx_hal_can_ex.h"
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
-/** @addtogroup CAN_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- * @{
- */
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
/**
- * @}
- */
+ * @}
+ */
-/** @addtogroup CAN_Exported_Functions_Group2
- * @brief I/O operation functions
- * @{
- */
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ * @{
+ */
+
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief Callback functions
+ * @{
+ */
+/* Callbacks functions ********************************************************/
+
+void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
/**
* @}
*/
-/** @addtogroup CAN_Exported_Functions_Group3
- * @brief CAN Peripheral State functions
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
* @{
*/
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+
/**
* @}
*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_FLAG_MASK (0x000000FFU)
/**
* @}
*/
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
@@ -748,49 +727,73 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
+ ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
+ ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
+ ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
+ ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
+ ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
+ ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
+ ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
+#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
+ ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
+ ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
+ ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-
+#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
+#if defined(CAN2)
+#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
+#endif
+#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
+ ((ACTIVATION) == CAN_FILTER_ENABLE))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
+#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
+#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
+#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-
+#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
+#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
+ CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
+ CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
+ CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
+ CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
+ CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
+ CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
/**
* @}
*/
+/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
+
+#endif /* CAN1 */
/**
* @}
*/
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
-
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F1xx_HAL_CAN_H */
+#endif /* STM32F1xx_HAL_CAN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf_template.h b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf_template.h
index 9942a81976e64b955025193795e437aa17810afb..37005f120cb56c6d3bf357d64406db8aa6894a95 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf_template.h
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf_template.h
@@ -53,6 +53,7 @@ extern "C" {
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
#define HAL_CEC_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
@@ -249,6 +250,10 @@ extern "C" {
#include "stm32f1xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #include "Legacy/stm32f1xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f1xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
index 09cb9604f53db58390b40b418c835853ca02bae1..b5e6f74bdf5ef79df1567d6fa7659b856ccab26b 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
@@ -74,8 +74,8 @@ typedef enum
/* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
index ea8aa92611d7cfb1020a7ec197a8e2c6724baa1e..aa5ac316d78dba6ee9c83f3ebf91c6a84d214fa7 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
@@ -458,8 +458,9 @@ typedef struct
/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input */
/**
* @}
*/
@@ -937,8 +938,9 @@ typedef struct
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING))
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
index f03a74a1aa43386e76b592106711dbdd6bc79dbb..4a2b69078fc4e7da9070e03f5648fddfe337e41b 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
@@ -1602,7 +1602,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
#if defined(RCC_CFGR2_PREDIV1)
return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
#else
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos);
#endif /*RCC_CFGR2_PREDIV1*/
}
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
index a2b7202d60232217a92f6933c0d9f94ca278dc6f..8c84a250eb742bbe3fc332530c0922ced8930dd4 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
@@ -1057,7 +1057,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
{
- SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
@@ -1068,7 +1068,7 @@ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
@@ -1148,6 +1148,9 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
* CR1 CMS LL_TIM_SetCounterMode
* @param TIMx Timer instance
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Release_Notes.html b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Release_Notes.html
index 0c01dc529caa12addde36189f1d3636da1d3f231..91c3deb6028673e4d41e66837a727a50c1ec652c 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Release_Notes.html
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Release_Notes.html
@@ -920,7 +920,26 @@ ul
Update History
- V1.1.2 / 09-March-2018 - General updates to fix known defects and enhancements implementation
- Remove Date and version from header files
- HAL Generic update
- stm32f1xx_hal_def.h file changes:
- Update UNUSED() macro implementation to avoid GCC warning
- The warning is detected when the UNUSED() macro is called from C++ file
- Update __weak and __packed defined values for ARM compiler
- Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
- Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type
- stm32f1xx_hal.c/.h file changes:
- Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms:
- Add the following APIs:
- HAL_GetTickPrio(): Returns a tick priority
- HAL_SetTickFreq(): Sets new tick frequency
- HAL_GetTickFreq(): Returns tick frequency
- Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and
1KHz (default)
- stm32f1xx_hal_conf_template.h file changes:
- Fix wrong defined value of LSI
- HAL GPIO update
- Rework AFIO remap macros to avoid issue with Read-modify-write sequence on AFIO_MAPR register
- HAL I2C update
- Fix wrong check of data size in HAL_I2C_Slave Receive() API
- Add a check on the minimum allowed PCLK1 frequency in HAL_I2C_Init() API
- Fix I2C_SPEED_FAST() and I2C_SPEED_STANDARD() speed calculation macros to not let I2C SCL to go beyond
400KHz in some conditions
- HAL RCC update
- Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to
- Be able to return HAL/LL status
- Add checks for HSI, PLL and PLLI2S ready before modifying RCC CFGR registers
- Clear all interrupt flags
- Initialize systick interrupt period
- Update HAL_RCC_GetSysClockFreq() to avoid risk of rounding error which may leads to a wrong returned value.
- HAL SMARTCARD update
- Update data processing in HAL smartcard transmit/receive processes(Polling/IT) to fix memory corruption issue.
- LL GPIO update
- Fix wrong management of GPIO pin position in LL_GPIO_Init() API when configuring GPIOx_CRH register
- Fix wrong check conditions on GPIO mode in LL_GPIO_Init() API
- LL I2C update
- Rename
+
V1.1.3 / 09-October-2018Main changes - Maintenance release to fix known defects and enhancements implementation
Generic drivers changes - Some global variables on stm32xxx_hal.c updated to be declared as extern
HAL drivers changes- The following changes done on the HAL drivers require an update on the application code based on older HAL versions
- Rework of HAL CAN driver (compatibility break)
- A
+new HAL CAN driver has been redesigned with new APIs, to bypass
+limitations on CAN Tx/Rx FIFO management present with previous HAL CAN
+driver version.
- The
+new HAL CAN driver is the recommended version. It is located as usual
+in Drivers/STM32F1xx_HAL_Driver/Src and
+Drivers/STM32f1xx_HAL_Driver/Inc folders. It can be enabled through
+switch HAL_CAN_MODULE_ENABLED in stm32f1xx_hal_conf.h
- The
+legacy HAL CAN driver is also present in the release in
+Drivers/STM32F1xx_HAL_Driver/Src/Legacy and
+Drivers/STM32F1xx_HAL_Driver/Inc/Legacy folders for software
+compatibility reasons. Its usage is not recommended as
+deprecated. It can however be enabled through switch
+HAL_CAN_LEGACY_MODULE_ENABLED in stm32f1xx_hal_conf.h
- HAL update
- Add definiton of HAL_CAN_LEGACY_MODULE_ENABLED swith in stm32f1xx_hal_conf_template.h
- HAL CAN update
- Fields of CAN_InitTypeDef structure are reworked:
- SJW
+to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to
+TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to
+AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to
+TransmitFifoPriority
- HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's
- HAL_CAN_Transmit()
+is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then
+HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.
- HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_AddTxMessage() for place Tx request.
- HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage()
to get Rx message. - HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then HAL_CAN_GetRxMessage()
in the receivecallback to get Rx message - HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
- HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().
- HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().
- More complete "How to use the new driver" is detailed in the driver header section itself.
V1.1.2 / 09-March-2018 - General updates to fix known defects and enhancements implementation
- Remove Date and version from header files
- HAL Generic update
- stm32f1xx_hal_def.h file changes:
- Update UNUSED() macro implementation to avoid GCC warning
- The warning is detected when the UNUSED() macro is called from C++ file
- Update __weak and __packed defined values for ARM compiler
- Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
- Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type
- stm32f1xx_hal.c/.h file changes:
- Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms:
- Add the following APIs:
- HAL_GetTickPrio(): Returns a tick priority
- HAL_SetTickFreq(): Sets new tick frequency
- HAL_GetTickFreq(): Returns tick frequency
- Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and
1KHz (default)
- stm32f1xx_hal_conf_template.h file changes:
- Fix wrong defined value of LSI
- HAL GPIO update
- Rework AFIO remap macros to avoid issue with Read-modify-write sequence on AFIO_MAPR register
- HAL I2C update
- Fix wrong check of data size in HAL_I2C_Slave Receive() API
- Add a check on the minimum allowed PCLK1 frequency in HAL_I2C_Init() API
- Fix I2C_SPEED_FAST() and I2C_SPEED_STANDARD() speed calculation macros to not let I2C SCL to go beyond
400KHz in some conditions
- HAL RCC update
- Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to
- Be able to return HAL/LL status
- Add checks for HSI, PLL and PLLI2S ready before modifying RCC CFGR registers
- Clear all interrupt flags
- Initialize systick interrupt period
- Update HAL_RCC_GetSysClockFreq() to avoid risk of rounding error which may leads to a wrong returned value.
- HAL SMARTCARD update
- Update data processing in HAL smartcard transmit/receive processes(Polling/IT) to fix memory corruption issue.
- LL GPIO update
- Fix wrong management of GPIO pin position in LL_GPIO_Init() API when configuring GPIOx_CRH register
- Fix wrong check conditions on GPIO mode in LL_GPIO_Init() API
- LL I2C update
- Rename
IS_I2C_CLOCK_SPEED() and IS_I2C_DUTY_CYCLE() respectively to
IS_LL_I2C_CLOCK_SPEED() and IS_LL_I2C_DUTY_CYCLE() to avoid
incompatible macros redefinition.
- LL RCC update
- Add LL_RCC_PLL_SetMainSource() macro to configure PLL main clock source
V1.1.1 / 12-May-2017 - General updates to fix known defects and enhancements implementation
- HAL Generic update
- stm32f1xx_hal_conf_template.h fix typo: update to refer to stm32f1xx_hal_mmc.h instead of stm32f4xx_hal_mmc.h
- LL SYSTEM update
- LL_DBGMCU_APB1_GRP1_I2C1_STOP and LL_DBGMCU_APB1_GRP1_I2C2_STOP literals are retarget to an available literals
- LL_DBGMCU_APB1_GRP1_RTC_STOP literal is not available for all STM32F1 devices
- HAL MMC update
- Add missing () to fix compilation warning detected with SW4STM32 when extra feature is enabled.
- HAL I2C update
- Update
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/Legacy/stm32f1xx_hal_can.c b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/Legacy/stm32f1xx_hal_can.c
new file mode 100644
index 0000000000000000000000000000000000000000..518fb11767b26ea3b105ac812f34eb2b2418f140
--- /dev/null
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/Legacy/stm32f1xx_hal_can.c
@@ -0,0 +1,1700 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_can.c
+ * @author MCD Application Team
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
+ -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
+
+ (#) CAN pins configuration
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (++) Connect and configure the involved CAN pins using the
+ following function HAL_GPIO_Init();
+
+ (#) Initialize and configure the CAN using HAL_CAN_Init() function.
+
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
+
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
+
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the CAN peripheral transmission and wait the end of this operation
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+ according to his end application
+ (+) Start the CAN peripheral reception and wait the end of this operation
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+ according to his end application
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
+
+ *** CAN HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in CAN HAL driver.
+
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+
+ [..]
+ (@) You can refer to the CAN HAL driver header file for more useful macros
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ *
© COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the CAN.
+ (+) De-initialize the CAN.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+ uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
+ uint32_t tickstart = 0U;
+ uint32_t tmp_mcr = 0U;
+
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+ if(hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Initialize the CAN state*/
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledge */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TTCM == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_TTCM);
+ }
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM);
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.ABOM == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_ABOM);
+ }
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM);
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AWUM == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_AWUM);
+ }
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM);
+ }
+ /* Set the no automatic retransmission */
+ if (hcan->Init.NART == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_NART);
+ }
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_NART);
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.RFLM == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_RFLM);
+ }
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM);
+ }
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TXFP == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_TXFP);
+ }
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP);
+ }
+
+ /* Update register MCR */
+ MODIFY_REG(hcan->Instance->MCR,
+ CAN_MCR_TTCM |
+ CAN_MCR_ABOM |
+ CAN_MCR_AWUM |
+ CAN_MCR_NART |
+ CAN_MCR_RFLM |
+ CAN_MCR_TXFP,
+ tmp_mcr);
+
+ /* Set the bit timing register */
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SJW |
+ hcan->Init.BS1 |
+ hcan->Init.BS2 |
+ (hcan->Init.Prescaler - 1U)));
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledged */
+ if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ status = CAN_INITSTATUS_SUCCESS;
+ }
+ }
+
+ if(status == CAN_INITSTATUS_SUCCESS)
+ {
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0U;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
+
+ filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
+
+ /* Initialisation mode for the filter */
+ /* Select the start slave bank */
+ MODIFY_REG(hcan->Instance->FMR ,
+ CAN_FMR_CAN2SB ,
+ CAN_FMR_FINIT |
+ (uint32_t)(sFilterConfig->BankNumber << 8U) );
+
+ /* Filter Deactivation */
+ CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
+ /* 32-bit identifier or First 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /*Id/Mask mode for the filter*/
+ CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
+ }
+ else
+ {
+ /* FIFO 1 assignation for the filter */
+ SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a CAN frame message.
+ (+) Receive a CAN frame message.
+ (+) Enter CAN peripheral in sleep mode.
+ (+) Wake up the CAN peripheral from sleep mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Select one empty transmit mailbox */
+ if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) |
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) |
+ hcan->pTxMsg->IDE |
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
+ /* Request transmission */
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check End of transmission flag */
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ /* Cancel transmission */
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcan);
+
+ /* Select one empty transmit mailbox */
+ if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+ hcan->pTxMsg->IDE |
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos));
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: FIFO Number value
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: Specify the FIFO number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Request Sleep mode */
+ MODIFY_REG(hcan->Instance->MCR,
+ CAN_MCR_INRQ ,
+ CAN_MCR_SLEEP );
+
+ /* Sleep mode status */
+ if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+ * is in the normal mode.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Wake up request */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Sleep mode status */
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+
+ /* Check Overrun flag for FIFO1 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
+ /* Check End of transmission flag */
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+ {
+ /* Check Transmit request completion status */
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
+ if(tmp1 || tmp2 || tmp3)
+ {
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
+ tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
+ tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
+ /* Check Transmit success */
+ if((tmp1) || (tmp2) || (tmp3))
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ else /* Transmit failure */
+ {
+ /* Set CAN error code to TXFAIL error */
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
+ }
+
+ /* Clear transmission status flags (RQCPx and TXOKx) */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
+ }
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
+ /* Check End of reception flag for FIFO0 */
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO0);
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
+ /* Check End of reception flag for FIFO1 */
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO1);
+ }
+
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Error Warning Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to EWG error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Error Passive Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to EPV error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Bus-Off Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to BOF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+ /* No need for clear of Bus-Off Flag as read-only */
+ }
+
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Last error code Flag */
+ if((!tmp1) && tmp2 && tmp3)
+ {
+ tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC);
+ switch(tmp1)
+ {
+ case(CAN_ESR_LEC_0):
+ /* Set CAN error code to STF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+ break;
+ case(CAN_ESR_LEC_1):
+ /* Set CAN error code to FOR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+ break;
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to ACK error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+ break;
+ case(CAN_ESR_LEC_2):
+ /* Set CAN error code to BR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to BD error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ {
+ /* Clear ERRI Flag */
+ hcan->Instance->MSR = CAN_MSR_ERRI;
+ /* Set the CAN state ready to be able to start again the process */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME );
+
+ /* Call Error callback function */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Check the CAN state.
+ (+) Check CAN Errors detected during interrupt process
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CAN state
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+ /* Return CAN state */
+ return hcan->State;
+}
+
+/**
+ * @brief Return the CAN error code
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ return hcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ /* Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Transmission complete callback */
+ HAL_CAN_TxCpltCallback(hcan);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ uint32_t tmp1 = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ tmp1 = hcan->State;
+ if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
+ {
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Receive complete callback */
+ HAL_CAN_RxCpltCallback(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
index 16f923dba277ee9f563bc1d3ad33800170b926c5..15b200f23c9cf8e2bd2e76355d7d0b44201d7f0c 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
@@ -69,11 +69,11 @@
* @{
*/
/**
- * @brief STM32F1xx HAL Driver version number V1.1.2
+ * @brief STM32F1xx HAL Driver version number V1.1.3
*/
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
-#define __STM32F1xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F1xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c
index 518fb11767b26ea3b105ac812f34eb2b2418f140..7fddced41067626983cc9ba11c2bdd19cae0f664 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c
@@ -3,79 +3,134 @@
* @file stm32f1xx_hal_can.c
* @author MCD Application Team
* @brief CAN HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Controller Area Network (CAN) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + Configuration functions
+ * + Control functions
+ * + Interrupts management
+ * + Callbacks functions
* + Peripheral State and Error functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
- -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (++) Connect and configure the involved CAN pins using the
- following function HAL_GPIO_Init();
-
- (#) Initialize and configure the CAN using HAL_CAN_Init() function.
-
- (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-
- (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
-
- (#) Receive a CAN frame using HAL_CAN_Receive() function.
-
- (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the CAN peripheral transmission and wait the end of this operation
- using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
- according to his end application
- (+) Start the CAN peripheral reception and wait the end of this operation
- using HAL_CAN_Receive(), at this stage user can specify the value of timeout
- according to his end application
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
- (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
- (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
- (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_TxCpltCallback
- (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_ErrorCallback
-
- *** CAN HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in CAN HAL driver.
-
- (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
- (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
- (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
- (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
- (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-
- [..]
- (@) You can refer to the CAN HAL driver header file for more useful macros
-
+ [..]
+ (#) Initialize the CAN low level resources by implementing the
+ HAL_CAN_MspInit():
+ (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
+ (++) Configure CAN pins
+ (+++) Enable the clock for the CAN GPIOs
+ (+++) Configure CAN pins as alternate function open-drain
+ (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
+ (+++) Configure the CAN interrupt priority using
+ HAL_NVIC_SetPriority()
+ (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
+
+ (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
+ function resorts to HAL_CAN_MspInit() for low-level initialization.
+
+ (#) Configure the reception filters using the following configuration
+ functions:
+ (++) HAL_CAN_ConfigFilter()
+
+ (#) Start the CAN module using HAL_CAN_Start() function. At this level
+ the node is active on the bus: it receive messages, and can send
+ messages.
+
+ (#) To manage messages transmission, the following Tx control functions
+ can be used:
+ (++) HAL_CAN_AddTxMessage() to request transmission of a new
+ message.
+ (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
+ message.
+ (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
+ mailboxes.
+ (++) HAL_CAN_IsTxMessagePending() to check if a message is pending
+ in a Tx mailbox.
+ (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
+ sent, if time triggered communication mode is enabled.
+
+ (#) When a message is received into the CAN Rx FIFOs, it can be retrieved
+ using the HAL_CAN_GetRxMessage() function. The function
+ HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
+ stored in the Rx Fifo.
+
+ (#) Calling the HAL_CAN_Stop() function stops the CAN module.
+
+ (#) The deinitialization is achieved with HAL_CAN_DeInit() function.
+
+
+ *** Polling mode operation ***
+ ==============================
+ [..]
+ (#) Reception:
+ (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
+ until at least one message is received.
+ (++) Then get the message using HAL_CAN_GetRxMessage().
+
+ (#) Transmission:
+ (++) Monitor the Tx mailboxes availability until at least one Tx
+ mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
+ (++) Then request transmission of a message using
+ HAL_CAN_AddTxMessage().
+
+
+ *** Interrupt mode operation ***
+ ================================
+ [..]
+ (#) Notifications are activated using HAL_CAN_ActivateNotification()
+ function. Then, the process can be controlled through the
+ available user callbacks: HAL_CAN_xxxCallback(), using same APIs
+ HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
+
+ (#) Notifications can be deactivated using
+ HAL_CAN_DeactivateNotification() function.
+
+ (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
+ CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
+ the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
+ HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
+ here.
+ (++) Directly get the Rx message in the callback, using
+ HAL_CAN_GetRxMessage().
+ (++) Or deactivate the notification in the callback without
+ getting the Rx message. The Rx message can then be got later
+ using HAL_CAN_GetRxMessage(). Once the Rx message have been
+ read, the notification can be activated again.
+
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (#) The CAN peripheral can be put in sleep mode (low power), using
+ HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
+ current CAN activity (transmission or reception of a CAN frame) will
+ be completed.
+
+ (#) A notification can be activated to be informed when the sleep mode
+ will be entered.
+
+ (#) It can be checked if the sleep mode is entered using
+ HAL_CAN_IsSleepActive().
+ Note that the CAN state (accessible from the API HAL_CAN_GetState())
+ is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
+ submitted (the sleep mode is not yet entered), and become
+ HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
+
+ (#) The wake-up from sleep mode can be trigged by two ways:
+ (++) Using HAL_CAN_WakeUp(). When returning from this function,
+ the sleep mode is exited (if return status is HAL_OK).
+ (++) When a start of Rx CAN frame is detected by the CAN peripheral,
+ if automatic wake up mode is enabled.
+
@endverbatim
-
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -109,1590 +164,1836 @@
* @{
*/
+#if defined(CAN1)
+
/** @defgroup CAN CAN
* @brief CAN driver modules
* @{
*/
-#ifdef HAL_CAN_MODULE_ENABLED
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
- defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
+#endif
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TIMEOUT_VALUE 10U
+#define CAN_TIMEOUT_VALUE 10U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
+
/** @defgroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Initialize and configure the CAN.
- (+) De-initialize the CAN.
-
+ (+) HAL_CAN_Init : Initialize and configure the CAN.
+ (+) HAL_CAN_DeInit : De-initialize the CAN.
+ (+) HAL_CAN_MspInit : Initialize the CAN MSP.
+ (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP.
+
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
- uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
- uint32_t tickstart = 0U;
- uint32_t tmp_mcr = 0U;
-
+ uint32_t tickstart;
+
/* Check CAN handle */
- if(hcan == NULL)
+ if (hcan == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
assert_param(IS_CAN_MODE(hcan->Init.Mode));
- assert_param(IS_CAN_SJW(hcan->Init.SJW));
- assert_param(IS_CAN_BS1(hcan->Init.BS1));
- assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
+ assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
+ assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-
- if(hcan->State == HAL_CAN_STATE_RESET)
+
+ if (hcan->State == HAL_CAN_STATE_RESET)
{
- /* Allocate lock resource and initialize it */
- hcan->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
+ /* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
-
- /* Initialize the CAN state*/
- hcan->State = HAL_CAN_STATE_BUSY;
-
+
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
- /* Request initialisation */
- SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Check acknowledge */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ /* Check Sleep mode leave acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
- /* Set the time triggered communication mode */
- if (hcan->Init.TTCM == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_TTCM);
- }
- else
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
- CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM);
- }
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- /* Set the automatic bus-off management */
- if (hcan->Init.ABOM == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_ABOM);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM);
- }
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
- /* Set the automatic wake-up mode */
- if (hcan->Init.AWUM == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_AWUM);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM);
- }
- /* Set the no automatic retransmission */
- if (hcan->Init.NART == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_NART);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_NART);
+ return HAL_ERROR;
}
+ }
- /* Set the receive FIFO locked mode */
- if (hcan->Init.RFLM == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_RFLM);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM);
- }
- /* Set the transmit FIFO priority */
- if (hcan->Init.TXFP == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_TXFP);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP);
- }
-
- /* Update register MCR */
- MODIFY_REG(hcan->Instance->MCR,
- CAN_MCR_TTCM |
- CAN_MCR_ABOM |
- CAN_MCR_AWUM |
- CAN_MCR_NART |
- CAN_MCR_RFLM |
- CAN_MCR_TXFP,
- tmp_mcr);
-
- /* Set the bit timing register */
- WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
- hcan->Init.SJW |
- hcan->Init.BS1 |
- hcan->Init.BS2 |
- (hcan->Init.Prescaler - 1U)));
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
- /* Request leave initialisation */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ /* Wait initialisation acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
- /* Check acknowledged */
- if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- status = CAN_INITSTATUS_SUCCESS;
+ return HAL_ERROR;
}
}
-
- if(status == CAN_INITSTATUS_SUCCESS)
+
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TimeTriggeredMode == ENABLE)
{
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
}
else
{
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
}
-}
-
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
- * contains the filter configuration information.
- * @retval None
- */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
- uint32_t filternbrbitpos = 0U;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
- assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
-
- filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
-
- /* Initialisation mode for the filter */
- /* Select the start slave bank */
- MODIFY_REG(hcan->Instance->FMR ,
- CAN_FMR_CAN2SB ,
- CAN_FMR_FINIT |
- (uint32_t)(sFilterConfig->BankNumber << 8U) );
-
- /* Filter Deactivation */
- CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
-
- /* Filter Scale */
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ /* Set the automatic bus-off management */
+ if (hcan->Init.AutoBusOff == ENABLE)
{
- /* 16-bit scale for the filter */
- CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
}
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AutoWakeUp == ENABLE)
{
- /* 32-bit scale for the filter */
- SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
- /* 32-bit identifier or First 32-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
}
- /* Filter Mode */
- if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ /* Set the automatic retransmission */
+ if (hcan->Init.AutoRetransmission == ENABLE)
{
- /*Id/Mask mode for the filter*/
- CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
}
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ else
{
- /*Identifier list mode for the filter*/
- SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
}
- /* Filter FIFO assignment */
- if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.ReceiveFifoLocked == ENABLE)
{
- /* FIFO 0 assignation for the filter */
- CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
}
else
{
- /* FIFO 1 assignation for the filter */
- SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TransmitFifoPriority == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
}
-
- /* Filter activation */
- if (sFilterConfig->FilterActivation == ENABLE)
+ else
{
- SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
}
- /* Leave the initialisation mode for the filter */
- CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
-
+ /* Set the bit timing register */
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SyncJumpWidth |
+ hcan->Init.TimeSeg1 |
+ hcan->Init.TimeSeg2 |
+ (hcan->Init.Prescaler - 1U)));
+
+ /* Initialize the error code */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Deinitializes the CANx peripheral registers to their default reset values.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @brief Deinitializes the CAN peripheral registers to their default
+ * reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
{
/* Check CAN handle */
- if(hcan == NULL)
+ if (hcan == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* DeInit the low level hardware */
+
+ /* Stop the CAN module */
+ (void)HAL_CAN_Stop(hcan);
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
-
+
+ /* Reset the CAN peripheral */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
+
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
/* Change CAN state */
hcan->State = HAL_CAN_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hcan);
-
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_MspInit can be implemented in the user file
- */
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
}
/**
* @brief DeInitializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_MspDeInit can be implemented in the user file
- */
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
}
+
/**
* @}
*/
-/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
- *
-@verbatim
+/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions.
+ *
+@verbatim
==============================================================================
- ##### IO operation functions #####
+ ##### Configuration functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Transmit a CAN frame message.
- (+) Receive a CAN frame message.
- (+) Enter CAN peripheral in sleep mode.
- (+) Wake up the CAN peripheral from sleep mode.
-
+ (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters
+
@endverbatim
* @{
*/
/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param Timeout: Specify Timeout value
- * @retval HAL status
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+ uint32_t filternbrbitpos;
+ CAN_TypeDef *can_ip = hcan->Instance;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- switch(hcan->State)
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
+
+#if defined(CAN2)
+ /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+ /* Select master instance to access the filter banks */
+ can_ip = CAN1;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+#else
+ /* CAN1 is single instance with 14 dedicated filters banks */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+#endif
+
+ /* Initialisation mode for the filter */
+ SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+#if defined(CAN2)
+ /* Select the start filter number of CAN2 slave instance */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+ SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+
+#endif
+ /* Convert filter number into bit position */
+ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
+
+ /* Filter Deactivation */
+ CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
{
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
+ /* 16-bit scale for the filter */
+ CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
}
- /* Select one empty transmit mailbox */
- if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
{
- transmitmailbox = CAN_TXMAILBOX_0;
+ /* 32-bit scale for the filter */
+ SET_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* 32-bit identifier or First 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* 32-bit mask or Second 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
}
- else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
{
- transmitmailbox = CAN_TXMAILBOX_1;
+ /* Id/Mask mode for the filter*/
+ CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
}
- else
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
- transmitmailbox = CAN_TXMAILBOX_2;
+ /* Identifier list mode for the filter*/
+ SET_BIT(can_ip->FM1R, filternbrbitpos);
}
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
{
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) |
- hcan->pTxMsg->RTR);
+ /* FIFO 0 assignation for the filter */
+ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
}
else
{
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) |
- hcan->pTxMsg->IDE |
- hcan->pTxMsg->RTR);
+ /* FIFO 1 assignation for the filter */
+ SET_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
+ {
+ SET_BIT(can_ip->FA1R, filternbrbitpos);
}
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
- /* Request transmission */
- SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+ /* Leave the initialisation mode for the filter */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_Start : Start the CAN module
+ (+) HAL_CAN_Stop : Stop the CAN module
+ (+) HAL_CAN_RequestSleep : Request sleep mode entry.
+ (+) HAL_CAN_WakeUp : Wake up from sleep mode.
+ (+) HAL_CAN_IsSleepActive : Check is sleep mode is active.
+ (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes
+ and activate the corresponding
+ transmission request
+ (+) HAL_CAN_AbortTxRequest : Abort transmission request
+ (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level
+ (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is
+ pending on the selected Tx mailbox
+ (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO
+ (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the CAN module.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart;
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_LISTENING;
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get tick */
tickstart = HAL_GetTick();
- /* Check End of transmission flag */
- while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- /* Cancel transmission */
- __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
}
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
else
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
- /* Return function status */
return HAL_ERROR;
}
}
/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @brief Stop the CAN module and enable access to configuration registers.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart;
- /* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ if (hcan->State == HAL_CAN_STATE_LISTENING)
{
- /* Process Locked */
- __HAL_LOCK(hcan);
-
- /* Select one empty transmit mailbox */
- if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
- {
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if(hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
- hcan->pTxMsg->IDE |
- hcan->pTxMsg->RTR);
- }
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos));
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos));
-
- /* Change CAN state */
- switch(hcan->State)
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
{
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
}
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME );
+ /* Return function status */
+ return HAL_OK;
}
else
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
- /* Return function status */
return HAL_ERROR;
}
-
- return HAL_OK;
}
/**
- * @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: FIFO Number value
- * @param Timeout: Specify Timeout value
- * @retval HAL status
+ * @brief Request the sleep mode (low power) entry.
+ * When returning from this function, Sleep mode will be entered
+ * as soon as the current CAN activity (transmission or reception
+ * of a CAN frame) has been completed.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
*/
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
{
- uint32_t tickstart = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
+ HAL_CAN_StateTypeDef state = hcan->State;
- /* Check if CAN state is not busy for RX FIFO0 */
- if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- return HAL_BUSY;
- }
+ /* Request Sleep mode */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
- /* Check if CAN state is not busy for RX FIFO1 */
- if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
{
- return HAL_BUSY;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ /* Return function status */
+ return HAL_ERROR;
}
+}
- /* Process locked */
- __HAL_LOCK(hcan);
+/**
+ * @brief Wake up from sleep mode.
+ * When returning with HAL_OK status from this function, Sleep mode
+ * is exited.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
+{
+ __IO uint32_t count = 0;
+ uint32_t timeout = 1000000U;
+ HAL_CAN_StateTypeDef state = hcan->State;
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- switch(hcan->State)
+ /* Wake up request */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Wait sleep mode is exited */
+ do
{
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
+ /* Increment counter */
+ count++;
+
+ /* Check if timeout is reached */
+ if (count > timeout)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ return HAL_ERROR;
+ }
}
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
+
+ /* Return function status */
+ return HAL_OK;
}
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check pending message */
- while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Check is sleep mode is active.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Status
+ * - 0 : Sleep mode is not active.
+ * - 1 : Sleep mode is active.
+ */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
+{
+ uint32_t status = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Check Sleep mode */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
+ status = 1U;
}
}
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Add a message to the first free Tx mailbox and activate the
+ * corresponding transmission request.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param pHeader pointer to a CAN_TxHeaderTypeDef structure.
+ * @param aData array containing the payload of the Tx frame.
+ * @param pTxMailbox pointer to a variable where the function will return
+ * the TxMailbox used to store the Tx message.
+ * This parameter can be a value of @arg CAN_Tx_Mailboxes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
+{
+ uint32_t transmitmailbox;
+ HAL_CAN_StateTypeDef state = hcan->State;
+ uint32_t tsr = READ_REG(hcan->Instance->TSR);
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(pHeader->IDE));
+ assert_param(IS_CAN_RTR(pHeader->RTR));
+ assert_param(IS_CAN_DLC(pHeader->DLC));
+ if (pHeader->IDE == CAN_ID_STD)
{
- pRxMsg = hcan->pRxMsg;
+ assert_param(IS_CAN_STDID(pHeader->StdId));
}
- else /* FIFONumber == CAN_FIFO1 */
+ else
{
- pRxMsg = hcan->pRx1Msg;
+ assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
+ assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
- /* Get the Id */
- pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ /* Check that all the Tx mailboxes are not full */
+ if (((tsr & CAN_TSR_TME0) != 0U) ||
+ ((tsr & CAN_TSR_TME1) != 0U) ||
+ ((tsr & CAN_TSR_TME2) != 0U))
+ {
+ /* Select an empty transmit mailbox */
+ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+ /* Check transmit mailbox value */
+ if (transmitmailbox > 2U)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
+
+ /* Store the Tx mailbox */
+ *pTxMailbox = (uint32_t)1 << transmitmailbox;
+
+ /* Set up the Id */
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
+ pHeader->RTR);
+ }
+ else
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
+ pHeader->IDE |
+ pHeader->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
+
+ /* Set up the Transmit Global Time mode */
+ if (pHeader->TransmitGlobalTime == ENABLE)
+ {
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
+ }
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
+ ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
+ ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
+ ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
+ ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
+ ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
+
+ /* Request transmission */
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
}
else
{
- pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
}
-
- pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the data field */
- pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
-
- /* Release the FIFO */
- if(FIFONumber == CAN_FIFO0)
+}
+
+/**
+ * @brief Abort transmission requests
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of the Tx Mailboxes to abort.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- /* Release FIFO0 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ /* Check Tx Mailbox 0 */
+ if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
+ {
+ /* Add cancellation request for Tx Mailbox 0 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
+ }
+
+ /* Check Tx Mailbox 1 */
+ if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
+ {
+ /* Add cancellation request for Tx Mailbox 1 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
+ }
+
+ /* Check Tx Mailbox 2 */
+ if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
+ {
+ /* Add cancellation request for Tx Mailbox 2 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
+ }
+
+ /* Return function status */
+ return HAL_OK;
}
- else /* FIFONumber == CAN_FIFO1 */
+ else
{
- /* Release FIFO1 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
}
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
+}
+
+/**
+ * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Number of free Tx Mailboxes.
+ */
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
+{
+ uint32_t freelevel = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- switch(hcan->State)
+ /* Check Tx Mailbox 0 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
{
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
+ freelevel++;
}
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
+
+ /* Check Tx Mailbox 1 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
{
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
+ freelevel++;
}
- }
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Check Tx Mailbox 2 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
+ {
+ freelevel++;
+ }
+ }
- /* Return function status */
- return HAL_OK;
+ /* Return Tx Mailboxes free level */
+ return freelevel;
}
/**
- * @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
+ * @brief Check if a transmission request is pending on the selected Tx
+ * Mailboxes.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of Tx Mailboxes to check.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval Status
+ * - 0 : No pending transmission request on any selected Tx Mailboxes.
+ * - 1 : Pending transmission request on at least one of the selected
+ * Tx Mailbox.
*/
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Check if CAN state is not busy for RX FIFO0 */
- if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ uint32_t status = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- return HAL_BUSY;
+ /* Check pending transmission request on the selected Tx Mailboxes */
+ if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
+ {
+ status = 1U;
+ }
}
- /* Check if CAN state is not busy for RX FIFO1 */
- if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Return timestamp of Tx message sent, if time triggered communication
+ mode is enabled.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailbox Tx Mailbox where the timestamp of message sent will be
+ * read.
+ * This parameter can be one value of @arg CAN_Tx_Mailboxes.
+ * @retval Timestamp of message sent from Tx Mailbox.
+ */
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
+{
+ uint32_t timestamp = 0U;
+ uint32_t transmitmailbox;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- return HAL_BUSY;
+ /* Select the Tx mailbox */
+ transmitmailbox = POSITION_VAL(TxMailbox);
+
+ /* Get timestamp */
+ timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
}
- /* Process locked */
- __HAL_LOCK(hcan);
+ /* Return the timestamp */
+ return timestamp;
+}
- /* Change CAN state */
- if(FIFONumber == CAN_FIFO0)
+/**
+ * @brief Get an CAN frame from the Rx FIFO zone into the message RAM.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Fifo number of the received message to be read.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
+ * of the Rx frame will be stored.
+ * @param aData array where the payload of the Rx frame will be stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- switch(hcan->State)
+ /* Check the Rx FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
{
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
}
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
+ else /* Rx element is assigned to Rx FIFO 1 */
{
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
+ /* Check that the Rx FIFO 1 is not empty */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
}
- }
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+ /* Get the header */
+ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
+ }
+ else
+ {
+ pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
+ }
+ pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
+ pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
+ pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
+
+ /* Get the data */
+ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
+ aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
+ aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
+ aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
+ aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
+ aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
+ aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
+ aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
+
+ /* Release the FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Release RX FIFO 0 */
+ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
+ }
+ else /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Release RX FIFO 1 */
+ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
+ }
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME );
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- if(FIFONumber == CAN_FIFO0)
- {
- /* Enable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ /* Return function status */
+ return HAL_OK;
}
else
{
- /* Enable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
}
+}
- /* Return function status */
- return HAL_OK;
+/**
+ * @brief Return Rx FIFO fill level.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @retval Number of messages available in Rx FIFO.
+ */
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
+{
+ uint32_t filllevel = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ if (RxFifo == CAN_RX_FIFO0)
+ {
+ filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
+ }
+ else /* RxFifo == CAN_RX_FIFO1 */
+ {
+ filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
+ }
+ }
+
+ /* Return Rx FIFO fill level */
+ return filllevel;
}
/**
- * @brief Enters the Sleep (low power) mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts management #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ActivateNotification : Enable interrupts
+ (+) HAL_CAN_DeactivateNotification : Disable interrupts
+ (+) HAL_CAN_IRQHandler : Handles CAN interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @retval HAL status.
+ * @param ActiveITs indicates which interrupts will be enabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
- uint32_t tickstart = 0U;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Request Sleep mode */
- MODIFY_REG(hcan->Instance->MCR,
- CAN_MCR_INRQ ,
- CAN_MCR_SLEEP );
-
- /* Sleep mode status */
- if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
- HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(ActiveITs));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Enable the selected interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
/* Return function status */
- return HAL_ERROR;
+ return HAL_OK;
}
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
- HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ else
{
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
}
/**
- * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
- * is in the normal mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Disable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @retval HAL status.
+ * @param InactiveITs indicates which interrupts will be disabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
{
- uint32_t tickstart = 0U;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Wake up request */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Sleep mode status */
- while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(InactiveITs));
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
+ /* Disable the selected interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
+
+ /* Return function status */
+ return HAL_OK;
}
- if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
+ else
{
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- /* Return function status */
return HAL_ERROR;
}
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
}
/**
- * @brief Handles CAN interrupt request
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
- uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
uint32_t errorcode = HAL_CAN_ERROR_NONE;
-
- /* Check Overrun flag for FIFO0 */
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
- if((tmp1 != 0U) && tmp2)
+ uint32_t interrupts = READ_REG(hcan->Instance->IER);
+ uint32_t msrflags = READ_REG(hcan->Instance->MSR);
+ uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
+ uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
+ uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
+ uint32_t esrflags = READ_REG(hcan->Instance->ESR);
+
+ /* Transmit Mailbox empty interrupt management *****************************/
+ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
{
- /* Set CAN error code to FOV0 error */
- errorcode |= HAL_CAN_ERROR_FOV0;
+ /* Transmit Mailbox 0 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP0) != 0U)
+ {
+ /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
- /* Clear FIFO0 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
- }
+ if ((tsrflags & CAN_TSR_TXOK0) != 0U)
+ {
+ /* Transmission Mailbox 0 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST0) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST0;
+ }
+ else if ((tsrflags & CAN_TSR_TERR0) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR0;
+ }
+ else
+ {
+ /* Transmission Mailbox 0 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0AbortCallback(hcan);
+ }
+ }
+ }
- /* Check Overrun flag for FIFO1 */
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
- if((tmp1 != 0U) && tmp2)
- {
- /* Set CAN error code to FOV1 error */
- errorcode |= HAL_CAN_ERROR_FOV1;
+ /* Transmit Mailbox 1 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP1) != 0U)
+ {
+ /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
- /* Clear FIFO1 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
- }
+ if ((tsrflags & CAN_TSR_TXOK1) != 0U)
+ {
+ /* Transmission Mailbox 1 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST1) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST1;
+ }
+ else if ((tsrflags & CAN_TSR_TERR1) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR1;
+ }
+ else
+ {
+ /* Transmission Mailbox 1 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1AbortCallback(hcan);
+ }
+ }
+ }
- /* Check End of transmission flag */
- if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
- {
- /* Check Transmit request completion status */
- tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
- tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
- tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
- if(tmp1 || tmp2 || tmp3)
+ /* Transmit Mailbox 2 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP2) != 0U)
{
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
- tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
- tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
- /* Check Transmit success */
- if((tmp1) || (tmp2) || (tmp3))
+ /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
+
+ if ((tsrflags & CAN_TSR_TXOK2) != 0U)
{
- /* Call transmit function */
- CAN_Transmit_IT(hcan);
+ /* Transmission Mailbox 2 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2CompleteCallback(hcan);
}
- else /* Transmit failure */
+ else
{
- /* Set CAN error code to TXFAIL error */
- errorcode |= HAL_CAN_ERROR_TXFAIL;
+ if ((tsrflags & CAN_TSR_ALST2) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST2;
+ }
+ else if ((tsrflags & CAN_TSR_TERR2) != 0U)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR2;
+ }
+ else
+ {
+ /* Transmission Mailbox 2 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2AbortCallback(hcan);
+ }
}
+ }
+ }
+
+ /* Receive FIFO 0 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
+ {
+ if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
+ {
+ /* Set CAN error code to Rx Fifo 0 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV0;
- /* Clear transmission status flags (RQCPx and TXOKx) */
- SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
- CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
}
}
-
- tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
- /* Check End of reception flag for FIFO0 */
- if((tmp1 != 0U) && tmp2)
+
+ /* Receive FIFO 0 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
{
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO0);
+ if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
+ {
+ /* Clear FIFO 0 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
+
+ /* Receive FIFO 0 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0FullCallback(hcan);
+ }
}
-
- tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
- /* Check End of reception flag for FIFO1 */
- if((tmp1 != 0U) && tmp2)
+
+ /* Receive FIFO 0 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
{
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO1);
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
+ {
+ /* Receive FIFO 0 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+ }
}
- /* Set error code in handle */
- hcan->ErrorCode |= errorcode;
+ /* Receive FIFO 1 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
+ {
+ if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
+ {
+ /* Set CAN error code to Rx Fifo 1 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+ }
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Error Warning Flag */
- if(tmp1 && tmp2 && tmp3)
+ /* Receive FIFO 1 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
{
- /* Set CAN error code to EWG error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
- /* No need for clear of Error Warning Flag as read-only */
+ if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
+ {
+ /* Clear FIFO 1 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
+
+ /* Receive FIFO 1 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1FullCallback(hcan);
+ }
}
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Error Passive Flag */
- if(tmp1 && tmp2 && tmp3)
+
+ /* Receive FIFO 1 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
{
- /* Set CAN error code to EPV error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
- /* No need for clear of Error Passive Flag as read-only */
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
+ {
+ /* Receive FIFO 1 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+ }
}
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Bus-Off Flag */
- if(tmp1 && tmp2 && tmp3)
+
+ /* Sleep interrupt management *********************************************/
+ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
{
- /* Set CAN error code to BOF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
- /* No need for clear of Bus-Off Flag as read-only */
+ if ((msrflags & CAN_MSR_SLAKI) != 0U)
+ {
+ /* Clear Sleep interrupt Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
+
+ /* Sleep Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_SleepCallback(hcan);
+ }
}
-
- tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Last error code Flag */
- if((!tmp1) && tmp2 && tmp3)
+
+ /* WakeUp interrupt management *********************************************/
+ if ((interrupts & CAN_IT_WAKEUP) != 0U)
{
- tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC);
- switch(tmp1)
+ if ((msrflags & CAN_MSR_WKUI) != 0U)
{
- case(CAN_ESR_LEC_0):
- /* Set CAN error code to STF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_STF;
- break;
- case(CAN_ESR_LEC_1):
- /* Set CAN error code to FOR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
- break;
- case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
- /* Set CAN error code to ACK error */
- hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
- break;
- case(CAN_ESR_LEC_2):
- /* Set CAN error code to BR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BR;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
- /* Set CAN error code to BD error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BD;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
- /* Set CAN error code to CRC error */
- hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
- break;
- default:
- break;
+ /* Clear WakeUp Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
+
+ /* WakeUp Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_WakeUpFromRxMsgCallback(hcan);
}
+ }
+
+ /* Error interrupts management *********************************************/
+ if ((interrupts & CAN_IT_ERROR) != 0U)
+ {
+ if ((msrflags & CAN_MSR_ERRI) != 0U)
+ {
+ /* Check Error Warning Flag */
+ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
+ ((esrflags & CAN_ESR_EWGF) != 0U))
+ {
+ /* Set CAN error code to Error Warning */
+ errorcode |= HAL_CAN_ERROR_EWG;
+
+ /* No need for clear of Error Warning Flag as read-only */
+ }
- /* Clear Last error code Flag */
- CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ /* Check Error Passive Flag */
+ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
+ ((esrflags & CAN_ESR_EPVF) != 0U))
+ {
+ /* Set CAN error code to Error Passive */
+ errorcode |= HAL_CAN_ERROR_EPV;
+
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-off Flag */
+ if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
+ ((esrflags & CAN_ESR_BOFF) != 0U))
+ {
+ /* Set CAN error code to Bus-Off */
+ errorcode |= HAL_CAN_ERROR_BOF;
+
+ /* No need for clear of Error Bus-Off as read-only */
+ }
+
+ /* Check Last Error Code Flag */
+ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
+ ((esrflags & CAN_ESR_LEC) != 0U))
+ {
+ switch (esrflags & CAN_ESR_LEC)
+ {
+ case (CAN_ESR_LEC_0):
+ /* Set CAN error code to Stuff error */
+ errorcode |= HAL_CAN_ERROR_STF;
+ break;
+ case (CAN_ESR_LEC_1):
+ /* Set CAN error code to Form error */
+ errorcode |= HAL_CAN_ERROR_FOR;
+ break;
+ case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Acknowledgement error */
+ errorcode |= HAL_CAN_ERROR_ACK;
+ break;
+ case (CAN_ESR_LEC_2):
+ /* Set CAN error code to Bit recessive error */
+ errorcode |= HAL_CAN_ERROR_BR;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Bit Dominant error */
+ errorcode |= HAL_CAN_ERROR_BD;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ errorcode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ }
+ }
+
+ /* Clear ERRI Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
}
/* Call the Error call Back in case of Errors */
- if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ if (errorcode != HAL_CAN_ERROR_NONE)
{
- /* Clear ERRI Flag */
- hcan->Instance->MSR = CAN_MSR_ERRI;
- /* Set the CAN state ready to be able to start again the process */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- /* - Disable FIFO 0 message pending Interrupt */
- /* - Disable FIFO 0 Overrun Interrupt */
- /* - Disable FIFO 1 message pending Interrupt */
- /* - Disable FIFO 1 Overrun Interrupt */
- /* - Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_FMP0|
- CAN_IT_FOV0|
- CAN_IT_FMP1|
- CAN_IT_FOV1|
- CAN_IT_TME );
+ /* Update error code in handle */
+ hcan->ErrorCode |= errorcode;
/* Call Error callback function */
+ /* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
- }
+ }
}
/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief CAN Callback functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..]
+ This subsection provides the following callback functions:
+ (+) HAL_CAN_TxMailbox0CompleteCallback
+ (+) HAL_CAN_TxMailbox1CompleteCallback
+ (+) HAL_CAN_TxMailbox2CompleteCallback
+ (+) HAL_CAN_TxMailbox0AbortCallback
+ (+) HAL_CAN_TxMailbox1AbortCallback
+ (+) HAL_CAN_TxMailbox2AbortCallback
+ (+) HAL_CAN_RxFifo0MsgPendingCallback
+ (+) HAL_CAN_RxFifo0FullCallback
+ (+) HAL_CAN_RxFifo1MsgPendingCallback
+ (+) HAL_CAN_RxFifo1FullCallback
+ (+) HAL_CAN_SleepCallback
+ (+) HAL_CAN_WakeUpFromRxMsgCallback
+ (+) HAL_CAN_ErrorCallback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmission Mailbox 0 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_TxCpltCallback can be implemented in the user file
+ the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
+ user file
*/
}
/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Transmission Mailbox 1 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_RxCpltCallback can be implemented in the user file
+ the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
+ user file
*/
}
/**
- * @brief Error CAN callback.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Transmission Mailbox 2 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_ErrorCallback can be implemented in the user file
+ the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
+ user file
*/
}
/**
- * @}
+ * @brief Transmission Mailbox 0 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
*/
+__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Check the CAN state.
- (+) Check CAN Errors detected during interrupt process
-
-@endverbatim
- * @{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 1 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
*/
+__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
+ user file
+ */
+}
/**
- * @brief return the CAN state
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Transmission Mailbox 2 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @retval HAL state
+ * @retval None
*/
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
- /* Return CAN state */
- return hcan->State;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
+ user file
+ */
}
/**
- * @brief Return the CAN error code
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Rx FIFO 0 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @retval CAN Error Code
+ * @retval None
*/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
- return hcan->ErrorCode;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
+ user file
+ */
}
/**
- * @}
+ * @brief Rx FIFO 0 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
*/
+__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0FullCallback could be implemented in the user
+ file
+ */
+}
/**
- * @}
+ * @brief Rx FIFO 1 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
*/
+__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
-/** @addtogroup CAN_Private_Functions
- * @{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
*/
+__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo1FullCallback could be implemented in the user
+ file
+ */
+}
+
/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
+ * @brief Sleep callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
*/
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
- /* Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR);
- }
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_SleepCallback could be implemented in the user file
+ */
+}
- /* Transmission complete callback */
- HAL_CAN_TxCpltCallback(hcan);
-
- return HAL_OK;
+/**
+ * @brief WakeUp from Rx message callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
+ user file
+ */
}
/**
- * @brief Receives a correct CAN frame.
- * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
+ * @brief Error CAN callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval None
*/
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
- uint32_t tmp1 = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
- {
- pRxMsg = hcan->pRxMsg;
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- pRxMsg = hcan->pRx1Msg;
- }
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
- /* Get the Id */
- pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
- }
- else
- {
- pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
- }
-
- pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the FMI */
- pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
- /* Get the data field */
- pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-
- /* Disable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-
- /* Disable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
- }
+/**
+ * @}
+ */
- tmp1 = hcan->State;
- if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
- {
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR);
- }
+/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) HAL_CAN_GetState() : Return the CAN state.
+ (+) HAL_CAN_GetError() : Return the CAN error codes if any.
+ (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CAN state.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
- switch(hcan->State)
+ /* Check sleep mode acknowledge flag */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
+ /* Sleep mode is active */
+ state = HAL_CAN_STATE_SLEEP_ACTIVE;
}
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
+ /* Check sleep mode request flag */
+ else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
{
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
+ /* Sleep mode request is pending */
+ state = HAL_CAN_STATE_SLEEP_PENDING;
}
+ else
+ {
+ /* Neither sleep mode request nor sleep mode acknowledge */
+ }
+ }
+
+ /* Return CAN state */
+ return state;
+}
+
+/**
+ * @brief Return the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ /* Return CAN error code */
+ return hcan->ErrorCode;
+}
+
+/**
+ * @brief Reset the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
+ {
+ /* Reset CAN error code */
+ hcan->ErrorCode = 0U;
}
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- /* Receive complete callback */
- HAL_CAN_RxCpltCallback(hcan);
+ status = HAL_ERROR;
+ }
- /* Return function status */
- return HAL_OK;
+ /* Return the status */
+ return status;
}
/**
* @}
*/
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
#endif /* HAL_CAN_MODULE_ENABLED */
+
/**
* @}
*/
+#endif /* CAN1 */
+
/**
* @}
*/
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
index d7fa7575cb6cf3dae7d83d90214dc4dea9b82966..cc28f15b3d00c0d760e44d9229e318adfb83aedb 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
@@ -216,13 +216,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
-
- /* Clean callbacks */
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
-
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -230,7 +223,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
hdma->State = HAL_DMA_STATE_READY;
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
-
+
return HAL_OK;
}
@@ -274,7 +267,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1;
}
- else
+ else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
@@ -289,10 +282,16 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
- /* Initialize the error code */
+ /* Clean all callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
+ /* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
- /* Initialize the DMA state */
+ /* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
/* Release Lock */
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c
index d3389d8e1f7c0a4d754b714718ebcf2c46d84c84..10dc407b5a6b91630c239f364bfd3f715ebd36b7 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c
@@ -1361,7 +1361,7 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
I2S_Receive_IT(hi2s);
}
- /* I2S Overrun error interrupt occured -------------------------------------*/
+ /* I2S Overrun error interrupt occurred -------------------------------------*/
if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
{
/* Disable RXNE and ERR interrupt */
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
index f3e2232272e3addc8904aeea13bc6ceb2077c07b..b5ac10842e64d6aa9fc9ff2f44b0e547b494125f 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
@@ -3,16 +3,16 @@
* @file stm32f1xx_hal_rcc.c
* @author MCD Application Team
* @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
- *
- @verbatim
+ *
+ @verbatim
==============================================================================
##### RCC specific features #####
==============================================================================
- [..]
+ [..]
After reset the device is running from Internal High Speed oscillator
(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
and all peripherals are off except internal SRAM, Flash and JTAG.
@@ -32,7 +32,7 @@
##### RCC Limitations #####
==============================================================================
- [..]
+ [..]
A delay between an RCC peripheral clock enable and the effective peripheral
enabling should be taken into account in order to manage the peripheral read/write
from/to registers.
@@ -148,7 +148,7 @@ static void RCC_Delay(uint32_t mdelay);
(#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
through the PLL as System clock source. Can be used also as RTC clock source.
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
(#) PLL (clocked by HSI or HSE), featuring different output clocks:
(++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
@@ -158,9 +158,9 @@ static void RCC_Delay(uint32_t mdelay);
and if a HSE clock failure occurs(HSE used directly or through PLL as System
clock source), the System clocks automatically switched to HSI and an interrupt
is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
- (Non-Maskable Interrupt) exception vector.
+ (Non-Maskable Interrupt) exception vector.
- (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
+ (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
[..] System, AHB and APB buses clocks configuration
@@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(RCC_OscInitStruct != NULL);
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
- /*------------------------------- HSE Configuration ------------------------*/
+ /*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
@@ -426,7 +426,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
+
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
@@ -450,10 +450,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
@@ -462,7 +462,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
return HAL_TIMEOUT;
}
}
-
+
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
@@ -470,10 +470,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
@@ -490,16 +490,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
+
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
@@ -516,10 +516,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
@@ -534,7 +534,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
FlagStatus pwrclkchanged = RESET;
-
+
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
@@ -545,12 +545,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
-
+
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
-
+
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
@@ -570,7 +570,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
@@ -584,7 +584,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
@@ -646,19 +646,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
return HAL_TIMEOUT;
}
}
-
+
/* Configure the HSE prediv2 factor --------------------------------*/
__HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
/* Configure the main PLL2 multiplication factors. */
__HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
-
+
/* Enable the main PLL2. */
__HAL_RCC_PLL2_ENABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till PLL2 is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
{
@@ -675,10 +675,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Disable the main PLL2. */
__HAL_RCC_PLL2_DISABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till PLL2 is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
{
@@ -705,13 +705,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-
+
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
@@ -729,7 +729,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
#if defined(RCC_CFGR2_PREDIV1SRC)
assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
-
+
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
@@ -743,10 +743,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
@@ -760,10 +760,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
+
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
@@ -809,7 +809,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
uint32_t tickstart = 0U;
-
+
/* Check the parameters */
assert_param(RCC_ClkInitStruct != NULL);
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
@@ -825,7 +825,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
-
+
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
@@ -838,6 +838,19 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
+ /* Set the highest APBx dividers in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ }
+
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ }
+
+ /* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
@@ -846,7 +859,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
+
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
@@ -878,7 +891,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/* Get Start Tick */
tickstart = HAL_GetTick();
-
+
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
@@ -916,7 +929,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
-
+
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
@@ -939,7 +952,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
-
+
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
@@ -1247,9 +1260,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
-
+
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-
+
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
index db203f8f95a798cdf79672c59d82d1606397bd06..4bb1875ddffbffa7664025e347cad2701073e8fb 100644
--- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
+++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
@@ -198,6 +198,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/**
* @brief Initializes the TIM Time base Unit according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim : TIM Base handle
* @retval HAL status
*/
@@ -474,6 +478,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
* @param htim : TIM Output Compare handle
* @retval HAL status
*/
@@ -979,6 +987,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Initializes the TIM PWM Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim : TIM handle
* @retval HAL status
*/
@@ -1487,6 +1499,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
* @param htim : TIM Input Capture handle
* @retval HAL status
*/
@@ -1957,6 +1973,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
* @param htim : TIM OnePulse handle
* @param OnePulseMode : Select the One pulse mode.
* This parameter can be one of the following values:
@@ -2243,6 +2263,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
*/
/**
* @brief Initializes the TIM Encoder Interface and create the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
* @param htim : TIM Encoder Interface handle
* @param sConfig : TIM Encoder Interface configuration structure
* @retval HAL status
@@ -5028,6 +5052,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
@@ -5082,6 +5107,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5116,6 +5142,7 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
@@ -5163,6 +5190,7 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5229,8 +5257,8 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
/* Select the Polarity and set the CC3E Bit */
- tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+ tmpccer &= ~(TIM_CCER_CC3P);
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
|