add eth driver

bsp/gd32450z-eval/applications/rtgui_demo.c

@@ -12,15 +12,7 @@
  */
 
 #include <rtthread.h>
-#include <rtgui/rtgui.h>
-#include <rtgui/rtgui_system.h>
-#include <rtgui/rtgui_app.h>
-
-#include <rtgui/widgets/window.h>
-#include <rtgui/dc.h>
-#include <rtgui/dc_hw.h>
-
-#include "finsh.h"
+#include <finsh.h>
 #include "rtgui_demo.h"
 
 #define DEBUG
@@ -33,6 +25,14 @@
 
 #ifdef RT_USING_GUIENGINE
 
+#include <rtgui/rtgui.h>
+#include <rtgui/rtgui_system.h>
+#include <rtgui/rtgui_app.h>
+
+#include <rtgui/widgets/window.h>
+#include <rtgui/dc.h>
+#include <rtgui/dc_hw.h>
+
 struct rtgui_win *main_win;
 rt_bool_t dc_event_handler(struct rtgui_object *object, rtgui_event_t *event);
 

bsp/gd32450z-eval/drivers/SConscript

@@ -11,6 +11,7 @@ drv_exmc_sdram.c
 drv_usart.c
 gd32f450z_lcd_eval.c
 drv_lcd.c
+drv_enet.c
 """)
 
 CPPPATH = [cwd]

bsp/gd32450z-eval/drivers/drv_enet.c

+/*
+ * File      : eth_driver.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-11-30     aozima       the first version.
+ * 2011-12-10     aozima       support dual ethernet.
+ * 2011-12-21     aozima       cleanup code.
+ * 2012-07-13     aozima       mask all GMAC MMC Interrupt.
+ * 2012-07-20     aozima       fixed mask all GMAC MMC Interrupt,and read clear.
+ * 2012-07-20     aozima       use memcpy replace byte copy.
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "lwipopts.h"
+#include <netif/ethernetif.h>
+#include <netif/etharp.h>
+#include <lwip/icmp.h>
+
+#include "gd32f4xx.h"
+#include "synopsys_emac.h"
+
+#define ETHERNET_MAC0    ((struct rt_synopsys_eth *)(0x40020000U + 0x00008000U))
+
+
+//#define EMAC_DEBUG
+//#define EMAC_RX_DUMP
+//#define EMAC_TX_DUMP
+
+#ifdef EMAC_DEBUG
+#define EMAC_TRACE	        rt_kprintf
+#else
+#define EMAC_TRACE(...)
+#endif
+
+#define EMAC_RXBUFNB        	4
+#define EMAC_TXBUFNB        	2
+
+#define EMAC_PHY_AUTO		    0
+#define EMAC_PHY_10MBIT		    1
+#define EMAC_PHY_100MBIT        2
+
+#define MAX_ADDR_LEN 6
+struct gd32_emac
+{
+    /* inherit from Ethernet device */
+    struct eth_device parent;
+
+    rt_uint8_t phy_mode;
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+
+    struct rt_synopsys_eth * ETHERNET_MAC;
+    IRQn_Type ETHER_MAC_IRQ;
+
+    ALIGN(RT_ALIGN_SIZE)
+    PRAGMA(data_alignment=RT_ALIGN_SIZE)
+    EMAC_DMADESCTypeDef  DMARxDscrTab[EMAC_RXBUFNB], DMATxDscrTab[EMAC_TXBUFNB];
+    ALIGN(RT_ALIGN_SIZE)
+    rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE];
+    ALIGN(RT_ALIGN_SIZE)
+    rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE];
+
+    EMAC_DMADESCTypeDef  *DMATxDescToSet;
+    EMAC_DMADESCTypeDef  *DMARxDescToGet;
+    
+    struct rt_semaphore tx_buf_free;
+};
+
+static struct gd32_emac gd32_emac_device0;
+
+/**
+  * Initializes the DMA Tx descriptors in chain mode.
+  */
+static void EMAC_DMA_tx_desc_init(EMAC_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+    uint32_t i = 0;
+    EMAC_DMADESCTypeDef *DMATxDesc;
+
+    /* Fill each DMATxDesc descriptor with the right values */
+    for(i=0; i < TxBuffCount; i++)
+    {
+        /* Get the pointer on the ith member of the Tx Desc list */
+        DMATxDesc = DMATxDescTab + i;
+        /* Set Second Address Chained bit */
+        DMATxDesc->Status = EMAC_DMATxDesc_TCH;
+
+        /* Set Buffer1 address pointer */
+        DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*EMAC_MAX_PACKET_SIZE]);
+
+        /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+        if(i < (TxBuffCount-1))
+        {
+            /* Set next descriptor address register with next descriptor base address */
+            DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+        }
+        else
+        {
+            /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+            DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
+        }
+    }
+}
+
+/**
+  * Initializes the DMA Rx descriptors in chain mode.
+  */
+static void EMAC_DMA_rx_desc_init(EMAC_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+    uint32_t i = 0;
+    EMAC_DMADESCTypeDef *DMARxDesc;
+
+    /* Fill each DMARxDesc descriptor with the right values */
+    for(i=0; i < RxBuffCount; i++)
+    {
+        /* Get the pointer on the ith member of the Rx Desc list */
+        DMARxDesc = DMARxDescTab+i;
+        /* Set Own bit of the Rx descriptor Status */
+        DMARxDesc->Status = EMAC_DMARxDesc_OWN;
+
+        /* Set Buffer1 size and Second Address Chained bit */
+        DMARxDesc->ControlBufferSize = EMAC_DMARxDesc_RCH | (uint32_t)EMAC_MAX_PACKET_SIZE;
+        /* Set Buffer1 address pointer */
+        DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*EMAC_MAX_PACKET_SIZE]);
+
+        /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+        if(i < (RxBuffCount-1))
+        {
+            /* Set next descriptor address register with next descriptor base address */
+            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
+        }
+        else
+        {
+            /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+        }
+    }
+}
+
+static rt_err_t gd32_emac_init(rt_device_t dev)
+{
+    struct gd32_emac * gd32_emac_device;
+    struct rt_synopsys_eth * ETHERNET_MAC;
+
+    gd32_emac_device = (struct gd32_emac *)dev;
+    ETHERNET_MAC = gd32_emac_device->ETHERNET_MAC;
+
+    /* Software reset */
+    ETHERNET_MAC->BMR |= (1<<0); /* [bit0]SWR (Software Reset) */
+
+    /* Wait for software reset */
+    while(ETHERNET_MAC->BMR & (1<<0));
+
+    /* Configure ETHERNET */
+    EMAC_init(ETHERNET_MAC, SystemCoreClock);
+
+    /* mask all GMAC MMC Interrupt.*/
+    ETHERNET_MAC->mmc_cntl = (1<<3) | (1<<0); /* MMC Counter Freeze and reset. */
+    ETHERNET_MAC->mmc_intr_mask_rx = 0xFFFFFFFF;
+    ETHERNET_MAC->mmc_intr_mask_tx = 0xFFFFFFFF;
+    ETHERNET_MAC->mmc_ipc_intr_mask_rx = 0xFFFFFFFF;
+
+    /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */
+    EMAC_INT_config(ETHERNET_MAC, EMAC_DMA_INT_NIS | EMAC_DMA_INT_R | EMAC_DMA_INT_T , ENABLE);
+
+    /* Initialize Tx Descriptors list: Chain Mode */
+    EMAC_DMA_tx_desc_init(gd32_emac_device->DMATxDscrTab, &gd32_emac_device->Tx_Buff[0][0], EMAC_TXBUFNB);
+    gd32_emac_device->DMATxDescToSet = gd32_emac_device->DMATxDscrTab;
+    /* Set Transmit Descriptor List Address Register */
+    ETHERNET_MAC->TDLAR = (uint32_t) gd32_emac_device->DMATxDescToSet;
+
+    /* Initialize Rx Descriptors list: Chain Mode  */
+    EMAC_DMA_rx_desc_init(gd32_emac_device->DMARxDscrTab, &gd32_emac_device->Rx_Buff[0][0], EMAC_RXBUFNB);
+    gd32_emac_device->DMARxDescToGet = gd32_emac_device->DMARxDscrTab;
+    /* Set Receive Descriptor List Address Register */
+    ETHERNET_MAC->RDLAR = (uint32_t) gd32_emac_device->DMARxDescToGet;
+
+    /* MAC address configuration */
+    EMAC_MAC_Addr_config(ETHERNET_MAC, EMAC_MAC_Address0, (uint8_t*)&gd32_emac_device->dev_addr[0]);
+
+    NVIC_EnableIRQ( gd32_emac_device->ETHER_MAC_IRQ );
+
+    /* Enable MAC and DMA transmission and reception */
+    EMAC_start(ETHERNET_MAC);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_emac_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t gd32_emac_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t gd32_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t gd32_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_err_t gd32_emac_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    struct gd32_emac * gd32_emac_device = (struct gd32_emac *)dev;
+
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) memcpy(args, &gd32_emac_device->dev_addr[0], MAX_ADDR_LEN);
+        else return -RT_ERROR;
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static void EMAC_IRQHandler(struct gd32_emac * gd32_emac_device)
+{
+    rt_uint32_t status, ier;
+    struct rt_synopsys_eth * ETHERNET_MAC;
+
+    ETHERNET_MAC = gd32_emac_device->ETHERNET_MAC;
+
+    /* get DMA IT status */
+    status = ETHERNET_MAC->SR;
+    ier = ETHERNET_MAC->IER;
+
+    /* GMAC MMC Interrupt. */
+    if(status & EMAC_DMA_INT_GMI)
+    {
+        volatile rt_uint32_t dummy;
+        volatile rt_uint32_t * reg;
+
+        EMAC_TRACE("EMAC_DMA_INT_GMI\r\n");
+
+        /* read clear all MMC interrupt. */
+        reg = &ETHERNET_MAC->mmc_cntl;
+        while((uint32_t)reg < (uint32_t)&ETHERNET_MAC->rxicmp_err_octets)
+        {
+            dummy = *reg++;
+        }
+    }
+
+    /* Normal interrupt summary. */
+    if(status & EMAC_DMA_INT_NIS)
+    {
+        rt_uint32_t nis_clear = EMAC_DMA_INT_NIS;
+
+        /* [0]:Transmit Interrupt. */
+        if((status & ier) & EMAC_DMA_INT_T) /* packet transmission */
+        {
+            rt_sem_release(&gd32_emac_device->tx_buf_free);
+
+            nis_clear |= EMAC_DMA_INT_T;
+        }
+
+        /* [2]:Transmit Buffer Unavailable. */
+
+        /* [6]:Receive Interrupt. */
+        if((status & ier) & EMAC_DMA_INT_R) /* packet reception */
+        {
+            /* a frame has been received */
+            eth_device_ready(&(gd32_emac_device->parent));
+
+            nis_clear |= EMAC_DMA_INT_R;
+        }
+
+        /* [14]:Early Receive Interrupt. */
+
+        EMAC_clear_pending(ETHERNET_MAC, nis_clear);
+    }
+
+    /* Abnormal interrupt summary. */
+    if( status & EMAC_DMA_INT_AIS)
+    {
+        rt_uint32_t ais_clear = EMAC_DMA_INT_AIS;
+
+        /* [1]:Transmit Process Stopped. */
+        /* [3]:Transmit Jabber Timeout. */
+        /* [4]: Receive FIFO Overflow. */
+        /* [5]: Transmit Underflow. */
+        /* [7]: Receive Buffer Unavailable. */
+        /* [8]: Receive Process Stopped. */
+        /* [9]: Receive Watchdog Timeout. */
+        /* [10]: Early Transmit Interrupt. */
+        /* [13]: Fatal Bus Error. */
+
+        EMAC_clear_pending(ETHERNET_MAC, ais_clear);
+    }
+}
+
+void ENET_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    EMAC_IRQHandler(&gd32_emac_device0);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+/* EtherNet Device Interface */
+rt_err_t gd32_emac_tx( rt_device_t dev, struct pbuf* p)
+{
+    struct pbuf* q;
+    char * to;
+    struct gd32_emac * gd32_emac_device;
+    struct rt_synopsys_eth * ETHERNET_MAC;
+
+    gd32_emac_device = (struct gd32_emac *)dev;
+    ETHERNET_MAC = gd32_emac_device->ETHERNET_MAC;
+
+    /* get free tx buffer */
+    {
+        rt_err_t result;
+        result = rt_sem_take(&gd32_emac_device->tx_buf_free, RT_TICK_PER_SECOND/10);
+        if (result != RT_EOK) return -RT_ERROR;
+    }
+
+    to = (char *)gd32_emac_device->DMATxDescToSet->Buffer1Addr;
+
+    for (q = p; q != NULL; q = q->next)
+    {
+        /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
+        memcpy(to, q->payload, q->len);
+        to += q->len;
+    }
+
+#ifdef EMAC_TX_DUMP
+    {
+        rt_uint32_t i;
+        rt_uint8_t *ptr = (rt_uint8_t*)(gd32_emac_device->DMATxDescToSet->Buffer1Addr);
+
+        EMAC_TRACE("\r\n%c%c tx_dump:", gd32_emac_device->parent.netif->name[0], gd32_emac_device->parent.netif->name[1]);
+        for(i=0; i<p->tot_len; i++)
+        {
+            if( (i%8) == 0 )
+            {
+                EMAC_TRACE("  ");
+            }
+            if( (i%16) == 0 )
+            {
+                EMAC_TRACE("\r\n");
+            }
+            EMAC_TRACE("%02x ",*ptr);
+            ptr++;
+        }
+        EMAC_TRACE("\r\ndump done!\r\n");
+    }
+#endif
+
+    /* Setting the Frame Length: bits[12:0] */
+    gd32_emac_device->DMATxDescToSet->ControlBufferSize = (p->tot_len & EMAC_DMATxDesc_TBS1);
+    /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
+    gd32_emac_device->DMATxDescToSet->Status |= EMAC_DMATxDesc_LS | EMAC_DMATxDesc_FS;
+    /* Enable TX Completion Interrupt */
+    gd32_emac_device->DMATxDescToSet->Status |= EMAC_DMATxDesc_IC;
+#ifdef CHECKSUM_BY_HARDWARE
+    gd32_emac_device->DMATxDescToSet->Status |= EMAC_DMATxDesc_ChecksumTCPUDPICMPFull;
+    /* clean ICMP checksum */
+    {
+        struct eth_hdr *ethhdr = (struct eth_hdr *)(gd32_emac_device->DMATxDescToSet->Buffer1Addr);
+        /* is IP ? */
+        if( ethhdr->type == htons(ETHTYPE_IP) )
+        {
+            struct ip_hdr *iphdr = (struct ip_hdr *)(gd32_emac_device->DMATxDescToSet->Buffer1Addr + SIZEOF_ETH_HDR);
+            /* is ICMP ? */
+            if( IPH_PROTO(iphdr) == IP_PROTO_ICMP )
+            {
+                struct icmp_echo_hdr *iecho = (struct icmp_echo_hdr *)(gd32_emac_device->DMATxDescToSet->Buffer1Addr + SIZEOF_ETH_HDR + sizeof(struct ip_hdr) );
+                iecho->chksum = 0;
+            }
+        }
+    }
+#endif
+    /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+    gd32_emac_device->DMATxDescToSet->Status |= EMAC_DMATxDesc_OWN;
+    /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+    if ((ETHERNET_MAC->SR & EMAC_DMASR_TBUS) != (uint32_t)RESET)
+    {
+        /* Clear TBUS ETHERNET DMA flag */
+        ETHERNET_MAC->SR = EMAC_DMASR_TBUS;
+        /* Transmit Poll Demand to resume DMA transmission*/
+        ETHERNET_MAC->TPDR = 0;
+    }
+
+    /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */
+    /* Chained Mode */
+    /* Selects the next DMA Tx descriptor list for next buffer to send */
+    gd32_emac_device->DMATxDescToSet = (EMAC_DMADESCTypeDef*) (gd32_emac_device->DMATxDescToSet->Buffer2NextDescAddr);
+
+    /* Return SUCCESS */
+    return RT_EOK;
+}
+
+/* reception a Ethernet packet. */
+struct pbuf * gd32_emac_rx(rt_device_t dev)
+{
+    struct pbuf* p;
+    rt_uint32_t framelength = 0;
+    struct gd32_emac * gd32_emac_device;
+    struct rt_synopsys_eth * ETHERNET_MAC;
+
+    gd32_emac_device = (struct gd32_emac *)dev;
+    ETHERNET_MAC = gd32_emac_device->ETHERNET_MAC;
+
+    /* init p pointer */
+    p = RT_NULL;
+
+    /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+    if(((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_OWN) != (uint32_t)RESET))
+    {
+        return p;
+    }
+
+    if (((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_ES) == (uint32_t)RESET) &&
+            ((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_LS) != (uint32_t)RESET) &&
+            ((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_FS) != (uint32_t)RESET))
+    {
+        /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+        framelength = ((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_FL)
+                       >> EMAC_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+
+        /* allocate buffer */
+        p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM);
+        if (p != RT_NULL)
+        {
+            const char * from;
+            struct pbuf* q;
+
+            from = (const char *)gd32_emac_device->DMARxDescToGet->Buffer1Addr;
+
+            for (q = p; q != RT_NULL; q= q->next)
+            {
+                /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+                memcpy(q->payload, from, q->len);
+                from += q->len;
+            }
+#ifdef EMAC_RX_DUMP
+            {
+                rt_uint32_t i;
+                rt_uint8_t *ptr = (rt_uint8_t*)(gd32_emac_device->DMARxDescToGet->Buffer1Addr);
+
+                EMAC_TRACE("\r\n%c%c rx_dump:", gd32_emac_device->parent.netif->name[0], gd32_emac_device->parent.netif->name[1]);
+                for(i=0; i<p->tot_len; i++)
+                {
+                    if( (i%8) == 0 )
+                    {
+                        EMAC_TRACE("  ");
+                    }
+                    if( (i%16) == 0 )
+                    {
+                        EMAC_TRACE("\r\n");
+                    }
+                    EMAC_TRACE("%02x ",*ptr);
+                    ptr++;
+                }
+                EMAC_TRACE("\r\ndump done!\r\n");
+            }
+#endif
+        }
+    }
+
+    /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+    gd32_emac_device->DMARxDescToGet->Status = EMAC_DMARxDesc_OWN;
+
+    /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+    if ((ETHERNET_MAC->SR & EMAC_DMASR_RBUS) != (uint32_t)RESET)
+    {
+        /* Clear RBUS ETHERNET DMA flag */
+        ETHERNET_MAC->SR = EMAC_DMASR_RBUS;
+        /* Resume DMA reception */
+        ETHERNET_MAC->RPDR = 0;
+    }
+
+    /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+    /* Chained Mode */
+    if((gd32_emac_device->DMARxDescToGet->ControlBufferSize & EMAC_DMARxDesc_RCH) != (uint32_t)RESET)
+    {
+        /* Selects the next DMA Rx descriptor list for next buffer to read */
+        gd32_emac_device->DMARxDescToGet = (EMAC_DMADESCTypeDef*) (gd32_emac_device->DMARxDescToGet->Buffer2NextDescAddr);
+    }
+    else /* Ring Mode */
+    {
+        if((gd32_emac_device->DMARxDescToGet->ControlBufferSize & EMAC_DMARxDesc_RER) != (uint32_t)RESET)
+        {
+            /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+            gd32_emac_device->DMARxDescToGet = (EMAC_DMADESCTypeDef*) (ETHERNET_MAC->RDLAR);
+        }
+        else
+        {
+            /* Selects the next DMA Rx descriptor list for next buffer to read */
+            gd32_emac_device->DMARxDescToGet = (EMAC_DMADESCTypeDef*) ((uint32_t)gd32_emac_device->DMARxDescToGet + 0x10 + ((ETHERNET_MAC->BMR & EMAC_DMABMR_DSL) >> 2));
+        }
+    }
+
+    return p;
+}
+
+/*
+GPIO               RMII0               RMII1                MII
+PC0/E_RXER0_RXDV1                      ch. 1 CRS_DV         ch. 0 RX_ER
+PC1/E_RX03_RX11                        ch. 1 RXD [1]        ch. 0 RXD [3]
+PC2/E_RX02_RX10                        ch. 1 RXD [0]        ch. 0 RXD [2]
+PC3/E_RX01         ch. 0 RXD [1]                            ch. 0 RXD [1]
+PC4/E_RX00         ch. 0 RXD [0]                            ch. 0 RXD [0]
+PC5/E_RXDV0        ch. 0 CRS_DV                             ch. 0 RX_DV
+PC6/E_MDIO0        ch. 0 MDIO                               ch. 0 MDIO
+PC7/E_MDC0         ch. 0 MDC                                ch. 0 MDC
+PC8/E_RXCK0_REFCK  ch. 0 REF_CLK       ch. 1 REF_CLK        ch. 0 RX_CLK
+
+PC9/E_COL0                                                  ch. 0 COL
+PCA/E_CRS0                                                  ch. 0 CRS
+PCB/E_COUT         REF_CLK output(??).
+
+PCC/E_MDIO1                            ch. 1 MDIO
+PCD/E_TCK0_MDC1                        ch. 1 MDC            ch. 0 TX_CLK
+PCE/E_TXER0_TXEN1                      ch. 1 TX_EN          ch. 0 TX_ER
+PCF/E_TX03_TX11                        ch. 1 TXD [1]        ch. 0 TXD [3]
+PD0/E_TX02_TX10                        ch. 1 TXD [0]        ch. 0 TXD [2]
+PD1/E_TX01         ch. 0 TXD [1]                            ch. 0 TXD [1]
+PD2/E_TX00         ch. 0 TXD [0]                            ch. 0 TXD [0]
+PD3/E_TXEN0        ch. 0 TX_EN                              ch. 0 TX_EN
+*/
+
+
+/*!
+    \brief      configures the nested vectored interrupt controller
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void nvic_configuration(void)
+{
+    nvic_vector_table_set(NVIC_VECTTAB_FLASH, 0x0);
+    nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
+    nvic_irq_enable(ENET_IRQn, 0, 0);
+}
+
+/*!
+    \brief      configures the different GPIO ports
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void enet_gpio_config(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_GPIOC);
+    rcu_periph_clock_enable(RCU_GPIOD);
+    rcu_periph_clock_enable(RCU_GPIOG);
+    rcu_periph_clock_enable(RCU_GPIOH);
+    rcu_periph_clock_enable(RCU_GPIOI);
+  
+    gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8);
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8);
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8);
+  
+    /* enable SYSCFG clock */
+    rcu_periph_clock_enable(RCU_SYSCFG);
+  
+    /* choose DIV2 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */
+    rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4);
+    syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII);
+
+    /* PA1: ETH_RMII_REF_CLK */
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1);
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1);
+    
+    /* PA2: ETH_MDIO */
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2);
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2);
+    
+    /* PA7: ETH_RMII_CRS_DV */
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7);
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7);   
+    
+    gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1);
+    gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2);
+    gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7);
+    
+    /* PB11: ETH_RMII_TX_EN */
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11);
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11);
+    
+    /* PB12: ETH_RMII_TXD0 */
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12);
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_12);
+    
+    /* PB13: ETH_RMII_TXD1 */
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13);
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13);   
+    
+    gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11);
+    gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12);
+    gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13);
+
+    /* PC1: ETH_MDC */
+    gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1);
+    gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1);
+
+    /* PC4: ETH_RMII_RXD0 */
+    gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4);
+    gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4);
+    
+    /* PC5: ETH_RMII_RXD1 */
+    gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5);
+    gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); 
+    
+    gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1);
+    gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4);
+    gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5);
+}
+
+
+int rt_hw_gd32_eth_init(void)
+{
+    rt_kprintf("rt_gd32_eth_init...\n");
+    
+    /* enable ethernet clock  */
+    rcu_periph_clock_enable(RCU_ENET);
+    rcu_periph_clock_enable(RCU_ENETTX);
+    rcu_periph_clock_enable(RCU_ENETRX);
+    
+    nvic_configuration();
+  
+    /* configure the GPIO ports for ethernet pins */
+    enet_gpio_config();
+    
+    
+    /* set autonegotiation mode */
+    gd32_emac_device0.phy_mode = EMAC_PHY_AUTO;
+    gd32_emac_device0.ETHERNET_MAC = ETHERNET_MAC0;
+    gd32_emac_device0.ETHER_MAC_IRQ  = ENET_IRQn;
+
+    // OUI 00-00-0E FUJITSU LIMITED
+    gd32_emac_device0.dev_addr[0] = 0x00;
+    gd32_emac_device0.dev_addr[1] = 0x00;
+    gd32_emac_device0.dev_addr[2] = 0x0E;
+    /* set mac address: (only for test) */
+    gd32_emac_device0.dev_addr[3] = 0x12;
+    gd32_emac_device0.dev_addr[4] = 0x34;
+    gd32_emac_device0.dev_addr[5] = 0x56;
+
+    gd32_emac_device0.parent.parent.init		 = gd32_emac_init;
+    gd32_emac_device0.parent.parent.open		 = gd32_emac_open;
+    gd32_emac_device0.parent.parent.close	 = gd32_emac_close;
+    gd32_emac_device0.parent.parent.read		 = gd32_emac_read;
+    gd32_emac_device0.parent.parent.write	 = gd32_emac_write;
+    gd32_emac_device0.parent.parent.control	 = gd32_emac_control;
+    gd32_emac_device0.parent.parent.user_data = RT_NULL;
+
+    gd32_emac_device0.parent.eth_rx			 = gd32_emac_rx;
+    gd32_emac_device0.parent.eth_tx			 = gd32_emac_tx;
+
+    /* init tx buffer free semaphore */
+    rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO);
+    eth_device_init(&(gd32_emac_device0.parent), "e0");
+    
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gd32_eth_init);

bsp/gd32450z-eval/drivers/drv_lcd.c

@@ -9,7 +9,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2009-01-05     Tanek        the first version
+ * 2017-08-23     Tanek        the first version
  */
 
 #include "gd32f450z_lcd_eval.h"

bsp/gd32450z-eval/drivers/fm3_emac.h

+#ifndef FM3_EMAC_H_INCLUDED
+#define FM3_EMAC_H_INCLUDED
+
+#include <stdint.h>
+//#include <mb9bf618s.h>
+#include <eth_driver.h>
+#include "gd32f4xx_enet.h"
+
+/******************************************************************************/
+/*                Ethernet MAC Registers bits definitions                     */
+/******************************************************************************/
+		/* Bit definition for Ethernet MAC Control Register register */
+#define EMAC_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
+#define EMAC_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
+#define EMAC_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
+#define EMAC_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+#define EMAC_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+#define EMAC_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+#define EMAC_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+#define EMAC_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */
+#define EMAC_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+#define EMAC_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+#define EMAC_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */
+#define EMAC_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
+#define EMAC_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
+#define EMAC_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
+#define EMAC_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
+#define EMAC_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
+#define EMAC_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
+#define EMAC_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
+#define EMAC_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
+#define EMAC_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+														a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define EMAC_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
+#define EMAC_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
+#define EMAC_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
+#define EMAC_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */
+#define EMAC_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
+#define EMAC_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
+#define EMAC_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+
+        /* Bit definition for Ethernet MAC Frame Filter Register */
+#define EMAC_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */
+#define EMAC_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */
+#define EMAC_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */
+#define EMAC_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */
+#define EMAC_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
+#define EMAC_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+#define EMAC_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
+#define EMAC_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */
+#define EMAC_MACFFR_PAM 	  ((uint32_t)0x00000010)  /* Pass all mutlicast */
+#define EMAC_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */
+#define EMAC_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */
+#define EMAC_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
+#define EMAC_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+
+        /* Bit definition for Ethernet MAC Hash Table High Register */
+#define EMAC_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+
+        /* Bit definition for Ethernet MAC Hash Table Low Register */
+#define EMAC_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+
+        /* Bit definition for Ethernet MAC MII Address Register */
+#define EMAC_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */
+#define EMAC_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */
+#define EMAC_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */
+#define EMAC_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define EMAC_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define EMAC_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define EMAC_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define EMAC_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-250 MHz; MDC clock= HCLK/102 */
+#define EMAC_MACMIIAR_CR_Div122  ((uint32_t)0x00000014)  /* HCLK:250-300 MHz; MDC clock= HCLK/122*/
+#define EMAC_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */
+#define EMAC_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */
+
+        /* Bit definition for Ethernet MAC MII Data Register */
+#define EMAC_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+        /* Bit definition for Ethernet MAC Flow Control Register */
+#define EMAC_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
+#define EMAC_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define EMAC_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+#define EMAC_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+#define EMAC_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+#define EMAC_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+#define EMAC_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */
+#define EMAC_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
+#define EMAC_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
+#define EMAC_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
+#define EMAC_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+
+        /* Bit definition for Ethernet MAC VLAN Tag Register */
+#define EMAC_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
+#define EMAC_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+        /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define EMAC_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+        /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+           Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+        /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+           Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+           Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+           Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+           Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+                                      RSVD - Filter1 Command - RSVD - Filter0 Command
+           Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+           Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+           Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+        /* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define EMAC_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define EMAC_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
+#define EMAC_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define EMAC_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
+#define EMAC_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
+#define EMAC_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
+#define EMAC_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+
+        /* Bit definition for Ethernet MAC Status Register */
+#define EMAC_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
+#define EMAC_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
+#define EMAC_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
+#define EMAC_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
+#define EMAC_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+
+        /* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define EMAC_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
+#define EMAC_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+
+        /* Bit definition for Ethernet MAC Address0 High Register */
+#define EMAC_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+
+        /* Bit definition for Ethernet MAC Address0 Low Register */
+#define EMAC_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+
+        /* Bit definition for Ethernet MAC Address1 High Register */
+#define EMAC_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define EMAC_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define EMAC_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define EMAC_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define EMAC_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define EMAC_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define EMAC_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define EMAC_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define EMAC_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */
+#define EMAC_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+        /* Bit definition for Ethernet MAC Address1 Low Register */
+#define EMAC_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+
+        /* Bit definition for Ethernet MAC Address2 High Register */
+#define EMAC_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define EMAC_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define EMAC_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+#define EMAC_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define EMAC_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define EMAC_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define EMAC_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define EMAC_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define EMAC_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define EMAC_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+        /* Bit definition for Ethernet MAC Address2 Low Register */
+#define EMAC_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+
+        /* Bit definition for Ethernet MAC Address3 High Register */
+#define EMAC_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define EMAC_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define EMAC_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+#define EMAC_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define EMAC_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define EMAC_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define EMAC_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define EMAC_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define EMAC_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define EMAC_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+
+        /* Bit definition for Ethernet MAC Address3 Low Register */
+#define EMAC_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+        /* Bit definition for Ethernet MMC Contol Register */
+#define EMAC_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
+#define EMAC_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
+#define EMAC_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
+#define EMAC_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+
+        /* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define EMAC_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define EMAC_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define EMAC_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+        /* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define EMAC_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define EMAC_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define EMAC_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+        /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define EMAC_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define EMAC_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define EMAC_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+        /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define EMAC_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define EMAC_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define EMAC_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+        /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define EMAC_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+        /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define EMAC_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+        /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define EMAC_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+        /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define EMAC_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+        /* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
+#define EMAC_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+        /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define EMAC_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+        /* Bit definition for Ethernet PTP Time Stamp Control Register */
+#define EMAC_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
+#define EMAC_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
+#define EMAC_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
+#define EMAC_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
+#define EMAC_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
+#define EMAC_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+
+        /* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define EMAC_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+
+        /* Bit definition for Ethernet PTP Time Stamp High Register */
+#define EMAC_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+
+        /* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define EMAC_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
+#define EMAC_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+
+        /* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define EMAC_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+
+        /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define EMAC_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
+#define EMAC_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+        /* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define EMAC_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+
+        /* Bit definition for Ethernet PTP Target Time High Register */
+#define EMAC_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+
+        /* Bit definition for Ethernet PTP Target Time Low Register */
+#define EMAC_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+        /* Bit definition for Ethernet DMA Bus Mode Register */
+#define EMAC_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
+#define EMAC_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
+#define EMAC_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
+#define EMAC_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
+#define EMAC_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define EMAC_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define EMAC_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define EMAC_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define EMAC_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define EMAC_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define EMAC_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define EMAC_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define EMAC_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define EMAC_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define EMAC_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define EMAC_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define EMAC_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
+#define EMAC_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
+#define EMAC_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define EMAC_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define EMAC_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define EMAC_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define EMAC_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define EMAC_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define EMAC_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define EMAC_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define EMAC_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define EMAC_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define EMAC_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define EMAC_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define EMAC_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
+#define EMAC_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
+#define EMAC_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
+#define EMAC_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+
+        /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define EMAC_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+
+        /* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define EMAC_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+
+        /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define EMAC_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+
+        /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define EMAC_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+
+        /* Bit definition for Ethernet DMA Status Register */
+#define EMAC_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
+#define EMAC_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
+#define EMAC_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
+#define EMAC_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+        /* combination with EBS[2:0] for GetFlagStatus function */
+#define EMAC_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+#define EMAC_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write transfer, 1-read transfer */
+#define EMAC_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define EMAC_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
+#define EMAC_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+#define EMAC_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+#define EMAC_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
+#define EMAC_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+#define EMAC_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailable */
+#define EMAC_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+#define EMAC_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
+#define EMAC_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+#define EMAC_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+#define EMAC_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
+#define EMAC_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+#define EMAC_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+#define EMAC_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the receive frame into host memory */
+#define EMAC_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
+#define EMAC_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define EMAC_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
+#define EMAC_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
+#define EMAC_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
+#define EMAC_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
+#define EMAC_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
+#define EMAC_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
+#define EMAC_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
+#define EMAC_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
+#define EMAC_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
+#define EMAC_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
+#define EMAC_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
+#define EMAC_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
+#define EMAC_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+
+        /* Bit definition for Ethernet DMA Operation Mode Register */
+#define EMAC_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define EMAC_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
+#define EMAC_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
+#define EMAC_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
+#define EMAC_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
+#define EMAC_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
+#define EMAC_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define EMAC_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define EMAC_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define EMAC_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define EMAC_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define EMAC_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define EMAC_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define EMAC_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define EMAC_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
+#define EMAC_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
+#define EMAC_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
+#define EMAC_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
+#define EMAC_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define EMAC_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define EMAC_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define EMAC_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define EMAC_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
+#define EMAC_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+
+        /* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define EMAC_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
+#define EMAC_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
+#define EMAC_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
+#define EMAC_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
+#define EMAC_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
+#define EMAC_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define EMAC_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
+#define EMAC_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define EMAC_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
+#define EMAC_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
+#define EMAC_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
+#define EMAC_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define EMAC_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define EMAC_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
+#define EMAC_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+
+        /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define EMAC_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define EMAC_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
+#define EMAC_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+#define EMAC_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+
+        /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define EMAC_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+        /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define EMAC_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+        /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define EMAC_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+        /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define EMAC_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+
+//typedef enum {
+//	RESET = 0, SET = !RESET
+//} FlagStatus, ITStatus;
+//typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+/**
+  * ETH MAC Init structure definition
+  */
+typedef struct
+{
+    /**
+     * MAC
+     */
+    uint32_t             EMAC_AutoNegotiation;           /* Selects or not the AutoNegotiation mode for the external PHY
+                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+                                                           and the mode (half/full-duplex).
+                                                           This parameter can be a value of @ref EMAC_AutoNegotiation */
+
+    uint32_t             EMAC_Watchdog;                  /* Selects or not the Watchdog timer
+                                                           When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                           When disabled, the MAC can receive up to 16384 bytes.
+                                                           This parameter can be a value of @ref EMAC_watchdog */
+
+    uint32_t             EMAC_Jabber;                    /* Selects or not Jabber timer
+                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                           When disabled, the MAC can send up to 16384 bytes.
+                                                           This parameter can be a value of @ref EMAC_Jabber */
+
+    uint32_t             EMAC_InterFrameGap;             /* Selects the minimum IFG between frames during transmission
+                                                           This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
+
+    uint32_t             EMAC_CarrierSense;              /* Selects or not the Carrier Sense
+                                                           This parameter can be a value of @ref EMAC_Carrier_Sense */
+
+    uint32_t             EMAC_Speed;                     /* Sets the Ethernet speed: 10/100 Mbps
+                                                           This parameter can be a value of @ref EMAC_Speed */
+
+    uint32_t             EMAC_ReceiveOwn;                /* Selects or not the ReceiveOwn
+                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+                                                           in Half-Duplex mode
+                                                           This parameter can be a value of @ref EMAC_Receive_Own */
+
+    uint32_t             EMAC_LoopbackMode;              /* Selects or not the internal MAC MII Loopback mode
+                                                           This parameter can be a value of @ref EMAC_Loop_Back_Mode */
+
+    uint32_t             EMAC_Mode;                      /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                           This parameter can be a value of @ref EMAC_Duplex_Mode */
+
+    uint32_t             EMAC_ChecksumOffload;           /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+                                                           This parameter can be a value of @ref EMAC_Checksum_Offload */
+
+    uint32_t             EMAC_RetryTransmission;         /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
+                                                           when a colision occurs (Half-Duplex mode)
+                                                           This parameter can be a value of @ref EMAC_Retry_Transmission */
+
+    uint32_t             EMAC_AutomaticPadCRCStrip;      /* Selects or not the Automatic MAC Pad/CRC Stripping
+                                                           This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
+
+    uint32_t             EMAC_BackOffLimit;              /* Selects the BackOff limit value
+                                                           This parameter can be a value of @ref EMAC_Back_Off_Limit */
+
+    uint32_t             EMAC_DeferralCheck;             /* Selects or not the deferral check function (Half-Duplex mode)
+                                                           This parameter can be a value of @ref EMAC_Deferral_Check */
+
+    uint32_t             EMAC_ReceiveAll;                /* Selects or not all frames reception by the MAC (No fitering)
+                                                           This parameter can be a value of @ref EMAC_Receive_All */
+
+    uint32_t             EMAC_SourceAddrFilter;          /* Selects the Source Address Filter mode
+                                                           This parameter can be a value of @ref EMAC_Source_Addr_Filter */
+
+    uint32_t             EMAC_PassControlFrames;         /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+                                                           This parameter can be a value of @ref EMAC_Pass_Control_Frames */
+
+    uint32_t             EMAC_BroadcastFramesReception;  /* Selects or not the reception of Broadcast Frames
+                                                           This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
+
+    uint32_t             EMAC_DestinationAddrFilter;     /* Sets the destination filter mode for both unicast and multicast frames
+                                                           This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
+
+    uint32_t             EMAC_PromiscuousMode;           /* Selects or not the Promiscuous Mode
+                                                           This parameter can be a value of @ref EMAC_Promiscuous_Mode */
+
+    uint32_t             EMAC_MulticastFramesFilter;     /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                           This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
+
+    uint32_t             EMAC_UnicastFramesFilter;       /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                           This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
+
+    uint32_t             EMAC_HashTableHigh;             /* This field holds the higher 32 bits of Hash table.  */
+
+    uint32_t             EMAC_HashTableLow;              /* This field holds the lower 32 bits of Hash table.  */
+
+    uint32_t             EMAC_PauseTime;                 /* This field holds the value to be used in the Pause Time field in the
+                                                           transmit control frame */
+
+    uint32_t             EMAC_ZeroQuantaPause;           /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
+                                                           This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
+
+    uint32_t             EMAC_PauseLowThreshold;         /* This field configures the threshold of the PAUSE to be checked for
+                                                           automatic retransmission of PAUSE Frame
+                                                           This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
+
+    uint32_t             EMAC_UnicastPauseFrameDetect;   /* Selects or not the MAC detection of the Pause frames (with MAC Address0
+                                                           unicast address and unique multicast address)
+                                                           This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
+
+    uint32_t             EMAC_ReceiveFlowControl;        /* Enables or disables the MAC to decode the received Pause frame and
+                                                           disable its transmitter for a specified time (Pause Time)
+                                                           This parameter can be a value of @ref EMAC_Receive_Flow_Control */
+
+    uint32_t             EMAC_TransmitFlowControl;       /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+                                                           or the MAC back-pressure operation (Half-Duplex mode)
+                                                           This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
+
+    uint32_t             EMAC_VLANTagComparison;         /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+                                                           comparison and filtering
+                                                           This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
+
+    uint32_t             EMAC_VLANTagIdentifier;         /* Holds the VLAN tag identifier for receive frames */
+
+    /**
+     * DMA
+     */
+
+    uint32_t             EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
+                                                             This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
+
+    uint32_t             EMAC_ReceiveStoreForward;         /* Enables or disables the Receive store and forward mode
+                                                             This parameter can be a value of @ref EMAC_Receive_Store_Forward */
+
+    uint32_t             EMAC_FlushReceivedFrame;          /* Enables or disables the flushing of received frames
+                                                             This parameter can be a value of @ref EMAC_Flush_Received_Frame */
+
+    uint32_t             EMAC_TransmitStoreForward;        /* Enables or disables Transmit store and forward mode
+                                                             This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
+
+    uint32_t             EMAC_TransmitThresholdControl;    /* Selects or not the Transmit Threshold Control
+                                                             This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
+
+    uint32_t             EMAC_ForwardErrorFrames;          /* Selects or not the forward to the DMA of erroneous frames
+                                                             This parameter can be a value of @ref EMAC_Forward_Error_Frames */
+
+    uint32_t             EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+                                                             and length less than 64 bytes) including pad-bytes and CRC)
+                                                             This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
+
+    uint32_t             EMAC_ReceiveThresholdControl;     /* Selects the threshold level of the Receive FIFO
+                                                             This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
+
+    uint32_t             EMAC_SecondFrameOperate;          /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
+                                                             frame of Transmit data even before obtaining the status for the first frame.
+                                                             This parameter can be a value of @ref EMAC_Second_Frame_Operate */
+
+    uint32_t             EMAC_AddressAlignedBeats;         /* Enables or disables the Address Aligned Beats
+                                                             This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
+
+    uint32_t             EMAC_FixedBurst;                  /* Enables or disables the AHB Master interface fixed burst transfers
+                                                             This parameter can be a value of @ref EMAC_Fixed_Burst */
+
+    uint32_t             EMAC_RxDMABurstLength;            /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+                                                             This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
+
+    uint32_t             EMAC_TxDMABurstLength;            /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+                                                             This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
+
+    uint32_t             EMAC_DescriptorSkipLength;        /* Specifies the number of word to skip between two unchained int (Ring mode) */
+
+    uint32_t             EMAC_DMAArbitration;              /* Selects the DMA Tx/Rx arbitration
+                                                             This parameter can be a value of @ref EMAC_DMA_Arbitration */
+} EMAC_InitTypeDef;
+
+/**--------------------------------------------------------------------------**/
+/**
+  *                            DMA int types
+  */
+/**--------------------------------------------------------------------------**/
+
+/**
+  * ETH DMA Descriptors data structure definition
+  */
+typedef struct
+{
+    uint32_t   Status;                /* Status */
+    uint32_t   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
+    uint32_t   Buffer1Addr;           /* Buffer1 address pointer */
+    uint32_t   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
+} EMAC_DMADESCTypeDef;
+
+/**--------------------------------------------------------------------------**/
+/**
+  *                           ETH Frames defines
+  */
+/**--------------------------------------------------------------------------**/
+
+#define EMAC_MAX_PACKET_SIZE    	1520    /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
+#define EMAC_HEADER               	14    	/* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define EMAC_CRC                   	4    	/* Ethernet CRC */
+#define EMAC_EXTRA                 	2    	/* Extra bytes in some cases */
+#define VLAN_TAG                  	4    	/* optional 802.1q VLAN Tag */
+#define MIN_EMAC_PAYLOAD          	46    	/* Minimum Ethernet payload size */
+#define MAX_EMAC_PAYLOAD        	1500    /* Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD    		9000    /* Jumbo frame payload size */
+
+/**--------------------------------------------------------------------------**/
+/**
+ *                  Ethernet DMA int registers bits definition
+ */
+/**--------------------------------------------------------------------------**/
+
+#define EMAC_DMATxDesc_OWN                     ((uint32_t)0x80000000)  /* OWN bit: descriptor is owned by DMA engine */
+#define EMAC_DMATxDesc_IC                      ((uint32_t)0x40000000)  /* Interrupt on Completion */
+#define EMAC_DMATxDesc_LS                      ((uint32_t)0x20000000)  /* Last Segment */
+#define EMAC_DMATxDesc_FS                      ((uint32_t)0x10000000)  /* First Segment */
+#define EMAC_DMATxDesc_DC                      ((uint32_t)0x08000000)  /* Disable CRC */
+#define EMAC_DMATxDesc_DP                      ((uint32_t)0x04000000)  /* Disable Padding */
+#define EMAC_DMATxDesc_TTSE                    ((uint32_t)0x02000000)  /* Transmit Time Stamp Enable */
+#define EMAC_DMATxDesc_CIC                     ((uint32_t)0x00C00000)  /* Checksum Insertion Control: 4 cases */
+#define EMAC_DMATxDesc_CIC_ByPass              ((uint32_t)0x00000000)  /* Do Nothing: Checksum Engine is bypassed */
+#define EMAC_DMATxDesc_CIC_IPV4Header          ((uint32_t)0x00400000)  /* IPV4 header Checksum Insertion */
+#define EMAC_DMATxDesc_CIC_TCPUDPICMP_Segment  ((uint32_t)0x00800000)  /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define EMAC_DMATxDesc_CIC_TCPUDPICMP_Full     ((uint32_t)0x00C00000)  /* TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define EMAC_DMATxDesc_TER                     ((uint32_t)0x00200000)  /* Transmit End of Ring */
+#define EMAC_DMATxDesc_TCH                     ((uint32_t)0x00100000)  /* Second Address Chained */
+#define EMAC_DMATxDesc_TTSS                    ((uint32_t)0x00020000)  /* Tx Time Stamp Status */
+#define EMAC_DMATxDesc_IHE                     ((uint32_t)0x00010000)  /* IP Header Error */
+#define EMAC_DMATxDesc_ES                      ((uint32_t)0x00008000)  /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define EMAC_DMATxDesc_JT                      ((uint32_t)0x00004000)  /* Jabber Timeout */
+#define EMAC_DMATxDesc_FF                      ((uint32_t)0x00002000)  /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define EMAC_DMATxDesc_PCE                     ((uint32_t)0x00001000)  /* Payload Checksum Error */
+#define EMAC_DMATxDesc_LCA                     ((uint32_t)0x00000800)  /* Loss of Carrier: carrier lost during transmission */
+#define EMAC_DMATxDesc_NC                      ((uint32_t)0x00000400)  /* No Carrier: no carrier signal from the transceiver */
+#define EMAC_DMATxDesc_LCO                     ((uint32_t)0x00000200)  /* Late Collision: transmission aborted due to collision */
+#define EMAC_DMATxDesc_EC                      ((uint32_t)0x00000100)  /* Excessive Collision: transmission aborted after 16 collisions */
+#define EMAC_DMATxDesc_VF                      ((uint32_t)0x00000080)  /* VLAN Frame */
+#define EMAC_DMATxDesc_CC                      ((uint32_t)0x00000078)  /* Collision Count */
+#define EMAC_DMATxDesc_ED                      ((uint32_t)0x00000004)  /* Excessive Deferral */
+#define EMAC_DMATxDesc_UF                      ((uint32_t)0x00000002)  /* Underflow Error: late data arrival from the memory */
+#define EMAC_DMATxDesc_DB                      ((uint32_t)0x00000001)  /* Deferred Bit */
+
+#define EMAC_DMATxDesc_TBS2  ((uint32_t)0x1FFF0000)  /* Transmit Buffer2 Size */
+#define EMAC_DMATxDesc_TBS1  ((uint32_t)0x00001FFF)  /* Transmit Buffer1 Size */
+
+#define EMAC_DMATxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /* Buffer1 Address Pointer */
+
+#define EMAC_DMATxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /* Buffer2 Address Pointer */
+
+#define EMAC_DMARxDesc_OWN         ((uint32_t)0x80000000)  /* OWN bit: descriptor is owned by DMA engine  */
+#define EMAC_DMARxDesc_AFM         ((uint32_t)0x40000000)  /* DA Filter Fail for the rx frame  */
+#define EMAC_DMARxDesc_FL          ((uint32_t)0x3FFF0000)  /* Receive descriptor frame length  */
+#define EMAC_DMARxDesc_ES          ((uint32_t)0x00008000)  /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define EMAC_DMARxDesc_DE          ((uint32_t)0x00004000)  /* Descriptor error: no more int for receive frame  */
+#define EMAC_DMARxDesc_SAF         ((uint32_t)0x00002000)  /* SA Filter Fail for the received frame */
+#define EMAC_DMARxDesc_LE          ((uint32_t)0x00001000)  /* Frame size not matching with length field */
+#define EMAC_DMARxDesc_OE          ((uint32_t)0x00000800)  /* Overflow Error: Frame was damaged due to buffer overflow */
+#define EMAC_DMARxDesc_VLAN        ((uint32_t)0x00000400)  /* VLAN Tag: received frame is a VLAN frame */
+#define EMAC_DMARxDesc_FS          ((uint32_t)0x00000200)  /* First descriptor of the frame  */
+#define EMAC_DMARxDesc_LS          ((uint32_t)0x00000100)  /* Last descriptor of the frame  */
+#define EMAC_DMARxDesc_IPV4HCE     ((uint32_t)0x00000080)  /* IPC Checksum Error: Rx Ipv4 header checksum error   */
+#define EMAC_DMARxDesc_LC          ((uint32_t)0x00000040)  /* Late collision occurred during reception   */
+#define EMAC_DMARxDesc_FT          ((uint32_t)0x00000020)  /* Frame type - Ethernet, otherwise 802.3    */
+#define EMAC_DMARxDesc_RWT         ((uint32_t)0x00000010)  /* Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define EMAC_DMARxDesc_RE          ((uint32_t)0x00000008)  /* Receive error: error reported by MII interface  */
+#define EMAC_DMARxDesc_DBE         ((uint32_t)0x00000004)  /* Dribble bit error: frame contains non int multiple of 8 bits  */
+#define EMAC_DMARxDesc_CE          ((uint32_t)0x00000002)  /* CRC error */
+#define EMAC_DMARxDesc_MAMPCE      ((uint32_t)0x00000001)  /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+#define EMAC_DMARxDesc_DIC   ((uint32_t)0x80000000)  /* Disable Interrupt on Completion */
+#define EMAC_DMARxDesc_RBS2  ((uint32_t)0x1FFF0000)  /* Receive Buffer2 Size */
+#define EMAC_DMARxDesc_RER   ((uint32_t)0x00008000)  /* Receive End of Ring */
+#define EMAC_DMARxDesc_RCH   ((uint32_t)0x00004000)  /* Second Address Chained */
+#define EMAC_DMARxDesc_RBS1  ((uint32_t)0x00001FFF)  /* Receive Buffer1 Size */
+
+#define EMAC_DMARxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /* Buffer1 Address Pointer */
+
+#define EMAC_DMARxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /* Buffer2 Address Pointer */
+
+#define PHY_READ_TO                     ((uint32_t)0x0004FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0004FFFF)
+
+#define PHY_ResetDelay                  ((uint32_t)0x000FFFFF)
+
+#define PHY_ConfigDelay                 ((uint32_t)0x00FFFFFF)
+
+#define PHY_BCR                          0          /* Tranceiver Basic Control Register */
+#define PHY_BSR                          1          /* Tranceiver Basic Status Register */
+
+#define PHY_Reset                       ((uint16_t)0x8000)      /* PHY Reset */
+//#define PHY_Loopback                    ((uint16_t)0x4000)      /* Select loop-back mode */
+//#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)      /* Set the full-duplex mode at 100 Mb/s */
+//#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)      /* Set the half-duplex mode at 100 Mb/s */
+//#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)      /* Set the full-duplex mode at 10 Mb/s */
+//#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)      /* Set the half-duplex mode at 10 Mb/s */
+//#define PHY_AutoNegotiation             ((uint16_t)0x1000)      /* Enable auto-negotiation function */
+//#define PHY_Restart_AutoNegotiation     ((uint16_t)0x0200)      /* Restart auto-negotiation function */
+//#define PHY_Powerdown                   ((uint16_t)0x0800)      /* Select the power down mode */
+//#define PHY_Isolate                     ((uint16_t)0x0400)      /* Isolate PHY from MII */
+//
+//#define PHY_AutoNego_Complete           ((uint16_t)0x0020)      /* Auto-Negotiation process completed */
+//#define PHY_Linked_Status               ((uint16_t)0x0004)      /* Valid link established */
+//#define PHY_Jabber_detection            ((uint16_t)0x0002)      /* Jabber condition detected */
+//
+//#define PHY_SR                           16     /* Transceiver Status Register */
+//
+//#define PHY_Speed_Status            ((uint16_t)0x0002)    /* Configured information of Speed: 10Mbps */
+//#define PHY_Duplex_Status           ((uint16_t)0x0004)    /* Configured information of Duplex: Full-duplex */
+
+#define EMAC_AutoNegotiation_Enable     ((uint32_t)0x00000001)
+#define EMAC_AutoNegotiation_Disable    ((uint32_t)0x00000000)
+
+#define EMAC_Watchdog_Enable       ((uint32_t)0x00000000)
+#define EMAC_Watchdog_Disable      ((uint32_t)0x00800000)
+
+#define EMAC_Jabber_Enable    ((uint32_t)0x00000000)
+#define EMAC_Jabber_Disable   ((uint32_t)0x00400000)
+
+#define EMAC_InterFrameGap_96Bit   ((uint32_t)0x00000000)  /* minimum IFG between frames during transmission is 96Bit */
+#define EMAC_InterFrameGap_88Bit   ((uint32_t)0x00020000)  /* minimum IFG between frames during transmission is 88Bit */
+#define EMAC_InterFrameGap_80Bit   ((uint32_t)0x00040000)  /* minimum IFG between frames during transmission is 80Bit */
+#define EMAC_InterFrameGap_72Bit   ((uint32_t)0x00060000)  /* minimum IFG between frames during transmission is 72Bit */
+#define EMAC_InterFrameGap_64Bit   ((uint32_t)0x00080000)  /* minimum IFG between frames during transmission is 64Bit */
+#define EMAC_InterFrameGap_56Bit   ((uint32_t)0x000A0000)  /* minimum IFG between frames during transmission is 56Bit */
+#define EMAC_InterFrameGap_48Bit   ((uint32_t)0x000C0000)  /* minimum IFG between frames during transmission is 48Bit */
+#define EMAC_InterFrameGap_40Bit   ((uint32_t)0x000E0000)  /* minimum IFG between frames during transmission is 40Bit */
+
+#define EMAC_CarrierSense_Enable   ((uint32_t)0x00000000)
+#define EMAC_CarrierSense_Disable  ((uint32_t)0x00010000)
+
+#define EMAC_Speed_10M        ((uint32_t)0x00000000)
+#define EMAC_Speed_100M       ((uint32_t)0x00004000)
+
+#define EMAC_ReceiveOwn_Enable     ((uint32_t)0x00000000)
+#define EMAC_ReceiveOwn_Disable    ((uint32_t)0x00002000)
+
+#define EMAC_LoopbackMode_Enable        ((uint32_t)0x00001000)
+#define EMAC_LoopbackMode_Disable       ((uint32_t)0x00000000)
+
+#define EMAC_Mode_FullDuplex       ((uint32_t)0x00000800)
+#define EMAC_Mode_HalfDuplex       ((uint32_t)0x00000000)
+
+#define EMAC_ChecksumOffload_Enable     ((uint32_t)0x00000400)
+#define EMAC_ChecksumOffload_Disable    ((uint32_t)0x00000000)
+
+#define EMAC_RetryTransmission_Enable   ((uint32_t)0x00000000)
+#define EMAC_RetryTransmission_Disable  ((uint32_t)0x00000200)
+
+#define EMAC_AutomaticPadCRCStrip_Enable     ((uint32_t)0x00000080)
+#define EMAC_AutomaticPadCRCStrip_Disable    ((uint32_t)0x00000000)
+
+#define EMAC_BackOffLimit_10  ((uint32_t)0x00000000)
+#define EMAC_BackOffLimit_8   ((uint32_t)0x00000020)
+#define EMAC_BackOffLimit_4   ((uint32_t)0x00000040)
+#define EMAC_BackOffLimit_1   ((uint32_t)0x00000060)
+
+#define EMAC_DeferralCheck_Enable       ((uint32_t)0x00000010)
+#define EMAC_DeferralCheck_Disable      ((uint32_t)0x00000000)
+
+#define EMAC_ReceiveAll_Enable     ((uint32_t)0x80000000)
+#define EMAC_ReceiveAll_Disable    ((uint32_t)0x00000000)
+
+#define EMAC_SourceAddrFilter_Normal_Enable       ((uint32_t)0x00000200)
+#define EMAC_SourceAddrFilter_Inverse_Enable      ((uint32_t)0x00000300)
+#define EMAC_SourceAddrFilter_Disable             ((uint32_t)0x00000000)
+
+#define EMAC_PassControlFrames_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+#define EMAC_PassControlFrames_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define EMAC_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
+
+#define EMAC_BroadcastFramesReception_Enable      ((uint32_t)0x00000000)
+#define EMAC_BroadcastFramesReception_Disable     ((uint32_t)0x00000020)
+
+#define EMAC_DestinationAddrFilter_Normal    ((uint32_t)0x00000000)
+#define EMAC_DestinationAddrFilter_Inverse   ((uint32_t)0x00000008)
+
+#define EMAC_PromiscuousMode_Enable     ((uint32_t)0x00000001)
+#define EMAC_PromiscuousMode_Disable    ((uint32_t)0x00000000)
+
+#define EMAC_MulticastFramesFilter_PerfectHashTable    ((uint32_t)0x00000404)
+#define EMAC_MulticastFramesFilter_HashTable           ((uint32_t)0x00000004)
+#define EMAC_MulticastFramesFilter_Perfect             ((uint32_t)0x00000000)
+#define EMAC_MulticastFramesFilter_None                ((uint32_t)0x00000010)
+
+#define EMAC_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
+#define EMAC_UnicastFramesFilter_HashTable        ((uint32_t)0x00000002)
+#define EMAC_UnicastFramesFilter_Perfect          ((uint32_t)0x00000000)
+
+#define EMAC_ZeroQuantaPause_Enable     ((uint32_t)0x00000000)
+#define EMAC_ZeroQuantaPause_Disable    ((uint32_t)0x00000080)
+
+#define EMAC_PauseLowThreshold_Minus4        ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+#define EMAC_PauseLowThreshold_Minus28       ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+#define EMAC_PauseLowThreshold_Minus144      ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+#define EMAC_PauseLowThreshold_Minus256      ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */
+
+#define EMAC_UnicastPauseFrameDetect_Enable  ((uint32_t)0x00000008)
+#define EMAC_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
+
+#define EMAC_ReceiveFlowControl_Enable       ((uint32_t)0x00000004)
+#define EMAC_ReceiveFlowControl_Disable      ((uint32_t)0x00000000)
+#define EMAC_TransmitFlowControl_Enable      ((uint32_t)0x00000002)
+#define EMAC_TransmitFlowControl_Disable     ((uint32_t)0x00000000)
+
+#define EMAC_VLANTagComparison_12Bit    ((uint32_t)0x00010000)
+#define EMAC_VLANTagComparison_16Bit    ((uint32_t)0x00000000)
+
+#define EMAC_MAC_FLAG_TST     ((uint32_t)0x00000200)  /* Time stamp trigger flag (on MAC) */
+#define EMAC_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /* MMC transmit flag  */
+#define EMAC_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /* MMC receive flag */
+#define EMAC_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /* MMC flag (on MAC) */
+#define EMAC_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /* PMT flag (on MAC) */
+
+#define EMAC_MAC_IT_TST       ((uint32_t)0x00000200)  /* Time stamp trigger interrupt (on MAC) */
+#define EMAC_MAC_IT_MMCT      ((uint32_t)0x00000040)  /* MMC transmit interrupt */
+#define EMAC_MAC_IT_MMCR      ((uint32_t)0x00000020)  /* MMC receive interrupt */
+#define EMAC_MAC_IT_MMC       ((uint32_t)0x00000010)  /* MMC interrupt (on MAC) */
+#define EMAC_MAC_IT_PMT       ((uint32_t)0x00000008)  /* PMT interrupt (on MAC) */
+
+#define EMAC_MAC_Address0     ((uint32_t)0x00000000)
+#define EMAC_MAC_Address1     ((uint32_t)0x00000008)
+#define EMAC_MAC_Address2     ((uint32_t)0x00000010)
+#define EMAC_MAC_Address3     ((uint32_t)0x00000018)
+
+#define EMAC_MAC_AddressFilter_SA       ((uint32_t)0x00000000)
+#define EMAC_MAC_AddressFilter_DA       ((uint32_t)0x00000008)
+
+#define EMAC_MAC_AddressMask_Byte6      ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define EMAC_MAC_AddressMask_Byte5      ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define EMAC_MAC_AddressMask_Byte4      ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define EMAC_MAC_AddressMask_Byte3      ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define EMAC_MAC_AddressMask_Byte2      ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define EMAC_MAC_AddressMask_Byte1      ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+
+#define EMAC_DMATxDesc_LastSegment      ((uint32_t)0x40000000)  /* Last Segment */
+#define EMAC_DMATxDesc_FirstSegment     ((uint32_t)0x20000000)  /* First Segment */
+
+#define EMAC_DMATxDesc_ChecksumByPass             ((uint32_t)0x00000000)   /* Checksum engine bypass */
+#define EMAC_DMATxDesc_ChecksumIPV4Header         ((uint32_t)0x00400000)   /* IPv4 header checksum insertion  */
+#define EMAC_DMATxDesc_ChecksumTCPUDPICMPSegment  ((uint32_t)0x00800000)   /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define EMAC_DMATxDesc_ChecksumTCPUDPICMPFull     ((uint32_t)0x00C00000)   /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+
+#define EMAC_DMARxDesc_Buffer1     ((uint32_t)0x00000000)  /* DMA Rx Desc Buffer1 */
+#define EMAC_DMARxDesc_Buffer2     ((uint32_t)0x00000001)  /* DMA Rx Desc Buffer2 */
+
+#define EMAC_DropTCPIPChecksumErrorFrame_Enable   ((uint32_t)0x00000000)
+#define EMAC_DropTCPIPChecksumErrorFrame_Disable  ((uint32_t)0x04000000)
+
+#define EMAC_ReceiveStoreForward_Enable      ((uint32_t)0x02000000)
+#define EMAC_ReceiveStoreForward_Disable     ((uint32_t)0x00000000)
+
+#define EMAC_FlushReceivedFrame_Enable       ((uint32_t)0x00000000)
+#define EMAC_FlushReceivedFrame_Disable      ((uint32_t)0x01000000)
+
+#define EMAC_TransmitStoreForward_Enable     ((uint32_t)0x00200000)
+#define EMAC_TransmitStoreForward_Disable    ((uint32_t)0x00000000)
+
+#define EMAC_TransmitThresholdControl_64Bytes     ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define EMAC_TransmitThresholdControl_128Bytes    ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define EMAC_TransmitThresholdControl_192Bytes    ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define EMAC_TransmitThresholdControl_256Bytes    ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define EMAC_TransmitThresholdControl_40Bytes     ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define EMAC_TransmitThresholdControl_32Bytes     ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define EMAC_TransmitThresholdControl_24Bytes     ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define EMAC_TransmitThresholdControl_16Bytes     ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+
+#define EMAC_ForwardErrorFrames_Enable       ((uint32_t)0x00000080)
+#define EMAC_ForwardErrorFrames_Disable      ((uint32_t)0x00000000)
+
+#define EMAC_ForwardUndersizedGoodFrames_Enable   ((uint32_t)0x00000040)
+#define EMAC_ForwardUndersizedGoodFrames_Disable  ((uint32_t)0x00000000)
+
+#define EMAC_ReceiveThresholdControl_64Bytes      ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define EMAC_ReceiveThresholdControl_32Bytes      ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define EMAC_ReceiveThresholdControl_96Bytes      ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define EMAC_ReceiveThresholdControl_128Bytes     ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+
+#define EMAC_SecondFrameOperate_Enable       ((uint32_t)0x00000004)
+#define EMAC_SecondFrameOperate_Disable      ((uint32_t)0x00000000)
+
+#define EMAC_AddressAlignedBeats_Enable      ((uint32_t)0x02000000)
+#define EMAC_AddressAlignedBeats_Disable     ((uint32_t)0x00000000)
+
+#define EMAC_FixedBurst_Enable     ((uint32_t)0x00010000)
+#define EMAC_FixedBurst_Disable    ((uint32_t)0x00000000)
+
+#define EMAC_RxDMABurstLength_1Beat          ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define EMAC_RxDMABurstLength_2Beat          ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define EMAC_RxDMABurstLength_4Beat          ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define EMAC_RxDMABurstLength_8Beat          ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define EMAC_RxDMABurstLength_16Beat         ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define EMAC_RxDMABurstLength_32Beat         ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define EMAC_RxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define EMAC_RxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define EMAC_RxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define EMAC_RxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define EMAC_RxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define EMAC_RxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+#define EMAC_TxDMABurstLength_1Beat          ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define EMAC_TxDMABurstLength_2Beat          ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define EMAC_TxDMABurstLength_4Beat          ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define EMAC_TxDMABurstLength_8Beat          ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define EMAC_TxDMABurstLength_16Beat         ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define EMAC_TxDMABurstLength_32Beat         ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define EMAC_TxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define EMAC_TxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define EMAC_TxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define EMAC_TxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define EMAC_TxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define EMAC_TxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+#define EMAC_DMAArbitration_RoundRobin_RxTx_1_1   ((uint32_t)0x00000000)
+#define EMAC_DMAArbitration_RoundRobin_RxTx_2_1   ((uint32_t)0x00004000)
+#define EMAC_DMAArbitration_RoundRobin_RxTx_3_1   ((uint32_t)0x00008000)
+#define EMAC_DMAArbitration_RoundRobin_RxTx_4_1   ((uint32_t)0x0000C000)
+#define EMAC_DMAArbitration_RxPriorTx             ((uint32_t)0x00000002)
+
+#define EMAC_DMA_FLAG_TST               ((uint32_t)0x20000000)  /* Time-stamp trigger interrupt (on DMA) */
+#define EMAC_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /* PMT interrupt (on DMA) */
+#define EMAC_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /* MMC interrupt (on DMA) */
+#define EMAC_DMA_FLAG_DataTransferError ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define EMAC_DMA_FLAG_ReadWriteError    ((uint32_t)0x01000000)  /* Error bits 0-write transfer, 1-read transfer */
+#define EMAC_DMA_FLAG_AccessError       ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+#define EMAC_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /* Normal interrupt summary flag */
+#define EMAC_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /* Abnormal interrupt summary flag */
+#define EMAC_DMA_FLAG_ER                ((uint32_t)0x00004000)  /* Early receive flag */
+#define EMAC_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /* Fatal bus error flag */
+#define EMAC_DMA_FLAG_ET                ((uint32_t)0x00000400)  /* Early transmit flag */
+#define EMAC_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /* Receive watchdog timeout flag */
+#define EMAC_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /* Receive process stopped flag */
+#define EMAC_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /* Receive buffer unavailable flag */
+#define EMAC_DMA_FLAG_R                 ((uint32_t)0x00000040)  /* Receive flag */
+#define EMAC_DMA_FLAG_TU                ((uint32_t)0x00000020)  /* Underflow flag */
+#define EMAC_DMA_FLAG_RO                ((uint32_t)0x00000010)  /* Overflow flag */
+#define EMAC_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /* Transmit jabber timeout flag */
+#define EMAC_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /* Transmit buffer unavailable flag */
+#define EMAC_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /* Transmit process stopped flag */
+#define EMAC_DMA_FLAG_T                 ((uint32_t)0x00000001)  /* Transmit flag */
+
+#define EMAC_DMA_INT_GLPII     ((uint32_t)(1UL<<30))  /* GMAC LPI Interrupt. */
+#define EMAC_DMA_INT_TTI       ((uint32_t)(1UL<<29))  /* Time-Stamp Trigger Interrupt. */
+#define EMAC_DMA_INT_GPI       ((uint32_t)(1UL<<28))  /* GMAC PMT Interrupt. */
+#define EMAC_DMA_INT_GMI       ((uint32_t)(1UL<<27))  /* GMAC MMC Interrupt. */
+#define EMAC_DMA_INT_GLI       ((uint32_t)(1UL<<26))  /* GMAC Line interface Interrupt. */
+#define EMAC_DMA_INT_NIS       ((uint32_t)(1UL<<16))  /* Normal interrupt summary. */
+#define EMAC_DMA_INT_AIS       ((uint32_t)(1UL<<15))  /* Abnormal interrupt summary. */
+#define EMAC_DMA_INT_ER        ((uint32_t)0x00004000)  /* Early receive interrupt */
+#define EMAC_DMA_INT_FBE       ((uint32_t)0x00002000)  /* Fatal bus error interrupt */
+#define EMAC_DMA_INT_ET        ((uint32_t)0x00000400)  /* Early transmit interrupt */
+#define EMAC_DMA_INT_RWT       ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt */
+#define EMAC_DMA_INT_RPS       ((uint32_t)0x00000100)  /* Receive process stopped interrupt */
+#define EMAC_DMA_INT_RBU       ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt */
+#define EMAC_DMA_INT_R         ((uint32_t)0x00000040)  /* Receive interrupt */
+#define EMAC_DMA_INT_TU        ((uint32_t)0x00000020)  /* Underflow interrupt */
+#define EMAC_DMA_INT_RO        ((uint32_t)0x00000010)  /* Overflow interrupt */
+#define EMAC_DMA_INT_TJT       ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt */
+#define EMAC_DMA_INT_TBU       ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt */
+#define EMAC_DMA_INT_TPS       ((uint32_t)0x00000002)  /* Transmit process stopped interrupt */
+#define EMAC_DMA_INT_T         ((uint32_t)0x00000001)  /* Transmit interrupt */
+
+#define EMAC_DMA_TransmitProcess_Stopped     ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued */
+#define EMAC_DMA_TransmitProcess_Fetching    ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+#define EMAC_DMA_TransmitProcess_Waiting     ((uint32_t)0x00200000)  /* Running - waiting for status */
+#define EMAC_DMA_TransmitProcess_Reading     ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+#define EMAC_DMA_TransmitProcess_Suspended   ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailable */
+#define EMAC_DMA_TransmitProcess_Closing     ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+
+#define EMAC_DMA_ReceiveProcess_Stopped      ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+#define EMAC_DMA_ReceiveProcess_Fetching     ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+#define EMAC_DMA_ReceiveProcess_Waiting      ((uint32_t)0x00060000)  /* Running - waiting for packet */
+#define EMAC_DMA_ReceiveProcess_Suspended    ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+#define EMAC_DMA_ReceiveProcess_Closing      ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+#define EMAC_DMA_ReceiveProcess_Queuing      ((uint32_t)0x000E0000)  /* Running - queuing the receive frame into host memory */
+
+#define EMAC_DMA_Overflow_RxFIFOCounter      ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define EMAC_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+
+#define EMAC_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define EMAC_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define EMAC_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /* Magic Packet Received */
+
+#define EMAC_MMC_IT_TGF       ((uint32_t)0x00200000)  /* When Tx good frame counter reaches half the maximum value */
+#define EMAC_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /* When Tx good multi col counter reaches half the maximum value */
+#define EMAC_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /* When Tx good single col counter reaches half the maximum value */
+#define EMAC_MMC_IT_RGUF      ((uint32_t)0x10020000)  /* When Rx good unicast frames counter reaches half the maximum value */
+#define EMAC_MMC_IT_RFAE      ((uint32_t)0x10000040)  /* When Rx alignment error counter reaches half the maximum value */
+#define EMAC_MMC_IT_RFCE      ((uint32_t)0x10000020)  /* When Rx crc error counter reaches half the maximum value */
+
+#define EMAC_MMCCR            ((uint32_t)0x00000100)  /* MMC CR register */
+#define EMAC_MMCRIR           ((uint32_t)0x00000104)  /* MMC RIR register */
+#define EMAC_MMCTIR           ((uint32_t)0x00000108)  /* MMC TIR register */
+#define EMAC_MMCRIMR          ((uint32_t)0x0000010C)  /* MMC RIMR register */
+#define EMAC_MMCTIMR          ((uint32_t)0x00000110)  /* MMC TIMR register */
+#define EMAC_MMCTGFSCCR       ((uint32_t)0x0000014C)  /* MMC TGFSCCR register */
+#define EMAC_MMCTGFMSCCR      ((uint32_t)0x00000150)  /* MMC TGFMSCCR register */
+#define EMAC_MMCTGFCR         ((uint32_t)0x00000168)  /* MMC TGFCR register */
+#define EMAC_MMCRFCECR        ((uint32_t)0x00000194)  /* MMC RFCECR register */
+#define EMAC_MMCRFAECR        ((uint32_t)0x00000198)  /* MMC RFAECR register */
+#define EMAC_MMCRGUFCR        ((uint32_t)0x000001C4)  /* MMC RGUFCR register */
+
+#define EMAC_PTP_FineUpdate        ((uint32_t)0x00000001)  /* Fine Update method */
+#define EMAC_PTP_CoarseUpdate      ((uint32_t)0x00000000)  /* Coarse Update method */
+
+#define EMAC_PTP_FLAG_TSARU        ((uint32_t)0x00000020)  /* Addend Register Update */
+#define EMAC_PTP_FLAG_TSITE        ((uint32_t)0x00000010)  /* Time Stamp Interrupt Trigger */
+#define EMAC_PTP_FLAG_TSSTU        ((uint32_t)0x00000008)  /* Time Stamp Update */
+#define EMAC_PTP_FLAG_TSSTI        ((uint32_t)0x00000004)  /* Time Stamp Initialize */
+
+#define EMAC_PTP_PositiveTime      ((uint32_t)0x00000000)  /* Positive time value */
+#define EMAC_PTP_NegativeTime      ((uint32_t)0x80000000)  /* Negative time value */
+
+#define EMAC_PTPTSCR     ((uint32_t)0x00000700)  /* PTP TSCR register */
+#define EMAC_PTPSSIR     ((uint32_t)0x00000704)  /* PTP SSIR register */
+#define EMAC_PTPTSHR     ((uint32_t)0x00000708)  /* PTP TSHR register */
+#define EMAC_PTPTSLR     ((uint32_t)0x0000070C)  /* PTP TSLR register */
+#define EMAC_PTPTSHUR    ((uint32_t)0x00000710)  /* PTP TSHUR register */
+#define EMAC_PTPTSLUR    ((uint32_t)0x00000714)  /* PTP TSLUR register */
+#define EMAC_PTPTSAR     ((uint32_t)0x00000718)  /* PTP TSAR register */
+#define EMAC_PTPTTHR     ((uint32_t)0x0000071C)  /* PTP TTHR register */
+#define EMAC_PTPTTLR     ((uint32_t)0x00000720)  /* PTP TTLR register */
+
+/* ETHERNET MAC address offsets */
+#define EMAC_MAC_ADDR_HBASE    (FM3_ETHERNET_MAC0_BASE + 0x40)  /* ETHERNET MAC address high offset */
+#define EMAC_MAC_ADDR_LBASE    (FM3_ETHERNET_MAC0_BASE + 0x44)  /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
+
+/* ETHERNET errors */
+#define  EMAC_ERROR              ((uint32_t)0)
+#define  EMAC_SUCCESS            ((uint32_t)1)
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define  EMAC_DMARXDESC_FRAME_LENGTHSHIFT           16
+
+uint32_t EMAC_init(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC);
+
+void  EMAC_start(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC);
+void set_ethernet_e_cout_clock(int is_rmii);
+
+uint16_t EMAC_PHY_read(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC, uint16_t PHYAddress, uint16_t PHYReg);
+uint32_t EMAC_PHY_write(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC, uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue);
+
+void EMAC_MAC_Addr_config(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC, uint32_t MacAddr, uint8_t *Addr);
+void EMAC_clear_pending(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC, uint32_t EMAC_DMA_IT);
+
+void EMAC_INT_config(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC, uint32_t EMAC_DMA_IT, FlagStatus NewState);
+void EMAC_resume_transmission(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC);
+void EMAC_resume_reception(FM3_ETHERNET_MAC_TypeDef * FM3_ETHERNET_MAC);
+
+#endif // FM3_EMAC_H_INCLUDED

bsp/gd32450z-eval/drivers/gd32f4xx_libopt.h

@@ -20,7 +20,7 @@
 #include "gd32f4xx_dbg.h"
 #include "gd32f4xx_dci.h"
 #include "gd32f4xx_dma.h"
-#include "gd32f4xx_enet.h"
+//#include "gd32f4xx_enet.h"
 #include "gd32f4xx_exmc.h"
 #include "gd32f4xx_exti.h"
 #include "gd32f4xx_fmc.h"

bsp/gd32450z-eval/drivers/synopsys_emac.c

+/*
+ * File      : rthw.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "synopsys_emac.h"
+
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
+extern EMAC_DMADESCTypeDef  *DMATxDescToSet;
+extern EMAC_DMADESCTypeDef  *DMARxDescToGet;
+
+
+/**
+  * Initializes the ETHERNET peripheral according to the specified
+  */
+rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock)
+{
+    rt_uint32_t  value = 0;
+
+    /*-------------------------------- MAC Config ------------------------------*/
+    /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
+    /* Get the ETHERNET MACMIIAR value */
+    value = ETHERNET_MAC->GAR;
+    /* Clear CSR Clock Range CR[2:0] bits */
+    value &= MACMIIAR_CR_MASK;
+
+    /* Get hclk frequency value */
+    /* Set CR bits depending on hclk value */
+    if((SystemCoreClock >= 20000000)&&(SystemCoreClock < 35000000))
+    {
+        /* CSR Clock Range between 20-35 MHz */
+        value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div16;
+    }
+    else if((SystemCoreClock >= 35000000)&&(SystemCoreClock < 60000000))
+    {
+        /* CSR Clock Range between 35-60 MHz */
+        value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div26;
+    }
+    else if((SystemCoreClock >= 60000000)&&(SystemCoreClock <= 100000000))
+    {
+        /* CSR Clock Range between 60-100 MHz */
+        value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div42;
+    }
+    else if((SystemCoreClock >= 100000000)&&(SystemCoreClock <= 150000000))
+    {
+        /* CSR Clock Range between 100-150 MHz */
+        value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div62;
+    }
+    else if((SystemCoreClock >= 150000000)&&(SystemCoreClock <= 250000000))
+    {
+        /* CSR Clock Range between 150-250 MHz */
+        value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div102;
+    }
+    else /* if((SystemCoreClock >= 250000000)&&(SystemCoreClock <= 300000000)) */
+    {
+        /* CSR Clock Range between 250-300 MHz */
+        value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div122;
+    }
+    /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+    ETHERNET_MAC->GAR = (rt_uint32_t)value;
+
+    /*------------------------ ETHERNET MACCR Configuration --------------------*/
+    /* Get the ETHERNET MACCR value */
+    value = ETHERNET_MAC->MCR;
+    /* Clear WD, PCE, PS, TE and RE bits */
+    value &= MACCR_CLEAR_MASK;
+
+    value |= (rt_uint32_t)(EMAC_Watchdog_Enable |
+                        EMAC_Jabber_Enable |
+                        EMAC_InterFrameGap_96Bit |
+                        EMAC_CarrierSense_Enable |
+                        EMAC_Speed_100M |
+                        EMAC_ReceiveOwn_Enable |
+                        EMAC_LoopbackMode_Disable |
+                        EMAC_Mode_FullDuplex |
+                        EMAC_ChecksumOffload_Enable |
+                        EMAC_RetryTransmission_Disable |
+                        EMAC_AutomaticPadCRCStrip_Disable |
+                        EMAC_BackOffLimit_10 |
+                        EMAC_DeferralCheck_Disable);
+
+    /* Write to ETHERNET MACCR */
+    value |= (1<<15);
+    value &= ~(1<<25);
+    value &= ~(1<<24);
+    ETHERNET_MAC->MCR = (rt_uint32_t)value;
+
+    /*----------------------- ETHERNET MACFFR Configuration --------------------*/
+    /* Write to ETHERNET MACFFR */
+    ETHERNET_MAC->MFFR = (rt_uint32_t)(EMAC_ReceiveAll_Enable |
+                                        EMAC_SourceAddrFilter_Disable |
+                                        EMAC_PassControlFrames_BlockAll |
+                                        EMAC_BroadcastFramesReception_Disable |
+                                        EMAC_DestinationAddrFilter_Normal |
+                                        EMAC_PromiscuousMode_Disable |
+                                        EMAC_MulticastFramesFilter_Perfect |
+                                        EMAC_UnicastFramesFilter_Perfect);
+
+    /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+    /* Write to ETHERNET MACHTHR */
+    ETHERNET_MAC->MHTRH = 0;
+    /* Write to ETHERNET MACHTLR */
+    ETHERNET_MAC->MHTRL = 0;
+    /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+    /* Get the ETHERNET MACFCR value */
+    value = ETHERNET_MAC->FCR;
+    /* Clear xx bits */
+    value &= MACFCR_CLEAR_MASK;
+
+    value |= (rt_uint32_t)((0 << 16) |
+                        EMAC_ZeroQuantaPause_Disable |
+                        EMAC_PauseLowThreshold_Minus4 |
+                        EMAC_UnicastPauseFrameDetect_Disable |
+                        EMAC_ReceiveFlowControl_Disable |
+                        EMAC_TransmitFlowControl_Disable);
+
+    /* Write to ETHERNET MACFCR */
+    ETHERNET_MAC->FCR = (rt_uint32_t)value;
+    /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+    ETHERNET_MAC->VTR = (rt_uint32_t)(EMAC_VLANTagComparison_16Bit |
+                                       0);
+
+    /*-------------------------------- DMA Config ------------------------------*/
+    /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
+    /* Get the ETHERNET DMAOMR value */
+    value = ETHERNET_MAC->OMR;
+    /* Clear xx bits */
+    value &= DMAOMR_CLEAR_MASK;
+
+    value |= (rt_uint32_t)(EMAC_DropTCPIPChecksumErrorFrame_Disable |
+                        EMAC_ReceiveStoreForward_Enable |
+                        EMAC_FlushReceivedFrame_Enable |
+                        EMAC_TransmitStoreForward_Enable |
+                        EMAC_TransmitThresholdControl_64Bytes |
+                        EMAC_ForwardErrorFrames_Disable |
+                        EMAC_ForwardUndersizedGoodFrames_Disable |
+                        EMAC_ReceiveThresholdControl_64Bytes |
+                        EMAC_SecondFrameOperate_Disable);
+
+    /* Write to ETHERNET DMAOMR */
+    ETHERNET_MAC->OMR = (rt_uint32_t)value;
+
+    /*----------------------- ETHERNET DMABMR Configuration --------------------*/
+    ETHERNET_MAC->BMR = (rt_uint32_t)(EMAC_AddressAlignedBeats_Enable |
+                                       EMAC_FixedBurst_Enable |
+                                       EMAC_RxDMABurstLength_32Beat | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                                       EMAC_TxDMABurstLength_32Beat |
+                                       (0 << 2) |
+                                       EMAC_DMAArbitration_RoundRobin_RxTx_2_1 |
+                                       EMAC_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+
+    /* Return Ethernet configuration success */
+    return EMAC_SUCCESS;
+}
+
+/**
+  * Enables or disables the specified ETHERNET DMA interrupts.
+  */
+void EMAC_INT_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT, rt_bool_t NewState)
+{
+    if (NewState)
+    {
+        /* Enable the selected ETHERNET DMA interrupts */
+        ETHERNET_MAC->IER |= EMAC_DMA_IT;
+    }
+    else
+    {
+        /* Disable the selected ETHERNET DMA interrupts */
+        ETHERNET_MAC->IER &=(~(rt_uint32_t)EMAC_DMA_IT);
+    }
+}
+
+/**
+  * Configures the selected MAC address.
+  */
+void EMAC_MAC_Addr_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t MacAddr, rt_uint8_t *Addr)
+{
+    rt_uint32_t value;
+
+    /* Calculate the selectecd MAC address high register */
+    value = ((rt_uint32_t)Addr[5] << 8) | (rt_uint32_t)Addr[4];
+    /* Load the selectecd MAC address high register */
+    //(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_HBASE + MacAddr)) = value;
+    ETHERNET_MAC->MARs[MacAddr].MARH = value;
+    /* Calculate the selectecd MAC address low register */
+    value = ((rt_uint32_t)Addr[3] << 24) | ((rt_uint32_t)Addr[2] << 16) | ((rt_uint32_t)Addr[1] << 8) | Addr[0];
+
+    /* Load the selectecd MAC address low register */
+    //(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_LBASE + MacAddr)) = value;
+    ETHERNET_MAC->MARs[MacAddr].MARL = value;
+}
+
+/**
+  * Enables or disables the MAC transmission.
+  */
+void EMAC_MACTransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
+{
+    if (NewState)
+    {
+        /* Enable the MAC transmission */
+        ETHERNET_MAC->MCR |= EMAC_MACCR_TE;
+    }
+    else
+    {
+        /* Disable the MAC transmission */
+        ETHERNET_MAC->MCR &= ~EMAC_MACCR_TE;
+    }
+}
+
+/**
+  * Clears the ETHERNET transmit FIFO.
+  */
+void EMAC_FlushTransmitFIFO(struct rt_synopsys_eth * ETHERNET_MAC)
+{
+    /* Set the Flush Transmit FIFO bit */
+    ETHERNET_MAC->OMR |= EMAC_DMAOMR_FTF;
+}
+
+/**
+  * Enables or disables the MAC reception.
+  */
+void EMAC_MACReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
+{
+    if (NewState)
+    {
+        /* Enable the MAC reception */
+        ETHERNET_MAC->MCR |= EMAC_MACCR_RE;
+    }
+    else
+    {
+        /* Disable the MAC reception */
+        ETHERNET_MAC->MCR &= ~EMAC_MACCR_RE;
+    }
+}
+
+/**
+  * Enables or disables the DMA transmission.
+  */
+void EMAC_DMATransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
+{
+    if (NewState)
+    {
+        /* Enable the DMA transmission */
+        ETHERNET_MAC->OMR |= EMAC_DMAOMR_ST;
+    }
+    else
+    {
+        /* Disable the DMA transmission */
+        ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_ST;
+    }
+}
+
+/**
+  * Enables or disables the DMA reception.
+  */
+void EMAC_DMAReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
+{
+    if (NewState)
+    {
+        /* Enable the DMA reception */
+        ETHERNET_MAC->OMR |= EMAC_DMAOMR_SR;
+    }
+    else
+    {
+        /* Disable the DMA reception */
+        ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_SR;
+    }
+}
+
+/**
+  * Enables ENET MAC and DMA reception/transmission
+  */
+void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC)
+{
+    /* Enable transmit state machine of the MAC for transmission on the MII */
+    EMAC_MACTransmissionCmd(ETHERNET_MAC, RT_TRUE);
+    /* Flush Transmit FIFO */
+    EMAC_FlushTransmitFIFO(ETHERNET_MAC);
+    /* Enable receive state machine of the MAC for reception from the MII */
+    EMAC_MACReceptionCmd(ETHERNET_MAC, RT_TRUE);
+
+    /* Start DMA transmission */
+    EMAC_DMATransmissionCmd(ETHERNET_MAC, RT_TRUE);
+    /* Start DMA reception */
+    EMAC_DMAReceptionCmd(ETHERNET_MAC, RT_TRUE);
+}
+
+/**
+  * Clears the ETHERNET's DMA interrupt pending bit.
+  */
+void EMAC_clear_pending(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t pending)
+{
+    /* Clear the selected ETHERNET DMA IT */
+    ETHERNET_MAC->SR = (rt_uint32_t) pending;
+}
+
+/**
+  * Resumes the DMA Transmission by writing to the DmaRxPollDemand register
+  *   (the data written could be anything). This forces the DMA to resume reception.
+  */
+void EMAC_resume_reception(struct rt_synopsys_eth * ETHERNET_MAC)
+{
+    ETHERNET_MAC->RPDR = 0;
+}
+
+/**
+  * Resumes the DMA Transmission by writing to the DmaTxPollDemand register
+  *   (the data written could be anything). This forces  the DMA to resume transmission.
+  */
+void EMAC_resume_transmission(struct rt_synopsys_eth * ETHERNET_MAC)
+{
+    ETHERNET_MAC->TPDR = 0;
+}
+
+/**
+  * Read a PHY register
+  */
+rt_uint16_t EMAC_PHY_read(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg)
+{
+    rt_uint32_t value = 0;
+    volatile rt_uint32_t timeout = 0;
+
+    /* Get the ETHERNET MACMIIAR value */
+    value = ETHERNET_MAC->GAR;
+    /* Keep only the CSR Clock Range CR[2:0] bits value */
+    value &= ~MACMIIAR_CR_MASK;
+    /* Prepare the MII address register value */
+    value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */
+    value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR);      /* Set the PHY register address */
+    value &= ~EMAC_MACMIIAR_MW;                              /* Set the read mode */
+    value |= EMAC_MACMIIAR_MB;                               /* Set the MII Busy bit */
+    /* Write the result value into the MII Address register */
+    ETHERNET_MAC->GAR = value;
+    /* Check for the Busy flag */
+    do
+    {
+        timeout++;
+        value = ETHERNET_MAC->GAR;
+    }
+    while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_READ_TO));
+    /* Return ERROR in case of timeout */
+    if(timeout == PHY_READ_TO)
+    {
+        return (rt_uint16_t)EMAC_ERROR;
+    }
+
+    /* Return data register value */
+    return (rt_uint16_t)(ETHERNET_MAC->GDR);
+}
+
+/**
+  * Write to a PHY register
+  */
+rt_uint32_t EMAC_PHY_write(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg, rt_uint16_t PHYValue)
+{
+    rt_uint32_t value = 0;
+    volatile rt_uint32_t timeout = 0;
+
+    /* Get the ETHERNET MACMIIAR value */
+    value = ETHERNET_MAC->GAR;
+    /* Keep only the CSR Clock Range CR[2:0] bits value */
+    value &= ~MACMIIAR_CR_MASK;
+    /* Prepare the MII register address value */
+    value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */
+    value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR);      /* Set the PHY register address */
+    value |= EMAC_MACMIIAR_MW;                               /* Set the write mode */
+    value |= EMAC_MACMIIAR_MB;                               /* Set the MII Busy bit */
+    /* Give the value to the MII data register */
+    ETHERNET_MAC->GDR = PHYValue;
+    /* Write the result value into the MII Address register */
+    ETHERNET_MAC->GAR = value;
+    /* Check for the Busy flag */
+    do
+    {
+        timeout++;
+        value = ETHERNET_MAC->GAR;
+    }
+    while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_WRITE_TO));
+    /* Return ERROR in case of timeout */
+    if(timeout == PHY_WRITE_TO)
+    {
+        return EMAC_ERROR;
+    }
+
+    /* Return SUCCESS */
+    return EMAC_SUCCESS;
+}

bsp/gd32450z-eval/drivers/synopsys_emac.h

+/*
+ * File      : rtdef.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __SYNOPSYS_EMAC_H__
+#define __SYNOPSYS_EMAC_H__
+
+#include <rtthread.h>
+     
+
+/******************************************************************************/
+/*                Ethernet MAC Registers bits definitions                     */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define EMAC_MACCR_WD           ((rt_uint32_t)0x00800000)  /* Watchdog disable */
+#define EMAC_MACCR_JD           ((rt_uint32_t)0x00400000)  /* Jabber disable */
+#define EMAC_MACCR_IFG          ((rt_uint32_t)0x000E0000)  /* Inter-frame gap */
+#define EMAC_MACCR_IFG_96Bit    ((rt_uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+#define EMAC_MACCR_IFG_88Bit    ((rt_uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+#define EMAC_MACCR_IFG_80Bit    ((rt_uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+#define EMAC_MACCR_IFG_72Bit    ((rt_uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+#define EMAC_MACCR_IFG_64Bit    ((rt_uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */
+#define EMAC_MACCR_IFG_56Bit    ((rt_uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+#define EMAC_MACCR_IFG_48Bit    ((rt_uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+#define EMAC_MACCR_IFG_40Bit    ((rt_uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */
+#define EMAC_MACCR_CSD          ((rt_uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
+#define EMAC_MACCR_FES          ((rt_uint32_t)0x00004000)  /* Fast ethernet speed */
+#define EMAC_MACCR_ROD          ((rt_uint32_t)0x00002000)  /* Receive own disable */
+#define EMAC_MACCR_LM           ((rt_uint32_t)0x00001000)  /* loopback mode */
+#define EMAC_MACCR_DM           ((rt_uint32_t)0x00000800)  /* Duplex mode */
+#define EMAC_MACCR_IPCO         ((rt_uint32_t)0x00000400)  /* IP Checksum offload */
+#define EMAC_MACCR_RD           ((rt_uint32_t)0x00000200)  /* Retry disable */
+#define EMAC_MACCR_APCS         ((rt_uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
+#define EMAC_MACCR_BL           ((rt_uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+															a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define EMAC_MACCR_BL_10     	((rt_uint32_t)0x00000000)  /* k = min (n, 10) */
+#define EMAC_MACCR_BL_8         ((rt_uint32_t)0x00000020)  /* k = min (n, 8) */
+#define EMAC_MACCR_BL_4         ((rt_uint32_t)0x00000040)  /* k = min (n, 4) */
+#define EMAC_MACCR_BL_1         ((rt_uint32_t)0x00000060)  /* k = min (n, 1) */
+#define EMAC_MACCR_DC           ((rt_uint32_t)0x00000010)  /* Defferal check */
+#define EMAC_MACCR_TE           ((rt_uint32_t)0x00000008)  /* Transmitter enable */
+#define EMAC_MACCR_RE           ((rt_uint32_t)0x00000004)  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define EMAC_MACFFR_RA          ((rt_uint32_t)0x80000000)  /* Receive all */
+#define EMAC_MACFFR_HPF         ((rt_uint32_t)0x00000400)  /* Hash or perfect filter */
+#define EMAC_MACFFR_SAF      	((rt_uint32_t)0x00000200)  /* Source address filter enable */
+#define EMAC_MACFFR_SAIF        ((rt_uint32_t)0x00000100)  /* SA inverse filtering */
+#define EMAC_MACFFR_PCF         ((rt_uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
+#define EMAC_MACFFR_PCF_BlockAll                ((rt_uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+#define EMAC_MACFFR_PCF_ForwardAll              ((rt_uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
+#define EMAC_MACFFR_BFD         ((rt_uint32_t)0x00000020)  /* Broadcast frame disable */
+#define EMAC_MACFFR_PAM       	((rt_uint32_t)0x00000010)  /* Pass all mutlicast */
+#define EMAC_MACFFR_DAIF        ((rt_uint32_t)0x00000008)  /* DA Inverse filtering */
+#define EMAC_MACFFR_HM     	    ((rt_uint32_t)0x00000004)  /* Hash multicast */
+#define EMAC_MACFFR_HU     	    ((rt_uint32_t)0x00000002)  /* Hash unicast */
+#define EMAC_MACFFR_PM     	    ((rt_uint32_t)0x00000001)  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define EMAC_MACHTHR_HTH   	    ((rt_uint32_t)0xFFFFFFFF)  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define EMAC_MACHTLR_HTL  	    ((rt_uint32_t)0xFFFFFFFF)  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define EMAC_MACMIIAR_PA  	    ((rt_uint32_t)0x0000F800)  /* Physical layer address */
+#define EMAC_MACMIIAR_MR 	   	((rt_uint32_t)0x000007C0)  /* MII register in the selected PHY */
+#define EMAC_MACMIIAR_CR 	    ((rt_uint32_t)0x0000001C)  /* CR clock range: 6 cases */
+#define EMAC_MACMIIAR_CR_Div42  ((rt_uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define EMAC_MACMIIAR_CR_Div62  ((rt_uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define EMAC_MACMIIAR_CR_Div16  ((rt_uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define EMAC_MACMIIAR_CR_Div26  ((rt_uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010)  /* HCLK:150-250 MHz; MDC clock= HCLK/102 */
+#define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014)  /* HCLK:250-300 MHz; MDC clock= HCLK/122*/
+#define EMAC_MACMIIAR_MW   	  	((rt_uint32_t)0x00000002)  /* MII write */
+#define EMAC_MACMIIAR_MB   		((rt_uint32_t)0x00000001)  /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define EMAC_MACMIIDR_MD  	 	((rt_uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define EMAC_MACFCR_PT    		((rt_uint32_t)0xFFFF0000)  /* Pause time */
+#define EMAC_MACFCR_ZQPD   		((rt_uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define EMAC_MACFCR_PLT    		((rt_uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+#define EMAC_MACFCR_PLT_Minus4   ((rt_uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+#define EMAC_MACFCR_PLT_Minus28  ((rt_uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+#define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+#define EMAC_MACFCR_PLT_Minus256 ((rt_uint32_t)0x00000030)  /* Pause time minus 256 slot times */
+#define EMAC_MACFCR_UPFD   ((rt_uint32_t)0x00000008)  /* Unicast pause frame detect */
+#define EMAC_MACFCR_RFCE   ((rt_uint32_t)0x00000004)  /* Receive flow control enable */
+#define EMAC_MACFCR_TFCE   ((rt_uint32_t)0x00000002)  /* Transmit flow control enable */
+#define EMAC_MACFCR_FCBBPA ((rt_uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define EMAC_MACVLANTR_VLANTC ((rt_uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
+#define EMAC_MACVLANTR_VLANTI ((rt_uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define EMAC_MACRWUFFR_D   ((rt_uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+   RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define EMAC_MACPMTCSR_WFFRPR ((rt_uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define EMAC_MACPMTCSR_GU     ((rt_uint32_t)0x00000200)  /* Global Unicast */
+#define EMAC_MACPMTCSR_WFR    ((rt_uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define EMAC_MACPMTCSR_MPR    ((rt_uint32_t)0x00000020)  /* Magic Packet Received */
+#define EMAC_MACPMTCSR_WFE    ((rt_uint32_t)0x00000004)  /* Wake-Up Frame Enable */
+#define EMAC_MACPMTCSR_MPE    ((rt_uint32_t)0x00000002)  /* Magic Packet Enable */
+#define EMAC_MACPMTCSR_PD     ((rt_uint32_t)0x00000001)  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define EMAC_MACSR_TSTS      ((rt_uint32_t)0x00000200)  /* Time stamp trigger status */
+#define EMAC_MACSR_MMCTS     ((rt_uint32_t)0x00000040)  /* MMC transmit status */
+#define EMAC_MACSR_MMMCRS    ((rt_uint32_t)0x00000020)  /* MMC receive status */
+#define EMAC_MACSR_MMCS      ((rt_uint32_t)0x00000010)  /* MMC status */
+#define EMAC_MACSR_PMTS      ((rt_uint32_t)0x00000008)  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define EMAC_MACIMR_TSTIM     ((rt_uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
+#define EMAC_MACIMR_PMTIM     ((rt_uint32_t)0x00000008)  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define EMAC_MACA0HR_MACA0H   ((rt_uint32_t)0x0000FFFF)  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define EMAC_MACA0LR_MACA0L   ((rt_uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define EMAC_MACA1HR_AE       ((rt_uint32_t)0x80000000)  /* Address enable */
+#define EMAC_MACA1HR_SA       ((rt_uint32_t)0x40000000)  /* Source address */
+#define EMAC_MACA1HR_MBC      ((rt_uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define EMAC_MACA1HR_MBC_HBits15_8    ((rt_uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define EMAC_MACA1HR_MBC_HBits7_0     ((rt_uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define EMAC_MACA1HR_MBC_LBits31_24   ((rt_uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define EMAC_MACA1HR_MBC_LBits23_16   ((rt_uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define EMAC_MACA1HR_MBC_LBits15_8    ((rt_uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define EMAC_MACA1HR_MBC_LBits7_0     ((rt_uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */
+#define EMAC_MACA1HR_MACA1H   ((rt_uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define EMAC_MACA1LR_MACA1L   ((rt_uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define EMAC_MACA2HR_AE       ((rt_uint32_t)0x80000000)  /* Address enable */
+#define EMAC_MACA2HR_SA       ((rt_uint32_t)0x40000000)  /* Source address */
+#define EMAC_MACA2HR_MBC      ((rt_uint32_t)0x3F000000)  /* Mask byte control */
+#define EMAC_MACA2HR_MBC_HBits15_8    ((rt_uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define EMAC_MACA2HR_MBC_HBits7_0     ((rt_uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define EMAC_MACA2HR_MBC_LBits31_24   ((rt_uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define EMAC_MACA2HR_MBC_LBits23_16   ((rt_uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define EMAC_MACA2HR_MBC_LBits15_8    ((rt_uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define EMAC_MACA2HR_MBC_LBits7_0     ((rt_uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define EMAC_MACA2HR_MACA2H   ((rt_uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define EMAC_MACA2LR_MACA2L   ((rt_uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define EMAC_MACA3HR_AE       ((rt_uint32_t)0x80000000)  /* Address enable */
+#define EMAC_MACA3HR_SA       ((rt_uint32_t)0x40000000)  /* Source address */
+#define EMAC_MACA3HR_MBC      ((rt_uint32_t)0x3F000000)  /* Mask byte control */
+#define EMAC_MACA3HR_MBC_HBits15_8    ((rt_uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define EMAC_MACA3HR_MBC_HBits7_0     ((rt_uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define EMAC_MACA3HR_MBC_LBits31_24   ((rt_uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define EMAC_MACA3HR_MBC_LBits23_16   ((rt_uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define EMAC_MACA3HR_MBC_LBits15_8    ((rt_uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define EMAC_MACA3HR_MBC_LBits7_0     ((rt_uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define EMAC_MACA3HR_MACA3H   ((rt_uint32_t)0x0000FFFF)  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define EMAC_MACA3LR_MACA3L   ((rt_uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define EMAC_MMCCR_MCF        ((rt_uint32_t)0x00000008)  /* MMC Counter Freeze */
+#define EMAC_MMCCR_ROR        ((rt_uint32_t)0x00000004)  /* Reset on Read */
+#define EMAC_MMCCR_CSR        ((rt_uint32_t)0x00000002)  /* Counter Stop Rollover */
+#define EMAC_MMCCR_CR         ((rt_uint32_t)0x00000001)  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define EMAC_MMCRIR_RGUFS     ((rt_uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define EMAC_MMCRIR_RFAES     ((rt_uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define EMAC_MMCRIR_RFCES     ((rt_uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define EMAC_MMCTIR_TGFS      ((rt_uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define EMAC_MMCTIR_TGFMSCS   ((rt_uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define EMAC_MMCTIR_TGFSCS    ((rt_uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define EMAC_MMCRIMR_RGUFM    ((rt_uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define EMAC_MMCRIMR_RFAEM    ((rt_uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define EMAC_MMCRIMR_RFCEM    ((rt_uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define EMAC_MMCTIMR_TGFM     ((rt_uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define EMAC_MMCTIMR_TGFMSCM  ((rt_uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define EMAC_MMCTIMR_TGFSCM   ((rt_uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define EMAC_MMCTGFSCCR_TGFSCC     ((rt_uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define EMAC_MMCTGFMSCCR_TGFMSCC   ((rt_uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define EMAC_MMCTGFCR_TGFC    ((rt_uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define EMAC_MMCRFCECR_RFCEC  ((rt_uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
+#define EMAC_MMCRFAECR_RFAEC  ((rt_uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define EMAC_MMCRGUFCR_RGUFC  ((rt_uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Control Register */
+#define EMAC_PTPTSCR_TSARU    ((rt_uint32_t)0x00000020)  /* Addend register update */
+#define EMAC_PTPTSCR_TSITE    ((rt_uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
+#define EMAC_PTPTSCR_TSSTU    ((rt_uint32_t)0x00000008)  /* Time stamp update */
+#define EMAC_PTPTSCR_TSSTI    ((rt_uint32_t)0x00000004)  /* Time stamp initialize */
+#define EMAC_PTPTSCR_TSFCU    ((rt_uint32_t)0x00000002)  /* Time stamp fine or coarse update */
+#define EMAC_PTPTSCR_TSE      ((rt_uint32_t)0x00000001)  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define EMAC_PTPSSIR_STSSI    ((rt_uint32_t)0x000000FF)  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define EMAC_PTPTSHR_STS      ((rt_uint32_t)0xFFFFFFFF)  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define EMAC_PTPTSLR_STPNS    ((rt_uint32_t)0x80000000)  /* System Time Positive or negative time */
+#define EMAC_PTPTSLR_STSS     ((rt_uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define EMAC_PTPTSHUR_TSUS    ((rt_uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define EMAC_PTPTSLUR_TSUPNS  ((rt_uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
+#define EMAC_PTPTSLUR_TSUSS   ((rt_uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define EMAC_PTPTSAR_TSA      ((rt_uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define EMAC_PTPTTHR_TTSH     ((rt_uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define EMAC_PTPTTLR_TTSL     ((rt_uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define EMAC_DMABMR_AAB       ((rt_uint32_t)0x02000000)  /* Address-Aligned beats */
+#define EMAC_DMABMR_FPM        ((rt_uint32_t)0x01000000)  /* 4xPBL mode */
+#define EMAC_DMABMR_USP       ((rt_uint32_t)0x00800000)  /* Use separate PBL */
+#define EMAC_DMABMR_RDP       ((rt_uint32_t)0x007E0000)  /* RxDMA PBL */
+#define EMAC_DMABMR_RDP_1Beat    ((rt_uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define EMAC_DMABMR_RDP_2Beat    ((rt_uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define EMAC_DMABMR_RDP_4Beat    ((rt_uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define EMAC_DMABMR_RDP_8Beat    ((rt_uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define EMAC_DMABMR_RDP_16Beat   ((rt_uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define EMAC_DMABMR_RDP_32Beat   ((rt_uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define EMAC_DMABMR_RDP_4xPBL_4Beat   ((rt_uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define EMAC_DMABMR_RDP_4xPBL_8Beat   ((rt_uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define EMAC_DMABMR_RDP_4xPBL_16Beat  ((rt_uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define EMAC_DMABMR_RDP_4xPBL_32Beat  ((rt_uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define EMAC_DMABMR_RDP_4xPBL_64Beat  ((rt_uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define EMAC_DMABMR_RDP_4xPBL_128Beat ((rt_uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define EMAC_DMABMR_FB        ((rt_uint32_t)0x00010000)  /* Fixed Burst */
+#define EMAC_DMABMR_RTPR      ((rt_uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_RTPR_1_1     ((rt_uint32_t)0x00000000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_RTPR_2_1     ((rt_uint32_t)0x00004000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_RTPR_3_1     ((rt_uint32_t)0x00008000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_RTPR_4_1     ((rt_uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+#define EMAC_DMABMR_PBL    ((rt_uint32_t)0x00003F00)  /* Programmable burst length */
+#define EMAC_DMABMR_PBL_1Beat    ((rt_uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define EMAC_DMABMR_PBL_2Beat    ((rt_uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define EMAC_DMABMR_PBL_4Beat    ((rt_uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define EMAC_DMABMR_PBL_8Beat    ((rt_uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define EMAC_DMABMR_PBL_16Beat   ((rt_uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define EMAC_DMABMR_PBL_32Beat   ((rt_uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define EMAC_DMABMR_PBL_4xPBL_4Beat   ((rt_uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define EMAC_DMABMR_PBL_4xPBL_8Beat   ((rt_uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define EMAC_DMABMR_PBL_4xPBL_16Beat  ((rt_uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define EMAC_DMABMR_PBL_4xPBL_32Beat  ((rt_uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define EMAC_DMABMR_PBL_4xPBL_64Beat  ((rt_uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define EMAC_DMABMR_PBL_4xPBL_128Beat ((rt_uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define EMAC_DMABMR_EDE       ((rt_uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
+#define EMAC_DMABMR_DSL       ((rt_uint32_t)0x0000007C)  /* Descriptor Skip Length */
+#define EMAC_DMABMR_DA        ((rt_uint32_t)0x00000002)  /* DMA arbitration scheme */
+#define EMAC_DMABMR_SR        ((rt_uint32_t)0x00000001)  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define EMAC_DMATPDR_TPD      ((rt_uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define EMAC_DMARPDR_RPD      ((rt_uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define EMAC_DMARDLAR_SRL     ((rt_uint32_t)0xFFFFFFFF)  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define EMAC_DMATDLAR_STL     ((rt_uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define EMAC_DMASR_TSTS       ((rt_uint32_t)0x20000000)  /* Time-stamp trigger status */
+#define EMAC_DMASR_PMTS       ((rt_uint32_t)0x10000000)  /* PMT status */
+#define EMAC_DMASR_MMCS       ((rt_uint32_t)0x08000000)  /* MMC status */
+#define EMAC_DMASR_EBS        ((rt_uint32_t)0x03800000)  /* Error bits status */
+/* combination with EBS[2:0] for GetFlagStatus function */
+#define EMAC_DMASR_EBS_DescAccess      ((rt_uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+#define EMAC_DMASR_EBS_ReadTransf      ((rt_uint32_t)0x01000000)  /* Error bits 0-write transfer, 1-read transfer */
+#define EMAC_DMASR_EBS_DataTransfTx    ((rt_uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define EMAC_DMASR_TPS         ((rt_uint32_t)0x00700000)  /* Transmit process state */
+#define EMAC_DMASR_TPS_Stopped         ((rt_uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+#define EMAC_DMASR_TPS_Fetching        ((rt_uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+#define EMAC_DMASR_TPS_Waiting         ((rt_uint32_t)0x00200000)  /* Running - waiting for status */
+#define EMAC_DMASR_TPS_Reading         ((rt_uint32_t)0x00300000)  /* Running - reading the data from host memory */
+#define EMAC_DMASR_TPS_Suspended       ((rt_uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailable */
+#define EMAC_DMASR_TPS_Closing         ((rt_uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+#define EMAC_DMASR_RPS         ((rt_uint32_t)0x000E0000)  /* Receive process state */
+#define EMAC_DMASR_RPS_Stopped         ((rt_uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+#define EMAC_DMASR_RPS_Fetching        ((rt_uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+#define EMAC_DMASR_RPS_Waiting         ((rt_uint32_t)0x00060000)  /* Running - waiting for packet */
+#define EMAC_DMASR_RPS_Suspended       ((rt_uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+#define EMAC_DMASR_RPS_Closing         ((rt_uint32_t)0x000A0000)  /* Running - closing descriptor */
+#define EMAC_DMASR_RPS_Queuing         ((rt_uint32_t)0x000E0000)  /* Running - queuing the receive frame into host memory */
+#define EMAC_DMASR_NIS        ((rt_uint32_t)0x00010000)  /* Normal interrupt summary */
+#define EMAC_DMASR_AIS        ((rt_uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define EMAC_DMASR_ERS        ((rt_uint32_t)0x00004000)  /* Early receive status */
+#define EMAC_DMASR_FBES       ((rt_uint32_t)0x00002000)  /* Fatal bus error status */
+#define EMAC_DMASR_ETS        ((rt_uint32_t)0x00000400)  /* Early transmit status */
+#define EMAC_DMASR_RWTS       ((rt_uint32_t)0x00000200)  /* Receive watchdog timeout status */
+#define EMAC_DMASR_RPSS       ((rt_uint32_t)0x00000100)  /* Receive process stopped status */
+#define EMAC_DMASR_RBUS       ((rt_uint32_t)0x00000080)  /* Receive buffer unavailable status */
+#define EMAC_DMASR_RS         ((rt_uint32_t)0x00000040)  /* Receive status */
+#define EMAC_DMASR_TUS        ((rt_uint32_t)0x00000020)  /* Transmit underflow status */
+#define EMAC_DMASR_ROS        ((rt_uint32_t)0x00000010)  /* Receive overflow status */
+#define EMAC_DMASR_TJTS       ((rt_uint32_t)0x00000008)  /* Transmit jabber timeout status */
+#define EMAC_DMASR_TBUS       ((rt_uint32_t)0x00000004)  /* Transmit buffer unavailable status */
+#define EMAC_DMASR_TPSS       ((rt_uint32_t)0x00000002)  /* Transmit process stopped status */
+#define EMAC_DMASR_TS         ((rt_uint32_t)0x00000001)  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define EMAC_DMAOMR_DTCEFD    ((rt_uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define EMAC_DMAOMR_RSF       ((rt_uint32_t)0x02000000)  /* Receive store and forward */
+#define EMAC_DMAOMR_DFRF      ((rt_uint32_t)0x01000000)  /* Disable flushing of received frames */
+#define EMAC_DMAOMR_TSF       ((rt_uint32_t)0x00200000)  /* Transmit store and forward */
+#define EMAC_DMAOMR_FTF       ((rt_uint32_t)0x00100000)  /* Flush transmit FIFO */
+#define EMAC_DMAOMR_TTC       ((rt_uint32_t)0x0001C000)  /* Transmit threshold control */
+#define EMAC_DMAOMR_TTC_64Bytes       ((rt_uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define EMAC_DMAOMR_TTC_128Bytes      ((rt_uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define EMAC_DMAOMR_TTC_192Bytes      ((rt_uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define EMAC_DMAOMR_TTC_256Bytes      ((rt_uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define EMAC_DMAOMR_TTC_40Bytes       ((rt_uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define EMAC_DMAOMR_TTC_32Bytes       ((rt_uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define EMAC_DMAOMR_TTC_24Bytes       ((rt_uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define EMAC_DMAOMR_TTC_16Bytes       ((rt_uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define EMAC_DMAOMR_ST        ((rt_uint32_t)0x00002000)  /* Start/stop transmission command */
+#define EMAC_DMAOMR_FEF       ((rt_uint32_t)0x00000080)  /* Forward error frames */
+#define EMAC_DMAOMR_FUGF      ((rt_uint32_t)0x00000040)  /* Forward undersized good frames */
+#define EMAC_DMAOMR_RTC       ((rt_uint32_t)0x00000018)  /* receive threshold control */
+#define EMAC_DMAOMR_RTC_64Bytes       ((rt_uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define EMAC_DMAOMR_RTC_32Bytes       ((rt_uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define EMAC_DMAOMR_RTC_96Bytes       ((rt_uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define EMAC_DMAOMR_RTC_128Bytes      ((rt_uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define EMAC_DMAOMR_OSF       ((rt_uint32_t)0x00000004)  /* operate on second frame */
+#define EMAC_DMAOMR_SR        ((rt_uint32_t)0x00000002)  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define EMAC_DMAIER_NISE      ((rt_uint32_t)0x00010000)  /* Normal interrupt summary enable */
+#define EMAC_DMAIER_AISE      ((rt_uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
+#define EMAC_DMAIER_ERIE      ((rt_uint32_t)0x00004000)  /* Early receive interrupt enable */
+#define EMAC_DMAIER_FBEIE     ((rt_uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
+#define EMAC_DMAIER_ETIE      ((rt_uint32_t)0x00000400)  /* Early transmit interrupt enable */
+#define EMAC_DMAIER_RWTIE     ((rt_uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define EMAC_DMAIER_RPSIE     ((rt_uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
+#define EMAC_DMAIER_RBUIE     ((rt_uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define EMAC_DMAIER_RIE       ((rt_uint32_t)0x00000040)  /* Receive interrupt enable */
+#define EMAC_DMAIER_TUIE      ((rt_uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
+#define EMAC_DMAIER_ROIE      ((rt_uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
+#define EMAC_DMAIER_TJTIE     ((rt_uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define EMAC_DMAIER_TBUIE     ((rt_uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define EMAC_DMAIER_TPSIE     ((rt_uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
+#define EMAC_DMAIER_TIE       ((rt_uint32_t)0x00000001)  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define EMAC_DMAMFBOCR_OFOC   ((rt_uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define EMAC_DMAMFBOCR_MFA    ((rt_uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
+#define EMAC_DMAMFBOCR_OMFC   ((rt_uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+#define EMAC_DMAMFBOCR_MFC    ((rt_uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define EMAC_DMACHTDR_HTDAP   ((rt_uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define EMAC_DMACHRDR_HRDAP   ((rt_uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define EMAC_DMACHTBAR_HTBAP  ((rt_uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define EMAC_DMACHRBAR_HRBAP  ((rt_uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+
+//typedef enum {
+//	RESET = 0, SET = !RESET
+//} FlagStatus, ITStatus;
+//typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+/**
+ * ETH MAC Init structure definition
+ */
+typedef struct
+{
+	/**
+	 * MAC
+	 */
+	rt_uint32_t             EMAC_AutoNegotiation;           /* Selects or not the AutoNegotiation mode for the external PHY
+															The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+															and the mode (half/full-duplex).
+															This parameter can be a value of @ref EMAC_AutoNegotiation */
+
+	rt_uint32_t             EMAC_Watchdog;                  /* Selects or not the Watchdog timer
+															When enabled, the MAC allows no more then 2048 bytes to be received.
+															When disabled, the MAC can receive up to 16384 bytes.
+															This parameter can be a value of @ref EMAC_watchdog */
+
+	rt_uint32_t             EMAC_Jabber;                    /* Selects or not Jabber timer
+															When enabled, the MAC allows no more then 2048 bytes to be sent.
+															When disabled, the MAC can send up to 16384 bytes.
+															This parameter can be a value of @ref EMAC_Jabber */
+
+	rt_uint32_t             EMAC_InterFrameGap;             /* Selects the minimum IFG between frames during transmission
+															This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
+
+	rt_uint32_t             EMAC_CarrierSense;              /* Selects or not the Carrier Sense
+															This parameter can be a value of @ref EMAC_Carrier_Sense */
+
+	rt_uint32_t             EMAC_Speed;                     /* Sets the Ethernet speed: 10/100 Mbps
+															This parameter can be a value of @ref EMAC_Speed */
+
+	rt_uint32_t             EMAC_ReceiveOwn;                /* Selects or not the ReceiveOwn
+															ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+															in Half-Duplex mode
+															This parameter can be a value of @ref EMAC_Receive_Own */
+
+	rt_uint32_t             EMAC_LoopbackMode;              /* Selects or not the internal MAC MII Loopback mode
+															This parameter can be a value of @ref EMAC_Loop_Back_Mode */
+
+	rt_uint32_t             EMAC_Mode;                      /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+															This parameter can be a value of @ref EMAC_Duplex_Mode */
+
+	rt_uint32_t             EMAC_ChecksumOffload;           /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+															This parameter can be a value of @ref EMAC_Checksum_Offload */
+
+	rt_uint32_t             EMAC_RetryTransmission;         /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
+															when a colision occurs (Half-Duplex mode)
+															This parameter can be a value of @ref EMAC_Retry_Transmission */
+
+	rt_uint32_t             EMAC_AutomaticPadCRCStrip;      /* Selects or not the Automatic MAC Pad/CRC Stripping
+															This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
+
+	rt_uint32_t             EMAC_BackOffLimit;              /* Selects the BackOff limit value
+															This parameter can be a value of @ref EMAC_Back_Off_Limit */
+
+	rt_uint32_t             EMAC_DeferralCheck;             /* Selects or not the deferral check function (Half-Duplex mode)
+															This parameter can be a value of @ref EMAC_Deferral_Check */
+
+	rt_uint32_t             EMAC_ReceiveAll;                /* Selects or not all frames reception by the MAC (No fitering)
+															This parameter can be a value of @ref EMAC_Receive_All */
+
+	rt_uint32_t             EMAC_SourceAddrFilter;          /* Selects the Source Address Filter mode
+															This parameter can be a value of @ref EMAC_Source_Addr_Filter */
+
+	rt_uint32_t             EMAC_PassControlFrames;         /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+															This parameter can be a value of @ref EMAC_Pass_Control_Frames */
+
+	rt_uint32_t             EMAC_BroadcastFramesReception;  /* Selects or not the reception of Broadcast Frames
+															This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
+
+	rt_uint32_t             EMAC_DestinationAddrFilter;     /* Sets the destination filter mode for both unicast and multicast frames
+															This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
+
+	rt_uint32_t             EMAC_PromiscuousMode;           /* Selects or not the Promiscuous Mode
+															This parameter can be a value of @ref EMAC_Promiscuous_Mode */
+
+	rt_uint32_t             EMAC_MulticastFramesFilter;     /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+															This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
+
+	rt_uint32_t             EMAC_UnicastFramesFilter;       /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+															This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
+
+	rt_uint32_t             EMAC_HashTableHigh;             /* This field holds the higher 32 bits of Hash table.  */
+
+	rt_uint32_t             EMAC_HashTableLow;              /* This field holds the lower 32 bits of Hash table.  */
+
+	rt_uint32_t             EMAC_PauseTime;                 /* This field holds the value to be used in the Pause Time field in the
+															transmit control frame */
+
+	rt_uint32_t             EMAC_ZeroQuantaPause;           /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
+															This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
+
+	rt_uint32_t             EMAC_PauseLowThreshold;         /* This field configures the threshold of the PAUSE to be checked for
+															automatic retransmission of PAUSE Frame
+															This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
+
+	rt_uint32_t             EMAC_UnicastPauseFrameDetect;   /* Selects or not the MAC detection of the Pause frames (with MAC Address0
+															unicast address and unique multicast address)
+															This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
+
+	rt_uint32_t             EMAC_ReceiveFlowControl;        /* Enables or disables the MAC to decode the received Pause frame and
+															disable its transmitter for a specified time (Pause Time)
+															This parameter can be a value of @ref EMAC_Receive_Flow_Control */
+
+	rt_uint32_t             EMAC_TransmitFlowControl;       /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+															or the MAC back-pressure operation (Half-Duplex mode)
+															This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
+
+	rt_uint32_t             EMAC_VLANTagComparison;         /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+															comparison and filtering
+															This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
+
+	rt_uint32_t             EMAC_VLANTagIdentifier;         /* Holds the VLAN tag identifier for receive frames */
+
+	/**
+	 * DMA
+	 */
+
+	rt_uint32_t             EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
+															  This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
+
+	rt_uint32_t             EMAC_ReceiveStoreForward;         /* Enables or disables the Receive store and forward mode
+															  This parameter can be a value of @ref EMAC_Receive_Store_Forward */
+
+	rt_uint32_t             EMAC_FlushReceivedFrame;          /* Enables or disables the flushing of received frames
+															  This parameter can be a value of @ref EMAC_Flush_Received_Frame */
+
+	rt_uint32_t             EMAC_TransmitStoreForward;        /* Enables or disables Transmit store and forward mode
+															  This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
+
+	rt_uint32_t             EMAC_TransmitThresholdControl;    /* Selects or not the Transmit Threshold Control
+															  This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
+
+	rt_uint32_t             EMAC_ForwardErrorFrames;          /* Selects or not the forward to the DMA of erroneous frames
+															  This parameter can be a value of @ref EMAC_Forward_Error_Frames */
+
+	rt_uint32_t             EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+															  and length less than 64 bytes) including pad-bytes and CRC)
+															  This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
+
+	rt_uint32_t             EMAC_ReceiveThresholdControl;     /* Selects the threshold level of the Receive FIFO
+															  This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
+
+	rt_uint32_t             EMAC_SecondFrameOperate;          /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
+															  frame of Transmit data even before obtaining the status for the first frame.
+															  This parameter can be a value of @ref EMAC_Second_Frame_Operate */
+
+	rt_uint32_t             EMAC_AddressAlignedBeats;         /* Enables or disables the Address Aligned Beats
+															  This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
+
+	rt_uint32_t             EMAC_FixedBurst;                  /* Enables or disables the AHB Master interface fixed burst transfers
+															  This parameter can be a value of @ref EMAC_Fixed_Burst */
+
+	rt_uint32_t             EMAC_RxDMABurstLength;            /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+															  This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
+
+	rt_uint32_t             EMAC_TxDMABurstLength;            /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+															  This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
+
+	rt_uint32_t             EMAC_DescriptorSkipLength;        /* Specifies the number of word to skip between two unchained int (Ring mode) */
+
+	rt_uint32_t             EMAC_DMAArbitration;              /* Selects the DMA Tx/Rx arbitration
+															  This parameter can be a value of @ref EMAC_DMA_Arbitration */
+} EMAC_InitTypeDef;
+
+/**--------------------------------------------------------------------------**/
+/**
+ *                            DMA int types
+ */
+/**--------------------------------------------------------------------------**/
+
+/**
+ * ETH DMA Descriptors data structure definition
+ */
+typedef struct
+{
+	rt_uint32_t   Status;                /* Status */
+	rt_uint32_t   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
+	rt_uint32_t   Buffer1Addr;           /* Buffer1 address pointer */
+	rt_uint32_t   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
+} EMAC_DMADESCTypeDef;
+
+/**--------------------------------------------------------------------------**/
+/**
+ *                           ETH Frames defines
+ */
+/**--------------------------------------------------------------------------**/
+
+#define EMAC_MAX_PACKET_SIZE    	1520    /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
+#define EMAC_HEADER               	14    	/* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define EMAC_CRC                   	4    	/* Ethernet CRC */
+#define EMAC_EXTRA                 	2    	/* Extra bytes in some cases */
+#define VLAN_TAG                  	4    	/* optional 802.1q VLAN Tag */
+#define MIN_EMAC_PAYLOAD          	46    	/* Minimum Ethernet payload size */
+#define MAX_EMAC_PAYLOAD        	1500    /* Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD    		9000    /* Jumbo frame payload size */
+
+/**--------------------------------------------------------------------------**/
+/**
+ *                  Ethernet DMA int registers bits definition
+ */
+/**--------------------------------------------------------------------------**/
+
+#define EMAC_DMATxDesc_OWN                     ((rt_uint32_t)0x80000000)  /* OWN bit: descriptor is owned by DMA engine */
+#define EMAC_DMATxDesc_IC                      ((rt_uint32_t)0x40000000)  /* Interrupt on Completion */
+#define EMAC_DMATxDesc_LS                      ((rt_uint32_t)0x20000000)  /* Last Segment */
+#define EMAC_DMATxDesc_FS                      ((rt_uint32_t)0x10000000)  /* First Segment */
+#define EMAC_DMATxDesc_DC                      ((rt_uint32_t)0x08000000)  /* Disable CRC */
+#define EMAC_DMATxDesc_DP                      ((rt_uint32_t)0x04000000)  /* Disable Padding */
+#define EMAC_DMATxDesc_TTSE                    ((rt_uint32_t)0x02000000)  /* Transmit Time Stamp Enable */
+#define EMAC_DMATxDesc_CIC                     ((rt_uint32_t)0x00C00000)  /* Checksum Insertion Control: 4 cases */
+#define EMAC_DMATxDesc_CIC_ByPass              ((rt_uint32_t)0x00000000)  /* Do Nothing: Checksum Engine is bypassed */
+#define EMAC_DMATxDesc_CIC_IPV4Header          ((rt_uint32_t)0x00400000)  /* IPV4 header Checksum Insertion */
+#define EMAC_DMATxDesc_CIC_TCPUDPICMP_Segment  ((rt_uint32_t)0x00800000)  /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define EMAC_DMATxDesc_CIC_TCPUDPICMP_Full     ((rt_uint32_t)0x00C00000)  /* TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define EMAC_DMATxDesc_TER                     ((rt_uint32_t)0x00200000)  /* Transmit End of Ring */
+#define EMAC_DMATxDesc_TCH                     ((rt_uint32_t)0x00100000)  /* Second Address Chained */
+#define EMAC_DMATxDesc_TTSS                    ((rt_uint32_t)0x00020000)  /* Tx Time Stamp Status */
+#define EMAC_DMATxDesc_IHE                     ((rt_uint32_t)0x00010000)  /* IP Header Error */
+#define EMAC_DMATxDesc_ES                      ((rt_uint32_t)0x00008000)  /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define EMAC_DMATxDesc_JT                      ((rt_uint32_t)0x00004000)  /* Jabber Timeout */
+#define EMAC_DMATxDesc_FF                      ((rt_uint32_t)0x00002000)  /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define EMAC_DMATxDesc_PCE                     ((rt_uint32_t)0x00001000)  /* Payload Checksum Error */
+#define EMAC_DMATxDesc_LCA                     ((rt_uint32_t)0x00000800)  /* Loss of Carrier: carrier lost during transmission */
+#define EMAC_DMATxDesc_NC                      ((rt_uint32_t)0x00000400)  /* No Carrier: no carrier signal from the transceiver */
+#define EMAC_DMATxDesc_LCO                     ((rt_uint32_t)0x00000200)  /* Late Collision: transmission aborted due to collision */
+#define EMAC_DMATxDesc_EC                      ((rt_uint32_t)0x00000100)  /* Excessive Collision: transmission aborted after 16 collisions */
+#define EMAC_DMATxDesc_VF                      ((rt_uint32_t)0x00000080)  /* VLAN Frame */
+#define EMAC_DMATxDesc_CC                      ((rt_uint32_t)0x00000078)  /* Collision Count */
+#define EMAC_DMATxDesc_ED                      ((rt_uint32_t)0x00000004)  /* Excessive Deferral */
+#define EMAC_DMATxDesc_UF                      ((rt_uint32_t)0x00000002)  /* Underflow Error: late data arrival from the memory */
+#define EMAC_DMATxDesc_DB                      ((rt_uint32_t)0x00000001)  /* Deferred Bit */
+
+#define EMAC_DMATxDesc_TBS2  ((rt_uint32_t)0x1FFF0000)  /* Transmit Buffer2 Size */
+#define EMAC_DMATxDesc_TBS1  ((rt_uint32_t)0x00001FFF)  /* Transmit Buffer1 Size */
+
+#define EMAC_DMATxDesc_B1AP  ((rt_uint32_t)0xFFFFFFFF)  /* Buffer1 Address Pointer */
+
+#define EMAC_DMATxDesc_B2AP  ((rt_uint32_t)0xFFFFFFFF)  /* Buffer2 Address Pointer */
+
+#define EMAC_DMARxDesc_OWN         ((rt_uint32_t)0x80000000)  /* OWN bit: descriptor is owned by DMA engine  */
+#define EMAC_DMARxDesc_AFM         ((rt_uint32_t)0x40000000)  /* DA Filter Fail for the rx frame  */
+#define EMAC_DMARxDesc_FL          ((rt_uint32_t)0x3FFF0000)  /* Receive descriptor frame length  */
+#define EMAC_DMARxDesc_ES          ((rt_uint32_t)0x00008000)  /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define EMAC_DMARxDesc_DE          ((rt_uint32_t)0x00004000)  /* Descriptor error: no more int for receive frame  */
+#define EMAC_DMARxDesc_SAF         ((rt_uint32_t)0x00002000)  /* SA Filter Fail for the received frame */
+#define EMAC_DMARxDesc_LE          ((rt_uint32_t)0x00001000)  /* Frame size not matching with length field */
+#define EMAC_DMARxDesc_OE          ((rt_uint32_t)0x00000800)  /* Overflow Error: Frame was damaged due to buffer overflow */
+#define EMAC_DMARxDesc_VLAN        ((rt_uint32_t)0x00000400)  /* VLAN Tag: received frame is a VLAN frame */
+#define EMAC_DMARxDesc_FS          ((rt_uint32_t)0x00000200)  /* First descriptor of the frame  */
+#define EMAC_DMARxDesc_LS          ((rt_uint32_t)0x00000100)  /* Last descriptor of the frame  */
+#define EMAC_DMARxDesc_IPV4HCE     ((rt_uint32_t)0x00000080)  /* IPC Checksum Error: Rx Ipv4 header checksum error   */
+#define EMAC_DMARxDesc_LC          ((rt_uint32_t)0x00000040)  /* Late collision occurred during reception   */
+#define EMAC_DMARxDesc_FT          ((rt_uint32_t)0x00000020)  /* Frame type - Ethernet, otherwise 802.3    */
+#define EMAC_DMARxDesc_RWT         ((rt_uint32_t)0x00000010)  /* Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define EMAC_DMARxDesc_RE          ((rt_uint32_t)0x00000008)  /* Receive error: error reported by MII interface  */
+#define EMAC_DMARxDesc_DBE         ((rt_uint32_t)0x00000004)  /* Dribble bit error: frame contains non int multiple of 8 bits  */
+#define EMAC_DMARxDesc_CE          ((rt_uint32_t)0x00000002)  /* CRC error */
+#define EMAC_DMARxDesc_MAMPCE      ((rt_uint32_t)0x00000001)  /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+#define EMAC_DMARxDesc_DIC   ((rt_uint32_t)0x80000000)  /* Disable Interrupt on Completion */
+#define EMAC_DMARxDesc_RBS2  ((rt_uint32_t)0x1FFF0000)  /* Receive Buffer2 Size */
+#define EMAC_DMARxDesc_RER   ((rt_uint32_t)0x00008000)  /* Receive End of Ring */
+#define EMAC_DMARxDesc_RCH   ((rt_uint32_t)0x00004000)  /* Second Address Chained */
+#define EMAC_DMARxDesc_RBS1  ((rt_uint32_t)0x00001FFF)  /* Receive Buffer1 Size */
+
+#define EMAC_DMARxDesc_B1AP  ((rt_uint32_t)0xFFFFFFFF)  /* Buffer1 Address Pointer */
+
+#define EMAC_DMARxDesc_B2AP  ((rt_uint32_t)0xFFFFFFFF)  /* Buffer2 Address Pointer */
+
+#define PHY_READ_TO                     ((rt_uint32_t)0x0004FFFF)
+#define PHY_WRITE_TO                    ((rt_uint32_t)0x0004FFFF)
+
+#define PHY_ResetDelay                  ((rt_uint32_t)0x000FFFFF)
+
+#define PHY_ConfigDelay                 ((rt_uint32_t)0x00FFFFFF)
+
+#define PHY_BCR                          0          /* Tranceiver Basic Control Register */
+#define PHY_BSR                          1          /* Tranceiver Basic Status Register */
+
+#define PHY_Reset                       ((rt_uint16_t)0x8000)      /* PHY Reset */
+//#define PHY_Loopback                    ((rt_uint16_t)0x4000)      /* Select loop-back mode */
+//#define PHY_FULLDUPLEX_100M             ((rt_uint16_t)0x2100)      /* Set the full-duplex mode at 100 Mb/s */
+//#define PHY_HALFDUPLEX_100M             ((rt_uint16_t)0x2000)      /* Set the half-duplex mode at 100 Mb/s */
+//#define PHY_FULLDUPLEX_10M              ((rt_uint16_t)0x0100)      /* Set the full-duplex mode at 10 Mb/s */
+//#define PHY_HALFDUPLEX_10M              ((rt_uint16_t)0x0000)      /* Set the half-duplex mode at 10 Mb/s */
+//#define PHY_AutoNegotiation             ((rt_uint16_t)0x1000)      /* Enable auto-negotiation function */
+//#define PHY_Restart_AutoNegotiation     ((rt_uint16_t)0x0200)      /* Restart auto-negotiation function */
+//#define PHY_Powerdown                   ((rt_uint16_t)0x0800)      /* Select the power down mode */
+//#define PHY_Isolate                     ((rt_uint16_t)0x0400)      /* Isolate PHY from MII */
+//
+//#define PHY_AutoNego_Complete           ((rt_uint16_t)0x0020)      /* Auto-Negotiation process completed */
+//#define PHY_Linked_Status               ((rt_uint16_t)0x0004)      /* Valid link established */
+//#define PHY_Jabber_detection            ((rt_uint16_t)0x0002)      /* Jabber condition detected */
+//
+//#define PHY_SR                           16     /* Transceiver Status Register */
+//
+//#define PHY_Speed_Status            ((rt_uint16_t)0x0002)    /* Configured information of Speed: 10Mbps */
+//#define PHY_Duplex_Status           ((rt_uint16_t)0x0004)    /* Configured information of Duplex: Full-duplex */
+
+#define EMAC_AutoNegotiation_Enable     ((rt_uint32_t)0x00000001)
+#define EMAC_AutoNegotiation_Disable    ((rt_uint32_t)0x00000000)
+
+#define EMAC_Watchdog_Enable       ((rt_uint32_t)0x00000000)
+#define EMAC_Watchdog_Disable      ((rt_uint32_t)0x00800000)
+
+#define EMAC_Jabber_Enable    ((rt_uint32_t)0x00000000)
+#define EMAC_Jabber_Disable   ((rt_uint32_t)0x00400000)
+
+#define EMAC_InterFrameGap_96Bit   ((rt_uint32_t)0x00000000)  /* minimum IFG between frames during transmission is 96Bit */
+#define EMAC_InterFrameGap_88Bit   ((rt_uint32_t)0x00020000)  /* minimum IFG between frames during transmission is 88Bit */
+#define EMAC_InterFrameGap_80Bit   ((rt_uint32_t)0x00040000)  /* minimum IFG between frames during transmission is 80Bit */
+#define EMAC_InterFrameGap_72Bit   ((rt_uint32_t)0x00060000)  /* minimum IFG between frames during transmission is 72Bit */
+#define EMAC_InterFrameGap_64Bit   ((rt_uint32_t)0x00080000)  /* minimum IFG between frames during transmission is 64Bit */
+#define EMAC_InterFrameGap_56Bit   ((rt_uint32_t)0x000A0000)  /* minimum IFG between frames during transmission is 56Bit */
+#define EMAC_InterFrameGap_48Bit   ((rt_uint32_t)0x000C0000)  /* minimum IFG between frames during transmission is 48Bit */
+#define EMAC_InterFrameGap_40Bit   ((rt_uint32_t)0x000E0000)  /* minimum IFG between frames during transmission is 40Bit */
+
+#define EMAC_CarrierSense_Enable   ((rt_uint32_t)0x00000000)
+#define EMAC_CarrierSense_Disable  ((rt_uint32_t)0x00010000)
+
+#define EMAC_Speed_10M        ((rt_uint32_t)0x00000000)
+#define EMAC_Speed_100M       ((rt_uint32_t)0x00004000)
+
+#define EMAC_ReceiveOwn_Enable     ((rt_uint32_t)0x00000000)
+#define EMAC_ReceiveOwn_Disable    ((rt_uint32_t)0x00002000)
+
+#define EMAC_LoopbackMode_Enable        ((rt_uint32_t)0x00001000)
+#define EMAC_LoopbackMode_Disable       ((rt_uint32_t)0x00000000)
+
+#define EMAC_Mode_FullDuplex       ((rt_uint32_t)0x00000800)
+#define EMAC_Mode_HalfDuplex       ((rt_uint32_t)0x00000000)
+
+#define EMAC_ChecksumOffload_Enable     ((rt_uint32_t)0x00000400)
+#define EMAC_ChecksumOffload_Disable    ((rt_uint32_t)0x00000000)
+
+#define EMAC_RetryTransmission_Enable   ((rt_uint32_t)0x00000000)
+#define EMAC_RetryTransmission_Disable  ((rt_uint32_t)0x00000200)
+
+#define EMAC_AutomaticPadCRCStrip_Enable     ((rt_uint32_t)0x00000080)
+#define EMAC_AutomaticPadCRCStrip_Disable    ((rt_uint32_t)0x00000000)
+
+#define EMAC_BackOffLimit_10  ((rt_uint32_t)0x00000000)
+#define EMAC_BackOffLimit_8   ((rt_uint32_t)0x00000020)
+#define EMAC_BackOffLimit_4   ((rt_uint32_t)0x00000040)
+#define EMAC_BackOffLimit_1   ((rt_uint32_t)0x00000060)
+
+#define EMAC_DeferralCheck_Enable       ((rt_uint32_t)0x00000010)
+#define EMAC_DeferralCheck_Disable      ((rt_uint32_t)0x00000000)
+
+#define EMAC_ReceiveAll_Enable     ((rt_uint32_t)0x80000000)
+#define EMAC_ReceiveAll_Disable    ((rt_uint32_t)0x00000000)
+
+#define EMAC_SourceAddrFilter_Normal_Enable       ((rt_uint32_t)0x00000200)
+#define EMAC_SourceAddrFilter_Inverse_Enable      ((rt_uint32_t)0x00000300)
+#define EMAC_SourceAddrFilter_Disable             ((rt_uint32_t)0x00000000)
+
+#define EMAC_PassControlFrames_BlockAll                ((rt_uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+#define EMAC_PassControlFrames_ForwardAll              ((rt_uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define EMAC_PassControlFrames_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
+
+#define EMAC_BroadcastFramesReception_Enable      ((rt_uint32_t)0x00000000)
+#define EMAC_BroadcastFramesReception_Disable     ((rt_uint32_t)0x00000020)
+
+#define EMAC_DestinationAddrFilter_Normal    ((rt_uint32_t)0x00000000)
+#define EMAC_DestinationAddrFilter_Inverse   ((rt_uint32_t)0x00000008)
+
+#define EMAC_PromiscuousMode_Enable     ((rt_uint32_t)0x00000001)
+#define EMAC_PromiscuousMode_Disable    ((rt_uint32_t)0x00000000)
+
+#define EMAC_MulticastFramesFilter_PerfectHashTable    ((rt_uint32_t)0x00000404)
+#define EMAC_MulticastFramesFilter_HashTable           ((rt_uint32_t)0x00000004)
+#define EMAC_MulticastFramesFilter_Perfect             ((rt_uint32_t)0x00000000)
+#define EMAC_MulticastFramesFilter_None                ((rt_uint32_t)0x00000010)
+
+#define EMAC_UnicastFramesFilter_PerfectHashTable ((rt_uint32_t)0x00000402)
+#define EMAC_UnicastFramesFilter_HashTable        ((rt_uint32_t)0x00000002)
+#define EMAC_UnicastFramesFilter_Perfect          ((rt_uint32_t)0x00000000)
+
+#define EMAC_ZeroQuantaPause_Enable     ((rt_uint32_t)0x00000000)
+#define EMAC_ZeroQuantaPause_Disable    ((rt_uint32_t)0x00000080)
+
+#define EMAC_PauseLowThreshold_Minus4        ((rt_uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+#define EMAC_PauseLowThreshold_Minus28       ((rt_uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+#define EMAC_PauseLowThreshold_Minus144      ((rt_uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+#define EMAC_PauseLowThreshold_Minus256      ((rt_uint32_t)0x00000030)  /* Pause time minus 256 slot times */
+
+#define EMAC_UnicastPauseFrameDetect_Enable  ((rt_uint32_t)0x00000008)
+#define EMAC_UnicastPauseFrameDetect_Disable ((rt_uint32_t)0x00000000)
+
+#define EMAC_ReceiveFlowControl_Enable       ((rt_uint32_t)0x00000004)
+#define EMAC_ReceiveFlowControl_Disable      ((rt_uint32_t)0x00000000)
+#define EMAC_TransmitFlowControl_Enable      ((rt_uint32_t)0x00000002)
+#define EMAC_TransmitFlowControl_Disable     ((rt_uint32_t)0x00000000)
+
+#define EMAC_VLANTagComparison_12Bit    ((rt_uint32_t)0x00010000)
+#define EMAC_VLANTagComparison_16Bit    ((rt_uint32_t)0x00000000)
+
+#define EMAC_MAC_FLAG_TST     ((rt_uint32_t)0x00000200)  /* Time stamp trigger flag (on MAC) */
+#define EMAC_MAC_FLAG_MMCT    ((rt_uint32_t)0x00000040)  /* MMC transmit flag  */
+#define EMAC_MAC_FLAG_MMCR    ((rt_uint32_t)0x00000020)  /* MMC receive flag */
+#define EMAC_MAC_FLAG_MMC     ((rt_uint32_t)0x00000010)  /* MMC flag (on MAC) */
+#define EMAC_MAC_FLAG_PMT     ((rt_uint32_t)0x00000008)  /* PMT flag (on MAC) */
+
+#define EMAC_MAC_IT_TST       ((rt_uint32_t)0x00000200)  /* Time stamp trigger interrupt (on MAC) */
+#define EMAC_MAC_IT_MMCT      ((rt_uint32_t)0x00000040)  /* MMC transmit interrupt */
+#define EMAC_MAC_IT_MMCR      ((rt_uint32_t)0x00000020)  /* MMC receive interrupt */
+#define EMAC_MAC_IT_MMC       ((rt_uint32_t)0x00000010)  /* MMC interrupt (on MAC) */
+#define EMAC_MAC_IT_PMT       ((rt_uint32_t)0x00000008)  /* PMT interrupt (on MAC) */
+
+#define EMAC_MAC_Address0     ((rt_uint32_t)0x00000000)
+#define EMAC_MAC_Address1     ((rt_uint32_t)0x00000008)
+#define EMAC_MAC_Address2     ((rt_uint32_t)0x00000010)
+#define EMAC_MAC_Address3     ((rt_uint32_t)0x00000018)
+
+#define EMAC_MAC_AddressFilter_SA       ((rt_uint32_t)0x00000000)
+#define EMAC_MAC_AddressFilter_DA       ((rt_uint32_t)0x00000008)
+
+#define EMAC_MAC_AddressMask_Byte6      ((rt_uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define EMAC_MAC_AddressMask_Byte5      ((rt_uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define EMAC_MAC_AddressMask_Byte4      ((rt_uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define EMAC_MAC_AddressMask_Byte3      ((rt_uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define EMAC_MAC_AddressMask_Byte2      ((rt_uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define EMAC_MAC_AddressMask_Byte1      ((rt_uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+
+#define EMAC_DMATxDesc_LastSegment      ((rt_uint32_t)0x40000000)  /* Last Segment */
+#define EMAC_DMATxDesc_FirstSegment     ((rt_uint32_t)0x20000000)  /* First Segment */
+
+#define EMAC_DMATxDesc_ChecksumByPass             ((rt_uint32_t)0x00000000)   /* Checksum engine bypass */
+#define EMAC_DMATxDesc_ChecksumIPV4Header         ((rt_uint32_t)0x00400000)   /* IPv4 header checksum insertion  */
+#define EMAC_DMATxDesc_ChecksumTCPUDPICMPSegment  ((rt_uint32_t)0x00800000)   /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define EMAC_DMATxDesc_ChecksumTCPUDPICMPFull     ((rt_uint32_t)0x00C00000)   /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+
+#define EMAC_DMARxDesc_Buffer1     ((rt_uint32_t)0x00000000)  /* DMA Rx Desc Buffer1 */
+#define EMAC_DMARxDesc_Buffer2     ((rt_uint32_t)0x00000001)  /* DMA Rx Desc Buffer2 */
+
+#define EMAC_DropTCPIPChecksumErrorFrame_Enable   ((rt_uint32_t)0x00000000)
+#define EMAC_DropTCPIPChecksumErrorFrame_Disable  ((rt_uint32_t)0x04000000)
+
+#define EMAC_ReceiveStoreForward_Enable      ((rt_uint32_t)0x02000000)
+#define EMAC_ReceiveStoreForward_Disable     ((rt_uint32_t)0x00000000)
+
+#define EMAC_FlushReceivedFrame_Enable       ((rt_uint32_t)0x00000000)
+#define EMAC_FlushReceivedFrame_Disable      ((rt_uint32_t)0x01000000)
+
+#define EMAC_TransmitStoreForward_Enable     ((rt_uint32_t)0x00200000)
+#define EMAC_TransmitStoreForward_Disable    ((rt_uint32_t)0x00000000)
+
+#define EMAC_TransmitThresholdControl_64Bytes     ((rt_uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define EMAC_TransmitThresholdControl_128Bytes    ((rt_uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define EMAC_TransmitThresholdControl_192Bytes    ((rt_uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define EMAC_TransmitThresholdControl_256Bytes    ((rt_uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define EMAC_TransmitThresholdControl_40Bytes     ((rt_uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define EMAC_TransmitThresholdControl_32Bytes     ((rt_uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define EMAC_TransmitThresholdControl_24Bytes     ((rt_uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define EMAC_TransmitThresholdControl_16Bytes     ((rt_uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+
+#define EMAC_ForwardErrorFrames_Enable       ((rt_uint32_t)0x00000080)
+#define EMAC_ForwardErrorFrames_Disable      ((rt_uint32_t)0x00000000)
+
+#define EMAC_ForwardUndersizedGoodFrames_Enable   ((rt_uint32_t)0x00000040)
+#define EMAC_ForwardUndersizedGoodFrames_Disable  ((rt_uint32_t)0x00000000)
+
+#define EMAC_ReceiveThresholdControl_64Bytes      ((rt_uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define EMAC_ReceiveThresholdControl_32Bytes      ((rt_uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define EMAC_ReceiveThresholdControl_96Bytes      ((rt_uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define EMAC_ReceiveThresholdControl_128Bytes     ((rt_uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+
+#define EMAC_SecondFrameOperate_Enable       ((rt_uint32_t)0x00000004)
+#define EMAC_SecondFrameOperate_Disable      ((rt_uint32_t)0x00000000)
+
+#define EMAC_AddressAlignedBeats_Enable      ((rt_uint32_t)0x02000000)
+#define EMAC_AddressAlignedBeats_Disable     ((rt_uint32_t)0x00000000)
+
+#define EMAC_FixedBurst_Enable     ((rt_uint32_t)0x00010000)
+#define EMAC_FixedBurst_Disable    ((rt_uint32_t)0x00000000)
+
+#define EMAC_RxDMABurstLength_1Beat          ((rt_uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define EMAC_RxDMABurstLength_2Beat          ((rt_uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define EMAC_RxDMABurstLength_4Beat          ((rt_uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define EMAC_RxDMABurstLength_8Beat          ((rt_uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define EMAC_RxDMABurstLength_16Beat         ((rt_uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define EMAC_RxDMABurstLength_32Beat         ((rt_uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define EMAC_RxDMABurstLength_4xPBL_4Beat    ((rt_uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define EMAC_RxDMABurstLength_4xPBL_8Beat    ((rt_uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define EMAC_RxDMABurstLength_4xPBL_16Beat   ((rt_uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define EMAC_RxDMABurstLength_4xPBL_32Beat   ((rt_uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define EMAC_RxDMABurstLength_4xPBL_64Beat   ((rt_uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define EMAC_RxDMABurstLength_4xPBL_128Beat  ((rt_uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+#define EMAC_TxDMABurstLength_1Beat          ((rt_uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define EMAC_TxDMABurstLength_2Beat          ((rt_uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define EMAC_TxDMABurstLength_4Beat          ((rt_uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define EMAC_TxDMABurstLength_8Beat          ((rt_uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define EMAC_TxDMABurstLength_16Beat         ((rt_uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define EMAC_TxDMABurstLength_32Beat         ((rt_uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define EMAC_TxDMABurstLength_4xPBL_4Beat    ((rt_uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define EMAC_TxDMABurstLength_4xPBL_8Beat    ((rt_uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define EMAC_TxDMABurstLength_4xPBL_16Beat   ((rt_uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define EMAC_TxDMABurstLength_4xPBL_32Beat   ((rt_uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define EMAC_TxDMABurstLength_4xPBL_64Beat   ((rt_uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define EMAC_TxDMABurstLength_4xPBL_128Beat  ((rt_uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+#define EMAC_DMAArbitration_RoundRobin_RxTx_1_1   ((rt_uint32_t)0x00000000)
+#define EMAC_DMAArbitration_RoundRobin_RxTx_2_1   ((rt_uint32_t)0x00004000)
+#define EMAC_DMAArbitration_RoundRobin_RxTx_3_1   ((rt_uint32_t)0x00008000)
+#define EMAC_DMAArbitration_RoundRobin_RxTx_4_1   ((rt_uint32_t)0x0000C000)
+#define EMAC_DMAArbitration_RxPriorTx             ((rt_uint32_t)0x00000002)
+
+#define EMAC_DMA_FLAG_TST               ((rt_uint32_t)0x20000000)  /* Time-stamp trigger interrupt (on DMA) */
+#define EMAC_DMA_FLAG_PMT               ((rt_uint32_t)0x10000000)  /* PMT interrupt (on DMA) */
+#define EMAC_DMA_FLAG_MMC               ((rt_uint32_t)0x08000000)  /* MMC interrupt (on DMA) */
+#define EMAC_DMA_FLAG_DataTransferError ((rt_uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define EMAC_DMA_FLAG_ReadWriteError    ((rt_uint32_t)0x01000000)  /* Error bits 0-write transfer, 1-read transfer */
+#define EMAC_DMA_FLAG_AccessError       ((rt_uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+#define EMAC_DMA_FLAG_NIS               ((rt_uint32_t)0x00010000)  /* Normal interrupt summary flag */
+#define EMAC_DMA_FLAG_AIS               ((rt_uint32_t)0x00008000)  /* Abnormal interrupt summary flag */
+#define EMAC_DMA_FLAG_ER                ((rt_uint32_t)0x00004000)  /* Early receive flag */
+#define EMAC_DMA_FLAG_FBE               ((rt_uint32_t)0x00002000)  /* Fatal bus error flag */
+#define EMAC_DMA_FLAG_ET                ((rt_uint32_t)0x00000400)  /* Early transmit flag */
+#define EMAC_DMA_FLAG_RWT               ((rt_uint32_t)0x00000200)  /* Receive watchdog timeout flag */
+#define EMAC_DMA_FLAG_RPS               ((rt_uint32_t)0x00000100)  /* Receive process stopped flag */
+#define EMAC_DMA_FLAG_RBU               ((rt_uint32_t)0x00000080)  /* Receive buffer unavailable flag */
+#define EMAC_DMA_FLAG_R                 ((rt_uint32_t)0x00000040)  /* Receive flag */
+#define EMAC_DMA_FLAG_TU                ((rt_uint32_t)0x00000020)  /* Underflow flag */
+#define EMAC_DMA_FLAG_RO                ((rt_uint32_t)0x00000010)  /* Overflow flag */
+#define EMAC_DMA_FLAG_TJT               ((rt_uint32_t)0x00000008)  /* Transmit jabber timeout flag */
+#define EMAC_DMA_FLAG_TBU               ((rt_uint32_t)0x00000004)  /* Transmit buffer unavailable flag */
+#define EMAC_DMA_FLAG_TPS               ((rt_uint32_t)0x00000002)  /* Transmit process stopped flag */
+#define EMAC_DMA_FLAG_T                 ((rt_uint32_t)0x00000001)  /* Transmit flag */
+
+#define EMAC_DMA_INT_GLPII     ((rt_uint32_t)(1UL<<30))  /* GMAC LPI Interrupt. */
+#define EMAC_DMA_INT_TTI       ((rt_uint32_t)(1UL<<29))  /* Time-Stamp Trigger Interrupt. */
+#define EMAC_DMA_INT_GPI       ((rt_uint32_t)(1UL<<28))  /* GMAC PMT Interrupt. */
+#define EMAC_DMA_INT_GMI       ((rt_uint32_t)(1UL<<27))  /* GMAC MMC Interrupt. */
+#define EMAC_DMA_INT_GLI       ((rt_uint32_t)(1UL<<26))  /* GMAC Line interface Interrupt. */
+#define EMAC_DMA_INT_NIS       ((rt_uint32_t)(1UL<<16))  /* Normal interrupt summary. */
+#define EMAC_DMA_INT_AIS       ((rt_uint32_t)(1UL<<15))  /* Abnormal interrupt summary. */
+#define EMAC_DMA_INT_ER        ((rt_uint32_t)0x00004000)  /* Early receive interrupt */
+#define EMAC_DMA_INT_FBE       ((rt_uint32_t)0x00002000)  /* Fatal bus error interrupt */
+#define EMAC_DMA_INT_ET        ((rt_uint32_t)0x00000400)  /* Early transmit interrupt */
+#define EMAC_DMA_INT_RWT       ((rt_uint32_t)0x00000200)  /* Receive watchdog timeout interrupt */
+#define EMAC_DMA_INT_RPS       ((rt_uint32_t)0x00000100)  /* Receive process stopped interrupt */
+#define EMAC_DMA_INT_RBU       ((rt_uint32_t)0x00000080)  /* Receive buffer unavailable interrupt */
+#define EMAC_DMA_INT_R         ((rt_uint32_t)0x00000040)  /* Receive interrupt */
+#define EMAC_DMA_INT_TU        ((rt_uint32_t)0x00000020)  /* Underflow interrupt */
+#define EMAC_DMA_INT_RO        ((rt_uint32_t)0x00000010)  /* Overflow interrupt */
+#define EMAC_DMA_INT_TJT       ((rt_uint32_t)0x00000008)  /* Transmit jabber timeout interrupt */
+#define EMAC_DMA_INT_TBU       ((rt_uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt */
+#define EMAC_DMA_INT_TPS       ((rt_uint32_t)0x00000002)  /* Transmit process stopped interrupt */
+#define EMAC_DMA_INT_T         ((rt_uint32_t)0x00000001)  /* Transmit interrupt */
+
+#define EMAC_DMA_TransmitProcess_Stopped     ((rt_uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued */
+#define EMAC_DMA_TransmitProcess_Fetching    ((rt_uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+#define EMAC_DMA_TransmitProcess_Waiting     ((rt_uint32_t)0x00200000)  /* Running - waiting for status */
+#define EMAC_DMA_TransmitProcess_Reading     ((rt_uint32_t)0x00300000)  /* Running - reading the data from host memory */
+#define EMAC_DMA_TransmitProcess_Suspended   ((rt_uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailable */
+#define EMAC_DMA_TransmitProcess_Closing     ((rt_uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+
+#define EMAC_DMA_ReceiveProcess_Stopped      ((rt_uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+#define EMAC_DMA_ReceiveProcess_Fetching     ((rt_uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+#define EMAC_DMA_ReceiveProcess_Waiting      ((rt_uint32_t)0x00060000)  /* Running - waiting for packet */
+#define EMAC_DMA_ReceiveProcess_Suspended    ((rt_uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+#define EMAC_DMA_ReceiveProcess_Closing      ((rt_uint32_t)0x000A0000)  /* Running - closing descriptor */
+#define EMAC_DMA_ReceiveProcess_Queuing      ((rt_uint32_t)0x000E0000)  /* Running - queuing the receive frame into host memory */
+
+#define EMAC_DMA_Overflow_RxFIFOCounter      ((rt_uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define EMAC_DMA_Overflow_MissedFrameCounter ((rt_uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+
+#define EMAC_PMT_FLAG_WUFFRPR      ((rt_uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define EMAC_PMT_FLAG_WUFR         ((rt_uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define EMAC_PMT_FLAG_MPR          ((rt_uint32_t)0x00000020)  /* Magic Packet Received */
+
+#define EMAC_MMC_IT_TGF       ((rt_uint32_t)0x00200000)  /* When Tx good frame counter reaches half the maximum value */
+#define EMAC_MMC_IT_TGFMSC    ((rt_uint32_t)0x00008000)  /* When Tx good multi col counter reaches half the maximum value */
+#define EMAC_MMC_IT_TGFSC     ((rt_uint32_t)0x00004000)  /* When Tx good single col counter reaches half the maximum value */
+#define EMAC_MMC_IT_RGUF      ((rt_uint32_t)0x10020000)  /* When Rx good unicast frames counter reaches half the maximum value */
+#define EMAC_MMC_IT_RFAE      ((rt_uint32_t)0x10000040)  /* When Rx alignment error counter reaches half the maximum value */
+#define EMAC_MMC_IT_RFCE      ((rt_uint32_t)0x10000020)  /* When Rx crc error counter reaches half the maximum value */
+
+#define EMAC_MMCCR            ((rt_uint32_t)0x00000100)  /* MMC CR register */
+#define EMAC_MMCRIR           ((rt_uint32_t)0x00000104)  /* MMC RIR register */
+#define EMAC_MMCTIR           ((rt_uint32_t)0x00000108)  /* MMC TIR register */
+#define EMAC_MMCRIMR          ((rt_uint32_t)0x0000010C)  /* MMC RIMR register */
+#define EMAC_MMCTIMR          ((rt_uint32_t)0x00000110)  /* MMC TIMR register */
+#define EMAC_MMCTGFSCCR       ((rt_uint32_t)0x0000014C)  /* MMC TGFSCCR register */
+#define EMAC_MMCTGFMSCCR      ((rt_uint32_t)0x00000150)  /* MMC TGFMSCCR register */
+#define EMAC_MMCTGFCR         ((rt_uint32_t)0x00000168)  /* MMC TGFCR register */
+#define EMAC_MMCRFCECR        ((rt_uint32_t)0x00000194)  /* MMC RFCECR register */
+#define EMAC_MMCRFAECR        ((rt_uint32_t)0x00000198)  /* MMC RFAECR register */
+#define EMAC_MMCRGUFCR        ((rt_uint32_t)0x000001C4)  /* MMC RGUFCR register */
+
+#define EMAC_PTP_FineUpdate        ((rt_uint32_t)0x00000001)  /* Fine Update method */
+#define EMAC_PTP_CoarseUpdate      ((rt_uint32_t)0x00000000)  /* Coarse Update method */
+
+#define EMAC_PTP_FLAG_TSARU        ((rt_uint32_t)0x00000020)  /* Addend Register Update */
+#define EMAC_PTP_FLAG_TSITE        ((rt_uint32_t)0x00000010)  /* Time Stamp Interrupt Trigger */
+#define EMAC_PTP_FLAG_TSSTU        ((rt_uint32_t)0x00000008)  /* Time Stamp Update */
+#define EMAC_PTP_FLAG_TSSTI        ((rt_uint32_t)0x00000004)  /* Time Stamp Initialize */
+
+#define EMAC_PTP_PositiveTime      ((rt_uint32_t)0x00000000)  /* Positive time value */
+#define EMAC_PTP_NegativeTime      ((rt_uint32_t)0x80000000)  /* Negative time value */
+
+#define EMAC_PTPTSCR     ((rt_uint32_t)0x00000700)  /* PTP TSCR register */
+#define EMAC_PTPSSIR     ((rt_uint32_t)0x00000704)  /* PTP SSIR register */
+#define EMAC_PTPTSHR     ((rt_uint32_t)0x00000708)  /* PTP TSHR register */
+#define EMAC_PTPTSLR     ((rt_uint32_t)0x0000070C)  /* PTP TSLR register */
+#define EMAC_PTPTSHUR    ((rt_uint32_t)0x00000710)  /* PTP TSHUR register */
+#define EMAC_PTPTSLUR    ((rt_uint32_t)0x00000714)  /* PTP TSLUR register */
+#define EMAC_PTPTSAR     ((rt_uint32_t)0x00000718)  /* PTP TSAR register */
+#define EMAC_PTPTTHR     ((rt_uint32_t)0x0000071C)  /* PTP TTHR register */
+#define EMAC_PTPTTLR     ((rt_uint32_t)0x00000720)  /* PTP TTLR register */
+
+/* ETHERNET MAC address offsets */
+#define EMAC_MAC_ADDR_HBASE    (ETHERNET_MAC0_BASE + 0x40)  /* ETHERNET MAC address high offset */
+#define EMAC_MAC_ADDR_LBASE    (ETHERNET_MAC0_BASE + 0x44)  /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_MASK    ((rt_uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_MASK    ((rt_uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_MASK   ((rt_uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_MASK   ((rt_uint32_t)0xF8DE3F23)
+
+/* ETHERNET errors */
+#define  EMAC_ERROR              ((rt_uint32_t)0)
+#define  EMAC_SUCCESS            ((rt_uint32_t)1)
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define  EMAC_DMARXDESC_FRAME_LENGTHSHIFT           16
+
+
+
+
+/* ETHERNET-MAC registers */
+/* ETHERNET-MAC registers */
+struct rt_synopsys_eth
+{
+    volatile rt_uint32_t MCR;
+    volatile rt_uint32_t MFFR;
+    volatile rt_uint32_t MHTRH;
+    volatile rt_uint32_t MHTRL;
+    volatile rt_uint32_t GAR;
+    volatile rt_uint32_t GDR;
+    volatile rt_uint32_t FCR;
+    volatile rt_uint32_t VTR;
+               rt_uint8_t RESERVED0[8];
+    
+    volatile rt_uint32_t RWFFR;
+    volatile rt_uint32_t PMTR;
+    volatile rt_uint32_t LPICSR;
+    volatile rt_uint32_t LPITCR;
+    volatile rt_uint32_t ISR;
+    volatile rt_uint32_t IMR;
+
+    struct MARS
+    {
+        volatile rt_uint32_t MARH;
+        volatile rt_uint32_t MARL;
+    } MARs[16];
+
+               rt_uint8_t RESERVED1[24];
+    volatile rt_uint32_t RGSR;
+               rt_uint8_t RESERVED2[36];
+    volatile rt_uint32_t mmc_cntl;
+    volatile rt_uint32_t mmc_intr_rx;
+    volatile rt_uint32_t mmc_intr_tx;
+    volatile rt_uint32_t mmc_intr_mask_rx;
+    volatile rt_uint32_t mmc_intr_mask_tx;
+    volatile rt_uint32_t txoctetcount_gb;
+    volatile rt_uint32_t txframecount_gb;
+    volatile rt_uint32_t txbroadcastframes_g;
+    volatile rt_uint32_t txmulticastframes_g;
+    volatile rt_uint32_t tx64octets_gb;
+    volatile rt_uint32_t tx65to127octets_gb;
+    volatile rt_uint32_t tx128to255octets_gb;
+    volatile rt_uint32_t tx256to511octets_gb;
+    volatile rt_uint32_t tx512to1023octets_gb;
+    volatile rt_uint32_t tx1024tomaxoctets_gb;
+    volatile rt_uint32_t txunicastframes_gb;
+    volatile rt_uint32_t txmulticastframes_gb;
+    volatile rt_uint32_t txbroadcastframes_gb;
+    volatile rt_uint32_t txunderflowerror;
+    volatile rt_uint32_t txsinglecol_g;
+    volatile rt_uint32_t txmulticol_g;
+    volatile rt_uint32_t txdeferred;
+    volatile rt_uint32_t txlatecol;
+    volatile rt_uint32_t txexesscol;
+    volatile rt_uint32_t txcarriererror;
+    volatile rt_uint32_t txoctetcount_g;
+    volatile rt_uint32_t txframecount_g;
+    volatile rt_uint32_t txexecessdef_g;
+    volatile rt_uint32_t txpauseframes;
+    volatile rt_uint32_t txvlanframes_g;
+               rt_uint8_t RESERVED3[8];
+    volatile rt_uint32_t rxframecount_gb;
+    volatile rt_uint32_t rxoctetcount_gb;
+    volatile rt_uint32_t rxoctetcount_g;
+    volatile rt_uint32_t rxbroadcastframes_g;
+    volatile rt_uint32_t rxmulticastframes_g;
+    volatile rt_uint32_t rxcrcerror;
+    volatile rt_uint32_t rxallignmenterror;
+    volatile rt_uint32_t rxrunterror;
+    volatile rt_uint32_t rxjabbererror;
+    volatile rt_uint32_t rxundersize_g;
+    volatile rt_uint32_t rxoversize_g;
+    volatile rt_uint32_t rx64octets_gb;
+    volatile rt_uint32_t rx65to127octets_gb;
+    volatile rt_uint32_t rx128to255octets_gb;
+    volatile rt_uint32_t rx256to511octets_gb;
+    volatile rt_uint32_t rx512to1023octets_gb;
+    volatile rt_uint32_t rx1024tomaxoctets_gb;
+    volatile rt_uint32_t rxunicastframes_g;
+    volatile rt_uint32_t rxlengtherror;
+    volatile rt_uint32_t rxoutofrangetype;
+    volatile rt_uint32_t rxpauseframes;
+    volatile rt_uint32_t rxfifooverflow;
+    volatile rt_uint32_t rxvlanframes_gb;
+    volatile rt_uint32_t rxwatchdogerror;
+               rt_uint8_t RESERVED4[32];
+    volatile rt_uint32_t mmc_ipc_intr_mask_rx;
+               rt_uint8_t RESERVED5[4];
+    volatile rt_uint32_t mmc_ipc_intr_rx;
+               rt_uint8_t RESERVED6[4];
+    volatile rt_uint32_t rxipv4_gd_frms;
+    volatile rt_uint32_t rxipv4_hdrerr_frms;
+    volatile rt_uint32_t rxipv4_nopay_frms;
+    volatile rt_uint32_t rxipv4_frag_frms;
+    volatile rt_uint32_t rxipv4_udsbl_frms;
+    volatile rt_uint32_t rxipv6_gd_frms;
+    volatile rt_uint32_t rxipv6_hdrerr_frms;
+    volatile rt_uint32_t rxipv6_nopay_frms;
+    volatile rt_uint32_t rxudp_gd_frms;
+    volatile rt_uint32_t rxudp_err_frms;
+    volatile rt_uint32_t rxtcp_gd_frms;
+    volatile rt_uint32_t rxtcp_err_frms;
+    volatile rt_uint32_t rxicmp_gd_frms;
+    volatile rt_uint32_t rxicmp_err_frms;
+               rt_uint8_t RESERVED7[8];
+    volatile rt_uint32_t rxipv4_gd_octets;
+    volatile rt_uint32_t rxipv4_hdrerr_octets;
+    volatile rt_uint32_t rxipv4_nopay_octets;
+    volatile rt_uint32_t rxipv4_frag_octets;
+    volatile rt_uint32_t rxipv4_udsbl_octets;
+    volatile rt_uint32_t rxipv6_gd_octets;
+    volatile rt_uint32_t rxipv6_hdrerr_octets;
+    volatile rt_uint32_t rxipv6_nopay_octets;
+    volatile rt_uint32_t rxudp_gd_octets;
+    volatile rt_uint32_t rxudp_err_octets;
+    volatile rt_uint32_t rxtcp_gd_octets;
+    volatile rt_uint32_t rxtcp_err_octets;
+    volatile rt_uint32_t rxicmp_gd_octets;
+    volatile rt_uint32_t rxicmp_err_octets;
+               rt_uint8_t RESERVED8[1144];
+    volatile rt_uint32_t TSCR;
+    volatile rt_uint32_t SSIR;
+    volatile rt_uint32_t STSR;
+    volatile rt_uint32_t STNR;
+    volatile rt_uint32_t STSUR;
+    volatile rt_uint32_t STNUR;
+    volatile rt_uint32_t TSAR;
+    volatile rt_uint32_t TTSR;
+    volatile rt_uint32_t TTNR;
+    volatile rt_uint32_t STHWSR;
+    volatile rt_uint32_t TSR;
+    volatile rt_uint32_t PPSCR;
+    volatile rt_uint32_t ATNR;
+    volatile rt_uint32_t ATSR;
+               rt_uint8_t RESERVED9[200];
+    volatile rt_uint32_t MAR16H;
+    volatile rt_uint32_t MAR16L;
+    volatile rt_uint32_t MAR17H;
+    volatile rt_uint32_t MAR17L;
+    volatile rt_uint32_t MAR18H;
+    volatile rt_uint32_t MAR18L;
+    volatile rt_uint32_t MAR19H;
+    volatile rt_uint32_t MAR19L;
+    volatile rt_uint32_t MAR20H;
+    volatile rt_uint32_t MAR20L;
+    volatile rt_uint32_t MAR21H;
+    volatile rt_uint32_t MAR21L;
+    volatile rt_uint32_t MAR22H;
+    volatile rt_uint32_t MAR22L;
+    volatile rt_uint32_t MAR23H;
+    volatile rt_uint32_t MAR23L;
+    volatile rt_uint32_t MAR24H;
+    volatile rt_uint32_t MAR24L;
+    volatile rt_uint32_t MAR25H;
+    volatile rt_uint32_t MAR25L;
+    volatile rt_uint32_t MAR26H;
+    volatile rt_uint32_t MAR26L;
+    volatile rt_uint32_t MAR27H;
+    volatile rt_uint32_t MAR27L;
+    volatile rt_uint32_t MAR28H;
+    volatile rt_uint32_t MAR28L;
+    volatile rt_uint32_t MAR29H;
+    volatile rt_uint32_t MAR29L;
+    volatile rt_uint32_t MAR30H;
+    volatile rt_uint32_t MAR30L;
+    volatile rt_uint32_t MAR31H;
+    volatile rt_uint32_t MAR31L;
+               rt_uint8_t RESERVED10[1920];
+    volatile rt_uint32_t BMR;
+    volatile rt_uint32_t TPDR;
+    volatile rt_uint32_t RPDR;
+    volatile rt_uint32_t RDLAR;
+    volatile rt_uint32_t TDLAR;
+    volatile rt_uint32_t SR;
+    volatile rt_uint32_t OMR;
+    volatile rt_uint32_t IER;
+    volatile rt_uint32_t MFBOCR;
+    volatile rt_uint32_t RIWTR;
+               rt_uint8_t RESERVED11[4];
+    volatile rt_uint32_t AHBSR;
+               rt_uint8_t RESERVED12[24];
+    volatile rt_uint32_t CHTDR;
+    volatile rt_uint32_t CHRDR;
+    volatile rt_uint32_t CHTBAR;
+    volatile rt_uint32_t CHRBAR;
+};
+typedef struct rt_synopsys_eth rt_synopsys_eth;
+
+
+rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock);
+
+void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC);
+
+rt_uint16_t EMAC_PHY_read(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg);
+rt_uint32_t EMAC_PHY_write(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg, rt_uint16_t PHYValue);
+
+void EMAC_MAC_Addr_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t MacAddr, rt_uint8_t *Addr);
+void EMAC_clear_pending(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT);
+
+void EMAC_INT_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT, rt_bool_t NewState);
+void EMAC_resume_transmission(struct rt_synopsys_eth * ETHERNET_MAC);
+void EMAC_resume_reception(struct rt_synopsys_eth * ETHERNET_MAC);
+
+#endif

bsp/gd32450z-eval/project.ewp

@@ -339,10 +339,14 @@
                 </option>
                 <option>
                     <name>CCIncludePath2</name>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src</state>
                     <state>$PROJ_DIR$\..\..\..\git\rt-thread\libcpu\arm\cortex-m4</state>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include</state>
                     <state>$PROJ_DIR$\..\..\..\git\rt-thread\include</state>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\arch\include</state>
                     <state>$PROJ_DIR$\drivers</state>
-                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\include</state>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include\ipv4</state>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include\netif</state>
                     <state>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Include</state>
                     <state>$PROJ_DIR$\.</state>
                     <state>$PROJ_DIR$\applications</state>
@@ -1367,10 +1371,14 @@
                 </option>
                 <option>
                     <name>CCIncludePath2</name>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src</state>
                     <state>$PROJ_DIR$\..\..\..\git\rt-thread\libcpu\arm\cortex-m4</state>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include</state>
                     <state>$PROJ_DIR$\..\..\..\git\rt-thread\include</state>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\arch\include</state>
                     <state>$PROJ_DIR$\drivers</state>
-                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\include</state>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include\ipv4</state>
+                    <state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include\netif</state>
                     <state>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Include</state>
                     <state>$PROJ_DIR$\.</state>
                     <state>$PROJ_DIR$\applications</state>
@@ -2072,6 +2080,9 @@
         <file>
             <name>$PROJ_DIR$\applications\mem_test.c</name>
         </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\apps\ping\ping.c</name>
+        </file>
         <file>
             <name>$PROJ_DIR$\applications\rtgui_demo.c</name>
         </file>
@@ -2141,6 +2152,9 @@
         <file>
             <name>$PROJ_DIR$\drivers\board.c</name>
         </file>
+        <file>
+            <name>$PROJ_DIR$\drivers\drv_enet.c</name>
+        </file>
         <file>
             <name>$PROJ_DIR$\drivers\drv_exmc_sdram.c</name>
         </file>
@@ -2153,6 +2167,9 @@
         <file>
             <name>$PROJ_DIR$\drivers\gd32f450z_lcd_eval.c</name>
         </file>
+        <file>
+            <name>$PROJ_DIR$\drivers\synopsys_emac.c</name>
+        </file>
     </group>
     <group>
         <name>finsh</name>
@@ -2293,174 +2310,159 @@
         </file>
     </group>
     <group>
-        <name>GUIEngine</name>
-        <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\asc12font.c</name>
-        </file>
-        <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\asc16font.c</name>
-        </file>
-        <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\blit.c</name>
-        </file>
-        <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\box.c</name>
-        </file>
-        <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\color.c</name>
-        </file>
+        <name>Kernel</name>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\container.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\clock.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\components.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_blend.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\device.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_buffer.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\idle.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_client.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\ipc.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_hw.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\irq.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_rotozoom.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\kservice.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_trans.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\mem.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\filerw.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\memheap.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\mempool.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_bmp.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\module.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_fnt.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\object.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_freetype.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\scheduler.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_hz_bmp.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\thread.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_hz_file.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\timer.c</name>
         </file>
+    </group>
+    <group>
+        <name>LwIP</name>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\hz12font.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\api_lib.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\hz16font.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\api_msg.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\autoip.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_bmp.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\def.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_hdc.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\dhcp.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_jpg.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\dns.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_png.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\err.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_xpm.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\netif\etharp.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\matrix.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\netif\ethernetif.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\mouse.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\icmp.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\region.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\igmp.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\rtgui_app.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\inet.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\rtgui_driver.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\inet_chksum.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\rtgui_object.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\init.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\rtgui_system.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\ip.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\server.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\ip_addr.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\title.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\ip_frag.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\topwin.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\memp.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\widget.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\netbuf.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\window.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\netdb.c</name>
         </file>
-    </group>
-    <group>
-        <name>Kernel</name>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\clock.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\netif.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\components.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\netifapi.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\device.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\pbuf.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\idle.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\raw.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\ipc.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\netif\slipif.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\irq.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\sockets.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\kservice.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\stats.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\mem.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\sys.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\memheap.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\arch\sys_arch.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\mempool.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\tcp.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\module.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\tcp_in.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\object.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\tcp_out.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\scheduler.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\tcpip.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\thread.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\timers.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\..\git\rt-thread\src\timer.c</name>
+            <name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\udp.c</name>
         </file>
     </group>
 </project>

bsp/gd32450z-eval/project.uvprojx

@@ -10,6 +10,7 @@
       <TargetName>rt-thread_gd32f4xx</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
       <TargetOption>
         <TargetCommonOption>
           <Device>GD32F450ZK</Device>
@@ -403,6 +404,11 @@
               <FileType>1</FileType>
               <FilePath>applications\startup.c</FilePath>
             </File>
+            <File>
+              <FileName>rtgui_demo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\applications\rtgui_demo.c</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>

bsp/gd32450z-eval/rtconfig.h

@@ -66,7 +66,7 @@
 
 /* SECTION: RTGUI support */
 /* using RTGUI support */
-#define RT_USING_GUIENGINE
+//#define RT_USING_GUIENGINE
 
 /* name length of RTGUI object */
 #define RTGUI_NAME_MAX		16
@@ -159,7 +159,7 @@
 // #define RT_USING_DFS_ROMFS
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
-//#define RT_USING_LWIP
+#define RT_USING_LWIP
 /* LwIP uses RT-Thread Memory Management */
 #define RT_LWIP_USING_RT_MEM
 /* Enable ICMP protocol*/
@@ -173,7 +173,7 @@
 /* Enable DHCP */
 #define RT_LWIP_DHCP
 /* Enable DEBUG */
-//#define RT_LWIP_DEBUG
+#define RT_LWIP_DEBUG
 
 /* the number of simulatenously active TCP connections*/
 #define RT_LWIP_TCP_PCB_NUM	5
@@ -181,13 +181,13 @@
 /* ip address of target*/
 #define RT_LWIP_IPADDR0	192
 #define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	1
-#define RT_LWIP_IPADDR3	201
+#define RT_LWIP_IPADDR2	10
+#define RT_LWIP_IPADDR3	222
 
 /* gateway address of target*/
 #define RT_LWIP_GWADDR0	192
 #define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR2	10
 #define RT_LWIP_GWADDR3	1
 
 /* mask address of target*/

bsp/stm32f10x/project.uvprojx

@@ -10,6 +10,8 @@
       <TargetName>rtthread-stm32</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>5050169::V5.05 update 2 (build 169)::.\ARMCC_505u2</pArmCC>
+      <pCCUsed>5050169::V5.05 update 2 (build 169)::.\ARMCC_505u2</pCCUsed>
       <TargetOption>
         <TargetCommonOption>
           <Device>STM32F103ZE</Device>

bsp/stm32f10x/rtconfig.h

@@ -194,4 +194,6 @@
 /* nanopb support */
 /* #define RT_USING_NANOPB */
 
+#define RT_USING_CPU_FFS
+
 #endif