From dbd67507d96154c5238a923b7f24d8812ab224a7 Mon Sep 17 00:00:00 2001 From: thread-liu Date: Sat, 5 Dec 2020 09:09:11 +0800 Subject: [PATCH] [add] qspi_flash driver. --- .../HAL_Drivers/config/mp1/qspi_config.h | 56 ++++++ bsp/stm32/libraries/HAL_Drivers/drv_config.h | 1 + bsp/stm32/libraries/HAL_Drivers/drv_qspi.c | 6 +- bsp/stm32/libraries/STM32MPxx_HAL/SConscript | 3 + .../CM4/Inc/stm32mp1xx_hal_conf.h | 2 +- bsp/stm32/stm32mp157a-st-ev1/board/Kconfig | 13 ++ bsp/stm32/stm32mp157a-st-ev1/board/SConscript | 3 + .../board/ports/drv_qspi_flash.c | 180 ++++++++++++++++++ bsp/stm32/stm32mp157a-st-ev1/rtconfig.py | 2 +- 9 files changed, 263 insertions(+), 3 deletions(-) create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h create mode 100644 bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h new file mode 100644 index 000000000..0dc48247e --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-22 zylx first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = QUADSPI, \ + .Init.FifoThreshold = 4, \ + .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \ + .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \ + } +#endif /* QSPI_BUS_CONFIG */ +#endif /* BSP_USING_QSPI */ + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Channel = QSPI_DMA_CHANNEL, \ + .Init.Direction = DMA_PERIPH_TO_MEMORY, \ + .Init.PeriphInc = DMA_PINC_DISABLE, \ + .Init.MemInc = DMA_MINC_ENABLE, \ + .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ + .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ + .Init.Mode = DMA_NORMAL, \ + .Init.Priority = DMA_PRIORITY_LOW \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ + +#define QSPI_IRQn QUADSPI_IRQn +#define QSPI_IRQHandler QUADSPI_IRQHandler + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index 95c144056..fcd0079b0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -109,6 +109,7 @@ extern "C" { #elif defined(SOC_SERIES_STM32MP1) #include "mp1/dma_config.h" #include "mp1/uart_config.h" +#include "mp1/qspi_config.h" #include "mp1/spi_config.h" #include "mp1/adc_config.h" #include "mp1/dac_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c index 52c184290..81413d863 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c @@ -52,8 +52,12 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG; qspi_bus->QSPI_Handler = QSPI_Handler_config; +#if defined(SOC_SERIES_STM32MP1) + while (cfg->max_hz < HAL_RCC_GetACLKFreq() / (i + 1)) +#else while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1)) - { +#endif + { i++; if (i == 255) { diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript index 815a29186..c6fb2a00c 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript @@ -97,6 +97,9 @@ if GetDepend(['BSP_USING_LTDC']): if GetDepend(['BSP_USING_FDCAN']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c'] +if GetDepend(['BSP_USING_QSPI']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c'] + path = [cwd + '/STM32MP1xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32MP1xx/Include', cwd + '/CMSIS/Core/Include', diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h index 0f22065b6..8671cee5d 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h @@ -55,7 +55,7 @@ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ -/*#define HAL_QSPI_MODULE_ENABLED */ +#define HAL_QSPI_MODULE_ENABLED /*#define HAL_RNG_MODULE_ENABLED */ #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig b/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig index 8a456120c..347caac74 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig +++ b/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig @@ -28,6 +28,13 @@ menu "Onboard Peripheral Drivers" select RT_MTD_NAND_DEBUG default n + config BSP_USING_QSPI_FLASH + bool "Enable QSPI FLASH (MX25L51245G)" + select BSP_USING_QSPI + select RT_USING_SFUD + select RT_SFUD_USING_QSPI + default n + config BSP_USING_OPENAMP bool "Enable OpenAMP" select RT_USING_OPENAMP @@ -92,6 +99,12 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y + config BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + menuconfig BSP_USING_UART bool "Enable UART" select RT_USING_SERIAL diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/SConscript b/bsp/stm32/stm32mp157a-st-ev1/board/SConscript index dec20f29e..963eb90ce 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/SConscript +++ b/bsp/stm32/stm32mp157a-st-ev1/board/SConscript @@ -43,6 +43,9 @@ if GetDepend(['BSP_USING_MFX']): if GetDepend(['BSP_USING_FDCAN']): src += Glob('ports/drv_fdcan.c') +if GetDepend(['BSP_USING_QSPI']): + src += Glob('ports/drv_qspi_flash.c') + if GetDepend(['BSP_USING_OPENAMP']): src += Glob('CubeMX_Config/CM4/Src/ipcc.c') src += Glob('CubeMX_Config/CM4/Src/openamp.c') diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c new file mode 100644 index 000000000..70fa97735 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-07 thread-liu first version + */ + +#include +#include +#include +#include +#include + +#ifdef BSP_USING_QSPI_FLASH + +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +/** +* @brief QSPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hqspi: QSPI handle pointer +* @retval None +*/ +void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspInit 0 */ + if (IS_ENGINEERING_BOOT_MODE()) + { + PeriphClkInit.Sdmmc12ClockSelection = RCC_QSPICLKSOURCE_ACLK; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_QSPI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* USER CODE END QUADSPI_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_QSPI_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**QUADSPI GPIO Configuration + PF6 ------> QUADSPI_BK1_IO3 + PF7 ------> QUADSPI_BK1_IO2 + PF8 ------> QUADSPI_BK1_IO0 + PF9 ------> QUADSPI_BK1_IO1 + PF10 ------> QUADSPI_CLK + PB6 ------> QUADSPI_BK1_NCS + */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7 | GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**QUADSPI GPIO Configuration + PC0 ------> QUADSPI_BK2_NCS + PH3 ------> QUADSPI_BK2_IO1 + PG7 ------> QUADSPI_BK2_IO3 + PG10 ------> QUADSPI_BK2_IO2 + PH2 ------> QUADSPI_BK2_IO0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF11_QUADSPI; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* USER CODE BEGIN QUADSPI_MspInit 1 */ + + /* USER CODE END QUADSPI_MspInit 1 */ + } +} + +/** +* @brief QSPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hqspi: QSPI handle pointer +* @retval None +*/ +void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) +{ + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ + + /* USER CODE END QUADSPI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_QSPI_CLK_DISABLE(); + + /**QUADSPI GPIO Configuration + PC0 ------> QUADSPI_BK2_NCS + PF10 ------> QUADSPI_CLK + PB6 ------> QUADSPI_BK1_NCS + PH3 ------> QUADSPI_BK2_IO1 + PG7 ------> QUADSPI_BK2_IO3 + PG10 ------> QUADSPI_BK2_IO2 + PF7 ------> QUADSPI_BK1_IO2 + PF6 ------> QUADSPI_BK1_IO3 + PH2 ------> QUADSPI_BK2_IO0 + PF8 ------> QUADSPI_BK1_IO0 + PF9 ------> QUADSPI_BK1_IO1 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_3|GPIO_PIN_2); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_7|GPIO_PIN_10); + + /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + + /* USER CODE END QUADSPI_MspDeInit 1 */ + } + +} + +static int rt_hw_qspi_flash_with_sfud_init(void) +{ + stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, RT_NULL, RT_NULL); + /* init MX25L51245G */ + if (RT_NULL == rt_sfud_flash_probe("MX25L51245G", "qspi10")) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_qspi_flash_with_sfud_init); + +#endif /* BSP_USING_QSPI_FLASH */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py index b1cad1d51..3daaf0c1d 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py +++ b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py @@ -23,7 +23,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + EXEC_PATH = r'D:\software\Embedded Workbench 8.3' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') -- GitLab