diff --git a/libcpu/arm/stm32/context_gcc.S b/libcpu/arm/stm32/context_gcc.S
index 04d45c132756be9d703aecb076e2dff244d84601..7124e77c44c545813731a2d19006d0b3ff964449 100644
--- a/libcpu/arm/stm32/context_gcc.S
+++ b/libcpu/arm/stm32/context_gcc.S
@@ -146,7 +146,9 @@ rt_hw_context_switch_to:
 	/* set the PendSV exception priority */
 	LDR		r0, =NVIC_SYSPRI2
 	LDR		r1, =NVIC_PENDSV_PRI
-	STR		r1, [r0]
+  LDR.W   r2, [r0,#0x00]       ; read
+  ORR     r1,r1,r2             ; modify
+  STR     r1, [r0]             ; write-back
 
 	LDR		r0, =NVIC_INT_CTRL      /* trigger the PendSV exception (causes context switch) */
 	LDR		r1, =NVIC_PENDSVSET
diff --git a/libcpu/arm/stm32/context_iar.S b/libcpu/arm/stm32/context_iar.S
index ee2bb0f5936dc02c977834b5a30221766175cefb..c4ad75abeec29b2a5fee6efeac3ffe7e236a691f 100644
--- a/libcpu/arm/stm32/context_iar.S
+++ b/libcpu/arm/stm32/context_iar.S
@@ -143,7 +143,9 @@ rt_hw_context_switch_to:
 	; set the PendSV exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
-    STR     r1, [r0]
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
 
     LDR     r0, =NVIC_INT_CTRL      ; trigger the PendSV exception (causes context switch)
     LDR     r1, =NVIC_PENDSVSET
diff --git a/libcpu/arm/stm32/context_rvds.S b/libcpu/arm/stm32/context_rvds.S
index e2dab09a80bf1eade576ea29d8b7b73cf6faecc2..15e526cca1d82ec541a4c7d7489e7d2011e59882 100644
--- a/libcpu/arm/stm32/context_rvds.S
+++ b/libcpu/arm/stm32/context_rvds.S
@@ -149,7 +149,9 @@ rt_hw_context_switch_to    PROC
 	; set the PendSV exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
-    STR     r1, [r0]
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
 
 	; trigger the PendSV exception (causes context switch)
     LDR     r0, =NVIC_INT_CTRL